WO2020093868A1 - 多核芯片、***，及其方法和存储介质 - Google Patents

多核芯片、***，及其方法和存储介质 Download PDF

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Publication number
WO2020093868A1
WO2020093868A1 PCT/CN2019/112684 CN2019112684W WO2020093868A1 WO 2020093868 A1 WO2020093868 A1 WO 2020093868A1 CN 2019112684 W CN2019112684 W CN 2019112684W WO 2020093868 A1 WO2020093868 A1 WO 2020093868A1
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Prior art keywords
core
voltage
physical core
memory
physical
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PCT/CN2019/112684
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English (en)
French (fr)
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相海涛
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西安中兴新软件有限责任公司
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Priority to US17/290,601 priority Critical patent/US20220004246A1/en
Publication of WO2020093868A1 publication Critical patent/WO2020093868A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4405—Initialisation of multiprocessor systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4893—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues taking into account power or heat criteria
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of communications, and in particular, to a multi-core chip, system, method, and storage medium.
  • Method one Use shutdown standby. If the user does not execute the actual shutdown during the execution of the user's shutdown instruction, the essence is not to shut down, so as to increase the next startup speed.
  • Method 2 Use software tailoring to reduce the kernel size and loading time of the operating system to increase the startup speed.
  • Embodiments of the present invention provide a multi-core chip and system to at least solve the problem of slow system startup speed in the related art.
  • a multi-core chip including: a main CPU and a main memory, the multi-core chip further includes: a first physical core, which is responsible for shutdown and startup of the system, and receives In the case, extract the system startup minimum resource set and save it in the first built-in memory, and notify the main CPU to shut down the system; when receiving the system boot instruction, the The system startup minimum resource set is copied to the main memory, and the system control is transferred to the main CPU, wherein the first physical core can work in a first voltage and a second voltage state, wherein the first A voltage is the normal working voltage of the first physical core, and the second voltage is the holding voltage of the first physical core when the system is off, the first voltage is greater than the second voltage; the first built-in Memory, used to save the minimum resource set for system startup; power management chip, used to realize multi-level voltage output through voltage conversion, used to provide the system with the system turned on Operating voltage, and providing the second voltage is the first physical core in the system off state.
  • a first physical core which is responsible for shutdown and startup
  • an electronic system is also provided.
  • the electronic system includes peripheral devices and the multi-core chip in the foregoing embodiment.
  • a system power management method based on the above embodiment, the method includes: when the power management chip receives a system power-on command, providing normal operating voltages for various components of the system And adjust the voltage of the first physical core from the second voltage to the first voltage; when the power management chip receives a system shutdown command, cut off the voltage of each component of the system The physical core continues to supply power, and adjusts the voltage of the first physical core from the first voltage to the second voltage.
  • a system shutdown method based on the above embodiment, the method comprising: the first physical core shuts down to receive a system shutdown instruction; the first physical core extraction system starts at a minimum The resource set and the current user process address and path are copied to the first built-in memory; the first physical core notifies the main CPU to perform a forced process shutdown, and notifies the power management chip to turn off the system power.
  • a system boot method based on the above embodiment, the method includes: the first physical core receives a system boot command; the first physical core converts the first The system startup minimum resource set saved in the built-in memory is copied to the main memory; the first physical core transfers the system control right to the main CPU.
  • a system recovery method based on the system of the above embodiment, the method comprising: the first physical core receives a command to recover to the state before the last shutdown; the first physical The core copies the boot instruction saved in the first built-in memory to the main memory to start the system; the first physical core copies the pre-shutdown memory image saved in the first built-in memory to the main memory, The first physical core transfers system control to the main CPU.
  • a system crash recovery method based on the system described in the above embodiment, the method includes: checking whether the first timer and the second timer time out; The first timer times out, and the second timer does not time out, then resets the main CPU and other physical cores except the first physical core; if the second timer times out, resets the first Physical core.
  • a peripheral device management method based on the system described in the above embodiment, the method includes: determining whether the system is in a normal working state or a low power consumption state; if the system is in a normal working state Status, check whether the peripheral device has abnormal start-up and / or detect whether the peripheral device has abnormal temperature, if yes, start the repair program and / or start the temperature protection program through the reliability function module to repair the peripheral device and / or temperature protection.
  • a storage medium in which a computer program is stored, wherein the computer program is configured to execute the steps in any one of the above method embodiments during runtime.
  • FIG. 1 is a schematic diagram of a multi-core chip structure according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a system with the multi-core chip according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a power management architecture according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of a power management method according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of a shutdown method according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of a boot method according to an alternative embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a memory structure according to an alternative embodiment of the present invention.
  • FIG. 8 is a flowchart of a system site restoration method according to an embodiment of the present invention.
  • FIG. 9 is a flowchart of a system crash recovery method according to an embodiment of the present invention.
  • FIG. 10 is a flowchart of a peripheral device reliability management method according to an embodiment of the present invention.
  • the multi-core chip provided by the embodiment of the present invention, a system having the core chip, a power management method based on the system, a fast boot method and a system recovery method, etc.
  • FIG. 1 is a schematic diagram of the structure of a multi-core chip of this embodiment.
  • the multi-core chip includes the main CPU 10 and the main memory 20 of the existing multi-core chip (the existing multi-core chip It also includes other components (not shown in the figure).
  • the multi-core chip further includes a first physical core 30, a first built-in memory 40, and a power management chip 50.
  • the first physical core 30 is responsible for shutting down and starting the system.
  • a system shutdown instruction is received, the system startup minimum resource set is extracted and saved in the first built-in memory 40, and the main CPU 10 is notified to shut down the office.
  • the system upon receiving the system boot command, copy the minimum set of system startup resources in the first built-in memory 40 to the main memory 20, and transfer system control to the main CPU 10 ,
  • the first physical core 30 can operate in a first voltage and a second voltage state, wherein the first voltage is the normal operating voltage of the first physical core 30, and the second voltage is the system In the shutdown state, the holding voltage of the first physical core 30 is greater than the second voltage;
  • the first built-in memory 40 is used to save the minimum resource set for system startup;
  • the power management chip 50 is used to realize multi-level voltage output through voltage conversion, to provide an operating voltage for the system when the system is turned on, and to provide the second voltage for the first physical core 30 when the system is turned off .
  • the first physical core can be multiplexed with any physical core in the current multi-core chip architecture, which can simplify the existing chip design.
  • the first physical core can also be implemented by adding a dedicated physical core to the current chip architecture.
  • the first built-in memory may use a built-in RAM with low capacity and low power consumption, thereby providing memory read-write efficiency.
  • the multi-core chip may also have a built-in reliability function module.
  • the reliability module has a built-in general reliability program, including a device repair program, a peripheral device temperature protection program, and a low-power peripheral device self-test program. This module can realize product peripheral equipment management and multi-core chip collapse self-rescue.
  • the multi-core chip includes multiple physical cores 205, multi-threads 206, multi-level cache 207, and high-speed built-in memory 208 ⁇ Memory ⁇ ⁇ 209.
  • the system also has peripheral circuits, which include: a system bus 202, a memory RAM 203, and an external memory ROM 204.
  • peripheral circuits which include: a system bus 202, a memory RAM 203, and an external memory ROM 204.
  • the entire system also includes a power management module 210.
  • the multi-core chip 105 and the memory RAM 103 and the external memory ROM 104 are connected and interacted through the system bus 102.
  • the physical core CORE refers to a low-power physical core specifically introduced for multi-core chips.
  • the physical core can be implemented by reusing a core of an existing multi-core chip or can be redesigned. There is a brand new physical core in the design. This embodiment uses a separate design example.
  • the typical characteristics of the physical core COREX include working under normal voltage, such as 3.6V, or working under low voltage. In this embodiment, 1.8V is used.
  • the physical core is configured with a cache or memory RAM0 that can work under low voltage. RAM0 is used to store the boot system instruction set, and optionally can also be used to store the address pointer of the currently running process.
  • a mainstream FLASH chip parameter is about 200MB / s read, 20MB / s
  • the mainstream mobile terminal LPDDR4RAM read and write efficiency parameter is about 25GB / s, write 10GB / s. It can be seen that the reading efficiency of RAM is about 100 times that of ROM, while the writing efficiency is about 50 times that of ROM. Therefore, RAM0 theory can greatly shorten the boot load time. It is assumed that the traditional boot program takes 20 seconds to load, and using RAM0 takes only 200 ms to complete the load. The efficiency is improved by about 20s.
  • Multi-core chip 201 it includes multiple physical cores CORE 0 to CORE X;
  • System bus 202 the bus connecting the chip with peripheral devices and peripheral devices, responsible for the communication between each chip and each internal device;
  • Main memory 203 namely, RAM, 2203, generally refers to memory for smart devices;
  • ROM 204 external storage, generally refers to FLASH for smart devices, used to store various installation or executable files;
  • CORE 205 Physical core X, which is a low-power physical core, mainly responsible for system reliability algorithm maintenance and performance optimization.
  • Thread X is responsible for parallel execution of instructions to improve the efficiency of physical core execution.
  • Cache 207 usually multi-level cache can be preset inside the chip, and each physical core can be configured with different cache capacity and number.
  • RAM0 which refers to the small-capacity memory specifically configured for the physical core COREX, or cache.
  • Memory management unit 209 MMU is responsible for mapping and addressing each physical memory in the system.
  • the power management chip 210 can convert the voltage to realize the output of multi-level voltages, so as to provide working voltages to the above functional components of the system. Continue to provide a lower maintenance voltage for CORE X205 when the system is off.
  • the present invention also provides a power management system.
  • the power management chip in the multi-core chip can provide multi-level voltage output and control.
  • the minimum voltage supply of the physical core can be maintained during shutdown Reduce power consumption.
  • Power management chip 301 This chip can provide a variety of voltage output and conversion, and can be programmed to achieve multi-level voltage output.
  • Physical core CORE X input circuit 302 This circuit can continue to maintain the input in the shutdown state, and maintain a variable voltage supply when the other CPU cores are powered off, which satisfies the normal operation of the CPU physical core CORE X.
  • CPU main input circuit 303 Provides normal current and voltage input to the CPU to ensure that the CPU works normally when it is turned on.
  • Bus input circuit 304 provides current and voltage input for the bus to ensure normal communication of the system bus.
  • RAM input circuit 305 provides current and voltage input to the main memory of the system to ensure that the memory is normally powered on.
  • ROM input circuit 306 provides current and voltage input to the system external memory to ensure that the external memory works normally at power-on, and other application processes can read and write normally.
  • an embodiment of the present invention also provides a power management method.
  • the power management method includes the following processes:
  • Step S401 User instruction input
  • Smart devices usually provide peripheral keys or operate the UI for user command input.
  • the power-on key can be provided, or different keys can define different events, and a variety of key combinations can be provided to meet different command inputs.
  • the state before the shutdown is button 1 + button 3, etc.
  • the power management chip can directly determine whether the current power-on or power-off command, or other commands, if it is a power-on command, perform step S302; otherwise, execute judgment C402.
  • Step S402 supply power to the CPU or peripheral RAM and circuit
  • the power management chip begins to provide power input for the peripheral CPU, RAM, ROM, etc., to ensure the normal working voltage of the physical device of the smart device.
  • Step S403 Adjust the physical core CORE X to the normal power supply voltage
  • the power management chip switches the voltage switch to ensure that the physical core CORE X works normally at a normal voltage.
  • Judgment C402 judge whether it is a shutdown command
  • step S404 is performed; otherwise, step 406 is performed, exception handling, usually ignore button press instruction is ignored.
  • Step S404 cut off the peripheral circuit power supply such as CPU main circuit power supply, RAM and ROM;
  • the power management chip When shutting down, the power management chip cuts off the main power input of the CPU and the power input of peripheral circuits such as RAM, ROM, bus, etc., to ensure that the physical core CORE X works with low power consumption in the shutdown state, and only the physical core CORE X works.
  • Step S405 Adjust the physical core CORE X to a 1.8v low voltage working state
  • the power management chip switches the physical core voltage to 1.8v low-power working state.
  • Step S406 exception handling
  • the user button is a switch button, but the button time is not satisfied or other conditions are not met, and the power management chip cannot determine the power-on or power-off command, the button command is ignored and no processing is performed.
  • An embodiment of the present invention also provides a shutdown method for a multi-core chip. As shown in FIG. 5, the shutdown method includes the following processes:
  • Step S501 POWER OFF
  • the system detects that the user input is a shutdown command.
  • Step S502 the power management chip receives the shutdown instruction
  • the power management chip detects a shutdown command.
  • Step S503 Notify the physical core CORE X shutdown message
  • the power management chip notifies the current CPU physical core CORE X shutdown message, and the physical core CORE X is responsible for system startup and shutdown.
  • Step S504 The physical core CORE statistics the current system user process information
  • the physical core COREX obtains the current system system user process information from the CPU0, including process ID, process entry address, process name and process path and other information, and at the same time distinguishes the current process as a system process or user process, especially for the current system running process, it needs to be identified
  • the current running process can be used to restore the last state after the system is booted.
  • Step S505 CORE X classifies the system process and the user process
  • the physical core CORE X classifies the system process and the user process.
  • the user process priority is lower than the system process. Usually, it can be simply judged as a system process by the system self-starting list, and non-self-starting processes can be regarded as user processes.
  • Step S506 Extract the system start minimum resource set
  • the physical core CORE needs to extract the minimum set of system startup resources and exclude peripherals and communication processes in the system process. For smart devices, it is generally considered that peripheral processes are unnecessary processes and communication chip-related processes are unnecessary processes.
  • the kernel mode thread is the first priority process.
  • Step S507 The physical core CORE extracts the current user process address and path, performs compression and encryption, and then copies it to the RAM0 different process mirror area;
  • the physical core CORE X extracts the user process address and path, then compresses and encrypts it, and saves it in the RAM0 user process mirror area.
  • the system process is copied to the system mirror area.
  • Step S508 The physical core CORE X notifies CORE 0 to perform a forced process shutdown
  • the physical core CORE X completes the information recording before shutdown, notifies CORE 0 to forcibly shut down the system process, and notifies the power management chip to shut down.
  • Step S509 the power management chip turns off the power input of peripheral circuits such as CPU, RAM, ROM, etc .;
  • the power management chip disconnects the power input of peripheral circuits such as CPU, RAM, ROM, etc., and only retains the CPU physical core CORE X power input, and at the same time adjusts the physical core CORE X voltage to 1.8v to keep the physical core working normally at low voltage.
  • an embodiment of the present invention provides a fast boot method. As shown in FIG. 6, the fast boot method includes the following steps:
  • Step S601 POWER ON
  • Step S602 the power management chip receives the boot instruction
  • the power management chip detects that the user has powered on.
  • Step S603 peripheral circuits such as CPU, RAM, and ROM are powered on;
  • the power management chip supplies power to peripheral circuits such as CPU, RAM, ROM, etc., to ensure the normal power input of the physical hardware of the system.
  • Step S604 the power management chip notifies the physical core CORE X boot command
  • the power management chip notifies the CPU physical core CORE X boot command.
  • Step S605 CORE X copies the system startup instruction set and startup program to the main memory RAM;
  • CORE X copies the system startup instruction set and startup program to the main memory RAM. Since RAM0 has stored the BOOT program and system address required for startup in the system startup instruction area, CORE X copying the startup information to the main CPU can greatly save the system from the outside. It takes time to save and copy to memory, and reduce the number of dynamic loading programs, and only give priority to start programs related to user experience, such as UI, indicators, and other programs that affect user experience.
  • Step S606 CORE X resets the other CPU core transfer control to CORE 0;
  • the physical core CORE X is responsible for resetting other physical cores of the CPU, and at the same time handing over system control to CORE 0 to complete the boot process.
  • Step S607 system startup
  • Step S608 Start the peripheral chip or process
  • the system starts to automatically start other low-priority processes or chips.
  • the communication chip or the Bluetooth chip or the WIFI chip has a fast startup speed and has a weak impact on the user experience, and then these peripheral chips can be started after the system is started. Speed up the startup process.
  • an embodiment of the present invention also provides a memory mapping structure, as shown in FIG. 7, the built-in small-capacity memory includes: a system reserved area 701, and the system startup refers to static Area 702, system startup mirror area 703 and user process mirror area 704;
  • System reserved area 701 Refers to the reserved system area specifically for CORE X for CORE X to backup its own system data.
  • the system startup static area 702 is used to save the system startup boot program and instruction set in the ROM.
  • System startup mirror area 703 refers to an address area that specifically saves the address and program data of key processes of the system before shutdown, and can be directly copied to the main memory for quick startup.
  • User process mirror area 704 It is used to save the user process address and program data before shutdown. It is used to quickly load the process after fast startup. Optional can be used to realize on-site recovery before shutdown.
  • an embodiment of the present invention also provides a fast on-site recovery method.
  • the fast on-site recovery method includes the following steps:
  • Step S801 normal boot process
  • Step S802 the power management chip supplies power to peripheral devices such as CPU, RAM, ROM, etc .;
  • Step S803 The physical core CORE X copies the boot instruction in RAM0 to the main memory;
  • Step S804 system startup
  • Step S805 The physical core CORE X copies RAM0 to memory before mirroring the main memory;
  • Step S806 The physical core CORE X transfers control to CORE 0;
  • an embodiment of the present invention also provides a system crash recovery method.
  • the system uses a watchdog strategy.
  • the watchdog uses a timer circuit whose timing output is connected to the reset terminal of the circuit.
  • the program clears the timer within a certain time range (commonly known as "feeding the dog") ), So when the program works normally, the timer cannot always overflow, and thus the reset signal cannot be generated. If the program fails, the watchdog will not be reset within the timing period, which will cause the watchdog timer to overflow and generate a reset signal and restart the system.
  • a dual watchdog strategy based on the physical core CORE X is proposed.
  • the main CPU uses a timer T1
  • the physical core CORE X uses a timer T2.
  • T2 is greater than T1, usually 1.5 * T1 long.
  • the physical core CORE is responsible for copying the process address data in the current main memory. In order to improve system efficiency, this implementation only copies key system process data, such as network processes, UI processes, etc., and then Reset the CPU, reload and save the process address data. ; Only when the timers T1 & T2 time out at the same time, restart the system and enter the process of restarting quickly.
  • the steps of the system crash recovery method of this implementation are:
  • Step S901 T1 reset
  • step S902 Check whether the physical core CORE X watchdog T2 times out. If the timer T2 times out, perform step S902; otherwise, perform step S806.
  • Step S902 Reset the physical core CORE X
  • T2 timeout means that the physical core CORE may have lost its response, at this time reset the physical core.
  • Step S903 The physical core CORE X copies the current out-of-process system memory process image to RAM0;
  • the physical core CORE X copies the other memory processes outside the current process in the current system to RAM0, and backs up the user process address and data.
  • Step S904 Restart the system
  • the power management chip disconnects the CPU, RAM, ROM and other power input, and then restart.
  • Step S905 The physical core CORE X loads system RAM0 key process data to the main memory;
  • the physical core CORE X copies the shutdown data in RAM0 to the main memory to maximize the state before the system crash.
  • Step S906 Clear the current CPU execution process data and processes
  • the physical core CORE X clears all register cache data from CORE 0 to CORE N.
  • Step S907 reset other CPU cores
  • the physical core CORE X resets the main CPU circuit.
  • Step S908 Maintain the standby state, that is, the system maintains the standby normal operating state.
  • the embodiments of the present invention also provide a method for peripheral device reliability management.
  • the built-in reliability module can dynamically check the running status of the peripheral device in the normal working mode and the low-power shutdown mode, or check whether the device is abnormal and try to repair it.
  • the reliability module may have built-in peripheral device repair programs, peripheral device temperature protection programs, and low-power peripheral device self-test programs. Through general reliability programs, including device repair programs, peripheral device temperature protection programs, and Low-power peripheral device self-test program, this module can implement peripheral device reliability checking algorithm and control peripheral devices under low power consumption.
  • the peripheral devices in this implementation include but are not limited to: memory, FLASH, indicator lights, screen, Bluetooth, WIFI, and communication modules.
  • the peripheral device reliability management method includes the following steps:
  • Judgment S1001 whether it is in the low power consumption state of shutdown
  • Judgment S1002 check whether the peripheral device has an abnormal start
  • step S1003 is executed to try to repair; otherwise, judgment S1004 is executed.
  • Step S1003 Start the repair program
  • Judgment S1004 check whether the operating temperature of the peripheral equipment is abnormal
  • step S1005 is executed; otherwise, step S1009 is executed.
  • Step S1005 Start the temperature protection program
  • Execute temperature protection program execute the built-in temperature protection program, such as common control rate, control working frequency and other methods.
  • Step S1006 Start the peripheral device self-test program
  • Judgment S1007 check whether the peripheral device is abnormal
  • step S1008 is executed; otherwise, step S1009 is executed.
  • Step S1008 start the repair program
  • Judgment S1009 judge whether peripheral equipment needs high reliability protection
  • Step S1010 adding a high reliability protection list
  • Step S1011 End.
  • the invention also provides a storage medium in which a computer program is stored, wherein the computer program is set to execute the steps in any of the above method embodiments when it is run.
  • a low-power physical core and a power management chip are introduced into the multi-core chip, and the multi-core chip is controlled by the power management chip in a hierarchical voltage power supply, so that the low-power physical core is shut down in the entire machine
  • the physical core can still work normally.
  • the physical core saves the necessary instruction set for booting through the built-in small-capacity memory. Therefore, when the boot command is received, the physical core is copied to the main memory through the memory map, which can greatly shorten the boot time.
  • modules or steps of the present invention can be implemented by a universal computing device, they can be concentrated on a single computing device, or distributed in a network composed of multiple computing devices Above, optionally, they can be implemented with program code executable by the computing device, so that they can be stored in the storage device to be executed by the computing device, and in some cases, can be in a different order than here
  • the steps shown or described are performed, or they are made into individual integrated circuit modules respectively, or multiple modules or steps among them are made into a single integrated circuit module to achieve. In this way, the present invention is not limited to any specific combination of hardware and software.

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Abstract

本发明提供了一种多核芯片、***，及其方法和存储介质。该多核芯片包括：第一物理核心，用于负责***的关机和启动，在收到***关机指令的情况下，提取***启动最小资源集并保存至第一内置内存中，并通知所述主CPU关闭所述***；在收到***开机指令的情况下，将所述第一内置内存中的所述***启动最小资源集拷贝至所述主内存，并将***控制权转交至所述主CPU；第一内置内存，用于保存所述***启动最小资源集；电源管理芯片，用于通过电压转换实现多级电压的输出，用于在***开机状态下为***提供工作电压，以及在***关机状态下为所述第一物理核心提供所述第二电压。

Description

多核芯片、***，及其方法和存储介质
相关申请的交叉引用
本申请基于申请号为201811314925.8、申请日为2018年11月6日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及通信领域，具体而言，涉及一种多核芯片、***，及其方法和存储介质。
背景技术
随着智能硬件和人工智能的发展，电子产品具备功能也越来越复杂，***容量越来越大，尤其智能硬件普遍具有操作***，随着***设备增多，开机时间较长。一方面，导致用户体验变差，另一方面，用户可能不愿意关机，从而导致功耗水平上升，不利于带电池的智能设备续航。
目前针对智能终端开机优化主要有如下两种方式：
方式一：采用关机待机，在用户关机指令执行中不执行真正关机，其本质是不关机，以提高下次开机速度。
方式二：采用软件裁剪，削减操作***内核大小以及加载时间，从而提高启动速度。
但是，在方式一中，由于待机功耗较高，从而会缩减电池寿命和续航时间，以及硬件长时间不断电缩短了产品使用寿命。而在方式二中，由于通用性不强，很难适用多个领域。特别是***越来越大，裁剪不当很难满足行业多样性发展。
发明内容
本发明实施例提供了一种多核芯片及***，以至少解决相关技术中***启动速度较慢的问题。
根据本发明的一个实施例，提供了一种多核芯片，包括：主CPU和主内存，该多核芯片还包括：第一物理核心，用于负责***的关机和启动，在收到***关机指令的情况下，提取***启动最小资源集并保存至第一内置内存中，并通知所述主CPU关闭所述***；在收到***开机指令的情况下，将所述第一内置内存中的所述***启动最小资源集拷贝至所述主内存，并将***控制权转交至所述主CPU，其中，所述第一物理核心可工作在第一电压和第二电压状态下，其中，所述第一电压为所述第一物理核心的正常工作电压，所述第二电压为***关机状态下，所述第一物理核心的保持电压，所述第一电压大于所述第二电压；第一内置内存，用于保存所述***启动最小资源集；电源管理芯片，用于通过电压转换实现多级电压的输出，用于在***开机状态下为***提供工作电压，以及在***关机状态下为所述第一物理核心提供所述第二电压。
根据本发明的另一个实施例，还提供了一种电子***，该电子***包括***设备以及上述实施例中的多核芯片。
根据本发明的再一个实施例，还提供了一种基于上述实施例的***的电源管理方法，该方法包括：当所述电源管理芯片接收到***开机指令时，为***各部件提供正常工作电压，并将所述第一物理核心的电压从所述第二电压调节至所述第一电压；当所述电源管理芯片接收到***关机指令时，切断***各部件的电压，对所述第一物理核心继续供电，并将所述第一物理核心的电压从所述第一电压调节至所述第二电压。
根据本发明的再一个实施例，还提供了一种基于上述实施例的***的关机方法，该方法包括：所述第一物理核心关机接收***关机指令；所述第一物理核心提取***启动最小资源集，以及当前用户进程地址和路径，并拷贝至所述第一内置内存中；所述第一物理核心通知所述主CPU进行强制进程关闭，并通知所述电源管理芯片关闭***电源。
根据本发明的再一个实施例，还提供了一种基于上述实施例的***的开机方法，该方法包括：所述第一物理核心接收***开机指令；所述第一物理核心将所述第一内置内存中保存的***启动最小资源集拷贝至所述主内存中；所述第一物理核心将***控制权转交至所述主CPU。
根据本发明的再一个实施例，还提供了一种基于上述实施例的***的***恢复方法，该方法包括：所述第一物理核心接收恢复到上次关机前状态指令；所述第一物理核心将所述第一内置内存中保存的开机指令拷贝到所述主内存以启动***；所述第一物理核心将所述第一内置内存中保存的关机前内存镜像拷贝到所述主内存，所述第一物理核心将***控制权转交至所述主CPU。
根据本发明的再一个实施例，还提供了一种基于上述实施例所述***的***崩溃恢复方法，该方法包括：检查所述第一定时器和所述第二定时器是否超时；如果所述第一定时器超时，所述第二定时器不超时，则复位所述主CPU以及除所述第一物理核心外的其它物理核心；如果所述第二定时器超时，复位所述第一物理核心。
根据本发明的再一个实施例，还提供了一种基于上述实施例所述***的***设备管理方法，该方法包括：判断***是处于正常工作状态还是关机低功耗状态；如果***处于正常工作状态，检查***设备是否存在启动异常和/或检测***设备是否存在温度异常，如果是，则通过可靠性功能模块启动修复程序和/或启动温度保护程序对所述***设备进行修复和/或温度保护。
根据本发明的再一个实施例，还提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是根据本发明实施例的多核芯片结构示意图；
图2是根据本发明实施例的具有该多核芯片的***结构示意图；
图3是根据本发明实施例的电源管理架构示意图；
图4是根据本发明实施例的电源管理方法流程图；
图5是根据本发明实施例的关机方法流程图；
图6是根据本发明可选实施例的开机方法流程图；
图7是根据本发明可选实施例的内存结构示意图；
图8是根据本发明实施例的***现场恢复方法流程图；
图9是根据本发明实施例的***崩溃恢复方法流程图；
图10是根据本发明实施例的***设备可靠性管理方法流程图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本发明实施例所提供的多核芯片、具有该核芯片的***以及基于该***的电源管理方法，快速开机方法以及***恢复方法等
本发明实施例提供了一种多核芯片。本实施例的所提供的多核芯片可以基于现有多核芯片来实现，即，在现有多核芯片的基础上增加相应的功能部件。图1为本实施例的多核芯片结构示意图，如图1所示，在本实施例中，该多核芯片除了包括现有多核芯片所具有的主CPU 10和主内存20外(现有的多核芯片还包括其他部件，在图中未示出)，该多核芯片还包括第一物理核心30、第一内置内存40和电源管理芯片50。
第一物理核心30，用于负责***的关机和启动，在收到***关机指令的情况下，提取***启动最小资源集并保存至第一内置内存40中，并通知所述主CPU 10关闭所述***；在收到***开机指令的情况下，将所述第一内置内存40中的所述***启动最小资源集拷贝至所述主内存20，并将***控制权转交至所述主CPU 10，其中，所述第一物理核心30可工作在第一电压和第二电压状态下，其中，所述第一电压为所述第一物理核心30的正常工作电压，所述第二电压为***关机状态下，所述第一物理核心30的保持电压，所述第一电压大于所述第二电压；
第一内置内存40，用于保存所述***启动最小资源集；
电源管理芯片50，用于通过电压转换实现多级电压的输出，用于在***开机状态下为***提供工作电压，以及在***关机状态下为所述第一物理核心30提供所述第二电压。
在上述实施例中，第一物理核心可以采用复用目前多核芯片架构中的任意一个物理核心，这样可以简化现有芯片设计。当然，第一物理核心也可以采用在目前芯片架构中增加一个专用物理核心来实现。
在上述实施例中，所述第一内置内存可以采用内置小容量、低功耗的RAM，从而提供内存的读写效率。
在上述实施例中，该多核芯片还可以内置可靠性功能模块，该可靠性模块内置通用的可靠性程序，包括设备修复程序、***设备温度保护程序以及低功耗***设备自检程序。该模块可以实现产品***设备管理以及多核芯片崩溃自救。
本发明实施例提供了一种具有上述多核芯片的***，如图2所示，在本实施例中，该多核芯片包括多个物理核心205、多线程206、多级缓存207、高速内置内存208以及内存管理单元209。
其中，在本实施例中，该***还具有***电路，该***电路包括：***总线202、内存RAM 203、外存ROM 204。除此之外整个***还包括电源管理模块210。其中，多核芯片105与内存RAM 103、外存ROM 104通过***总线102连接交互。
在本实施例中，物理核心CORE X是指专门为多核芯片引入的一颗低功耗物理核心，该物理核心既可以采用复用现有多核芯片某个核心实现，也可以重新设计，在现有设计中设计全新的物理核心。本实施例采用单独设计举例。
该物理核心CORE X典型特征包括可以工作在常电压下例如3.6V，也可以工作在低电压下工作，本实施例采用1.8V。该物理核心配置了可以在低电压下工作的高速缓存或者内存RAM0，RAM0用来存放开机***指令集，可选地也可以用来存放当前运行进程地址指针。
考虑目前RAM读写效率远远大于主流FLASH芯片读写效率，例如某主流FLASH芯片参数约为读取200MB/s，写入20MB/s，而主流移动终端LPDDR4RAM读写效率参数约为读取25GB/s，写入10GB/s。可见，RAM读效率约为ROM的100倍，而写效率约为ROM的50倍。因此RAM0理论可以大大缩短开机加载时间，假设传统开机程序加载需要20秒，而使用RAM0仅耗时200ms就可完成加载。效率提升约20s。
该多核芯片各模块功能描述如下：
多核芯片201：其包括多个物理核心CORE 0至CORE X；
***总线202：即连接芯片与***设备、***器件的总线，负责各个芯片与各个内部器件的通信；
主内存203：即，RAM,2203，针对智能设备一般是指memory；
ROM 204：即外存，针对智能设备一般是指FLASH，用来存放各种安装或者可执行文件；
CORE X 205：即物理核心X，该物理核心是一颗低功耗物理核心，主要负责***可靠性算法维护以及性能优化。
多线程206：即Thread X，负责指令并行执行，提高物理核心执行效率。
高速缓存207：即Cache，通常芯片内部可预置多级高速缓存，并且每个物理核心都可配置不同的缓存容量和个数。
内存208：即RAM0，是指专门为物理核心COREX配置的小容量内存，或者高速缓存。
内存管理单元209：即MMU，负责针对***中各个物理内存进行映射和寻址。
电源管理芯片210，可以通过对电压进行转换实现多级电压的输出，从而对***的上述各功能部件提供工作电压。在***关机状态下继续为CORE X 205提供较低的维持电压。
基于上述的多核芯片，本发明还提供了一种电源管理***。在本实施例中，多核芯片中的电源管理芯片可以提供多级电压输出和控制，为保持低功耗物理核心在关机状态达到省电的目的，可以在关机时保持物理核心最低电压供给，从而降低功耗。如图3所示，本实施例中各模块功能描述如下：
电源管理芯片301：该芯片可以提供多种电压输出与转换，并可以编程实现多级电压输出。
物理核心CORE X输入电路302：该电路可以在关机状态继续保持输入，在整个CPU其他核心断电状态下依然保持可变电压供给，满足该CPU物理核心CORE X正常工作。
CPU主输入电路303：为CPU提供正常电流电压输入，保证CPU在开机状态下正常工作。
总线输入电路304：为总线提供电流电压输入，保证***总线正常通信。
RAM输入电路305：为***主内存提供电流电压输入，保证内存正常上电工作。
ROM输入电路306：为***外存提供电流电压输入，保证外存正常上电工作，其他应用进程可以正常读写。
基于前文实施例中的多核芯片，本发明实施例还提供了一种电源管理方法，如图4所示，该电源管理方法包括如下流程：
步骤S401：用户指令输入；
智能设备通常提供***按键或者操作UI进行用户指令输入，例如可提供开机按键，或者不同按键定义不同事件，并且可以提供多种按键组合满足不同指令输入，例如快速开机为按键1，恢复到上次关机前状态为按键1+按键3等。
判断C401：是否为开机指令；
按键指令输入后，通常电源管理芯片可以直接判定当前是否开开机或者关机指令，或者其他指令，如果是开机指令则执行步骤S302；否者执行判断C402。
步骤S402：为CPU或者***RAM以及电路供电；
如果当前输入为开机指令，则电源管理芯片开始为***CPU、RAM、ROM等提供电源输入，保证智能设备物理器件正常工作电压。
步骤S403：调节物理核心CORE X为正常供电电压；
与此同时，电源管理芯片切换电压开关，保证物理核心CORE X在正常电压正常工作。
判断C402：判断是否为关机指令；
如果用户输入为关机指令，则执行步骤S404；否则执行步骤406，异常处理，通常采用忽略不处理按按键指令。
步骤S404：切断CPU主路电源、RAM与ROM等***电路电源；
关机时，电源管理芯片切断CPU主电源输入，以及RAM，ROM，总线等***电路电源输入，保证关机状态下物理核心CORE X以低耗电工作，且仅只有物理核心CORE X工作。
步骤S405：调节物理核心CORE X为1.8v低电压工作状态；
电源管理芯片切换物理核心电压为1.8v低功耗工作状态。
步骤S406：异常处理；
用户按键为开关机按键，但是按键时间不满足或者其他条件不满足，电源管理芯片无法判断为开机或者关机指令，则忽略该按键指令，不做任何处理。
步骤S407：结束；
本发明实施例还提供了一种多核芯片关机方法，如图5所示，该关机方法包括如下流程：
步骤S501：POWER OFF；
***检测用户输入为关机指令。
步骤S502：电源管理芯片收到关机指令；
电源管理芯片检测为关机指令。
步骤S503：通知物理核心CORE X关机消息；
电源管理芯片通知当前CPU物理核心CORE X关机消息，物理核心CORE X负责***开机和关机。
步骤S504：物理核心CORE X统计当前***用户进程信息；
物理核心CORE X从CPU 0获取当前******用户进程信息，包括进程ID，进程入口地址，进程名和进程路径等信息，同时区分当前进程为***进程或者用户进程，尤其针对当前***运行进程，需要标识当前运行进程，可选的可以用于***开机恢复上次状态。
步骤S505：CORE X对***进程和用户进程进行分级；
物理核心CORE X对***进程和用户进程分级，用户进程优先级低于***进程，通常简单可以通过***自启动列表判断是否为***进程，非自启动进程都可以认为用户进程。
步骤S506：提取***启动最小资源集；
物理核心CORE X需要提取***启动最小资源集，在***进程中排除外设和通信进程，针对智能设备，通常认为外设进程为非必须进程，通信芯片相关进程为非必须进程。内核态线程为第一优先进程。
步骤S507：物理核心CORE X提取当前用户进程地址和路径，进行压缩加密，然后拷贝到RAM0不同进程镜像区；
物理核心CORE X提取用户进程地址和路径，然后进行压缩加密，保存在RAM0用户进程镜像区。***进程拷贝到***镜像区。
步骤S508：物理核心CORE X通知CORE 0进行强制进程关闭；
物理核心CORE X完成关机前信息记录，通知CORE 0强制关闭***进程，通知电源管理芯片关机。
步骤S509：电源管理芯片关闭CPU，RAM，ROM等***电路电源输入；
电源管理芯片断开CPU，RAM，ROM等***电路电源输入，仅保留CPU物理核心CORE X电源输入，同时调节该物理核心CORE X电压为1.8v，保持该物理核心在低电压下正常工作。
基于前文实施例中的多核芯片架构，本发明实施例提供了一种快速开机方法，如图6所示，该快速开机方法包括如下步骤：
步骤S601：POWER ON；
用户开机，用户按下开机按键。
步骤S602：电源管理芯片收到开机指令；
电源管理芯片检测到用户开机。
步骤S603：CPU，RAM，ROM等***电路上电；
电源管理芯片为CPU，RAM，ROM等***电路供电，保证***物理硬件正常电源输入。
步骤S604：电源管理芯片通知物理核心CORE X开机指令；
电源管理芯片通知CPU物理核心CORE X开机指令。
步骤S605：CORE X拷贝***启动指令集和开机程序到主内存RAM；
物理核心CORE X拷贝***启动指令集和开机程序到主内存RAM，由于RAM0已经在***启动指令区存储了开机需要的BOOT程序和***地址，CORE X拷贝启动信息到主CPU可以大大节约***从 外存拷贝到内存需要时间，并且缩小动态加载程序数量，只优先启动和用户体验相关程序，例如UI，指示灯等影响用户体验的程序。
步骤S606：CORE X复位CPU其他核心转交控制权到CORE 0；
物理核心CORE X负责复位CPU其他物理核心，同时转交***控制权到CORE 0，完成开机过程。
步骤S607：***启动；
此时，***完成启动，对应在智能设备体现为UI准备就绪。
步骤S608：启动外设芯片或者进程；
然后***开始自启动其它低优先级进程或者芯片，例如，在智能手机中通信芯片或者蓝牙芯片或者WIFI芯片启动速度快，而且对用户体验影响弱，则可以在***启动后启动这些***芯片。加速启动过程。
基于前文实施例中的多核芯片架构中的内置小容量内存，本发明实施例还提供了一种内存映射结构，如图7，该内置小容量内存包括：***预留区701、***启动指静态区702、***启动镜像区703和用户进程镜像区704；
下面结合附图对该内存映射结构进行详细说明：
***预留区701：指专门为CORE X预留***区，供CORE X备份自身***数据。
***启动静态区702，用于保存ROM中***启动引导程序和指令集。
***启动镜像区703：指专门保存关机前***关键进程地址和程序数据，供快速开机可以直接拷贝到主内存使用的地址区间。
用户进程镜像区704：指用来保存关机前用户进程地址和程序数据，用来实现快速启动后进程快速加载，可选的可用来实现关机前现场恢复。
基于前文实施例中的多核芯片架构，本发明实施例还提供了一种快速现场恢复方法，如图8所示，该快速现场恢复方法包括如下步骤：
判断C801：是否恢复到上次关机前状态；
步骤S801：正常开机流程；
步骤S802：电源管理芯片为CPU，RAM，ROM等***设备供电；
步骤S803：物理核心CORE X拷贝RAM0中开机指令到主内存；
步骤S804：***启动；
步骤S805：物理核心CORE X拷贝RAM0关机前内存镜像到主内存；
步骤S806：物理核心CORE X转交控制权到CORE 0；
步骤S807：结束；
基于前文实施例中的多核芯片架构，本发明实施例还提供了一种***崩溃恢复方法。在本实施例中，***采用看门狗策略，看门狗是利用一个定时器电路，其定时输出连接到电路的复位端，程序在一定时间范围内对定时器清零(俗称“喂狗”)，因此程序正常工作时，定时器总不能溢出，也就不能产生复位信号。如果程序出现故障，不在定时周期内复位看门狗，就使得看门狗定时器溢出 产生复位信号并重启***。本发明中提出基于物理核心CORE X的双看门狗策略，主CPU采用定时器T1，物理核心CORE X采用定时器T2，T2大于T1，通常采用1.5*T1值长。当T1超时T2未超时，则清空当前进程数据，物理核心CORE X负责拷贝当前主内存中进程地址数据，为提高***效率，本实施只拷贝***关键进程数据，例如网络进程，UI进程等，然后重置CPU，重新加载保存进程地址数据。；只有当定时器T1&T2同时超时，重启***，进入重新快速开机流程。
如图9所示，本实施的***崩溃恢复方法的步骤为：
步骤S901：T1复位；
定时器T1未超时时，复位T1。
判断C901：定时器T1是否超时；
检查主CPU看门狗T1是否超时，如果定时器T1超时，则执行判断C902；否则执行步骤S901。
判断C902：定时器T2是否超时；
检查物理核心CORE X看门狗T2是否超时，如果定时器T2超时，则执行步骤S902；否则执行步骤S806。
步骤S902：复位物理核心CORE X；
T2超时意味着物理核心CORE X可能已经失去响应，此时复位该物理核心。
步骤S903：物理核心CORE X拷贝当前进程外***内存进程镜像到RAM0；
物理核心CORE X拷贝当前***中出当前进程外其他内存进程镜像到RAM0，备份用户进程地址与数据。
步骤S904：重启***；
重启***，电源管理芯片断开CPU，RAM，ROM等电源输入，然后重新启动。
步骤S905：物理核心CORE X加载***RAM0关键进程数据到主内存；
物理核心CORE X拷贝RAM0中关机数据到主内存，最大限度恢复***崩溃前状态。
步骤S906：清除当前CPU执行进程数据和进程；
物理核心CORE X清除CORE 0到CORE N所有寄存器缓存数据。
步骤S907：复位其他CPU核心；
物理核心CORE X复位主CPU电路。
步骤S908：保持待机状态，即，***保持待机正常运行状态。
基于前文实施例中的多核芯片架构，本发明实施例还提供了一种***设备可靠性管理方法。在本实施例中，通过内置的可靠性模块可以在正常工作模式下与低功耗关机模式下，动态检查***设备运行状态，或者检查设备是否出现异常并尝试修复。
在本实施例中，该可靠性模块可内置***设备修复程序、***设备温度保护程序以及低功耗***设备自检程序，通过通用的可靠性程序，包括设备修复程序、***设备温度保护程序以及低功耗***设备自检程序，该模块可以实现***设备可靠性检查算法，并在低功耗下对***设备进行控制。
本实施中***设备包括不限于：内存、FLASH、指示灯、屏幕、蓝牙，WIFI以及通信模组等。
如图10所示，该***设备可靠性管理方法包括如下步骤：
判断S1001：是否处于关机低功耗状态；
判断当时多核芯片是处于正常工作状态还是已经关机进入低功耗状态，如果处于正常工作状态，执行判断S1002；如果处于非正常工作状态，即关机低功耗状态，则执行判断S1004。
判断S1002：检查***设备是否存在启动异常；
判断当前***设备是否存在启动异常，如果存在启动异常，则执行步骤S1003，进行尝试修复；否则执行判断S1004。
步骤S1003：启动修复程序；
执行修复程序，尝试重新启动***设备，或者重新加载***设备。
判断S1004：检查***设备工作温度是否异常；
判断检查***设备工作温度是否正常，如果工作温度异常，则执行步骤S1005；否则执行步骤S1009。
步骤S1005：启动温度保护程序；
执行温度保护程序，执行内置的温度保护程序，例如常用控制速率，控制工作频率等方式。
步骤S1006：启动***设备自检程序；
启动***设备自检程序，检查***设备工作日志中存在的异常。
判断S1007：检查***设备是否异常；
判断检查***设备是否存在异常，如果存在则执行步骤S1008；否则执行步骤S1009。
步骤S1008：启动修复程序；
启动修复程序，尝试修复***设备运行中的异常，根据异常日志中异常分类，启用不用修复方法。
判断S1009：判断***设备是否需要高可靠性保护；
判断***设备是否需要高可靠性保护，如果是的话执行S1010；否则执行S1011。
步骤S1010：加入高可靠性保护列表；
对该***设备或者应用进行高可靠性保护。
步骤S1011：结束。
本发明还提供了一种存储介质，该存储介质中存储有计算机程序，其中，该计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
在本发明的上述实施例中，在多核芯片中引入一个低功耗物理核心和电源管理芯片，通过电源管理芯片对多核芯片进行分级电压电源控制，使得该低功耗物理核心在整机关机断电条件下仍可正常工作，该物理核心通过内置小容量内存保存开机必要指令集，因此收到开机指令时，该物理核心通过内存映射拷贝到主内存中，从而可以大大缩短开机时间。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来 实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (20)

  1. 一种多核芯片，包括主CPU和主内存，其中还包括：
    第一物理核心，用于负责***的关机和启动，在收到***关机指令的情况下，提取***启动最小资源集并保存至第一内置内存中，并通知所述主CPU关闭所述***；在收到***开机指令的情况下，将所述第一内置内存中的所述***启动最小资源集拷贝至所述主内存，并将***控制权转交至所述主CPU，其中，所述第一物理核心可工作在第一电压和第二电压状态下，其中，所述第一电压为所述第一物理核心的正常工作电压，所述第二电压为***关机状态下，所述第一物理核心的保持电压，所述第一电压大于所述第二电压；
    第一内置内存，用于保存所述***启动最小资源集；
    电源管理芯片，用于通过电压转换实现多级电压的输出，用于在***开机状态下为***提供工作电压，以及在***关机状态下为所述第一物理核心提供所述第二电压。
  2. 根据权利要求1所述的多核芯片，其中，
    所述第一物理核心，还用于在***关机时，拷贝所述主CPU运行进程数据到所述第一内置内存，在下次开机启动时，根据第一内置内存中所保存的主CPU运行进程数据将***恢复至***关机前运行状态。
  3. 根据权利要求1所述的多核芯片，其中所述多核芯片还包括多个物理核心、与所述多个物理核心对应的多线程和多级缓存、对***中的各个物理内存进行映射和寻址的内存管理单元MMU、***电路，其中所述***电路包括以下至少之一：***总线、主内存、外存。
  4. 根据权利要求1所述的多核芯片，其中还包括：
    第一物理核心输入电路，用于在***开机状态下，将所述电源管理芯片提供的所述第一电压输入至所述第一物理核心，以及在***关机状态下，将所述电源管理芯片提供的所述第二电压输入至所述第一物理核心；
    主CPU输入电路，用于将所述电源管理芯片提供的主CPU工作电压输入至所述主CPU；
    ***总线输入电路，用于将所述电源管理芯片提供的***总线工作电压输入至所述***总线；
    主内存输入电路，用于将所述电源管理芯片提供的主内存工作电压输入至所述主内存。
  5. 根据权利要求1所述的多核芯片，其中所述第一内置内存包括：
    ***预留区，为所述第一物理核心的预留***区，用于所述第一物理核心备份自身***数据；
    ***启动静态区，用于保存***启动引导程序和***启动指令集；
    ***启动镜像区，用于保存关机前***进程地址和程序数据；
    用户进程镜像区，用于保存关机前用户进程地址和程序数据。
  6. 根据权利要求1所述的多核芯片，其中还包括：
    看门狗电路，包括第一定时器和第二定时器，其中，所述第一定时器用于所述主CPU的复位，所述第二定时器用于所述第一物理核心的复位，所述第二定时器的值长大于所述第二定时器。
  7. 根据权利要求1所述的多核芯片，其中还包括可靠性功能模块，所述可靠性功能模块用于***设备的修复和检测，所述可靠性功能模块包括以下至少之一：用于***设备的程序修复的修复单元、用于***设备的温度保护的保护单元、用于***设备的自检的自检单元。
  8. 一种电子***，包括***设备以及权利要求1至7中任一项所述的多核芯片。
  9. 一种基于权利要求8所述的***的电源管理方法，其中包括：
    当所述电源管理芯片接收到***开机指令时，为***各部件提供正常工作电压，并将所述第一物理核心的电压从所述第二电压调节至所述第一电压；
    当所述电源管理芯片接收到***关机指令时，切断***各部件的电压，对所述第一物理核心继续供电，并将所述第一物理核心的电压从所述第一电压调节至所述第二电压。
  10. 一种基于权利要求8所述的***的关机方法，其中包括：
    所述第一物理核心关机接收***关机指令；
    所述第一物理核心提取***启动最小资源集，以及当前用户进程地址和路径，并拷贝至所述第一内置内存中；
    所述第一物理核心通知所述主CPU进行强制进程关闭，并通知所述电源管理芯片关闭***电源。
  11. 根据权利要求10所述的关机方法，其中所述第一物理核心通知所述电源管理芯片关闭***电源之后，还包括：
    所述电源管理芯片切断***各部件的电压，对所述第一物理核心继续供电，并将所述第一物理核心的电压从所述第一电压调节至所述第二电压。
  12. 一种基于权利要求8所述的***的开机方法，其中包括：
    所述第一物理核心接收***开机指令；
    所述第一物理核心将所述第一内置内存中保存的***启动最小资源集拷贝至所述主内存中；
    所述第一物理核心将***控制权转交至所述主CPU。
  13. 根据权利要求12所述的开机方法，其中在所述第一物理核心接收开机指令之前，还包括：
    所述电源管理芯片接收到所述***开机指令后，为***各部件提供正常工作电压，并将所述第一物理核心的电压从所述第二电压调节至所述第一电压；
    所述电源管理芯片将所述***开机指令通知所述第一物理核心。
  14. 一种基于权利要求8所述***的***恢复方法，其中包括：
    所述第一物理核心接收恢复到上次关机前状态指令；
    所述第一物理核心将所述第一内置内存中保存的开机指令拷贝到所述主内存以启动***；
    所述第一物理核心将所述第一内置内存中保存的关机前内存镜像拷贝到所述主内存，所述第一物理核心将***控制权转交至所述主CPU。
  15. 一种基于权利要求8所述***的***崩溃恢复方法，其中包括：
    检查所述第一定时器和所述第二定时器是否超时；
    如果所述第一定时器超时，所述第二定时器不超时，则复位所述主CPU以及除所述第一物理核心外的其它物理核心；
    如果所述第二定时器超时，复位所述第一物理核心。
  16. 根据权利要求15所述的***崩溃方法，其中在复位所述第一物理核心之后，还包括：
    所述第一物理核心拷贝当前进程外的***内存进程镜像到所述第一内置内存；
    所述重启***，所述第一物理核心将所述第一内置内存中保存的***内存进程镜像加载到所述 主内存；
    所述第一物理核心复位所述主CPU以及除所述第一物理核心之外的其他物理核心。
  17. 一种基于权利要求8所述的***的***设备管理方法，其中包括：
    判断***是处于正常工作状态还是关机低功耗状态；
    如果***处于正常工作状态，检查***设备是否存在启动异常和/或检测***设备是否存在温度异常，如果是，则通过可靠性功能模块启动修复程序和/或启动温度保护程序对所述***设备进行修复和/或温度保护。
  18. 根据权利要求17所述的***设备管理方法，其中，
    如果***处于关机低功耗状态，则启动***设备自检程序检查***设备是否异常；
    如果所述***设备存在异常，则启动修复程序对所述***设备进行修复。
  19. 根据权利要求18所述的***设备管理方法，其中还进一步包括：
    判断***设备是否需要高可靠性保护，如果是，则将所述***设备加入至高可靠性保护列表。
  20. 一种存储介质，其中所述存储介质中存储有计算机程序，其中所述计算机程序被设置为运行时执行所述权利要求9-19中任一项所述的方法。
PCT/CN2019/112684 2018-11-06 2019-10-23 多核芯片、***，及其方法和存储介质 WO2020093868A1 (zh)

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CN109614153B (zh) * 2018-11-06 2021-01-26 西安中兴新软件有限责任公司 多核芯片及***
CN110232030B (zh) * 2019-06-12 2021-08-10 上海兆芯集成电路有限公司 多芯片***及缓存处理方法
CN115104084A (zh) * 2020-02-24 2022-09-23 华为技术有限公司 存储器、芯片及存储器的修复信息的保存方法
CN117931529A (zh) * 2024-03-21 2024-04-26 上海励驰半导体有限公司 启动管理方法和设备、电子设备及存储介质

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