WO2020060487A1

WO2020060487A1 - Solar cell and method for fabricating a solar cell

Info

Publication number: WO2020060487A1
Application number: PCT/SG2019/050464
Authority: WO
Inventors: Zhipeng LING; Rolf Stangl; Puqun WANG
Original assignee: National University Of Singapore
Priority date: 2018-09-17
Filing date: 2019-09-17
Publication date: 2020-03-26

Abstract

A solar cell (200) is described. In a described embodiment, the solar cell (200) comprises a silicon wafer (206) having a front side arranged to receive incident light and a rear side. The solar cell (200) comprises: a front-side dielectric tunnel layer (204) formed on the front side of the silicon wafer (206); a front-side doped semiconductor layer (202) deposited on the front-side dielectric tunnel layer (204), the front-side doped semiconductor layer (202) and the front-side dielectric tunnel layer (204) forming a conductive contact passivation layer stack arranged to contact a top solar cell to form a tandem solar cell and to allow the incident light to pass through to the silicon wafer (206), the conductive contact passivation layer stack having a thickness of less than 20 nm.

Description

Solar cell and Method for fabricating a solar cell

Technical Field

The present disclosure relates to a solar cell and also a method for fabricating a solar cell, in particular, a solar cell for a tandem solar cell structure. Preferably, the solar cell of the present disclosure relates to a wafer based bottom solar cell for a tandem solar cell structure.

Background

The photovoltaic market is currently dominated by wafer based, crystalline silicon (Si) solar cells. These single junction Si solar cells, however, are reaching their theoretical Auger efficiency limit of 29%, with a current efficiency record of 26.6%. One promising approach to overcoming this single junction limit is to deposit a thin-film solar cell with a larger bandgap than Si on top of a Si solar cell, thereby forming a two-terminal thin-film on silicon tandem solar cell with feasible efficiencies of more than 30%. The two-terminal thin-film on Si tandem solar cell typically includes two solar cells having different bandgaps being stacked together, with a top thin-film solar cell absorbing and converting a high energy range of the solar spectrum (i.e. blue and green light) and a bottom Si solar cell absorbing and converting a transmitted lower energy range of the solar spectrum (i.e. red and infrared light). Perovskite thin-film solar cells are very promising candidates for use in the aforementioned thin-film on Si tandem integration due to (1) their high power conversion efficiency (up to 22.7% at the single junction level), (2) their sharp optical absorption edge, and (3) their tuneable bandgap which lies in an ideal range for Si based tandem devices. By depositing a thin-film perovskite solar cell on top of a Si solar cell, a tandem solar cell efficiency of more than 30% is feasible at reasonable production costs.

However, current standard high-efficiency perovskite processing technology typically involves spin coating which requires a planar surface to process on. Moreover, this planar surface should be passivating the Si wafer of the Si solar cell, conductive and exhibiting low infrared parasitic absorption if it is to be device integrated into the two- terminal perovskite thin-film on silicon tandem solar cell. It is therefore desirable to provide method for fabricating a solar cell and a solar cell which address the problems of the prior art and/or provides the public with a useful alternative.

Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.

Summary

Aspects of the present application relate to a method for fabricating a solar cell in a tandem solar cell structure and the solar cell thereof.

In accordance with a first aspect, there is provided a solar cell comprising a silicon wafer having a front side arranged to receive incident light and a rear side, the solar cell comprising:

a front-side dielectric tunnel layer on the front side of the silicon wafer; and a front-side doped semiconductor layer on the front-side dielectric tunnel layer; wherein the front-side doped semiconductor layer and the front-side dielectric tunnel layer form a conductive contact passivation layer stack arranged to contact a top solar cell to form a tandem solar cell and to allow the incident light to pass through to the silicon wafer, the conductive contact passivation layer stack having a thickness of less than 20 nm.

Thus, the described embodiment provides a solar cell in a tandem solar cell structure. In particular, the solar cell comprises a conductive contact passivation layer stack arranged to contact a top solar cell to form a tandem solar cell which has a thickness of less than 20 nm. The ultra-thin thickness of 20 nm of the conductive contact passivation layer stack significantly decreases front-side parasitic absorption, thus enhancing a short-circuit current of the solar cell and thereby improving an efficiency of the two-terminal tandem solar cell.

The solar cell may comprise a rear-side dielectric tunnel a rear-side dielectric tunnel layer on the rear side of the silicon wafer, and a rear-side doped semiconductor layer on the rear-side dielectric tunnel layer, the rear-side doped semiconductor layer having an opposite polarity to the front-side doped semiconductor layer. The solar cell may comprise multiple layers of alternating materials with varying refractive indices on the rear-side doped semiconductor layer to form a non-conductive distributed Bragg reflector.

The multiple layers of alternating materials may comprise alternating layers of silicon oxide and silicon nitride, or alternating layers of aluminium oxide and silicon nitride.

The solar cell may comprise rear-side contact openings penetrating the non-conductive distributed Bragg reflector formed using femtosecond laser ablation.

The solar cell may comprise a rear contact layer formed on the non-conductive distributed Bragg reflector to form a rear-side contact, the rear-side contact being in electrical contact with the rear-side doped semiconductor layer via the rear-side contact openings.

The solar cell may comprise a p-type emitter region formed at the front side of the silicon wafer.

The rear side of the silicon wafer may comprise a textured surface.

The front-side dielectric tunnel layer may comprise a silicon oxide or an aluminium oxide.

In accordance with a second aspect, there is provided a method for fabricating a solar cell, the solar cell comprising a silicon wafer having a front side arranged to receive incident light and a rear side, the method comprising:

forming a front-side dielectric tunnel layer on the front side of the silicon wafer; depositing an initial doped semiconductor layer on the front-side dielectric tunnel layer, the initial doped semiconductor layer having an initial thickness; and

etching the initial doped semiconductor layer to form a front-side doped semiconductor layer having a thickness less than the initial thickness, the front-side doped semiconductor layer and the front-side dielectric tunnel layer forming a conductive contact passivation layer stack arranged to contact a top solar cell to form a tandem solar cell and to allow the incident light to pass through to the silicon wafer.

Thus, the described embodiment provides a method for fabricating a solar cell in a tandem solar cell structure. In particular, the method comprises forming a front-side dielectric tunnel layer followed by depositing an initial doped semiconductor layer with an initial thickness on the front-side oxide layer on a front side (or a top-side) of a silicon wafer of the solar cell, and etching the initial doped semiconductor to form a front-side doped semiconductor layer having a thickness less than the initial thickness, where the front-side doped semiconductor layer and the front-side dielectric tunnel layer form a conductive contact passivation layer stack which is arranged to contact a top solar cell to form a tandem solar cell and to allow the incident light to pass through to the silicon wafer. The process of etching the initial doped semiconductor provides a means to allow for a controlled thinning down of the initial doped semiconductor layer to form an ultra- thin front-side doped semiconductor layer, thereby advantageously enabling an ultra-thin (e.g. less than 20 nm) contact passivation layer stack to be formed on the front side of the silicon wafer for further two-terminal tandem solar cell integration. Formation of the ultra-thin front-side contact passivation layer stack significantly decreases front-side parasitic absorption, thereby improving an efficiency of the two-terminal tandem solar cell.

The method may comprise forming a rear-side dielectric tunnel layer on the rear side of the silicon wafer and depositing a rear-side doped semiconductor layer on the rear-side dielectric tunnel layer, the rear-side doped semiconductor layer having an opposite polarity to the front-side doped semiconductor layer.

The method may comprise depositing multiple layers of alternating materials with varying refractive indices on the rear-side doped semiconductor layer to form a non-conductive distributed Bragg reflector.

The step of depositing multiple layers of alternating materials may comprise depositing alternating layers of silicon oxide and silicon nitride, or depositing alternating layers of aluminium oxide and silicon nitride.

The method may comprise ablating a portion of the non-conductive distributed Bragg reflector using a femtosecond laser to provide rear-side contact openings penetrating the non-conductive distributed Bragg reflector for contacting the rear-side doped semiconductor layer.

The method may comprise depositing a rear contact layer on the non-conductive distributed Bragg reflector (DBR) to form a rear-side contact, the rear-side contact being in electrical contact with the rear-side doped semiconductor layer via the rear-side contact openings. This advantageously maximises internal rear-side reflection in the infrared spectrum of the incident light in the solar cell, thereby enhances a short-circuit current in the solar cell and improving its efficiency.

The initial doped semiconductor layer may comprise a p-doped polysilicon layer, and the etching step may include etching the p-doped polysilicon layer with a mixture of potassium hydroxide, sodium hypochlorite and deionised water.

The method may comprise doping a front surface of the silicon wafer with a p-type dopant to form an emitter region at the front side of the silicon wafer.

The initial doped semiconductor layer may comprise an n-doped polysilicon layer, and the etching step may include etching the n-doped polysilicon layer with sodium hypochlorite.

The method may comprise etching the rear side of the silicon wafer to form a textured surface.

The step of forming the front-side dielectric tunnel layer on the front side of the silicon wafer may comprise atomic-layer depositing an aluminium oxide or wet oxidising the front side of the silicon wafer to form silicon oxide.

The conductive contact passivation layer stack may have a thickness of less than 20 nm.

The method may comprise forming the top solar cell on the front side of the silicon wafer to form a two-terminal tandem solar cell.

In accordance with a third aspect, there is provided a tandem solar cell comprising: a top solar cell; and

a bottom solar cell, wherein the bottom solar cell comprises a silicon wafer having a front side arranged to receive incident light via the top solar cell and a rear side, the bottom solar cell comprising:

a front-side dielectric tunnel layer on the front side of the silicon wafer; and

a front-side doped semiconductor layer on the front-side dielectric tunnel layer;

wherein the front-side doped semiconductor layer and the front-side dielectric tunnel layer form a conductive contact passivation layer stack arranged to contact the top solar cell and to allow the incident light from the top solar cell to pass through to the silicon wafer of the bottom solar cell, the conductive contact passivation layer stack having a thickness of less than 20 nm.

Thus, the described embodiment provides a tandem solar cell. In particular, the tandem solar cell comprises a bottom solar cell where the bottom solar cell includes a conductive contact passivation layer stack arranged to contact a top solar cell to form a tandem solar cell which has a thickness of less than 20 nm. The ultra-thin thickness of 20 nm of the conductive contact passivation layer stack significantly decreases front-side parasitic absorption, thus enhancing a short-circuit current of the bottom solar cell and thereby improving an efficiency of the two-terminal tandem solar cell.

The top solar cell and the bottom solar cell may be integrated to form a two-terminal tandem solar cell structure.

It should be appreciated features relating to one aspect may be applicable for the other aspects. Embodiments therefore provide a method for fabricating a solar cell in a tandem solar cell structure and the solar cell thereof. The controlled thinning down of the initial doped semiconductor layer by etching advantageously forms an ultra-thin front-side doped semiconductor layer, thereby allowing an ultra-thin contact passivation layer stack to be formed on a front side of the Si wafer for further two-terminal tandem solar cell integration. Formation of the ultra-thin front-side contact passivation layer stack significantly decreases front-side parasitic absorption, thereby improving an efficiency of the two-terminal tandem solar cell. Moreover, a non-conductive distributed Bragg reflector (DBR) deposited on a rear-side contact passivation layer stack at the rear side of the Si wafer significantly enhances a rear-side internal back- reflection in the infrared region of the transmitted light. This enhances absorption of the infra-red light in the bottom Si solar cell to improve the solar cell’s efficiency. This is particularly true for the present embodiment since the deployment of a (non-conductive) DBR stack on top of a conventional conductive rear-side contact passivation layer stack provides a means to significantly enhance internal rear-reflection and thus short-circuit current as compared to conventional formed screen printed contacts applied on conventional rear-side contact passivation layers (i.e. comparing the“conventional rear-side contact passivation system” a rear-side SiO_x-tunnel-layer/poly-Si-capping-layer/SiN_x-passivation-layer stack, which is subsequently metal screen printed and fired through by a metal grid, i.e. the metal grid fingers interpenetrate the SiN_x and form a contact to the poly-Si, to the“newly proposed rear-side contact passivation system”, i.e. a rear-side SiO_x-tunnel-layer/poly-Si-capping- layer/insulating-DBR-layer stack, which is subsequently point-like laser opened and then metal screen printed or full-area sputtered or full-area evaporated in order to form a metal contact to the poly-Si, i.e. the metal contacts the poly-Si only by the point-like openings). Furthermore, deploying an insulating DBR stack instead of a conductive DBR stack enables a significantly decreased infra-red absorption of the transmitted light. Further, use of femtosecond laser ablation of a portion of the non-conductive DBR to form rear- side contact openings advantageously provides for localised damage-free contact openings without affecting a minority carrier lifetime of the rear-side contact passivation, thereby further enhancing a performance of the fabricated solar cell.

Brief description of the drawings

Embodiments will now be described, by way of example only, with reference to the following drawings, in which:

Figure 1 is a flowchart showing steps of a method for fabricating a solar cell in a tandem solar cell structure in accordance with an embodiment;

Figure 2 is a schematic structure of the solar cell fabricated using the method of Figure

1 ;

Figures 3A, 3B and 3C illustrate experimental findings of a passivation quality of a SiO_x/n⁺ poly-Si passivated contact, where Figure 3A is a schematic structure of the SiO_x/ n⁺ poly-Si passivated contact being investigated, Figure 3B is a graph of minority carrier lifetime as a function of the n⁺ poly-Si capping layer’s thickness, and Figure 3C is a graph of implied open-circuit voltage at 1 sun (i.e. 1 kW/m²) illumination intensity as a function of the n⁺ poly-Si capping layer’s thickness;

Figures 4A, 4B and 4C illustrate experimental findings of a passivation quality of a SiO_x/p⁺ poly-Si passivated contact in comparison to the SiO_x/n⁺ poly-Si passivated contact of Figure 3, where Figure 4A is a schematic structure of the SiO_x/p⁺ poly-Si passivated contact being investigated, Figure 4B is a graph of minority carrier lifetime as a function of poly-Si capping layer thickness, and Figure 4C is a graph of implied open- circuit voltage at 1 sun (i.e. 1 kW/m²) illumination intensity as a function of the poly-Si capping layer thickness. Using an etch-back technology, the p-doped poly-Si capping layer may be reduced to a thickness of ~3 nm only, while maintaining high lifetime, whereas for n-doped poly-Si capping layers the lifetime breaks down at a reduced poly- Si thickness of approximately ~70 nm;

Figures 5A, 5B and 5C illustrate experimental findings of a passivation quality of a SiO_x/n⁺ poly-Si passivated contact on a textured surface, where Figure 5A is a schematic structure of the SiO_x/n⁺ poly-Si passivated contact being tested, Figure 5B is a graph of minority carrier lifetime as a function of silicon slow etch (SSE) time (or etch-back time), and Figure 5C is a graph of implied open-circuit voltage at 1 sun illumination intensity (i.e. 1 kW/m²) as a function of the SSE time;

Figures 6A, 6B, 6C and 6D shows experimental findings of a double-sided contact passivated silicon bottom cell pre-cursor, where Figures 6A and 6B are schematic structures of the double-sided contact passivated silicon bottom cell pre-cursor with- and without- additional layers of SiN_x respectively, Figure 6C is a graph of minority carrier lifetime as a function of minority carrier density for each of the structures of Figures 6A and 6B, and Figure 6D is a graph of illumination intensity as a function of implied open- circuit voltage for each of the structures of Figures 6A and 6B;

Figures 7A and 7B show numerical calculations for optimising a distributed Bragg reflector (DBR) comprising alternating layers of SiO_x and SiN_x on a planar rear-surface of an n-type planar Si wafer, where Figure 7 A is a schematic structure of the DBR stack used in the numerical calculations and Figure 7B is a graph of calculated reflectance of the DBR stack as a function of a wavelength of the reflected light for 1 to 10 alternating layers of the DBR stack;

Figures 8A and Figure 8B show calculated and measured reflectance of a planar Si wafer with a distributed Bragg reflector (DBR) comprising alternating layers of SiO_x and SiN_x, where Figure 8A is a graph of reflectance of the DBR stack as a function of a wavelength of the reflected light for 1 to 3 layers of the DBR stack, and Figure 8B is a graph of peak reflectance as a function of the number of layers of the DBR stack;

Figure 9 shows a flowchart of a method for investigating enhanced internal IR back- reflection of a rear-side contact using expected current gains for different solar cell architectures;

Figures 10A, 10B and 10C show three different solar cell architectures used in the investigation of enhanced internal IR back-reflection using the method of Figure 9, where Figure 10A shows a“conventional” rear-side heterojunction contact, Figure 10B shows a “conventional” rear-side contact-passivation contact with the rear-side passivated contact being SiN_x passivated and contacted by metal screen printing, i.e. NOT using a DBR stack, and Figure 10C shows the proposed rear-side contact-passivation contact using a DBR stack (being point-like laser opened and contacted by metal screen printing or full-area sputtering or full-area evaporation), for a one-layer, two-layer, three-layer or a four-layer DBR stack;

Figures 11 A, 11 B and 11C show graphs of calculated expected current gains for the architectures as shown in Figures 10A, 10B and 10C, where Figure 11A shows a graph of correspondingly absorbed photocurrent within the Si wafer, Figure 11 B shows a graph of parasitically absorbed photocurrent in all other layers (except the Si wafer), and Figure 1 1C shows a graph of photocurrent for the escaped photons (i.e. photons which enter the Si wafer but escaping it from its front-side);

Figures 12A and 12B show charts of optical analysis comparing an ability to trap light between a double-sided textured solar cell architecture (“Front-textured”; see Figure 12A) and a rear-side only textured solar cell architecture (“Front-planar”; see Figure 12B), where each of these architectures comprises a front- and a rear-side passivated contact, and a rear-side three-layer DBR stack on the rear-side passivated contact (note that the “front-planar” solar cell architecture is similar to that shown in Figure 10C);

Figures 13A, 13B, 13C, 13D, 13E and 13F show cell structures of a SiO_x/poly-Si contact passivated test-sample with a rear-side AIO_x/SiN_x passivation layer stack and their corresponding photoluminescence (PL) images at different stages of contact openings formation using local femtosecond laser ablation, where Figures 13A and 13B show the structure and its corresponding PL image before femtosecond laser ablation, Figures 13C and 13D show the structure and its corresponding PL image after femtosecond laser ablation, and Figures 13E and 13F show the structure and its corresponding PL image after rear-side metallisation by thermal evaporation (note that all PL images shown have the same intensity scale);

Figures 14A, 14B, 14C and 14D show PL images (see Figures 14A and 14B) and optical microscope images (see Figures 14C and 14D) of double-sided SiO_x/poly-Si/SiN_x contact passivated test-samples, fabricated using a textured wafer (see Figures 14A and 14C) or a planar wafer (see Figures 14B and 14D), which have been locally femtosecond laser ablated;

Figure 15 shows a schematic structure of a front- and rear-side contact-passivated Si- wafer-based bottom solar cell for tandem application which deploys an additional front side p-diffused wafer surface in order to support a formation of an emitter region of the bottom solar cell in accordance with an alternative embodiment;

Figure 16 shows a schematic structure of a front- and rear-side contact-passivated silicon-wafer-based bottom solar cell for tandem application similar to the solar cell structure of Figure 2 but deploys a front-side n⁺ poly-Si capping layer and a rear-side p⁺ poly-Si layer in accordance with an alternative embodiment;

Figure 17 shows a schematic structure of a front- and rear-side contact-passivated silicon-wafer-based bottom solar cell for tandem application similar to the solar cell structure of Figure 16 but with an additional rear-side p-diffused wafer surface in accordance with an alternative embodiment; and

Figure 18 shows a schematic structure of a two-terminal tandem solar cell which has a bottom Si solar cell structure as shown in Figure 2.

Detailed description

An exemplary embodiment relates to a method for fabricating a solar cell, in particular, a wafer based bottom solar cell for a tandem solar cell structure, and the solar cell thereof.

Figure 1 shows a flowchart showing steps of a method 100 for fabricating a solar cell in a tandem solar cell structure in accordance with an embodiment. In this embodiment, an n-type monocrystalline silicon (Si) wafer is used as a starting substrate for fabricating the solar cell. As would be appreciated by the skilled person in the art, preparatory steps (e.g. cleaning the Si wafer surface) may be necessary before each fabrication step, and these preparatory steps have been omitted for clarity and succinctness of the present method 100.

In a step 102, a front-side dielectric layer is formed on a front side of the Si wafer. Here, a front side of the Si wafer or the solar cell refers to the side or surface which receives incident light. A rear side of the Si wafer refers to an opposite side to the front side, and in this case, is the side where a rear-side contact is formed. The front-side dielectric layer functions as a tunnel layer and forms part of the contact passivation for the solar cell. The dielectric layer can be formed either by atomic layer depositing an ultra-thin aluminium oxide (AIO_x or SiN_x or TiO_x layer or by wet-chemical or thermal or ozone- enhanced oxidation of the Si wafer surface, which forms a silicon oxide (SiO_x) layer. A thickness of the front-side dielectric tunnel layer formed by either of these ways can be controlled and can therefore be ultra-thin (e.g. less than a few nanometres thick). The front-side dielectric tunnel layer formed may have a high negative or a high positive interface charge density.

In a step 104, an initial doped semiconductor layer having an initial thickness is deposited on the front-side dielectric tunnel layer at the front side of the Si wafer. In this embodiment, the initial doped semiconductor layer is a highly doped p⁺ polysilicon layer (e.g. boron- doped). Although a highly doped p⁺ polysilicon (poly-Si) layer is used in this embodiment, the initial doped semiconductor layer can also be a highly doped n⁺ poly-Si layer or a layer with a high or a low work-function. The initial doped semiconductor layer can be formed with an initial thickness of tens of nanometres (e.g. 50 nm to 200 nm), for example by using conventional methods such as low pressure chemical vapour deposition (LPCVD) or plasma enhanced chemical vapour deposition (PECVD). In forming the initial doped semiconductor layer using the LPCVD or the PECVD process, either intrinsic Si or doped Si can be deposited. If the initially deposited Si comprises intrinsic Si, this initial Si layer receives a subsequent high-temperature diffusion process to form the initial doped semiconductor layer. The high-temperature diffusion process not only doped the initial intrinsic Si layer, but also sintered this initial intrinsic Si layer so as to transform the intrinsic Si layer to a doped poly-Si layer. If the initially deposited Si comprises doped Si, the deposited doped Si will receive a high-temperature annealing step to transform the doped thin-film-Si to a doped poly-Si layer. In any of these two cases, the initial doped semiconductor layer comprising a doped poly-Si layer is formed.

In a step 106, the initial doped semiconductor is etched to form a front-side doped semiconductor layer having a thickness less than the initial thickness. The front-side doped semiconductor layer constitutes a“capping layer” and together with the front-side dielectric tunnel layer (i.e. the“tunnel layer”) forms a conductive contact passivation layer stack on the front side of the Si wafer (i.e. a front-side contact passivation layer stack). By etching initial doped semiconductor to form an ultra-thin front-side doped semiconductor layer, an ultra-thin front-side contact passivation layer stack of up to a few nanometres thick can be obtained. The front-side contact passivation layer stack, in a variation, may be of a thickness of preferably less than 20 nm, up to 10 nm or up to 5 nm or up to 3 nm. In particular, it has been found that if the front-side passivation layer stack is >= 20 nm (i.e. more than or equal to 20 nm), this may not deliver high current to the Si wafer due to too high parasitic absorption.

In the present embodiment, the etchant used to etch down the highly boron-doped p⁺ poly-Si layer comprises an etch mixture of potassium hydroxide (KOH), sodium hypochlorite (NaOCI) and deionised water (Dl-W) in a ratio of Dl-W: KOH (3.5%): NaOCI (63.25%) at 80 °C. The typically etch rate for this step is about 0.1 nm/s. The sample (i.e. the Si wafer with the front-side dielectric tunnel layer and the initial doped semiconductor layer) is also circulated within the etch mixture in order to ensure a uniform etching. Although a temperature of 80 °C has been used for etching in the present embodiment, lower temperatures may also be used. Other details in regards to a chemistry of this etchant and its technology used on doped Si wafer can be found in an earlier application PCT/SG2013/000183.

Further, the present etch-back technology in relation to the step 106 provides a controlled way for producing an ultra-thin (e.g. less than 20 nm, or less than 10 nm, or less than 5 nm) contact passivation layer stack without compromising on a quality of the contact passivation layer stack. This advantageously decreases front-side parasitic absorption and thereby improving an efficiency of the two-terminal tandem solar cell. Figures 4A to 4C, which are discussed below, provide experimental evidence to demonstrate a quality of the ultra-thin contact passivation layer stack provided using this etch-back technology.

Although specific types of semiconductor wafer, dielectric tunnel layer and doped semiconductor layers aforementioned are used in this embodiment, it should be appreciated that the general concept of etching back on the initial doped semiconductor layer so as to eventually form an ultra-thin contact passivation can be applied to other suitable semiconductor, dielectric tunnel layer and doped semiconductor layers for fabricating a solar cell in a tandem solar cell structure.

In a step 108, a surface of a rear side (i.e. an opposite side to the front side of the Si wafer) of the Si wafer is etched to provide a textured surface. This is an optional step which has been performed in the present embodiment in order to enhance a performance of the solar cell fabricated by providing enhanced light trapping of the infrared spectrum. However, it should be appreciated that a non-textured rear-side surface solar cell would also work. The etching performed in this step 108 comprises using a standard etching technology for n-type monocrystalline Si wafer, such as wet etching by a hydrofluoric acid (HF) based mixture or by using the aforementioned etchant of the step 106. To perform the etching step 108, the front-side of the Si wafer is masked to protect the front side passivation layer stack.

Steps 1 10 and 112 are performed to provide for a rear-side contact passivation layer stack on the textured rear-side surface of the Si wafer obtained using the step 108, and are similar to the respective steps 102 and 104 as previously described.

In the step 1 10, a dielectric layer is formed on the rear side of the Si wafer. The dielectric layer can be either AIO_x or SiO_x formed in a similar manner as previously described in the step 102. This dielectric layer formed on the rear side of the Si wafer is termed a “rear-side dielectric tunnel layer” to differentiate it from the front-side dielectric tunnel layer formed in the step 102. Similar to the front-side dielectric tunnel layer, the rear-side dielectric layer functions as a tunnel layer and forms part of the rear-side contact passivation layer stack of the Si solar cell.

In the step 1 12, a rear-side doped semiconductor layer is deposited on the second dielectric layer once the rear-side dielectric tunnel layer has been formed in the step 110. The rear-side doped semiconductor layer is of an opposite polarity to the front-side doped semiconductor layer. In this embodiment, the rear-side doped semiconductor layer is a highly doped n⁺ poly-Si layer (e.g. phosphorous-doped). Similar to the front side doped semiconductor layer, this rear-side doped semiconductor layer can be formed with a thickness of tens of nanometres (e.g. 50 nm to 200 nm), for example by using conventional methods such as LPCVD or PECVD. The rear-side doped semiconductor layer forms a“capping layer” and together with the rear-side dielectric tunnel layer (i.e. a“tunnel layer”) forms the rear-side contact passivation layer stack on the rear side of the Si wafer. Differing from the front-side contact passivation layer stack, there is less requirement for the rear-side passivation layer stack to be ultra-thin since light is incident via the front side of the Si wafer and therefore parasitic absorption of light by the rear- side passivation layer stack is a much minor concern (e.g. a further reduction of a thickness of less than 50 nm may not have any measurable effect). However, to improve a performance of the solar cell, enhanced internal reflection is required. In a step 114, multiple layers of alternating materials with varying refractive indices are deposited on the rear-side doped semiconductor layer to form a non-conductive distributed Bragg reflector (DBR). The non-conductive DBR is provided in order to selectively enhance an internal rear-side reflection of the infrared (IR) part of the incoming light spectra (i.e. in the range 900 - 1200 nm) in the solar cell. In the present embodiment, this involves depositing alternating layers of silicon oxide (SiO_x) and silicon nitride (SiN_x), or depositing alternating layers of aluminium oxide (AIO_x) and silicon nitride (SiN_x). The alternating layers of SiO_x and SiN_x are deposited using PECVD. Alternatively, if the combination of alternating layers of aluminium oxide and silicon oxide is used, these can be deposited using ALD or PECVD. Although a DBR has been used in this embodiment, in a variation, other layer or layers (e.g. a passivation layer or a conductive DBR) which can reflect the IR spectrum of the incoming light may also be used

In a step 116, a portion of the non-conductive DBR is ablated using a femtosecond laser to provide rear-side contact openings in the non-conductive DBR for contacting the second doped semiconductor layer. The non-conductive DBR is advantageous in reducing a parasitic IR absorption compared to a conductive DBR. However, due to the electrically insulating nature of the non-conductive DBR, rear-side contact openings have to be formed in the non-conductive DBR in order to make electrical contact with the conductive rear-side contact passivation layer stack of the solar cell. In the present embodiment, femtosecond laser ablation is used to form these contact openings as it is experimentally shown that this method advantageously provides for damage-free (or near damage-free) contact openings and thereby preserving a passivation quality of the rear-side contact passivation. This is demonstrated in relation to Figures 13A to 14D below.

In a step 1 18, a rear contact layer is deposited on the non-conductive DBR to form a rear-side contact so that the rear-side contact is in electrical contact with the rear-side doped semiconductor layer via the rear-side contact openings. In the present embodiment, a metal layer (e.g. aluminum layer) is deposited as the rear contact layer by either conventional screen printing, sputtering or evaporation.

Figure 2 is a schematic structure of the solar cell 200 fabricated using the method 100 of Figure 1. The solar cell 200 can be used as a front- and rear-side contact passivated bottom cell in a tandem solar cell structure. The solar cell 200 or the Si wafer has a front side 201 and a rear side 203 as shown in Figure 2.

The solar cell 200 comprises a p⁺ poly-Si capping layer 202 (e.g. boron doped) and a front-side tunnel layer 204 formed on a front side of an n-type monocrystalline Si wafer 206. The p⁺ poly-Si capping layer 202 and the tunnel layer 204 together formed a front side contact passivation layer stack which is suitable for tandem solar cell integration. This front-side contact passivation layer stack can be formed using the steps 102 and 104 as previously described. The capping layer 202 is ultra-thin of around a few nanometres. This can be achieved using the etch-back process step 106 as previously described. The front-side tunnel layer 204 comprises either a wet-chemically formed SiO_x tunnel layer or an atomic-layer deposited AIO_x. With the etch-back process step 106 to thin down the capping layer, an ultra-thin front-side contact passivation layer stack with a thickness of a few nanometers can be achieved. Due to the ultra-thin front-side contact passivation layer stack, parasitic IR absorption is reduced to a minimum. A bottom solar cell having this ultra-thin front-side contact passivation layer stack is therefore suitable for tandem solar cell integration.

The solar cell 200 also comprises a rear-side contact passivation layer stack comprising a rear-side tunnel layer 208 and an n⁺ poly-Si capping layer 210 (e.g. phosphorus doped) formed on a rear-side of the Si wafer 206. The rear-side tunnel layer 208 and the n⁺ poly- Si capping layer 210 can be formed using the steps 110 and 112. Similar to the front side tunnel layer 204, the rear-side tunnel layer 208 comprises either a wet-chemically formed SiO_x tunnel layer or an atomic-layer deposited AIO_x. As shown in Figure 2, the rear-side passivation layer stack is formed on a textured rear-side surface 212 of the Si wafer 206. The textured rear-side surface 212 can be formed using the step 108 as previously described. Deposited on the rear-side contact passivation layer stack is a non- conductive DBR stack 214 which comprises either alternating layers of SiO_x and SiN_x or alternating layers of AIO_xand SiN_x. This non-conductive DBR stack 214 provides a rear- side internal reflectance enhancement, and can be formed using the step 114. The non- conductive DBR stack 214 is configured to selectively enhance the internal rear-side reflection of the IR spectrum of the incoming light spectra (i.e. in the range 900 - 1200 nm). By combining a high/low refractive index passivating DBR stack 214 with the tunnel- layer 208/capping-layer 210 passivated contact at the rear-side of the textured Si wafer 206, a highly IR-reflecting passivated contact can be realized. In addition, rear-side contact openings 216 are formed penetrating the non-conductive DBR stack 214 using the step 116 so that a rear-side contact layer 218 deposited on the rear-side of the Si wafer using the step 118 can make electrical contact to the conductive rear-side contact passivation layer stack as shown in Figure 2. In the present embodiment, the rear-side contact layer 218 is a metal layer (e.g. a gold or aluminum layer) which can be formed using an industrial high through-put processing, such as by sputtering or by thermal evaporation. As shown in Figure 2, the rear-side contact layer 218 which forms a full- area deposited layer on the rear-side of the solar cell 200 is therefore locally point contacting the rear-side contact passivation layer stack via the contact openings 216.

The solar cell 200 as shown in the present embodiment therefore embodies a front- and rear-side contact passivated Si bottom solar cell suitable for conventional perovskite on Si tandem solar cell integration. The resultant solar cell 200 comprises an ultra-thin highly p-doped (i.e. p⁺-doped) poly-Si capping layer, thereby forming a front-side hole extracting contact and providing a conductive front-side passivation layer stack on a planar surface suitable for further two-terminal thin-film perovskite on Si tandem solar cell integration. As previously described, the ultra-thin poly-Si capping layer is advantageous for front side passivated contact as it minimises parasitic absorption in the front-side contact passivation layer stack. Moreover, although the ultra-thin poly-Si capping layer has a resulting high lateral resistivity (due to its reduced thickness), this is not critical in the case of a subsequent two-terminal tandem solar cell integration as no lateral electrical transport in the poly-Si layer is required in the two-terminal tandem solar cell solar cell, in contrast to a single junction solar cell.

The solar cell 200 combines a number of features to provide a number of advantages. First, the front- and rear- sides contact passivation layer stacks which form full-area passivated electrically conductive contacts enable high open-circuit voltages of the solar cell 200 by suppressing contact recombination for both the front and rear-side passivated contacts, reaching a total recombination current density of less than 30 fAcnr² Second, the planar ultra-thin front-side conductive and highly passivating contact allows for further thin-film on crystalline-Si tandem solar cell integration, particularly since the front-side contact passivation is ultra-thin (e.g. 3-4 nm thick) and thereby effectively reduces parasitic infrared IR absorption within the front-side contact passivation layer stack to a minimum. Third, the non-conductive DBR stack 214 is configured to allow a significantly enhanced rear-side internal back-reflection in the IR spectrum of the incident light and thereby improving short circuit current and thus efficiency of the solar cell 200. By combining the above three features, high open circuit voltage (achieved by using contact passivation layer stacks for the front-side as well as for the rear-side of a solar cell), with high short-circuit currents (achieved by a combination of an ultra-thin front-side conductive contact passivation layer stack (SiO_x-tunnel-layer/poly-Si-capping-layer) with a point-like contacted rear-side insulating contact passivation layer stack (SiO_x-tunnel- layer/poly-Si-capping-layer/insulating-Bragg-reflector) may therefore be achieved. Further, the solar cell (before the formation of the rear-side contact layer 218) is configured to be able to withstand processing temperatures for further device integration of up to 800 °C, this enables flexibility in the fabrication of the solar cell for tandem cell integration (before the final metallization step).

The solar cell 200 of the present disclosure is able to significantly outperform conventionally used heterojunction contacts deployed for further thin-film on Si tandem solar cell integration, thereby gaining a roughly 2 times 0.5 mA cm^-2 = ~ 1 mA cm^-2 in photon current and at the same time allowing much higher deposition temperatures for further thin-film on silicon tandem solar cell integration. The estimated photon current gain is based on the fact that a heterojunction contact has parasitic absorption not only in the doped a-Si:H layers but also in the transparent conductive oxide (TCO) layers on top of them. A front-side contact-passivation layer stack is able to have less parasitic absorption using an ultra-thin (~ 3nm) poly Si as compared to a moderately thin (-10-15 nm) a-Si:H. Further, there is no front-side TCO required in the present embodiment, thus again saving on parasitic absorption of the incident light.

Figures 3A, 3B and 3C illustrate experimental findings of a passivation quality of a SiO_x/n⁺ poly-Si passivated contact.

As shown in Figure 3A, a double-passivated SiO_x/n⁺ poly-Si passivated contact structure 300 for investigating the passivation quality is shown. The double-passivated structure 300 comprises a front-side n⁺ poly-Si capping layer 302 deposited on a SiO_x tunnel layer 304 on a front-side of an n-type crystalline Si wafer 306, and a rear-side n⁺ poly-Si capping layer 310 deposited on a SiO_x tunnel layer 308 on a rear-side of the n-type crystalline Si wafer 306.

Figures 3B and 3C show experimental results for testing a passivation quality of the structure as shown in Figure 3A. Figure 3B is a graph of minority carrier lifetime as a function of the n⁺ poly-Si capping layer thickness, and Figure 3C is a graph of implied open-circuit voltage at 1 sun (i.e. 1 kW/m²) illumination intensity as a function of the n⁺ poly-Si capping layer thickness. As shown in Figures 3B and 3C, the SiO_x/n⁺ poly-Si passivated contact provides for a minority carrier lifetime of >6 ms and an implied open- circuit voltage of >720 mV but this passivation quality breaks down as soon as the thickness of the n⁺ poly-Si capping layer is less than 70 nm.

Figures 4A, 4B and 4C illustrate experimental findings of a passivation quality of a SiO_x/p⁺ poly-Si passivated contact for comparison with the SiO_x/n⁺ poly-Si passivated contact of Figure 3.

Figure 4A shows a double-passivated hole extraction SiO_x/p⁺ poly-Si passivated contact structure 400 for testing the passivation quality. The double-passivated structure 400 comprises a front-side p⁺ poly-Si capping layer 402 deposited on a SiO_x tunnel layer 404 on a front-side of an n-type crystalline Si wafer 406, and a rear-side p⁺ poly-Si capping layer 410 deposited on a SiO_x tunnel layer 408 on a rear-side of the n-type crystalline Si wafer 406. The passivated contact structure 400 is similar to the passivated contact structure 300 but for the polarity of the capping layers. In a variation, a ALD-AIO_x/p⁺ poly- Si passivated contact, which exhibits a higher hole selectivity due to the high negative interface charge density of AIO_x, can also be used.

Figures 4B and 4C show experimental results for testing a passivation quality of the structure 400 as shown in Figure 4A. Figure 4B is a graph of minority carrier lifetime as a function of poly-Si capping layer thickness, and Figure 4C is a graph of implied open- circuit voltage at 1 sun (i.e. 1 kW/m²) illumination intensity as a function of the poly-Si capping layer thickness. Both the experimental results for testing the passivation qualities of the SiO_x/n⁺ poly-Si passivated contact 300 and the SiO_x/p⁺ poly-Si passivated contact 400 are shown in Figures 4B and 4C for easy comparison. As shown in Figures 4B and 4C, the passivation quality of the SiO_x/p⁺ poly-Si passivated contact is preserved down to a thickness of as thin as 3-4 nm (e.g. 3.1 nm as shown in Figures 4B and 4C). This can be observed from Figures 4B and 4C where the minority carrier lifetime is preserved at more than 1.5 ms lifetime (see Figure 4B) with an implied open-circuit voltage of more than 685 mV (see Figure 4C) at a poly-Si thickness of about 3-4 nm. The good passivation quality of the p⁺ doped poly-Si capping layer down to an ultra-thin thickness of about 3-4 nm means that this ultra-thin capping layer is fitted to be used to form an ultra-thin front-side contact passivation layer stack. By incorporating the ultra- thin front-side passivation layer stack as presented above, parasitic infrared (IR) absorption can be suppressed to a higher extent as compared to conventional heterojunction solar cells, which are conventionally deployed for ultra-high-efficiency silicon bottom cell tandem application, while enabling a comparable passivation quality. Comparing the parasitic IR absorption in a conventional heterojunction solar cells which typically includes a 70 nm thick front side TCO on top of a typically 10 nm i/p a-Si H passivation layer as the interlayer between a top solar cell and a bottom solar cell in the two-terminal tandem solar cell structure, the parasitic absorption for the above 3-4 nm thick p⁺ poly-Si layer exhibits a significantly larger short circuit current gain while maintaining a comparable high open-circuit voltage. The ultra-thin p⁺ poly-Si capping layer therefore allows for a low recombination conductive passivation layer stack to be incorporated for further two-terminal tandem solar cell integration.

As previously described in the step 106, a slow silicon etch (SSE) is used in order to reduce a thickness of the poly-Si capping layer in a controlled way. By etching down a moderately thick layer doped poly-Si capping layer (initially in the 50 to 200 nm thickness range) to a final target thickness of a few nm only, an actively doped ultra-thin poly-Si capping layer can be obtained without having to establish a diffusion process. This is therefore advantageous over existing processing technologies such as deposition by PECVD or LPCVD as these processes require a high temperature annealing or sintering step to form the highly doped poly-Si capping layer.

Although SiO_x is used as the tunnel layer for the present experiments, there are experimental indications that using atomic layer deposited (ALD) AIO_x instead of the wet- chemically formed SiO_x tunnel layer can result in enhanced silicon bottom cell efficiency due to a selectivity of the eventual contact passivation layer stack.

As is shown in the solar cell structure 200 in Figure 2, the front surface of the Si wafer 206 is kept planar so as to ease subsequent processing of a top solar cell (e.g. a solution processed perovskite solar cell) in a tandem solar cell structure. However, using a planar front surface reduces a light trapping capability of the solar cell 200 as compared to a textured surface. Therefore, in order to enhance an efficiency of the bottom Si solar cell so as to be suited for further two terminal tandem integration, adequate light trapping for the infrared (IR) part of the solar spectrum (i.e. within the wavelength range of 900 - 1200 nm) is required. To achieve this, a rear-side textured surface and a feature which promotes rear-side internal IR reflection may be incorporated. This is further discussed in relation to Figures 5-11 below.

Figures 5A, 5B and 5C illustrate experimental findings of a passivation quality of a SiO_x/n⁺ poly-Si passivated contact with a textured surface.

Figure 5A is a schematic structure 500 of the SiO_x/n⁺ poly-Si passivated contact being tested. Similar to Figure 3A, except for the textured surface on both a front and rear-side of the n-Si wafer, a double-passivated SiO_x/n⁺ poly-Si passivated contact structure 500 is used for testing the passivation quality is shown. The double-passivated structure 500 comprises a front-side n⁺ poly-Si capping layer 502 deposited on a SiO_x tunnel layer 504 on a textured front-side of an n-type Si wafer 506, and a rear-side n⁺ poly-Si capping layer 510 deposited on a SiO_x tunnel layer 508 on a textured rear-side of the n-type Si wafer 506.

Figure 5B is a graph of minority carrier lifetime as a function of silicon slow etch (SSE) time (or etch-back time), while Figure 5C is a graph of an implied open-circuit voltage at 1 sun illumination intensity (right), as a function of SSE time. As shown in Figures 5B and 5C, a thinning of the poly-Si layer is possible up to an etch-back time of more than 1800 sec without compromising a passivation quality of the textured passivation contact. This corresponds to a thickness estimation of roughly less than 70 nm which may be verifiable using ellipsometry. As shown by the results, it is therefore feasible to form an etched-back, high-lifetime electron-extracting SiO_x/n⁺ poly-Si passivated contact on a textured surface of a Si wafer, however only down to a thickness of ~70 nm. It is noted that thickness may be reduced further to ~30 nm using other optimized etching method (e.g. using a single component etch of NaOCI, see Fig. 16 and its description). It is noted however that this may not be the case for hole extracting SiO_x/p⁺ poly-Si passivated contacts which seems to show a comparatively low passivation quality on a textured Si wafer surface. In other words, SiO_x/p⁺ poly-Si passivated contacts seems to work better on a planar Si wafer surface. This is however adequate in the application of a front-side passivation contact for a bottom Si solar cell in a tandem solar cell structure given that a planar surface is advantageous for subsequent fabrication of a top solar cell (e.g. solution processed perovskite top solar cell). Focusing on the application of a passivation contact in a bottom Si solar cell of a tandem solar cell structure, a combined high-efficiency front-side planar (hole extracting) and a rear-side textured (electron extracting) silicon bottom solar cell pre-cursor is investigated.

Figures 6A, 6B, 6C and 6D shows experimental findings of a double-sided contact passivated silicon bottom cell pre-cursor.

Figures 6A and 6B are schematic structures 600, 601 of the double-sided contact passivated silicon bottom cell pre-cursor with- and without- additional layers of SiN_x respectively. The double-sided contact passivated silicon bottom cell pre-cursor structure 600 of Figure 6A comprises a front-side p⁺ poly-Si capping layer 602 deposited on a SiO_x tunnel layer 604 on a planar front-side of an n-type crystalline Si wafer 606, and a rear-side n⁺ poly-Si capping layer 610 deposited on a SiO_x tunnel layer 608 on a textured rear-side of the n-type crystalline Si wafer 606. The double-sided contact passivated silicon bottom cell pre-cursor structure 601 of Figure 6B is similar to that of the structure 600 of Figure 6A except that additional SiN_x passivation layers 612, 614 are deposited on each of the planar front-side and the textured rear-side of the n-type crystalline Si wafer 606 respectively.

Figure 6C is a graph of minority carrier lifetime as a function of minority carrier density for each of the structures of Figures 6A (black squares) and 6B (white squares), while Figure 6D is a graph of illumination intensity as a function of implied open-circuit voltage for each of the structures of Figures 6A (black squares) and 6B (white squares). As shown in Figures 6C and 6D, solar cell pre-cursors with a high minority carrier lifetime of more than 1.5 ms can be obtained for the double-sided contact passivated silicon bottom cell pre-cursor 600, 601. Moreover, these solar cell pre-cursors 600, 601 have implied open circuit voltages at 1 sun illumination intensity of 690 mV for the pre-cursor structure 600 without additional layers of SiN_x and 713 mV for the pre-cursor structure 601 with additional layers of SiN_x respectively. Therefore, a solar-cell pre-cursor lifetime of more than 1.3 ms and a total recombination current density of less than 40 fA cm^-2 have been achieved. The total recombination current density is extracted using a Kane-Swanson plot using the measured intensity dependent lifetime data.

Further, as previously discussed, a performance of the bottom solar cell with a planar front-side passivation contact can be improved with a rear-side internal reflectance enhancement. For example, this can be realised by depositing a rear-side distributed Bragg reflector (DBR) stack on top of the rear-side textured electron extracting SiO_x/n⁺ poly-Si passivated contact, in order to selectively enhance an internal rear-side reflection of the IR spectrum of the incoming light spectra (i.e. in the range 900 - 1200 nm). A distributed Bragg reflector (DBR) comprising alternating low/high refractive index passivation layers, which if designed in the right way (e.g. being thickness optimized), is able to significantly enhance internal rear-side IR reflectance by means of coherent interference.

A schematic structure 700 used in numerical calculations for optimising a DBR is shown in Figure 7A. The structure 700 comprises an n-type planar Si wafer 702 with alternating layers of SiO_x 704 and SiN_x 706 deposited on a planar rear-side surface of the n-type planar Si wafer 702. The alternating layers of SiO_x 704 and SiN_x 706 formed the rear- side DBR stack 708. The DBR stack 708 shown in Figure 7 A is a three-layer DBR stack 708 comprising three layers of SiO_x 704 and three layers of SiN_x 706 arranged in an alternating fashion (i.e. three SiO_x-SiN_x layer stacks).

Figure 7B is a graph of calculated internal reflectance of the DBR stack 708, using 1 to 10 alternating layers for the DBR stack 708, as a function of a wavelength of the internally reflected light. As shown in Figure 7B, an enhanced reflectance is observed for the wavelength of about 900 nm to 1 150 nm which falls within the IR light spectrum. Further, the graph of Figure 7B shows an increasing reflectance with an increasing number of layers for the DBR stack 708, which saturates at around the six SiO_x-SiN_x layer DBR stack. SiO_x-SiN_x layer stacks are used in this calculation as these low-cost passivation layers are readily available (e.g. by conventional PECVD deposition).

The above calculations performed as shown in Figures 7A and 7B are also validated experimentally. This is shown in Figures 8A and 8B by fabricating structures 700 with deposited rear-side one-layer, two-layer and three-layer SiO_x/SiN_x DBR stacks and measuring the resulting IR reflection for each of these structures.

Figure 8A is a graph of reflectance of the structure 700 with a one-layer, a two-layer or a three-layer DBR stack as a function of a wavelength of the reflected light. The DBR stack comprises layers of 170 nm thick SiO_x and 120 nm thick SiN_x. As shown in Figure 8A, there is a good match of the reflectance results between the simulated results of the structure 700 (with different number of DBR stack) and the corresponding measured results. Figure 8B is a graph of calculated peak reflectance as a function of the number of layers of the DBR stack. As shown in Figure 8B, in comparison with a conventional structure to improve internal reflection which deploys a standard 70 nm SiN_x rear-side passivation layer, the internal IR reflection can be significantly enhanced when using a one-layer, two-layer, or three-layer DBR stack 708. The resulting total IR reflectance (i.e. peak reflectance which is mostly contributed by escaped light which has entered the Si wafer, being internally reflected and escaped from the wafer front-side) increases from -17% to -55%, 75% or 85% using an optimized one layer, two-layer and three-layer DBR stack respectively. Although a planar surface structure 700 is used in this simulation, in a variation, the calculation for optimising a thickness of each layer of the DBR stack can also be performed for a textured rear-side Si wafer surface. In a variation, a DBR stack comprising AIO_x (in place of SiO_x) and SiN_x or other suitably chosen materials can also be simulated.

Numerical simulation/calculations are also performed to calculate expected current gains for different rear-side contacts. This is discussed in relation to Figures 9 to 11 below with reference to (i) a“conventional” rear-side heterojunction contact structure, (ii) a rear-side passivated contact structure without an additional rear-side DBR stack, and (iii) a rear- side passivated contact structure with an additional rear-side DBR stack in order to enhance internal IR back-reflection.

Figure 9 shows a flowchart of a method 900 for investigating enhanced internal IR back- reflection of a rear-side of a heterojunction contact using expected current gains for different solar cell architectures. The measured reflectance obtained (e.g. using fabricated structures as shown in Figures 10A, 10B and 10C) is fitted to an optical ray- tracer combined with thin-film optics (e.g. using Sunsolve™ from PVLighthouse) in order to quantify (i) directly reflected light, (ii) light which enters the Si wafer but is internally reflected and has escaped from the front side of the Si wafer, (iii) light which is absorbed by the Si wafer and (iv) light which is parasitically absorbed in all the other layers.

In a step 902, a truncated AM1.5 spectrum at 780 nm, mimicking a perovskite top cell absorption with an assumed perovskite bandgap of 1.6 eV, is used as an irradiance light source input for the different solar cell architectures being investigated. In a step 904, the different solar cell architectures are then constructed for simulation. In a step 906, different current gains can then be simulated using the light source input from the step 902 and the different solar cell architectures obtained in the step 904. The different current gains are stimulated in order to predict an effect of the truncated spectrum (having obtained a quantitative calibration from a non-truncated spectrum).

Figures 10A, 10B and 10C show three different solar cell architectures 1002, 1004, 1006 used in an investigation of enhanced internal IR back-reflection using the method 900 of Figure 9.

Figure 10A, 10B and 10C show three different solar cell architectures, with all of them comprising a front-side contact-passivation structure, i.e. with the front silver contact 1022 contacting a front-side p⁺ poly-Si capping layer 1008 deposited on a SiO_x tunnel layer 1010 on a planar front-side of an n-type crystalline Si wafer 1012. Fig. 10A shows a conventional rear-side heterojunction contact structure 1002, with the rear-side n⁺ amorphous-Si layer 1016 formed on an intrinsic amorphous Si layer 1014 on a textured rear-side of the n-type crystalline Si wafer 1012. An indium-tin oxide (ITO) layer 1018 is then deposited on the rear-side of the n⁺ amorphous-Si capping layer 1016 followed by a silver metal layer 1020.

Figure 10B shows a conventional rear-side passivated contact 1004, i.e. not using a DBR stack. The rear-side passivated contact 1004 comprises similar layers as the corresponding front-side layers. In particular, the rear-side passivated contact 1004 comprises a rear-side n⁺ poly-Si capping layer 1026 deposited on a rear-side tunnel layer 1024 (e.g. SiO_x) on a textured rear-side of the n-type crystalline Si wafer 1012 in place of the layers 1014 and 1016. There is an additional SiN_x passivation layer 1028 deposited on the rear-side n⁺ poly-Si capping layer 1026. Metallization (Silver-paste) is achieved by screen printing on top of this SiNx passivation layer 1028 and subsequent contact firing. As shown in Figure 10B, the silver contact layer 1020 in this case penetrates through a portion of the SiN_x passivation layer 1028 in order to contact the rear-side n⁺ poly-Si capping layer 1026.

Figure 10C shows a rear-side passivated contact 1006, deploying a rear-side passivated contact and a three-layer DBR stack 1030 (in variations, a one-layer, two-layer or four- layer DBR stack can also be used). The rear-side passivated contact 1006 is similar to the rear-side passivated contact 1004 except for the DBR stack 1030 which is deployed in place of the SiN_x passivation layer 1028. Similar to the rear-side passivated contact 1004 of Figure 10B, the silver contact layer 1020 in this case penetrated through a portion of the DBR stack 1030 in order to contact the rear-side n⁺ poly-Si capping layer 1026.

Figures 11 A, 11 B and 11C show graphs of calculated expected current gains for the architectures as shown in Figures 10A, 10B and 10C. Figure 11A shows a graph of correspondingly absorbed photocurrent within the Si wafer 1012 of each of the structures 1002, 1004, 1006, Figure 11 B shows a graph of parasitically absorbed photocurrent in all other layers (except for the Si wafer 1012), and Figure 11 C shows a graph of photocurrent for the escaped photons (entering the Si wafer 1012 but escaping it front side again).

As shown in Figure 1 1A, the expected gain in absorbed photocurrent amounts to 0.55 mA cm^-2, for example, when comparing the rear-side heterojunction with the three-layer DBR stack layer 1006 with the conventional rear-side heterojunction contact 1002. Figure 11 B shows that the parasitically absorbed photocurrent in all other layers (except for the Si wafer 1012) is higher for the conventional rear-side heterojunction contact 1002 compared to that of the passivated contact without a DBR stack 1004 or the passivated contact with a DBR stack 1006. As shown in Figure 11 C, as a results of improved internal reflection by the DBR stack, it is observed that the photocurrent for the escaped photons is higher for the passivated contact without a DBR stack 1004 or the passivated contact with a DBR stack 1006 as compared to that of the conventional rear-side heterojunction contact 1002.

The calculated expected current gain (0.55 mA cm^-2) thus far has only considered the rear-side contact. Similar effects will be effective for the front-side contact as well. These will be even more pronounced as the front-side p⁺ poly-Si layer can be significantly reduced in thickness (down to 4 nm), which thus far we cannot achieve for the rear-side n-poly-layer (thickness reduction thus far works only down to 70 nm). The total expected current gain as compared to a “standard” heterojunction bottom cell is thus at minimum >1 mA cm² or it may likely be even higher.

Figures 12A and 12B show charts of optical analysis comparing an ability to trap light for a double-sided textured solar cell architecture (“Front- textured”; see Figure 12A) to a rear-side only textured solar cell architecture (“Front-planar”; see Figure 12B). Each of these solar cell architecture deploys a front- and a rear-side passivated contact with an additional rear-side three-layer DBR stack. A rear-side only textured solar cell architecture is for example the passivated contact structure 1006 as shown in Figure 10C. A double-sided textured solar cell architecture (not shown) is one which is similar to the passivated contact structure 1006 as shown in Figure 10C except that the front side surface of the n-Si wafer 1012 is textured.

The front- textured (i.e. double-side textured) and the front-planar (i.e. rear-side textured only) solar cell architectures are compared in order to verify that loss of the IR photons being absorbed (light-trapped) in the Si wafer 1012 is insignificant even if only the rear- side surface of the Si wafer is textured. This is helpful because if the IR photons absorbed by the front-planar solar cell architecture is comparable to that of the front- textured solar cell architecture, the front-planar solar cell architecture is favoured given that a planar front side surface of the Si wafer significantly simplifies a subsequent perovskite thin-film device integration process (since perovskite solar cells are typically formed by means of spin coating which requires a planar surface). As shown in Figures 12A and 12B, the percentage of the amount of photons absorbed after entering the Si wafer is even slightly higher for the front-planar solar cell architecture (87.88%) as compared to that of the front- textured solar cell architecture (87.72%).

Although the above is a simulation study, there is experimental evidence that a rear-side DBR solar cell architecture does work. This has been successfully tested in a similar concept for heterojunction solar cells which deploys a rear-side conductive distributed Bragg reflector consisting of alternating a-Si:H/TCO layers in order to enhance the internal reflection of heterojunction solar cells (c.f. Zhipeng Ling, Armin Aberle, Thomas Mueller, Rolf Stangl,“Development of a conductive Distributed Bragg Reflector using n- doped microcrystalline silicon and Al-doped zinc-oxide thin-films and its application in silicon heterojunction solar cells”, IEEE Journal of Photovoltaics, Vol.4, No.6, 1320).

It is noteworthy however that the optimization criteria is very different for the above publication as the above heterojunction solar cells are optimized: (i) to include a broader wavelength range for internal rear reflectance (as opposed to the IR spectrum in the present embodiment), (ii) to minimize parasitic IR absorption in the conductive TCO and a-Si:H layers (as opposed to the SiO_x/SiN_x DBR stack), and (iii) without considering contact issues for the DBR stack since the conductive distributed Bragg reflector consisting of alternating a-Si:H/TCO layers was used. In the present embodiment, however, a non-conductive DBR comprising alternating layers of SiO_x and SiN_x is used instead of a conductive one, thereby significantly decreases a parasitic IR absorption in the solar cell structure 200. However, contacting the rear-side contact passivation through the non-conductive DBR is not a trivial matter. The method of forming contact with the underlying contact passivation layer stack via the non-conductive distributed Bragg reflector should be performed without damaging the underlying contact passivation layers. Furthermore, the contact formed using this method should employ an industrial high-throughput process.

In the present embodiment, femtosecond (fs) laser ablation used to locally form damage- free contact openings in an AIO_x/SiN_x passivation layer stack deposited on top of a poly- Si layer has been investigated.

Figures 13A, 13B, 13C, 13D, 13E and 13F show cell structures of a SiO_x/poly-Si contact passivated test-sample with a rear-side AIO_x/SiN_x passivation layer stack and their corresponding photoluminescence (PL) images at different stages of contact openings formation using local femtosecond laser ablation. In the present investigation, a cell structure 1300 is used. The cell structure 1300 comprises a rear-side poly-Si capping layer 1302 deposited on a SiO_x tunnel layer 1304 formed on a planar rear side of an n- type monocrystalline Si wafer 1306, with an AIO_x layer 1308 and a SiN_x layer 1310 subsequently deposited on the rear-side poly-Si capping layer 1302. Similar layered structure is also deposited on a front side of the n-type Si wafer 1306. In other words, a front-side poly-Si capping layer is also deposited on a SiO_x tunnel layer formed on a planar front side of the n-type monocrystalline Si wafer 1306, with an AIO_x layer and a SiN_x layer subsequently deposited on the front-side poly-Si capping layer.

Figures 13A and 13B show the structure and the corresponding PL image before using the femtosecond laser ablation, Figures 13C and 13D show the structure and the corresponding PL image after using the femtosecond laser ablation to form contact openings 1312, and Figures 13E and 13F show the structure and the corresponding PL image after rear-side metallisation 1314 using thermal evaporation (note that all PL images are of the same size and having a same intensity scale).

The PL intensity measured as shown in Figures 13B, 13D and 13F provide experimental evidences for degradation, if any, of the passivation quality (measured by a decrease in the PL intensity) after the processing steps of local fs laser ablation (see Figure 13D) and metallization using thermal evaporation (see Figure 13F). As shown in Figures 13B, 13D and 13F, there is nearly no reduction in passivation quality (corresponding to a decrease in PL intensity) after local fs laser ablation (as shown in Figures 13C and 13D) and after metallization (as shown in Figures 13E and 13F). In other words, the femtosecond laser ablation used is able to form contact openings in the DBR stack without destroying the poly-Si layer underneath and thus without affecting the minority carrier lifetime in the contact passivation layer stack even after local contact opening and/or after metallization (see Figures 9 to 1 1C). In performing the above, a process window for forming these local contact openings using the local femtosecond laser ablation has been identified by optimizing a laser fluence and a laser pulse overlap of the femtosecond laser process. It is understood that an AIO_x/SiN_x layer stack can in principle form a distributed Bragg reflector (DBR) stack in an analogous manner to the SiO_x/SiN_x DBR stack investigated in relation to the above e.g. Figures 3A to 11 C. Although only results for the AIO_x/SiN_x layer stack are shown, it is understood that a corresponding fs laser ablation process with an optimized process window can be similarly obtained for a one-layer SiO_x/SiN_x DBR or a multi-layer SiO_x/SiN_x DBR. Please note that this is not at all trivial, i.e. conventional laser ablation processes (e.g. nanosecond laser ablation) and/or screen printing will damage the underlying poly-Si contact passivation layer and will thereby significantly reduce a passivation quality (e.g. in terms of minority carrier lifetimes and implied open-circuit voltages) of the underlying poly-Si capping layer.

Figures 14A, 14B, 14C and 14D show PL images (see Figures 14A and 14B) and optical microscope images (see Figures 14C and 14D) of double-sided SiO_x/poly-Si/SiN_x contact passivated test-samples using a textured wafer (see Figures 14A and 14C) or a planar wafer (see Figures 14B and 14D).

The PL and the optical microscopic images as shown in Figures 14B and 14D respectively for the planar wafer sample demonstrate that the SiN_x contact passivation layer can be removed by fs laser processing without destroying the contact passivation, since it is evident that there is nearly no difference between the photoluminescence intensity observed between an area exposed to the fs laser 1402 and an area which is not exposed to the fs laser 1404. This is however not true in the case of the textured wafer sample. As shown in Figure 14A, a lower PL intensity (i.e. a darkened box) is observed for the area exposed to the fs laser. The process for the textured wafer sample can be further optimised.

With the above experimental results as shown in Figures 14B and 14D, it is viable that damage-free local contact openings using femtosecond laser ablation can be achieved for at least a one-layer rear-side SiO_x/SiN_x DBR stack deposited on top of a SiO_x/n⁺-poly- Si passivated contact without affecting its passivation quality. This enables a high throughput industrial local metallisation of a rear-side passivating non-conductive DBR stack (e.g. by sputtering) without degrading the underlying contact passivation layers. The above investigations can be repeated for a rear-side textured Si wafer surface as well.

Variations to the present embodiment are now discussed in relation to Figures 15 to 17.

The present embodiment comprises an ultra-thin p⁺-poly-Si capping layer with a thickness of only a few nanometers (e.g. 3-4 nm) which may therefore benefit from an additional conventional front-side diffusion layer formed to support the formation of the solar cell emitter layer. This is shown in Figure 15.

Figure 15 shows a schematic structure 1500 of a front and back contact-passivated silicon-wafer-based bottom solar cell for tandem application which deploys an additional front-side p-diffusion layer 1502 on a front-side of the Si wafer surface in order to support the formation of the emitter region of the solar cell. The only difference between the structure 1500 and the structure 200 as shown in Figure 2 is the formation of the front side p-diffused layer 1502 on a front-side of the Si wafer 206. The front-side p-diffused layer 1502 may be formed by doping a front surface of the Si wafer 206. This may be formed by using conventional boron tube diffusion.

Figure 16 shows a schematic structure 1600 of a front and back contact-passivated silicon-wafer-based bottom solar cell for tandem application which deploys a thin SiO_x/n⁺ poly-Si planar front-side passivated contact, and a rear-side textured AIO_x/p⁺ poly-Si or SiO_x/p⁺ poly-Si passivated contact combined with a distributed Bragg reflector. Compared to the structure 200 as shown in Figure 2, the structure 1600 of this alternative embodiment comprises a front-side n⁺ poly-Si capping layer 1602 (in place of the p⁺ poly- Si capping layer 202) and a rear-side p⁺ poly-Si layer 1604 (in place of the n⁺ poly-Si capping layer 210). The front-side n⁺ poly-Si capping layer 1602 may be phosphorous doped and the rear-side p⁺ poly-Si capping layer 1604 may be boron doped.

To etch down the front-side n⁺ poly-Si capping layer in this alternative embodiment, a similar etchant as that used for the front-side p⁺ poly-Si capping layer may be used (i.e. the etch mixture of potassium hydroxide (KOH), sodium hypochlorite (NaOCI) and deionised water (Dl-W) in a ratio of DI-W:KOH (3.5%):NaOCI (63.25%) at 80 °C as described in the step 106). However, this only works up to a thickness of about 70 nm for the n⁺ phosphorous-doped poly-Si capping layer 1602 (with an etch rate of ~0.3 to 0.5 nm/sec at 80 °C) without compromising a passivation quality of the n⁺ phosphorous- doped poly-Si capping layer 1602. This may be because the p⁺ poly-Si capping layer (e.g. boron doped) is more chemically stable and so it exhibits a lower etch rate.

An alternative etch solution comprising a single component etch of NaOCI for the n⁺ phosphorous-doped poly-Si capping layer has also been investigated. The typically etch rate for this single component etchant is about 0.1 nm/s at 80 °C with the Si wafer structure circulated within the etchant in order to ensure a uniform etching. Although a temperature of 80 °C has been used for etching, lower temperatures may also be used. Use of this single component etchant allows etching the n⁺ phosphorous-doped poly-Si capping layer to a thickness of about 30 nm without loss in uniformity and minority carrier lifetime observed.

Figure 17 shows a schematic structure 1700 of a front and back contact-passivated silicon-wafer-based bottom solar cell for tandem application which deploys a thin SiO_x/n⁺ poly-Si planar front-side passivated contact, and a rear-side textured SiO_x/p⁺ poly-Si or AIO_x/p-poly-Si passivated contact combined with a distributed Bragg reflector and an additional rear-side p-diffused layer 1702 on the rear side Si wafer surface. The only difference between the structure 1700 and the structure 1600 as shown in Figure 16 is the formation of the rear-side p-diffused layer 1702 on the rear-side of the Si wafer 206. The rear-side p-diffused layer 1702 may be formed by doping a rear surface of the Si wafer. The rear-side p-diffused layer 1702 may be formed using boron tube diffusion.

The present embodiment is able to replace currently used heterojunction solar cells to be deployed as bottom cells for two-terminal tandem solar cell integration (i.e. targeting perovskite on silicon tandem solar cells with an efficiency > 30%) as shown in Figure 18. Figure 18 shows a schematic of a two-terminal tandem solar cell 1800 comprising a top solar cell 1801 and a bottom solar cell 1802. The bottom solar cell 1802 employs a similar structure 200 as previously discussed in relation to Figure 2 and this is not repeated here. In particular, the planar front-side of the n-type Si wafer 206 advantageously simplifies formation of a solution processed top perovskite solar cell 1801 on the planar front-side p⁺ poly-Si capping layer 202.

In order to form the two-terminal tandem solar cell 1800, once the bottom Si solar cell 1802 has been fabricated, sometimes transparent recombination layer 1803 is deposited on the front-side contact passivation layer stack 202, 204 of the bottom Si solar cell 1802. The recombination layer is needed if majority transport conversion from hole transport to electron transport (or vice versa) is needed in order to device integrate a perovskite top cell. The perovskite top cell comprises either a hole transport layer (HTM), the perovskite absorber (P) and an electron transport layer (ETM), which is a p-i-n configuration of a perovskite cell, or an electron transport layer (ETM), the perovskite absorber (P) and a hole transport layer (HTM), which is a n-i-p configuration of a perovskite top cell. In order to contact the front layer of the perovskite top cell (ETM or HTM) a transparent conductive oxide (TCO) is typically used. A perovskite top cell 1804 (e.g. comprising the HTM, P, and ETM layers as outlined above) for forming the device integrated top perovskite solar cell 1801 is then deposited on the recombination layer 1803 using a process that does not damage the underlying recombination layer 1803 and the bottom Si solar cell 1802. In the present case where n-type monocrystalline Si wafer is used, a buffer layer 1806 is configured to avoid sputter damage from the top transparent electrode 1808. A top transparent electrode 1808 has a low sheet resistance and a high transparency. Metal gridlines 1810 are then deposited on the top transparent electrode 1808 to minimise series resistance through the top transparent electrode 1808.

Although SiO_x which has a moderate positive charge density has been used as the tunnel layer in the previously described embodiment, in a variation, the tunnel layer can also be formed by atomic layer deposited AIO_x which has a high negative interface charge density.

The described embodiment should not be construed as limitative. For example, other alternative embodiments are possible and this may include (1) using a double-side textured Si wafer, (2) using a double-sided planar Si wafer, (3) using additional multi- layered front-side anti-reflection layers, (4) using a p-doped Si wafer instead of the n- doped Si wafer used as described above, and (5) using a multi-crystalline wafer instead of a mono wafer.

To elaborate on the alternative embodiment (1) above where a double-side textured Si wafer is used to form the solar cell, adjustments to the method as illustrated in Figure 1 may have to be made. In particular, a double side textured wafer would be provided at the very beginning, i.e. using conventional KOH etching technology. In an event that LPCVD, which is a double-sided deposition process, is used to form the poly-Si capping layers, it may be of an advantage to start with a planar double side SiO_x/poly-Si contact passivation stack, which is subsequently front-side mask protected, and then rear-side textured (i.e. the step 108) to form the texturing of the rear-side and at the same time remove the unwanted rear-side contact passivation layer stack formed by the double sided LPCVD deposition in one process step. This would also apply to the opposite situation, where, in another embodiment a front side textured-only Si wafer is desired.

The present disclosure relies on tube deposition technologies to form the front- and rear- side contact passivation layer stacks (e.g. by using masking layers). This results in a double-side deposition process being deployed. However, if one would be able to use a single-side deposition technology in order to form a passivated contact, the amount of process steps needed would decrease significantly.

Instead of LPCVD, it is envisaged that plasma enhanced chemical vapour deposition (PECVD) might be a possibility for the poly-Si capping layer deposition in order to form ultra-thin ~10 nm (& highly passivating) front-side conductive contact passivation layers.

Indeed, using a single-side deposition technology such as the PECVD, the aforementioned embodiments may be applied to front-side passivated contact application in conventional single-junction solar cells (targeting silicon solar cells with an efficiency >25%) as well.

Further, if the single-side deposition technology (e.g. PECVD) is matured, a direct PECVD deposition of the doped p-poly capping layer may eventually be possible to achieve the ultra-thin front-side p⁺ poly-Si capping layer, without the aforementioned etch- back step (i.e. the step 106). For example, PECVD deposited ultra-thin highly doped a-Si:H layers which are subsequently sintered towards poly-Si could be used. The resulting structure for the proposed silicon bottom cell would be the same as the previously described structure 200.

Although only certain embodiments of the present invention have been described in detail, many variations are possible in accordance with the appended claims. For example, features described in relation to one embodiment may be incorporated into one or more other embodiments and vice versa.

Claims

1. A solar cell comprising a silicon wafer having a front side arranged to receive incident light and a rear side, the solar cell comprising:

a front-side dielectric tunnel layer formed on the front side of the silicon wafer; and

a front-side doped semiconductor layer deposited on the front-side dielectric tunnel layer;

wherein the front-side doped semiconductor layer and the front-side dielectric tunnel layer form a conductive contact passivation layer stack arranged to contact a top solar cell to form a tandem solar cell and to allow the incident light to pass through to the silicon wafer, the conductive contact passivation layer stack having a thickness of less than 20 nm.

2. The solar cell of claim 1 , further comprising:

a rear-side dielectric tunnel layer on the rear side of the silicon wafer; and a rear-side doped semiconductor layer on the rear-side dielectric tunnel layer, the rear-side doped semiconductor layer having an opposite polarity to the front-side doped semiconductor layer.

3. The solar cell of claim 2, further comprising multiple layers of alternating materials with varying refractive indices on the rear-side doped semiconductor layer to form a non- conductive distributed Bragg reflector.

4. The solar cell of claim 3, wherein the multiple layers of alternating materials comprises alternating layers of silicon oxide and silicon nitride, or alternating layers of aluminium oxide and silicon nitride.

5. The solar cell of claim 3 or claim 4, further comprising rear-side contact openings penetrating the non-conductive distributed Bragg reflector formed using femtosecond laser ablation.

6. The solar cell of claim 5, further comprising a rear contact layer formed on the non- conductive distributed Bragg reflector to form a rear-side contact, the rear-side contact being in electrical contact with the rear-side doped semiconductor layer via the rear-side contact openings.

7. The solar cell of any one of claims 1 to 6 further comprises a p-type emitter region formed at the front side of the silicon wafer.

8. The solar cell of any one of claims 1 to 7, wherein the rear side of the silicon wafer comprises a textured surface.

9. The solar cell of any one of claims 1 to 8, wherein the front-side dielectric tunnel layer comprises a silicon oxide or an aluminium oxide.

10. A method for fabricating a solar cell, the solar cell comprising a silicon wafer having a front side arranged to receive incident light and a rear side, the method comprising: forming a front-side dielectric tunnel layer on the front side of the silicon wafer; depositing an initial doped semiconductor layer on the front-side dielectric tunnel layer, the initial doped semiconductor layer having an initial thickness; and

1 1. The method of claim 10, further comprising:

forming a rear-side dielectric tunnel layer on the rear side of the silicon wafer; and depositing a rear-side doped semiconductor layer on the rear-side dielectric tunnel layer, the rear-side doped semiconductor layer having an opposite polarity to the front-side doped semiconductor layer.

12. The method of claim 11 , further comprising depositing multiple layers of alternating materials with varying refractive indices on the rear-side doped semiconductor layer to form a non-conductive distributed Bragg reflector.

13. The method of claim 12, wherein the step of depositing multiple layers of alternating materials comprises depositing alternating layers of silicon oxide and silicon nitride, or depositing alternating layers of aluminium oxide and silicon nitride.

14. The method of claim 12 or claim 13, further comprising ablating a portion of the non- conductive distributed Bragg reflector using a femtosecond laser to provide rear-side contact openings penetrating the non-conductive distributed Bragg reflector for contacting the rear-side doped semiconductor layer.

15. The method of claim 14, further comprising depositing a rear contact layer on the non-conductive distributed Bragg reflector to form a rear-side contact, the rear-side contact being in electrical contact with the rear-side doped semiconductor layer via the rear-side contact openings.

16. The method of any one claims 10 to 15, wherein the initial doped semiconductor layer comprises a p-doped polysilicon layer, the etching step includes etching the p- doped polysilicon layer with a mixture of potassium hydroxide, sodium hypochlorite and deionised water.

17. The method of claim 16, further comprises doping a front surface of the silicon wafer with a p-type dopant to form an emitter region at the front side of the silicon wafer.

18. The method of any one of claims 10 to 15, wherein the initial doped semiconductor layer comprises an n-doped polysilicon layer, the etching step includes etching the n- doped polysilicon layer with sodium hypochlorite.

19. The method of any one of claims 10 to 18, further comprises etching the rear side of the silicon wafer to form a textured surface.

20. The method of any one of claims 10 to 19, wherein the step of forming the front-side dielectric tunnel layer on the front side of the silicon wafer comprises atomic-layer depositing an aluminium oxide or wet oxidising the front side of the silicon wafer to form silicon oxide.

21. The method of any one of claims 10 to 20, wherein the conductive contact passivation layer stack has a thickness of less than 20 nm.

22. The method of any one of claims 10 to 21 , further comprising forming the top solar cell on the front side of the silicon wafer to form a two-terminal tandem solar cell.

23. A tandem solar cell comprising:

a top solar cell; and

24. The tandem solar cell of claim 23, wherein the top solar cell and the bottom solar cell are integrated to form a two-terminal tandem solar cell structure.