WO2020026641A1 - Inductor, composite inductor, dc/dc converter, and circuit - Google Patents

Inductor, composite inductor, dc/dc converter, and circuit Download PDF

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Publication number
WO2020026641A1
WO2020026641A1 PCT/JP2019/024706 JP2019024706W WO2020026641A1 WO 2020026641 A1 WO2020026641 A1 WO 2020026641A1 JP 2019024706 W JP2019024706 W JP 2019024706W WO 2020026641 A1 WO2020026641 A1 WO 2020026641A1
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Prior art keywords
conductor
inductor
current
hole
core
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PCT/JP2019/024706
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French (fr)
Japanese (ja)
Inventor
幸伯 山田
圭司 田代
有吉　剛
裕典 岡川
Original Assignee
住友電気工業株式会社
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Priority claimed from JP2018192845A external-priority patent/JP2021180199A/en
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Publication of WO2020026641A1 publication Critical patent/WO2020026641A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/04—Fixed inductances of the signal type  with magnetic core
    • H01F17/06—Fixed inductances of the signal type  with magnetic core with core substantially closed in itself, e.g. toroid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F37/00—Fixed inductances not covered by group H01F17/00
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac

Definitions

  • the present disclosure relates to an inductor, a composite inductor, a DC / DC converter, and a circuit.
  • This application claims the priority based on Japanese Patent Application No. 2018-142502 filed on Jul. 30, 2018 and the priority based on Japanese Patent Application No. 2018-192845 filed on Oct. 11, 2018. All the contents described in the above are used.
  • DC / DC converters for raising and lowering a DC voltage are widely used as power supplies for in-vehicle equipment and industrial equipment. Converters are classified into an insulated type and a non-insulated type depending on whether or not the input and output are insulated by a transformer. The control method of the insulated converter is divided into a forward method and a flyback method.
  • a single choke coil (inductor) having a winding wound around a core is interposed on the high potential side of a secondary circuit through which an output current flows (Japanese Patent Application Laid-Open No. H11-163873). 1).
  • An inductor includes a core having a first through-hole, a portion inserted into the first through-hole, a first conductor through which a first current flows, and a first conductor passing through the first through-hole. And a second conductor through which a second current flows, wherein one of the first current and the second current is generated when the other current passes through the outside of the inductor.
  • the direction of the first current and the second current in the first through hole, which is the current returning to the inductor, is the same as the direction of the first through hole.
  • a composite inductor according to an aspect of the present disclosure is a composite inductor including the above-described inductor, and includes a plurality of the cores in which the first conductor and the second conductor are inserted into the first through-hole.
  • a DC / DC converter includes the above-described inductor or composite inductor, a switching element, and a transformer having a primary winding connected in series to the switching element, wherein the first conductor includes: An outflow current flowing out of the secondary winding of the transformer to the outside is connected so as to flow as the first current, and the second conductor is a return current returning to the secondary winding from the outside flows as the second current. Connected.
  • the present application can be realized not only as an inductor, a composite inductor, and a DC / DC converter having such a characteristic configuration, but also as a part of the DC / DC converter as a semiconductor integrated circuit, Or may be implemented as a composite inductor or other system including a DC / DC converter.
  • FIG. 1 is a block diagram illustrating a configuration example of the DC / DC converter according to the first embodiment.
  • FIG. 2 is an explanatory diagram illustrating an example of an operation state during a period in which power is transmitted from the primary side to the secondary side of the transformer.
  • FIG. 3 is an explanatory diagram illustrating an example of an operation state during a period in which the load current flows back on the secondary side of the transformer.
  • FIG. 4 is a perspective view of the inductor according to the first embodiment as viewed obliquely from above.
  • FIG. 5 is a cross-sectional view taken along line VV of FIG. 4, and is a longitudinal cross-sectional view schematically illustrating a state after the inductor according to the first embodiment is assembled.
  • FIG. 5 is a cross-sectional view taken along line VV of FIG. 4, and is a longitudinal cross-sectional view schematically illustrating a state after the inductor according to the first embodiment is assembled.
  • FIG. 6 is a perspective view of the inductor according to the second embodiment as viewed obliquely from above.
  • FIG. 7 is a cross-sectional view taken along line VII-VII of FIG. 6, and is a longitudinal cross-sectional view schematically illustrating a state after assembly of the inductor according to the second embodiment.
  • FIG. 8A is a plan view showing a first conductor inserted into both of the through holes according to the second embodiment.
  • FIG. 8B is a plan view illustrating the second conductor inserted into both of the through holes according to the second embodiment.
  • FIG. 9A is a plan view showing the first conductor inserted into all of the through holes according to the first modification.
  • FIG. 9B is a plan view showing the second conductor inserted through all of the through holes according to the first modification.
  • FIG. 10A is a plan view schematically illustrating a first conductor according to Modification Example 2.
  • FIG. 10B is a plan view schematically showing a second conductor according to Modification 2.
  • FIG. 13 is a perspective view of an inductor according to Modification Example 3 as viewed obliquely from above. It is a side view which shows the inductor attached to the housing
  • FIG. 11 is a block diagram illustrating a configuration example of a DC / DC converter according to a third embodiment.
  • FIG. 13 is a plan view schematically showing a transformer and an inductor formed on a printed wiring board of the DC / DC converter according to the third embodiment.
  • FIG. 13 is a plan view schematically illustrating a transformer and an inductor formed on a printed wiring board of the DC / DC converter according to the fourth embodiment.
  • FIG. 16A is a graph illustrating frequency components of switching noise caused by the DC / DC converter according to the second embodiment.
  • FIG. 16B is a graph illustrating frequency components of switching noise caused by the DC / DC converter according to the fourth embodiment.
  • FIG. 17 is a circuit diagram illustrating a configuration example of a DC / DC converter according to the fifth embodiment.
  • the inductor is interposed on the high voltage side of the secondary circuit. Since the magnitude of the inductance required for this inductor is inversely proportional to the switching frequency at which the switch is turned on / off, the switching frequency must be relatively high in order to reduce the size of the inductor.
  • An inductor includes a core having a first through-hole, a first conductor having a portion inserted through the first through-hole, and through which a first current flows; A second conductor having a portion inserted through the through-hole and through which a second current flows, wherein one of the first current and the second current is connected to the outside of the inductor by the other current. And the direction of the first current and the second current in the first through-hole is the same as the direction of the penetration of the first through-hole.
  • the core has the first through hole formed therein.
  • the first conductor and the second conductor inserted into the first through-hole are connected to the outside such that the first current and the second current flow in the same direction as the direction in which the first through-hole penetrates.
  • the core further includes a second through-hole penetrating in the same direction as the first through-hole, the first conductor further includes a portion inserted through the second through-hole, The two conductor further has a portion inserted into the second through-hole, and the directions of the first current and the second current in the second through-hole are relative to a direction in which the second through-hole passes.
  • the directions of the first current and the second current in the first through hole are opposite to each other.
  • the core may include three or more through holes.
  • the first through-hole and the second through-hole whose through directions are aligned in the same direction are formed in the core.
  • the directions of the first current and the second current in the second through-hole are configured to be opposite to the directions of the first current and the second current in the first through-hole.
  • the first conductor has a first U-shaped portion, and the first U-shaped portion includes the portion where the first conductor is inserted into the first through hole and the second through hole. It is preferable to include the above-mentioned part penetrated.
  • the portions inserted into the first through-hole and the second through-hole and the portions connecting these portions are U-shaped.
  • the conductor has a relatively simple shape that is point-symmetric or line-symmetric in plan view.
  • the second conductor has a second U-shaped portion disposed so as to be opposite to the first U-shaped portion, and the second U-shaped portion is formed of the second conductor. Preferably includes the portion inserted through the first through-hole and the portion inserted through the second through-hole.
  • the U-shaped portions of the first conductor and the second conductor are configured to be opposite to each other. Accordingly, one end and the other end of the first conductor and the second conductor are separated from each other on both sides in the through direction of the through hole, so that connection to the outside is facilitated.
  • the core is preferably any of EE type, EI type and ER type.
  • any of the EE type, EI type and ER type cores having two through holes in abutted state is used, so that widely used cores can be used.
  • each of the first conductor and the second conductor has a rectangular cross section.
  • the cross section of each of the first conductor and the second conductor is rectangular, the thickness of the cross section in the short side direction can be suppressed. Further, since the surface area with respect to the cross-sectional area of each of the first conductor and the second conductor is large, heat dissipation is good.
  • the first conductor and the second conductor are conductor patterns included in different layers of a multilayer wiring board.
  • the conductor patterns included in different inner layers or outer layers of the multilayer wiring board are used as the first conductor and the second conductor, the first conductor and the second conductor including the peripheral circuit can be easily formed. Can be formed.
  • the core is a ferrite core or a magnetic material dust core.
  • the ferrite core is formed by sintering a magnetic material.
  • the dust core is formed by pressing powder containing a magnetic material.
  • the core is a ferrite core or a dust core, high-frequency characteristics are good.
  • the core may be a nanocrystalline soft magnetic material core or an amorphous core.
  • the inductor preferably further includes a heat transfer layer containing a heat transfer material.
  • the heat transfer layer Between the first conductor and the second conductor, and It is preferable that the core is disposed on at least one of the first and second conductors and the core.
  • the heat transfer material is interposed between the pair of conductors and / or between the pair of conductors and the core, the heat generated in the conductors passes through holes. Heat is transferred to the outside.
  • the core includes a pair of core members that can abut each other, and that the first through hole penetrates in a direction along the abutting surface in a state where the pair of the core members abut each other. .
  • a composite inductor according to an aspect of the present disclosure is a composite inductor including the above-described inductor, and includes a plurality of the cores each having the first conductor and the second conductor inserted through the first through hole. Prepare.
  • the size of each core can be reduced.
  • the inductor formed by inserting the first conductor and the second conductor into the first through hole and the second through hole of the core is regarded as a two-terminal pair circuit including two inductance elements.
  • Each two-terminal pair circuit is cascaded.
  • the overall transmission characteristics are derived based on the transmission characteristics of each two-port pair circuit.
  • a capacitor is connected to one terminal pair in at least one of the two-terminal pair circuits.
  • a DC / DC converter includes the above-described inductor, a switching element, and a transformer having a primary winding connected in series to the switching element. An outflow current flowing out of the secondary winding of the transformer to the outside is connected so as to flow as the first current, and the second conductor is a return current returning from the outside to the secondary winding as the second current. Connected.
  • the switching element is connected in series to the primary winding of the transformer, and the outflow current and return current to the secondary winding of the transformer flow through the first and second conductors of the inductor.
  • a DC / DC converter includes the above-described composite inductor, a switching element, and a transformer having a primary winding connected in series to the switching element.
  • the current flowing out of the secondary winding of the transformer to the outside is connected as the first current, and the second conductor is connected to the return current returning from the outside to the secondary winding by the second current. Connected as flowing.
  • the switching element is connected in series to the primary winding of the transformer, and the outflow current and return current to the secondary winding of the transformer flow through the first conductor and the second conductor of the composite inductor.
  • the first conductor is formed integrally with the secondary winding, and at least one of the first conductor and the second conductor is formed integrally with an output-side electric path. Is preferred.
  • the first conductor is formed integrally with the secondary winding of the transformer, and at least one of the first conductor and the second conductor is formed integrally with the output-side electric circuit.
  • the number of joints between components can be reduced.
  • both the first conductor and the second conductor may be formed integrally with the electric circuit on the output side.
  • a DC / DC converter includes the above-described inductor, a switching element, and a transformer having a primary winding, and at least the switching element, the inductor, and the primary winding. And are connected in series.
  • a circuit according to one embodiment of the present disclosure includes the above-described inductor, and a circuit element connected in series to the first conductor and the second conductor outside the inductor.
  • the first conductor, the circuit element, and the second conductor are connected in series, one of the first current and the second current flows through the circuit element. Passing it becomes the second current.
  • FIG. 1 is a block diagram illustrating a configuration example of the DC / DC converter 100 according to the first embodiment.
  • the DC / DC converter 100 includes a transformer 10, and the potential of the input-side terminals A and B and the potential of the output-side terminals C and D are separated by the transformer 10.
  • a capacitor 20 is connected between the terminals A and B on the input side, and a predetermined voltage is applied from an external DC power supply (not shown).
  • a capacitor 21 is connected between the output side terminals C and D, and an external load is further connected.
  • the terminal D is connected to, for example, the ground potential.
  • the DC / DC converter 100 also includes an Nch-type MOSFET (Metal Oxide Semiconductor Connector Field Effect Transistor: hereinafter referred to as an FET) 31 (corresponding to a switching element) connected between one end of the primary winding 11 of the transformer 10 and the terminal B. ), A series circuit of the FET 32 and the capacitor 22 connected between one end of the primary winding 11 and the terminal A, and a control unit 4 for controlling on / off of the FETs 31 and 32. The other end of the primary winding 11 is connected to the terminal A.
  • the FETs 31 and 32 may be other switching elements such as a bipolar transistor and an IGBT (Insulated Gate Bipolar Transistor).
  • the FET 31 has a drain connected to one end of the primary winding 11, a source connected to the terminal B, and a gate connected to the control unit 4.
  • the FET 32 has a drain connected to one end of the capacitor 22, a source connected to one end of the primary winding 11, and a gate connected to the control unit 4.
  • the other end of the capacitor 22 is connected to the terminal A.
  • Each of the FETs 31 and 32 has a body diode connected in anti-parallel at both ends. The order in which the FET 32 and the capacitor 22 constituting the active clamp circuit are connected in series may be changed.
  • the secondary winding 12 of the transformer 10 has one end connected to the cathode of the diode 51 and the other end connected to the cathode of the diode 52.
  • the cathode of the diode 52 is further connected to one end of the capacitor 21 and the terminal C via a conductor 61 included in the inductor 6 as a choke coil.
  • the anodes of the diodes 51 and 52 are connected to the other end of the capacitor 21 and the terminal D via a conductor 62 included in the inductor 6.
  • the inductor 6 is integrated including the pair of cores and the conductors 61 and 62.
  • the inductor 6 is represented as if a coil is wound around a core.
  • the conductors 61 and 62 correspond to the coil. Details of the inductor 6 will be described later.
  • the DC / DC converter 100 having the above-described configuration is a so-called single-rock type forward converter, and multiplies a predetermined voltage supplied from the terminals A and B by ⁇ (duty ratio of the FET 31) / (turn ratio of the transformer 10) ⁇ . Are output from terminals C and D.
  • the DC / DC converter 100 is not limited to a single-stone type, and may be any of a multi-stone type push-pull type, a half-bridge type, and a full-bridge type. The description of the example of the multiple stone type is omitted since the type itself is known.
  • voltage conversion is performed by performing PWM (Pulse Width Modulation) control on the FET 31 at a predetermined cycle. Therefore, the voltage conversion operation of the DC / DC converter 100 will be described first. 2 and 3, the illustration of the capacitor 20, the control unit 4, and the terminals C and D is omitted.
  • PWM Pulse Width Modulation
  • FIG. 2 is an explanatory diagram illustrating an example of an operation state during a period in which power is transmitted from the primary side to the secondary side of the transformer 10.
  • the FET 31 is turned on and the FET 32 is turned off under the control of the control unit 4.
  • a predetermined voltage is applied to the primary winding 11 of the transformer 10 from the terminals A and B to induce a constant voltage in the secondary winding 12, the diode 51 conducts, and the load current that increases linearly in the inductor 6. Flows.
  • a current (substantial output current) flowing from the secondary winding 12 (corresponding to a predetermined current source) to the capacitor 21 and the load via the conductor 61 is set as an outflow current, and the conductor 62 is transferred from the capacitor 21 and the load.
  • Current flowing through a so-called return path that returns to the secondary winding 12 via the control circuit is defined as a return current. The magnitudes of the outflow current and the return current are the same.
  • a current obtained by adding the load current (more precisely, the current obtained by dividing the magnitude of the load current on the secondary side by the turns ratio of the transformer 10) and the exciting current is applied to the primary winding 11 in a straight line. Flows to increase gradually.
  • the magnetic flux due to the load current flowing through each of the primary winding 11 and the secondary winding 12 cancels each other, while the exciting current creates a magnetic flux in the core of the transformer 10.
  • the capacitor 22 is charged with a voltage that makes the drain side of the FET 32 positive until the current PWM cycle.
  • a case where the potential of the other end is higher than the one end of the primary winding 11 is defined as a positive voltage.
  • the current flowing from the other end of the primary winding 11 to one end is defined as a positive current.
  • FIG. 3 is an explanatory diagram showing an example of an operation state during a period in which the load current flows on the secondary side of the transformer 10.
  • the FET 31 is turned off, the load current and the exciting current stop flowing through the FET 31, and the positive exciting current commutates to the body diode of the FET 32 (see the solid line).
  • the commutated exciting current decreases linearly, the capacitor 22 is charged while the direction of the exciting current is positive.
  • the load current flowing through one secondary winding 12 via the diode 51 flows back through the diode 52.
  • the FET 32 is turned on by the control of the control unit 4, and the exciting current flowing through the body diode of the FET 32 flows through the channel region, but the exciting current continues to decrease. Since a negative voltage is applied from the capacitor 22 to the primary winding 11 throughout the period shown in FIG. 3, the exciting current decreases linearly and the polarity is inverted from positive to negative in the middle of the entire period. (See broken line). At this time, the capacitor 22 starts discharging. Then, at the end of the period in which the FET 32 is on, the release of the energy stored in the transformer 10 ends. The load current on the secondary side of the transformer 10 continues to flow back through the diode 52.
  • FIG. 4 is a perspective view of the inductor 6 according to the first embodiment viewed obliquely from above
  • FIG. 5 is a longitudinal sectional view schematically illustrating a state after the assembly of the inductor 6 according to the first embodiment.
  • a through hole 60 is formed along a mating surface XX of a pair of cores 63 and 64 having a U-shaped cross section, and the pair of conductors 61 and 62 overlap the through hole 60.
  • One of the pair of conductors 61, 62 is referred to as a first conductor 61, and the other is referred to as a second conductor 62.
  • the vertical relationship between the conductors 61 and 62 may be opposite to that shown in FIGS.
  • a current flowing through the first conductor 61 is called a first current
  • a current flowing through the second conductor 62 is called a second current.
  • the first current is an outflow current
  • the second current is a return current.
  • the second current is a current in which the first current returns to the inductor 6 via a load which is a circuit element outside the inductor 6.
  • the first current may be considered to be a current that returns to the inductor 6 via the secondary winding 12 or the diode 52 that is a circuit element outside the inductor 6.
  • the cores (magnetic cores) 63 and 64 include a magnetic material.
  • the cores 63 and 64 are configured by abutting a pair of core members 63 and 64.
  • One of the pair of core members 63 and 64 is referred to as a first core member 63, and the other is referred to as a second core member.
  • the first core member 63 may be simply referred to as a core 63
  • the second core member 64 may be simply referred to as a core 64.
  • the pair of core members 63 and 64 may be referred to as a pair of cores 63 and 64.
  • the pair of cores 63 and 64 may have any shape in cross section and outer shape as long as a through hole is formed by abutting the cores.
  • the conductors 61 and 62 are rectangular copper wires or bus bars having a rectangular cross section, and the aspect ratio (the ratio of the long side to the short side) is, for example, in the range of 2: 1 to 20: 1. It is not limited. By thus increasing the aspect ratio by making the cross section rectangular, heat dissipation of the conductors 61 and 62 becomes easy.
  • the cores 63 and 64 are made of a powder compact formed by pressing a powder containing a ferrite or a magnetic material formed by sintering a magnetic material, the cores 63 and 64 have good high-frequency characteristics. That is, the cores 63 and 64 are ferrite cores or dust cores.
  • the material of the cores 63 and 64 is not limited to these, and may be, for example, a composite material containing a powder of a soft magnetic material and a resin, or may be a laminate in which plate-like magnetic materials are laminated.
  • the cores 63 and 64 may be nanocrystalline soft magnetic material cores or amorphous cores.
  • An insulating layer 65 is provided between the conductors 61 and 62.
  • An insulating layer 66 is provided between the conductors 61 and 62 and the cores 63 and 64.
  • the material of the insulating layers 65 and 66 is a heat dissipation material such as a silicon sheet, the heat dissipation of the conductors 61 and 62 is improved.
  • the heat transfer layers 67, 67 containing a heat transfer material such as a carbon sheet Is further provided.
  • a heat transfer layer (not shown) may be further provided between the conductors 61 and 62.
  • the conductors 61 and 62 are placed at positions where the through holes 60 are to be formed in the core 64 before butting the cores 63 and 64, and then the core 63 is butted against the core 64. Assembled.
  • the inductor 6 is connected to the peripheral circuit, it is considered that the outflow current flowing through the conductor 61 and the return current flowing through the conductor 62 flow in the same direction as the through-hole 60.
  • the applicable range and performance of the inductor 6 configured as described above will be described.
  • required inductance is inversely proportional to a switching frequency, and when the switching frequency is low, the coil cannot be replaced with a conductor having no winding shape. Therefore, in the first embodiment, it is assumed that the switching frequency of the FETs 31 and 32 by the control unit 4 is in the range of 300 kHz to 3 MHz, and that the inductance required for the inductor 6 is in the range of 0.1 ⁇ H to 3 ⁇ H.
  • the insulating layer 66 is disposed between the conductors 61 and 62 and the cores 63 and 64.
  • the cylindrical portion inserted into the through hole 60 and the two openings of the through hole 60 are formed.
  • the conductors 61 and 62 may be inserted through a bobbin made of an insulator having a flange-shaped flange along the opening surface. Further, the conductors 61 and 62 may be formed by conductor patterns in different inner layers or outer layers of the multilayer wiring board.
  • a part of the insulating layer 65 and the insulating layer 66 can be replaced with a prepreg containing epoxy resin and glass fiber, or a part of the insulating layer 66 can be replaced with a resist layer on the substrate surface.
  • the through-hole 60 is formed along the butting surface XX where the pair of cores 63 and 64 including the magnetic material is butted.
  • Conductors 61 and 62 are connected to peripheral circuits so that the outflow current from the secondary winding 12 of the transformer 10 and the return current to the secondary winding 12 flow in the same direction as the penetration direction of the through hole 60. It is connected.
  • the magnetomotive force F is doubled and the inductance is substantially quadrupled as compared with the case where one conductor is inserted into the through holes 60 of the cores 63 and 64. Therefore, even when the conductor inserted into the cores 63 and 64 is not wound, it is possible to secure necessary inductance.
  • the cross section of each of the pair of conductors 61 and 62 is rectangular, the thickness of the cross section in the short side direction can be suppressed, and the height of the inductor 6 can be suppressed. . Further, since the surface area with respect to the cross-sectional area of each of the pair of conductors 61 and 62 is large, the heat dissipation is improved.
  • the pair of conductors 61 and 62 including the peripheral circuit can be easily formed. Can be formed.
  • the ferrite or the compact is used as the material of the cores 63 and 64, the high frequency characteristics are good.
  • the heat transfer layers 67, 67 are interposed between the pair of conductors 61, 62 and the cores 63, 64, the heat generated in the conductors 61, 62 penetrates. Heat is preferably transferred to the outside of the hole 60.
  • a heat transfer layer is also provided between the pair of conductors 61 and 62, the heat transfer is further improved.
  • the FET 31 is connected in series to the primary winding 11 of the transformer 10, and the outflow current and the return current to the secondary winding 12 of the transformer 10 are each a pair of conductors 61 and 62 of the inductor 6. Flows to As a result, when the FET 31 is turned on / off, a current is induced in the secondary winding 12 of the transformer 10, and this current flows through the pair of conductors 61 and 62 of the inductor 6, thereby effectively reducing the output current. Can be smoothed.
  • one through hole 60 is formed in a state where a pair of cores 63 and 64 are abutted, whereas in the second embodiment, two through holes 60 are formed in a state where a pair of cores 63b and 64b are butted.
  • through holes 601 and 602 are formed. Since the block configuration of the DC / DC converter according to the second embodiment is the same as that of the DC / DC converter 100 according to the first embodiment, the illustration is omitted, and the portions corresponding to the first embodiment are denoted by the same reference numerals. The description is omitted.
  • FIG. 6 is a perspective view of the inductor 6b according to the second embodiment viewed obliquely from above
  • FIG. 7 is a vertical cross-sectional view schematically showing a state after the inductor 6b is assembled.
  • 8A and 8B are plan views respectively showing the conductors 61b and 62b inserted into both the through holes 601 and 602 according to the second embodiment.
  • FIG. 8A shows the first conductor 61b
  • FIG. 8B shows the second conductor 62b.
  • through holes 601 and 602 whose through directions are aligned in the same direction are formed along the abutting surfaces Xb-Xb of the EE-type cores 63b and 64b, and a pair of conductive holes are respectively formed in the through holes 601 and 602.
  • the bodies 61b and 62b are inserted so as to overlap each other.
  • the vertical relationship between the conductors 61b and 62b may be opposite to that shown in FIGS.
  • the pair of cores 63b and 64b may have another shape such as, for example, an EI type or an ER type.
  • the first conductor 61b has a first U-shaped portion 61bu including a portion inserted into the through holes 601 and 602 and a portion connecting these portions.
  • the second conductor 62b has a second U-shaped portion 62bu including a portion inserted into the through holes 601 and 602 and a portion connecting these portions.
  • portions including one end and the other end in the direction in which current flows are opposite to each other in a direction intersecting the through holes 601 and 602. Although it is bent, it may not be bent in this way.
  • the portions bent in this manner are referred to as one end and the other end.
  • the conductors 61b and 62b have a simple line-symmetric shape in plan view. Further, with respect to each of the conductors 61b and 62b, the current flowing through the portions inserted into the through holes 601 and 602 is necessarily in the opposite direction, and the magnetic flux cancels out in the core between the through holes 601 and 602. There is no. Therefore, if the size of the pair of cores 63b and 64b is substantially equal to the size of two pairs of the cores 63 and 64 according to the first embodiment arranged side by side, the inductance of the inductor 6b is substantially equal to the inductance of the inductor 6. Double.
  • An insulating layer 65 is provided between the conductors 61b and 62b.
  • An insulating layer 66 is provided between the conductors 61b and 62b and the cores 63b and 64b.
  • heat transfer layers 67, 67 are further provided between the conductors 61b, 62b and the insulating layer 66.
  • a heat transfer layer (not shown) may be further provided between the conductors 61b and 62b.
  • the conductors 61b and 62b are placed at positions where the through holes 601 and 602 are to be formed in the core 64b before the cores 63b and 64b are abutted. Are assembled together.
  • the inductor 6b is connected to a peripheral circuit, the outflow current flowing through the conductor 61b and the return current flowing through the conductor 62b flow in the same direction as the through direction of the through-hole 601 and pass through the through-hole 602. It is taken into consideration that the fluid flows in the same direction.
  • the U-shaped portions 61bu and 62bu are configured to be opposite to each other with respect to the direction in which the through holes 601 and 602 penetrate. Even if there is some change in the connection with the peripheral circuit, a similar effect can be obtained as the inductor 6b.
  • two through holes 601 and 602 whose through directions are aligned in the same direction along the abutting surface Xb-Xb of the cores 63b and 64b are formed in the cores 63b and 64b.
  • Each of one and the other of the pair of conductors 61b, 62b is configured such that currents flowing in portions inserted into two adjacent through holes 601 and 602 are in opposite directions. Therefore, the magnetic flux does not cancel out in the core between the adjacent through holes 601 and 602, and the inductance can be further increased substantially in proportion to the number of the through holes 601 and 602.
  • each of the pair of conductors 61b and 62b can have a relatively simple shape that is line-symmetric in plan view.
  • the U-shaped portions 61bu and 62bu of the pair of conductors 61b and 62b are configured to be opposite to each other. Therefore, one end and the other end of the pair of conductors 61b, 62b are separated on both sides in the through direction of the through holes 601 and 602, so that the connection with the secondary winding 12 and the terminals C and D is easily performed. be able to.
  • an EE-type, EI-type, or ER-type core having two through holes 601 and 602 in abutted state can be used.
  • Embodiment 2 is a mode in which two through holes 601 and 602 are formed in a state where a pair of cores 63b and 64b are abutted, whereas Modification 1 is a state where a pair of cores 63c and 64c are abutted.
  • three through holes 601, 602, and 603 are formed.
  • the configuration of the pair of cores 63c and 64c according to the first modification is the same as that of the second embodiment except that the through-holes 601, 602, and 603 are formed in the same direction. Detailed description is omitted.
  • the case where the number of through holes formed in the pair of cores is four or more is the same as in the case of the second embodiment or the first modification.
  • FIGS. 9A and 9B are plan views respectively showing the conductors 61c and 62c inserted into all of the through holes 601, 602, and 603 according to the first modification.
  • FIG. 9A shows the first conductor 61c
  • FIG. 9B shows the second conductor 62c.
  • the first conductor 61c includes a first U-shaped portion 61cu including a portion inserted into the through holes 601 and 602 and a portion connecting these portions, a portion inserted into the through holes 602 and 603, and these portions.
  • the two U-shaped portions 61cu partially overlap.
  • the second conductor 62c includes a second U-shaped portion 62cu including a portion inserted into the through holes 601 and 602 and a portion connecting these portions, a portion inserted into the through holes 602 and 603, and And a second U-shaped portion 62cu including a portion connecting the portions.
  • the conductors 61c and 62c have a simple point-symmetrical shape in plan view. Further, for each of the conductors 61c and 62c, the current flowing in the portion inserted into the adjacent through-holes 601 and 602 is necessarily in the opposite direction, and the magnetic flux cancels out in the core between the through-holes 601 and 602. It doesn't fit. Similarly, the currents flowing in the portions inserted into the adjacent through holes 602 and 603 are necessarily in opposite directions, and the magnetic flux does not cancel out in the core between the through holes 602 and 603.
  • the inductance of the inductor according to the first modification is the same as that of the first embodiment. This is approximately three times the inductance of the inductor 6 according to (1).
  • the corresponding U-shaped portions 61cu and 62cu are configured to be opposite to each other, so that one ends of the conductors 61c and 62c and the other ends of the conductors 61c and 62c are opposite to each other. These are separated from each other on both sides of the through-holes 601, 602, and 603 in the direction of penetration, so that connection with peripheral circuits is facilitated.
  • an electric path from the other end of the secondary winding 12 is connected to one end of the conductor 61c, and one end of the conductor 62c is connected to anodes of the diodes 51 and 52.
  • the other end of the conductor 61c is connected to the electric path to the terminal C, and the electric path from the terminal D is connected to the other end of the electric conductor 62c.
  • three through holes 601, 602, and 603 whose through directions are aligned in the same direction along the abutting surfaces of the cores 63 c and 64 c are formed in the cores 63 c and 64 c.
  • One and the other of the pair of conductors 61c, 62c are configured such that currents flowing in portions inserted into two adjacent through holes 601 and 602 (or through holes 602 and 603) are in opposite directions. Have been. Accordingly, the magnetic flux does not cancel out in the core between the adjacent through holes 601 and 602 (or the through holes 602 and 603), and the inductance is further increased substantially in proportion to the number of the through holes 601, 602, and 603. be able to.
  • each of the pair of conductors 61c and 62c a portion inserted into two adjacent through holes 601 and 602 (or through holes 602 and 603) and a portion connecting these portions. Are U-shaped. Therefore, each of the pair of conductors 61c and 62c can have a relatively simple shape that is point-symmetric in plan view.
  • the U-shaped portions 61cu and 62cu of the pair of conductors 61c and 62c are configured to be opposite to each other. Therefore, one end and the other end of the pair of conductors 61c, 62c are separated from each other on both sides of the through-holes 601, 602, 603 in the penetrating direction. Can be done.
  • Modification 2 is a form in which the pair of conductors 61b and 62b are formed separately from the peripheral circuit, whereas Modification 2 is a form in which the pair of conductors 61d and 62d are formed integrally with the peripheral circuit. is there.
  • the configuration of the pair of cores 63b and 64b according to the second modification is exactly the same as that of the second embodiment.
  • FIGS. 10A and 10B are plan views schematically showing a pair of conductors 61d and 62d according to the second modification.
  • One end of the conductor 61d is formed integrally with the one-turn secondary winding 12 of the transformer 10, and the other end is formed integrally with the terminal C, as compared with the conductor 61b according to the second embodiment.
  • the conductor 61d may not be integrated with the terminal C.
  • the other conductor 62d has the other end formed integrally with the terminal D as compared with the conductor 62b according to the second embodiment, but does not necessarily have to be so integrated.
  • the conductor 61b of the second embodiment illustrated in FIG. 6 is integrated with the secondary winding 12 and the terminal C, and the conductor 62b is integrated with the terminal D.
  • the conductor 61 shown in FIG. 4 of the first embodiment may be integrated with the secondary winding 12 and the terminal C, and the conductor 62 may be integrated with the terminal D, or the conductor shown in FIG. 9C may be integrated with the secondary winding 12 and the terminal C, and the conductor 62c shown in FIG.
  • the conductor 61d is formed integrally with the secondary winding 12 and the terminal C of the transformer 10, and the conductor 62d is formed integrally with the terminal D.
  • the number of joints between them can be reduced.
  • Modification 3 Embodiment 2 is a mode in which the mounting method of the inductor 6b is not specified, whereas Modification 3 is a mode in which the inductor 6c is mounted on the housing 7.
  • the configuration of the pair of cores 63b and 64b according to the third modification is completely the same as that of the second embodiment.
  • FIG. 11 is a perspective view of the inductor 6c according to the third modification viewed from obliquely above
  • FIG. 12 is a side view schematically showing the inductor 6c attached to the housing 7.
  • the inductor 6c is different from the inductor 6b according to the second embodiment in that the conductor 61b is replaced by a conductor 61e, and the pair of cores 63b and 64b and the conductor 62b are common to those in the second embodiment. is there.
  • the inductor 6b according to the second embodiment is laid flat on a plane, the lower surface of the conductor 61b is higher than the lower surface of the conductor 62b (see FIGS. 6 and 7). Therefore, in the third modification, as shown in FIG. 11, one end and the other end of the conductor 61e bent in opposite directions are bent stepwise in a thickness direction at a position not overlapping with the conductor 62b. It is.
  • the inductor 6c is placed flat on the housing 7 with the core 64b facing down, the lower surface of one end and the other end of the conductor 61e and the lower surface of the one end and the other end of the conductor 62b. , And the height from the housing 7 becomes the same.
  • projecting portions 71 and 72 having the same height are provided on the upper surface of the housing 7.
  • the protrusion 71 is disposed at a position overlapping one end and the other end of the conductor 62b.
  • the protrusion 72 is disposed at a position overlapping one end and the other end of the conductor 61e.
  • An insulating layer 68 is provided between the upper surface of the protrusion 71 and the lower surfaces of the one end and the other end of the conductor 62b.
  • An insulating layer 69 is provided between the upper surface of the protrusion 72 and the lower surfaces of the one end and the other end of the conductor 61e.
  • An insulating layer 65 is provided between portions where the conductor 61e and the conductor 62b overlap.
  • the inductor 6c can be easily attached to the housing 7.
  • Embodiment 3 is a mode in which only a pair of cores 63 and 64 are provided, whereas Embodiment 3 is a mode in which a plurality of pairs of cores 63 and 64 are provided.
  • the third embodiment is a form including a composite inductor including a plurality of inductors 6 in which a pair of conductors 61 and 62 are inserted into a through hole 60 formed by abutting a pair of cores 63 and 64.
  • FIG. 13 is a block diagram illustrating a configuration example of a DC / DC converter 100b according to the third embodiment.
  • the DC / DC converter 100b is connected between the transformer 10 for separating the potentials of the input-side terminals A and B and the potentials of the output-side terminals C and D, a pair of conductors 61 and 62, and between the terminals C and D. And a capacitor 23 connected between the conductors 61 and 62.
  • the secondary winding 12 of the transformer 10 has one end connected to the drain of the FET 51b and the other end connected to the drain of the FET 52b.
  • the drain of the FET 52b is further connected to one end of the capacitor 23 via a conductor 61 included in one inductor (hereinafter, referred to as a first inductor) 6.
  • One end of the capacitor 23 is further connected to one end of the capacitor 21 and a terminal C via a conductor 61 included in the other inductor (hereinafter, referred to as a second inductor) 6.
  • the sources of the FETs 51 b and 52 b are connected to the other end of the capacitor 23 via a conductor 62 included in the first inductor 6.
  • the other end of the capacitor 23 is further connected to the other end of the capacitor 21 and the terminal D via a conductor 62 included in the second inductor 6.
  • the gates of the FETs 51b and 52b are connected to the control unit 4.
  • the same reference numerals are given to portions corresponding to the first embodiment, and description thereof will be omitted.
  • the FETs 51b and 52b may be replaced with the diodes 51 and 52 used in the first embodiment.
  • the number of inductors 6 is not limited to two, and may be three or more.
  • the above-described inductors 6 and 6 correspond to the composite inductor 600.
  • Each inductor 6 is regarded as a two-port pair circuit, and these two-port pair circuits are cascaded. Outflow current flows through the conductor 61 included in the composite inductor 600, and return current flows through the conductor 62.
  • a capacitor is not connected to one terminal pair of the two-terminal pair circuit formed by the first inductor 6, a capacitor may be connected here.
  • the capacitor 23 may be regarded as being connected to the other terminal pair of the two-terminal pair circuit formed by the first inductor 6 or connected to one terminal pair of the two-terminal pair circuit formed by the second inductor 6. May be considered.
  • the capacitor 21 may be deleted and included in an external load. It is not always necessary to connect a capacitor between the conductors 61 and 62 at the connection portion of the two-terminal pair circuit adjacent by the inductors 6, 6,.
  • FIG. 14 is a plan view schematically showing the transformer 10 and the inductors 6 and 6 formed on the printed wiring board 8 of the DC / DC converter 100b according to the third embodiment.
  • the printed wiring board 8 uses a six-layer multi-layer substrate having four inner layers, but the number of inner layers may be three or less or five or more. Although a so-called PQ type core is used for the transformer 10 and a U-shaped core is used for the inductors 6 and 6, the present invention is not limited to this.
  • three legs of a PQ-type core are separately inserted into three openings provided at equal intervals in a direction intersecting the longitudinal direction at one longitudinal end of the printed wiring board 8. .
  • two legs of cores 63 and 64 having a U-shaped cross section are separately provided in two openings provided in the longitudinal direction substantially at the center of the printed wiring board 8 in the longitudinal direction. It has been inserted.
  • two legs of cores 63 and 64 having a U-shaped cross section are separately provided in two openings provided in the longitudinal direction at the other end of the printed wiring board 8 in the longitudinal direction. It has been inserted.
  • a conductor 61 inserted into the through holes 60, 60 of the inductors 6, 6 is formed by a conductor pattern. This conductor pattern is integrated with the one-turn secondary winding 12 of the transformer 10 and the terminal C.
  • a conductor 62 inserted into the through holes 60, 60 of the inductors 6, 6 is formed by a conductor pattern (shown by a broken line). One end, the center, and the other end of the conductor pattern are electrically connected to different conductor patterns formed in one outer layer via via via holes 621, 622, and 623, respectively.
  • the entirety of the conductor pattern formed on the specific inner layer and one outer layer and electrically connected in this way corresponds to the conductor 62.
  • the conductor pattern formed on one outer layer of the conductor 62 at the other end in the longitudinal direction of the printed wiring board 8 is integrated with the terminal D.
  • the primary winding 11 of the transformer 10 is formed in an inner layer of the printed wiring board 8.
  • the number of turns (number of turns) of the primary winding 11 may be two or more, for example, by a spiral conductor pattern formed on an arbitrary inner layer.
  • the windings may be connected in series by via holes connecting the inner layers.
  • the primary winding 11 is shown by a broken line except for an overlapping portion with the conductor 61 and the secondary winding 12.
  • the conductor 62 is indicated by a broken line including a portion where the conductor 62 overlaps the conductor 62.
  • the FET 51b is surface-mounted between the secondary winding 12 and the outer conductor 62 at a location between the transformer 10 and the first inductor 6.
  • An FET 52b is surface-mounted between a conductor 61 and an outer conductor 62 at a portion between the transformer 10 and the first inductor 6.
  • the capacitor 23 is surface-mounted between the conductor 61 and the outer conductor 62 at a portion between the inductors 6 and 6.
  • the capacitor 23 is formed by connecting three capacitors in parallel, but is not limited to this. For example, one capacitor may be used.
  • the capacitor 21 is surface-mounted between the conductor 61 and the conductor 62 in the outer layer at a portion closer to the terminals C and D than the second inductor 6.
  • the capacitor 21 is formed by connecting three capacitors in parallel, but is not limited to this. For example, one capacitor may be used.
  • the capacitors 21 and 23 are multilayer ceramic capacitors, for example, a lead type ceramic capacitor or a film capacitor may be used.
  • the pair of conductors 61 and 62 are formed by the conductor pattern of the printed wiring board 8, an increase in the number of components, an increase in connection points, an increase in processing steps, and the like are suppressed, and noise is reduced. An effect is obtained that a DC / DC converter having a high reduction effect can be easily manufactured.
  • a bus bar can be used for the pair of conductors 61 and 62.
  • soldering or welding is separately performed between the conductors 61 and 62 and the capacitor 23 and between the conductors 61 and 62 and the capacitor 21 without depending on the connection on the printed wiring board 8. Connection and the number of connection points and man-hours increase.
  • the inductance of the composite inductor 600 is distributed to the two inductors 6 and 6 by two pairs of the pair of cores 63 and 64.
  • the volume can be reduced.
  • each inductor 6 formed by inserting a pair of conductors 61 and 62 into a through hole 60 of a pair of cores 63 and 64 is regarded as a two-terminal pair circuit including two inductance elements.
  • the two terminal pair circuits are cascaded. Therefore, the output of the first inductor 6 can be taken over by the input of the second inductor 6.
  • the FET 31 is connected in series to the primary winding 11 of the transformer 10, and the outflow current and return current to the secondary winding 12 of the transformer 10 are controlled by the pair of conductors 61 and 62 of the composite inductor 600. Flows to As a result, when the FET 31 is turned on / off, a current is induced in the secondary winding 12 of the transformer 10, and this current flows through the pair of conductors 61 and 62 in the composite inductor 600, so that the output current is effectively reduced. Can be smoothed.
  • the third embodiment is a form in which the composite inductor 600 includes the inductors 6 and 6 according to the first embodiment
  • the fourth embodiment is a form in which the composite inductor 600b includes the inductors 6b and 6b according to the second embodiment.
  • the block diagram of the DC / DC converter 100b according to the fourth embodiment is the same as that shown in FIG. 13 of the third embodiment, and only the signs of the composite inductor 600 and the inductor 6 are changed.
  • the same reference numerals are given to the portions corresponding to the third embodiment, and the description is omitted.
  • FIG. 15 is a plan view schematically showing the transformer 10 and the inductors 6b, 6b formed on the printed wiring board 8b of the DC / DC converter 100b according to the fourth embodiment.
  • a so-called PQ type core is used for the transformer 10 and an EI type core is used for the inductors 6b and 6b, the present invention is not limited to this.
  • three legs of a PQ-type core are separately inserted into three openings provided at equal intervals in a direction intersecting the longitudinal direction at one longitudinal end of the printed wiring board 8b. .
  • three legs of the EI-type cores 63b and 64b are separately inserted into three openings provided at equal intervals in the longitudinal direction at substantially the center in the longitudinal direction of the printed wiring board 8b. Have been.
  • three legs of the EI type cores 63b and 64b are separately inserted into three openings provided at equal intervals in the longitudinal direction at the other end in the longitudinal direction of the printed wiring board 8b. Have been.
  • a conductor 61 to be inserted into the two through holes 601 and 602 of the inductors 6b and 6b is formed by a conductor pattern.
  • This conductor pattern is integrated with the one-turn secondary winding 12 of the transformer 10 and the terminal C.
  • a conductor 62 inserted into the two through holes 601 and 602 of the inductors 6b and 6b is formed by a conductor pattern (shown by a broken line).
  • One end, the center, and the other end of the conductor pattern are electrically connected to different conductor patterns formed in one outer layer via via via holes 621, 622, and 623, respectively.
  • the via hole portions 621, 622, and 623 are an aggregate of via holes connecting between the specific inner layer and one of the outer layers.
  • the entirety of the conductor pattern formed on the specific inner layer and one outer layer and electrically connected in this way corresponds to the conductor 62.
  • a conductor pattern formed on one outer layer at the other end in the longitudinal direction of the printed wiring board 8b is integrated with the terminal D.
  • the primary winding 11 of the transformer 10 is spirally formed in the inner layer of the printed wiring board 8.
  • the primary winding 11 is shown by a broken line except for an overlapping portion with the conductor 61 and the secondary winding 12.
  • the conductor 62 is indicated by a broken line including a portion where the conductor 62 overlaps the conductor 62.
  • the FET 51b is surface-mounted between the secondary winding 12 and the outer conductor 62 at a location between the transformer 10 and the first inductor 6b.
  • An FET 52b is surface-mounted between a conductor 61 and an outer conductor 62 at a portion between the transformer 10 and the first inductor 6b.
  • the capacitor 23 is surface-mounted between the conductor 61 and the outer conductor 62 in a portion between the inductors 6b, 6b.
  • the capacitor 21 is surface-mounted between the conductor 61 and the outer conductor 62 at a portion closer to the terminals C and D than the second inductor 6b.
  • FIG. 16A is a graph illustrating frequency components of switching noise caused by the DC / DC converter 100 according to the second embodiment.
  • FIG. 16B is a graph illustrating frequency components of switching noise caused by the DC / DC converter 100b according to the fourth embodiment.
  • the vertical axis represents the noise level (dB ⁇ V)
  • the horizontal axis represents the relative frequency to the switching frequency (fundamental wave).
  • a broken line indicated by a dashed line in the drawing is a series of peaks of a fundamental wave and a harmonic wave of noise.
  • the volumes of the cores 63b and 64b, the inductance of the inductor 6b, and the capacitances of the capacitors 21 and 23 used in the simulation are as follows.
  • the cores 63b and 64b according to the second embodiment use the cores 63b and 64b having a volume ratio of about 1/4. Also, the noise level of harmonics can be reduced by 10 dB to 20 dB or more.
  • the inductance of the composite inductor 600b is distributed to the two inductors 6b and 6b by the two pairs of the pair of cores 63b and 64b.
  • the volume can be reduced.
  • each of the inductors 6b formed by inserting the pair of conductors 61 and 62 into the two through holes 601 and 602 of the pair of cores 63b and 64b has two terminals including two inductance elements. It is regarded as a pair circuit, and each two-terminal pair circuit is cascaded. Therefore, the output of the first inductor 6b can be taken over by the input of the second inductor 6b.
  • a two-stage low-pass filter can be formed. it can.
  • the conductor 61 is formed integrally with the secondary winding 12 and the terminal C of the transformer 10 and the conductor 62 is formed integrally with the terminal D, Can be reduced.
  • FIG. 17 is a circuit diagram illustrating a configuration example of the DC / DC converter 100 according to the fifth embodiment.
  • the inductor 6 is provided on the input side (the primary winding 11 side) of the transformer 10.
  • the details of the inductor 6 of the fifth embodiment are the same as those of the inductor 6 described above.
  • the same inductance for example, 1 to 3 ⁇ H as the above-described inductor 6 is required.
  • the DC / DC converter 100 is of a full-bridge type, and four switching elements 35, 36, 37, and 38 forming a full bridge are provided on the input side (primary winding 11 side) of a transformer 10. Have been.
  • the full bridge is configured by connecting switching elements 35 and 36 connected in series and switching elements 37 and 38 connected in series.
  • the inductors 6 according to the first to fourth embodiments are provided on the output side (the secondary winding 12 side) of the transformer 10 included in the DC / DC converter 100.
  • the inductors 6 according to the first to fourth embodiments are used to smooth an AC current and convert it to a DC.
  • the inductor 6 is provided on the input side (the primary winding 11 side) of the transformer 10 included in the DC / DC converter 100.
  • the inductor 6 of the fifth embodiment is used for performing a ZVS (Zero Voltage Switching) operation due to a resonance phenomenon.
  • one end of the first conductor 61 is connected between the switching element 35 and the switching element 36 connected in series.
  • the other end of the first conductor 61 is connected to one end of the primary winding 11 of the transformer 10. Therefore, the switching element 35, the first conductor 61 (the inductor 6), and the primary winding 11 are connected in series.
  • One end of the second conductor is connected between the switching element 35 and the switching element 36 connected in series.
  • the other end of the second conductor 62 is connected to the other end of the primary winding 11 of the transformer 10. Therefore, the switching element 37, the second conductor 62 (the inductor 6), and the primary winding 11 are connected in series.
  • the switching element 35, the first conductor 61, the first winding 11, the second conductor 62, and the switching element 38 are connected in series. Therefore, when the switching element 35 and the switching element 38 are turned on, a current flows from the switching element 35 to the switching element 38 in the order of the first conductor 61, the first winding 11, and the second conductor 62. In this case, the first current flows through the first conductor 61 and goes to the primary winding 11 which is a circuit element outside the inductor 6.
  • the second current is a current that returns to the second conductor 62 via the primary winding 11.
  • the switching element 37, the second conductor 62, the first winding 11, the first conductor 61, and the switching element 36 are connected in series. Therefore, when the switching element 37 and the switching element 36 are turned on, a current flows from the switching element 37 to the switching element 36 in the order of the second conductor 62, the first winding 11, and the first conductor 61. In this case, the second current flows through the second conductor 62 and goes to the primary winding 11 which is a circuit element outside the inductor 6.
  • the first current is a current in which the second current returns to the first conductor 61 via the primary winding 11.
  • the magnitude of the current flowing through the first conductor 61 and the second conductor 62 is assumed to be in the range of 5 to 20 A, and is a relatively small current.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The disclosed inductor is provided with a core having a first through-hole, a first electrical conductor which has a part inserted through the first through-hole, and through which a first current flows, and a second electrical conductor which has a part inserted through the first through-hole, and through which a second current flows, wherein: one of the first current and the second current is a current comprising the other current, returning to the inductor by way of a portion outside the inductor; and the directions of the first current and the second current in the first through-hole are the same as the direction of penetration through the first through-hole.

Description

インダクタ、複合インダクタ、ＤＣ／ＤＣコンバータ及び回路Inductors, composite inductors, DC / DC converters and circuits
　本開示は、インダクタ、複合インダクタ、ＤＣ／ＤＣコンバータ及び回路に関する。本出願は、２０１８年７月３０日出願の日本出願第２０１８－１４２５０２号に基づく優先権及び２０１８年１０月１１日出願の日本出願第２０１８－１９２８４５号に基づく優先権を主張し、これら日本出願に記載された全ての記載内容を援用するものである。 The present disclosure relates to an inductor, a composite inductor, a DC / DC converter, and a circuit. This application claims the priority based on Japanese Patent Application No. 2018-142502 filed on Jul. 30, 2018 and the priority based on Japanese Patent Application No. 2018-192845 filed on Oct. 11, 2018. All the contents described in the above are used.
　直流電圧を昇降圧するＤＣ／ＤＣコンバータ（以下、単にコンバータともいう）が車載機器や産業用機器の電源として広く用いられている。コンバータの種類は、入出力間をトランスで絶縁するか否かによって絶縁型及び非絶縁型に分けられる。絶縁型のコンバータの制御方式は、フォワード方式及びフライバック方式に分けられる。 2. Description of the Related Art DC / DC converters (hereinafter, also simply referred to as converters) for raising and lowering a DC voltage are widely used as power supplies for in-vehicle equipment and industrial equipment. Converters are classified into an insulated type and a non-insulated type depending on whether or not the input and output are insulated by a transformer. The control method of the insulated converter is divided into a forward method and a flyback method.
　一般的に絶縁型のフォワード方式によるコンバータでは、出力電流が流れる二次側の回路の高電位側に、巻線をコアに巻回した１つのチョークコイル（インダクタ）が介装される（特許文献１参照）。 In general, in an insulated forward converter, a single choke coil (inductor) having a winding wound around a core is interposed on the high potential side of a secondary circuit through which an output current flows (Japanese Patent Application Laid-Open No. H11-163873). 1).
特開平１１－２０６１１８号公報JP-A-11-206118
　本開示の一態様に係るインダクタは、第１貫通孔を有するコアと、前記第１貫通孔に挿通された部位を有し、第１電流が流れる第１導電体と、前記第１貫通孔に挿通された部位を有し、第２電流が流れる第２導電体と、を備え、前記第１電流及び前記第２電流のうちの一方の電流は、他方の電流が前記インダクタ外部を経由して前記インダクタへ戻る電流であり、前記第１貫通孔内における前記第１電流及び前記第２電流の向きは、前記第１貫通孔の貫通方向に対して同一である。 An inductor according to an embodiment of the present disclosure includes a core having a first through-hole, a portion inserted into the first through-hole, a first conductor through which a first current flows, and a first conductor passing through the first through-hole. And a second conductor through which a second current flows, wherein one of the first current and the second current is generated when the other current passes through the outside of the inductor. The direction of the first current and the second current in the first through hole, which is the current returning to the inductor, is the same as the direction of the first through hole.
　本開示の一態様に係る複合インダクタは、上述のインダクタを含む複合インダクタであって、前記第１導電体及び第２導電体が前記第１貫通孔に挿通された前記コアを複数備える。 複合 A composite inductor according to an aspect of the present disclosure is a composite inductor including the above-described inductor, and includes a plurality of the cores in which the first conductor and the second conductor are inserted into the first through-hole.
　本開示の一態様に係るＤＣ／ＤＣコンバータは、上述のインダクタ又は複合インダクタと、スイッチング素子と、一次巻線が前記スイッチング素子に直列に接続されたトランスとを備え、前記第１導電体は、前記トランスの二次巻線から外部へ流出する流出電流が前記第１電流として流れるよう接続され、前記第２導電体は、外部から前記二次巻線に戻る戻り電流が前記第２電流として流れるように接続されている。 A DC / DC converter according to an aspect of the present disclosure includes the above-described inductor or composite inductor, a switching element, and a transformer having a primary winding connected in series to the switching element, wherein the first conductor includes: An outflow current flowing out of the secondary winding of the transformer to the outside is connected so as to flow as the first current, and the second conductor is a return current returning to the secondary winding from the outside flows as the second current. Connected.
　なお、本願は、このような特徴的な構成を備えるインダクタ、複合インダクタ及びＤＣ／ＤＣコンバータとして実現することができるだけでなく、ＤＣ／ＤＣコンバータの一部を半導体集積回路として実現したり、インダクタ、複合インダクタ又はＤＣ／ＤＣコンバータを含むその他のシステムとして実現したりすることができる。 The present application can be realized not only as an inductor, a composite inductor, and a DC / DC converter having such a characteristic configuration, but also as a part of the DC / DC converter as a semiconductor integrated circuit, Or may be implemented as a composite inductor or other system including a DC / DC converter.
図１は、実施形態１に係るＤＣ／ＤＣコンバータの構成例を示すブロック図である。FIG. 1 is a block diagram illustrating a configuration example of the DC / DC converter according to the first embodiment. 図２は、トランスの一次側から二次側に電力を伝達する期間での動作状態の一例を示す説明図である。FIG. 2 is an explanatory diagram illustrating an example of an operation state during a period in which power is transmitted from the primary side to the secondary side of the transformer. 図３は、トランスの二次側で負荷電流が還流する期間での動作状態の一例を示す説明図である。FIG. 3 is an explanatory diagram illustrating an example of an operation state during a period in which the load current flows back on the secondary side of the transformer. 図４は、実施形態１に係るインダクタを斜め上方から見た斜視図である。FIG. 4 is a perspective view of the inductor according to the first embodiment as viewed obliquely from above. 図５は、図４のＶ－Ｖ線断面図であり、実施形態１に係るインダクタの組み立て後の状態を模式的に示す縦断面図である。FIG. 5 is a cross-sectional view taken along line VV of FIG. 4, and is a longitudinal cross-sectional view schematically illustrating a state after the inductor according to the first embodiment is assembled. 図６は、実施形態２に係るインダクタを斜め上方から見た斜視図である。FIG. 6 is a perspective view of the inductor according to the second embodiment as viewed obliquely from above. 図７は、図６のＶＩＩ－ＶＩＩ線断面図であり、実施形態２に係るインダクタの組み立て後の状態を模式的に示す縦断面図である。FIG. 7 is a cross-sectional view taken along line VII-VII of FIG. 6, and is a longitudinal cross-sectional view schematically illustrating a state after assembly of the inductor according to the second embodiment. 図８Ａは、実施形態２に係る貫通孔の双方に挿通された第１導電体を示す平面図である。FIG. 8A is a plan view showing a first conductor inserted into both of the through holes according to the second embodiment. 図８Ｂは、実施形態２に係る貫通孔の双方に挿通された第２導電体を示す平面図である。FIG. 8B is a plan view illustrating the second conductor inserted into both of the through holes according to the second embodiment. 図９Ａは、変形例１に係る貫通孔の全てに挿通された第１導電体を示す平面図である。FIG. 9A is a plan view showing the first conductor inserted into all of the through holes according to the first modification. 図９Ｂは、変形例１に係る貫通孔の全てに挿通された第２導電体を示す平面図である。FIG. 9B is a plan view showing the second conductor inserted through all of the through holes according to the first modification. 図１０Ａは、変形例２に係る第１導電体を模式的に示す平面図である。FIG. 10A is a plan view schematically illustrating a first conductor according to Modification Example 2. FIG. 図１０Ｂは、変形例２に係る第２導電体を模式的に示す平面図である。FIG. 10B is a plan view schematically showing a second conductor according to Modification 2. 変形例３に係るインダクタを斜め上方から見た斜視図である。FIG. 13 is a perspective view of an inductor according to Modification Example 3 as viewed obliquely from above. 筐体に取り付けたインダクタを模式的に示す側面図である。It is a side view which shows the inductor attached to the housing | casing typically. 実施形態３に係るＤＣ／ＤＣコンバータの構成例を示すブロック図である。FIG. 11 is a block diagram illustrating a configuration example of a DC / DC converter according to a third embodiment. 実施形態３に係るＤＣ／ＤＣコンバータの印刷配線基板上に形成されたトランス及びインダクタを模式的に示す平面図である。FIG. 13 is a plan view schematically showing a transformer and an inductor formed on a printed wiring board of the DC / DC converter according to the third embodiment. 実施形態４に係るＤＣ／ＤＣコンバータの印刷配線基板上に形成されたトランス及びインダクタを模式的に示す平面図である。FIG. 13 is a plan view schematically illustrating a transformer and an inductor formed on a printed wiring board of the DC / DC converter according to the fourth embodiment. 図１６Ａは、実施形態２に係るＤＣ／ＤＣコンバータによるスイッチングノイズの周波数成分を示すグラフである。FIG. 16A is a graph illustrating frequency components of switching noise caused by the DC / DC converter according to the second embodiment. 図１６Ｂは、実施形態４に係るＤＣ／ＤＣコンバータによるスイッチングノイズの周波数成分を示すグラフである。FIG. 16B is a graph illustrating frequency components of switching noise caused by the DC / DC converter according to the fourth embodiment. 図１７は、実施形態５に係るＤＣ／ＤＣコンバータの構成例を示す回路図である。FIG. 17 is a circuit diagram illustrating a configuration example of a DC / DC converter according to the fifth embodiment.
［本開示における実施形態が解決しようとする課題］
　前述のように、特許文献１に記載のコンバータでは、二次側の回路の高圧電位側にインダクタが介装されている。このインダクタに必要とされるインダクタンスの大きさは、スイッチをオン／オフするスイッチング周波数に反比例するため、インダクタを小型化するにはスイッチング周波数を比較的高くしなければならない。 [Problems to be solved by embodiments of the present disclosure]
As described above, in the converter described in Patent Literature 1, the inductor is interposed on the high voltage side of the secondary circuit. Since the magnitude of the inductance required for this inductor is inversely proportional to the switching frequency at which the switch is turned on / off, the switching frequency must be relatively high in order to reduce the size of the inductor.
　しかしながら、コンバータにおけるスイッチのスイッチング周波数を高くするほどスイッチングロスが増加したり、配線が難しくなったりするトレードオフがあり、インダクタの小型化に必要とされるところまでスイッチング周波数を高くするには課題が多い。特に、コアに挿通する導体部を巻形状にしない場合は、必要なインダクタンスを確保することが困難であった。 However, as the switching frequency of the switch in the converter increases, there is a trade-off in that the switching loss increases and the wiring becomes difficult, and there is a problem in increasing the switching frequency to the point required for downsizing of the inductor. Many. In particular, it is difficult to secure a necessary inductance unless the conductor portion inserted into the core is formed in a wound shape.
　コアに挿通する導体を巻形状にしない場合であっても必要なインダクタンスを確保することが可能であることが望まれる。 It is desired that the required inductance can be ensured even when the conductor inserted into the core is not wound.
［本開示の実施形態の説明］
　最初に本開示の実施態様を列記して説明する。また、以下に記載する実施形態の少なくとも一部を任意に組み合わせてもよい。 [Description of Embodiment of the Present Disclosure]
First, embodiments of the present disclosure will be listed and described. Further, at least some of the embodiments described below may be arbitrarily combined.
（１）本開示の一態様に係るインダクタは、第１貫通孔を有するコアと、前記第１貫通孔に挿通された部位を有し、第１電流が流れる第１導電体と、前記第１貫通孔に挿通された部位を有し、第２電流が流れる第２導電体と、を備え、前記第１電流及び前記第２電流のうちの一方の電流は、他方の電流が前記インダクタ外部を経由して前記インダクタへ戻る電流であり、前記第１貫通孔内における前記第１電流及び前記第２電流の向きは、前記第１貫通孔の貫通方向に対して同一である。 (1) An inductor according to an aspect of the present disclosure includes a core having a first through-hole, a first conductor having a portion inserted through the first through-hole, and through which a first current flows; A second conductor having a portion inserted through the through-hole and through which a second current flows, wherein one of the first current and the second current is connected to the outside of the inductor by the other current. And the direction of the first current and the second current in the first through-hole is the same as the direction of the penetration of the first through-hole.
　本態様にあっては、コアには、第１貫通孔が形成されている。第１貫通孔に挿通された第１導電体及び第２導電体は、第１電流及び第２電流が、第１貫通孔の貫通方向に対して同一方向に流れるように外部と接続される。これにより、コアの貫通孔に１つの導電体を挿通する場合と比較して、起磁力Ｆ（Ｆ＝ＮＩ：Ｎは巻数、Ｉは電流）が２倍となり、インダクタンスが略４倍になる。 In this aspect, the core has the first through hole formed therein. The first conductor and the second conductor inserted into the first through-hole are connected to the outside such that the first current and the second current flow in the same direction as the direction in which the first through-hole penetrates. As a result, the magnetomotive force F (F = NI: N is the number of turns and I is the current) is doubled and the inductance is substantially quadrupled as compared with the case where one conductor is inserted into the through hole of the core.
（２）前記コアは、前記第１貫通孔と同一方向に貫通する第２貫通孔を更に備え、前記第１導電体は、前記第２貫通孔に挿通された部位を更に有し、前記第２導電体は、前記第２貫通孔に挿通された部位を更に有し、前記第２貫通孔内における前記第１電流及び前記第２電流の向きは、前記第２貫通孔の貫通方向に対して同一であり、前記第１貫通孔内における前記第１電流及び前記第２電流の向きとは逆であることが好ましい。なお、コアは、３以上の貫通孔を備えてもよい。 (2) The core further includes a second through-hole penetrating in the same direction as the first through-hole, the first conductor further includes a portion inserted through the second through-hole, The two conductor further has a portion inserted into the second through-hole, and the directions of the first current and the second current in the second through-hole are relative to a direction in which the second through-hole passes. Preferably, the directions of the first current and the second current in the first through hole are opposite to each other. Note that the core may include three or more through holes.
　本態様にあっては、貫通方向が同一方向に揃っている第１貫通孔及び第２貫通孔がコアに形成されている。第２貫通孔内における第１電流及び第２電流の向きは、第１貫通孔内における第１電流及び第２電流の向きとは逆になるように構成されている。これにより、第１貫通孔と第２貫通孔との間のコア内で磁束が打ち消し合うことがなく、貫通孔の数に略比例してインダクタンスが更に増大する。 In this embodiment, the first through-hole and the second through-hole whose through directions are aligned in the same direction are formed in the core. The directions of the first current and the second current in the second through-hole are configured to be opposite to the directions of the first current and the second current in the first through-hole. As a result, the magnetic flux does not cancel each other in the core between the first through hole and the second through hole, and the inductance further increases substantially in proportion to the number of the through holes.
（３）前記第１導電体は、第１Ｕ字状部を有し、前記第１Ｕ字状部は、前記第１導電体が前記第１貫通孔に挿通された前記部位及び前記第２貫通孔に挿通された前記部位を含むことが好ましい。 (3) The first conductor has a first U-shaped portion, and the first U-shaped portion includes the portion where the first conductor is inserted into the first through hole and the second through hole. It is preferable to include the above-mentioned part penetrated.
　本態様にあっては、第１貫通孔及び第２貫通孔に挿通された部位及びこれらの部位を接続する部位がＵ字状をなしている。これにより、導電体が、平面視にて点対称又は線対称の比較的単純な形状となる。 In this aspect, the portions inserted into the first through-hole and the second through-hole and the portions connecting these portions are U-shaped. As a result, the conductor has a relatively simple shape that is point-symmetric or line-symmetric in plan view.
（４）前記第２導電体は、前記第１Ｕ字状部に対して逆向きになるように配置された第２Ｕ字状部を有し、前記第２Ｕ字状部は、前記第２導電体が前記第１貫通孔に挿通された前記部位及び前記第２貫通孔に挿通された前記部位を含むことが好ましい。 (4) The second conductor has a second U-shaped portion disposed so as to be opposite to the first U-shaped portion, and the second U-shaped portion is formed of the second conductor. Preferably includes the portion inserted through the first through-hole and the portion inserted through the second through-hole.
　本態様にあっては、第１導電体及び第２導電体におけるＵ字状部が互いに逆向きに構成されている。これにより、第１導電体及び第２導電体の一端同士及び他端同士が貫通孔の貫通方向の両側に離隔されるため、外部との接続が容易となる。 In this aspect, the U-shaped portions of the first conductor and the second conductor are configured to be opposite to each other. Accordingly, one end and the other end of the first conductor and the second conductor are separated from each other on both sides in the through direction of the through hole, so that connection to the outside is facilitated.
（５）前記コアは、ＥＥ型、ＥＩ型及びＥＲ型の何れかであることが好ましい。 (5) The core is preferably any of EE type, EI type and ER type.
　本態様にあっては、突き合わせた状態で２つの貫通孔を有するＥＥ型、ＥＩ型及びＥＲ型の何れかのコアを用いるため、広く普及しているコアが利用できる。 In this embodiment, any of the EE type, EI type and ER type cores having two through holes in abutted state is used, so that widely used cores can be used.
（６）前記第１導電体及び前記第２導電体の夫々は、断面が矩形状をなしていることが好ましい。 (6) It is preferable that each of the first conductor and the second conductor has a rectangular cross section.
　本態様にあっては、第１導電体及び第２導電体夫々の断面が矩形状であるため、断面の短辺方向の厚さを抑えることができる。また、第１導電体及び第２導電体夫々の断面積に対する表面積が大きいため、放熱性が良好である。 In this aspect, since the cross section of each of the first conductor and the second conductor is rectangular, the thickness of the cross section in the short side direction can be suppressed. Further, since the surface area with respect to the cross-sectional area of each of the first conductor and the second conductor is large, heat dissipation is good.
（７）前記第１導電体及び前記第２導電体は、多層配線基板の異なる層に含まれる導体パターンであることが好ましい。 (7) It is preferable that the first conductor and the second conductor are conductor patterns included in different layers of a multilayer wiring board.
　本態様にあっては、多層配線基板の異なる内層又は外層に含まれる導体パターンを第１導電体及び第２導電体として用いるため、周辺回路を含めて第１導電体及び第２導電体を容易に形成することができる。 In this aspect, since the conductor patterns included in different inner layers or outer layers of the multilayer wiring board are used as the first conductor and the second conductor, the first conductor and the second conductor including the peripheral circuit can be easily formed. Can be formed.
（８）前記コアは、フェライトコア又は磁性体圧粉コアであることが好ましい。フェライトコアは、磁性体を焼結して形成される。圧粉コアは、磁性体を含む粉末を加圧して形成される。 (8) Preferably, the core is a ferrite core or a magnetic material dust core. The ferrite core is formed by sintering a magnetic material. The dust core is formed by pressing powder containing a magnetic material.
　本態様にあっては、コアがフェライトコア又は圧粉コアであるため、高周波特性が良好である。なお、コアは、ナノ結晶軟磁性材料コアであってもよいし、アモルファスコアであってもよい。 高周波 In this embodiment, since the core is a ferrite core or a dust core, high-frequency characteristics are good. Note that the core may be a nanocrystalline soft magnetic material core or an amorphous core.
（９）インダクタは、伝熱材料を含む伝熱層を更に備えることが好ましい。
　前記伝熱層は、
　　前記第１導電体と、前記第２導電体と、の間、及び、
　　前記第１導電体及び前記第２導電体と、前記コアと、の間
の少なくとも何れか一方に配置されているのが好ましい。 (9) The inductor preferably further includes a heat transfer layer containing a heat transfer material.
The heat transfer layer,
Between the first conductor and the second conductor, and
It is preferable that the core is disposed on at least one of the first and second conductors and the core.
　本態様にあっては、一対の導電体の間及び一対の導電体とコアとの間の何れか一方又は両方に伝熱材料が介装されているため、導電体で発生した熱が貫通孔の外部に伝熱される。 In this embodiment, since the heat transfer material is interposed between the pair of conductors and / or between the pair of conductors and the core, the heat generated in the conductors passes through holes. Heat is transferred to the outside.
（１０）前記コアは、互いに突き合わせ可能な一対のコア部材を備え、前記第１貫通孔は、前記一対のコア部材を突き合せた状態で突合せ面に沿った方向に貫通しているのが好ましい。 (10) It is preferable that the core includes a pair of core members that can abut each other, and that the first through hole penetrates in a direction along the abutting surface in a state where the pair of the core members abut each other. .
（１１）本開示の一態様に係る複合インダクタは、上述のインダクタを含む複合インダクタであって、前記第１導電体及び前記第２導電体が前記第１貫通孔に挿通された前記コアを複数備える。 (11) A composite inductor according to an aspect of the present disclosure is a composite inductor including the above-described inductor, and includes a plurality of the cores each having the first conductor and the second conductor inserted through the first through hole. Prepare.
　本態様にあっては、複数のコアによって全体のインダクタンスが複数のインダクタに分散されるため、各コアのサイズを小さくすることができる。 According to the present aspect, since the entire inductance is distributed to the plurality of inductors by the plurality of cores, the size of each core can be reduced.
（１２）各コアの前記第１貫通孔に前記第１導電体及び第２導電体が挿通されることによって形成されるインダクタによる２端子対回路が縦続接続となるようにしてあることが好ましい。 (12) It is preferable that a two-terminal pair circuit formed by inserting the first conductor and the second conductor into the first through hole of each core is cascaded.
　本態様にあっては、コアの第１貫通孔及び第２貫通孔に第１導電体及び第２導電体が挿通されて形成されるインダクタが２つのインダクタンス要素を含む２端子対回路と見なされ、各２端子対回路が縦続接続されている。これにより、各２端子対回路の伝送特性に基づいて全体の伝送特性が導き出される。 In this aspect, the inductor formed by inserting the first conductor and the second conductor into the first through hole and the second through hole of the core is regarded as a two-terminal pair circuit including two inductance elements. , Each two-terminal pair circuit is cascaded. As a result, the overall transmission characteristics are derived based on the transmission characteristics of each two-port pair circuit.
（１３）少なくとも１つの前記２端子対回路における一方の端子対にキャパシタを接続してあることが好ましい。 (13) It is preferable that a capacitor is connected to one terminal pair in at least one of the two-terminal pair circuits.
　本態様にあっては、縦続接続された複数の２端子対回路における少なくとも１つの端子対にキャパシタが接続されているため、低域通過フィルタが形成される。 In this embodiment, since the capacitor is connected to at least one terminal pair in the cascade-connected two-terminal pair circuit, a low-pass filter is formed.
（１４）本開示の一態様に係るＤＣ／ＤＣコンバータは、上述のインダクタと、スイッチング素子と、一次巻線が前記スイッチング素子に直列に接続されたトランスとを備え、前記第１導電体は、前記トランスの二次巻線から外部へ流出する流出電流が前記第１電流として流れるように接続され、前記第２導電体は、外部から前記二次巻線に戻る戻り電流が第２電流として流れるように接続されている。 (14) A DC / DC converter according to an aspect of the present disclosure includes the above-described inductor, a switching element, and a transformer having a primary winding connected in series to the switching element. An outflow current flowing out of the secondary winding of the transformer to the outside is connected so as to flow as the first current, and the second conductor is a return current returning from the outside to the secondary winding as the second current. Connected.
　本態様にあっては、トランスの一次巻線にスイッチング素子が直列に接続され、トランスの二次巻線に対する流出電流及び戻り電流がインダクタの第１導電体及び第２導電体に流れる。これにより、スイッチング素子がオン／オフしたときにトランスの二次巻線に電流が誘起し、この電流が上述のインダクタにおける第１導電体及び第２導電体に流れるため、出力電流が効果的に平滑される。 In this embodiment, the switching element is connected in series to the primary winding of the transformer, and the outflow current and return current to the secondary winding of the transformer flow through the first and second conductors of the inductor. As a result, when the switching element is turned on / off, a current is induced in the secondary winding of the transformer, and this current flows through the first conductor and the second conductor of the inductor, so that the output current is effectively reduced. Smoothed.
（１５）本開示の一態様に係るＤＣ／ＤＣコンバータは、上述の複合インダクタと、スイッチング素子と、一次巻線が前記スイッチング素子に直列に接続されたトランスとを備え、前記第１導電体は、前記トランスの二次巻線から外部へ流出する流出電流が前記第１電流として流れるように接続され、前記第２導電体は、外部から前記二次巻線に戻る戻り電流が前記第２電流として流れるように接続されている。 (15) A DC / DC converter according to an aspect of the present disclosure includes the above-described composite inductor, a switching element, and a transformer having a primary winding connected in series to the switching element. The current flowing out of the secondary winding of the transformer to the outside is connected as the first current, and the second conductor is connected to the return current returning from the outside to the secondary winding by the second current. Connected as flowing.
　本態様にあっては、トランスの一次巻線にスイッチング素子が直列に接続され、トランスの二次巻線に対する流出電流及び戻り電流が複合インダクタの第１導電体及び第２導電体に流れる。これにより、スイッチング素子がオン／オフしたときにトランスの二次巻線に電流が誘起し、この電流が上述の複合インダクタにおける第１導電体及び第２導電体に流れるため、出力電流が効果的に平滑される。 In this embodiment, the switching element is connected in series to the primary winding of the transformer, and the outflow current and return current to the secondary winding of the transformer flow through the first conductor and the second conductor of the composite inductor. Thereby, when the switching element is turned on / off, a current is induced in the secondary winding of the transformer, and this current flows through the first conductor and the second conductor in the above-described composite inductor, so that the output current is effectively reduced. Is smoothed.
（１６）前記第１導電体は、前記二次巻線と一体的に形成されており、前記第１導電体及び前記第２導電体の少なくとも一方が出力側の電路と一体的に形成されていることが好ましい。 (16) The first conductor is formed integrally with the secondary winding, and at least one of the first conductor and the second conductor is formed integrally with an output-side electric path. Is preferred.
　本態様にあっては、第１導電体がトランスの二次巻線と一体的に形成され、第１導電体及び第２導電体の少なくとも一方が出力側の電路と一体的に形成されるため、部品間の接合箇所を削減することができる。なお、第１導電体及び第２導電体の両方が、出力側の電路と一体的に形成されてもよい。 In this aspect, the first conductor is formed integrally with the secondary winding of the transformer, and at least one of the first conductor and the second conductor is formed integrally with the output-side electric circuit. Thus, the number of joints between components can be reduced. Note that both the first conductor and the second conductor may be formed integrally with the electric circuit on the output side.
（１７）本開示の一態様に係るＤＣ／ＤＣコンバータは、上述のインダクタと、スイッチング素子と、一次巻線を有するトランスと、を備え、少なくとも、前記スイッチング素子と、前記インダクタと、前記一次巻線と、が直列接続されている。 (17) A DC / DC converter according to an aspect of the present disclosure includes the above-described inductor, a switching element, and a transformer having a primary winding, and at least the switching element, the inductor, and the primary winding. And are connected in series.
　本態様にあっては、インダクタと、スイッチング素子と、一次巻線と、が直列接続されているため、スイッチング素子がオン／オフしたときに、インダクタを介して、トランスの一次巻線に電流が流れる。 In this aspect, since the inductor, the switching element, and the primary winding are connected in series, when the switching element is turned on / off, a current flows to the primary winding of the transformer via the inductor. Flows.
（１８）本開示の一態様に係る回路は、上述のインダクタと、前記インダクタ外部において、前記第１導電体及び前記第２導電体に直列接続された回路素子と、を備える。 (18) A circuit according to one embodiment of the present disclosure includes the above-described inductor, and a circuit element connected in series to the first conductor and the second conductor outside the inductor.
　本態様にあっては、前記第１導電体と、前記回路素子と、前記第２導電体と、が直列接続されているため、第１電流又は第２電流の一方の電流が、回路素子を通ることで、第２電流となる。 In the present aspect, since the first conductor, the circuit element, and the second conductor are connected in series, one of the first current and the second current flows through the circuit element. Passing it becomes the second current.
［本開示の実施形態の詳細］
　本開示の実施形態に係るインダクタ、複合インダクタ及びＤＣ／ＤＣコンバータの具体例を、以下に図面を参照しつつ説明する。なお、本発明はこれらの例示に限定されるものではなく、特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。また、各実施形態で記載されている技術的特徴は、お互いに組み合わせることが可能である。 [Details of Embodiment of the Present Disclosure]
Specific examples of the inductor, the composite inductor, and the DC / DC converter according to the embodiment of the present disclosure will be described below with reference to the drawings. It should be noted that the present invention is not limited to these exemplifications, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims. Further, the technical features described in each embodiment can be combined with each other.
（実施形態１）
　図１は、実施形態１に係るＤＣ／ＤＣコンバータ１００の構成例を示すブロック図である。ＤＣ／ＤＣコンバータ１００は、トランス１０を備え、入力側の端子Ａ及びＢの電位と出力側の端子Ｃ及びＤの電位とがトランス１０によって分離されている。入力側の端子Ａ及びＢ間には、キャパシタ２０が接続されており、外部の直流電源（不図示）から所定電圧が印加される。出力側の端子Ｃ及びＤ間には、キャパシタ２１が接続されており、更に外部の負荷が接続される。端子Ｄは例えば接地電位に接続されている。 (Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration example of the DC / DC converter 100 according to the first embodiment. The DC / DC converter 100 includes a transformer 10, and the potential of the input-side terminals A and B and the potential of the output-side terminals C and D are separated by the transformer 10. A capacitor 20 is connected between the terminals A and B on the input side, and a predetermined voltage is applied from an external DC power supply (not shown). A capacitor 21 is connected between the output side terminals C and D, and an external load is further connected. The terminal D is connected to, for example, the ground potential.
　ＤＣ／ＤＣコンバータ１００は、また、トランス１０の一次巻線１１の一端及び端子Ｂ間に接続されたＮｃｈ型のＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ：以下、ＦＥＴと言う）３１（スイッチング素子に相当）と、一次巻線１１の一端及び端子Ａ間に接続されたＦＥＴ３２及びキャパシタ２２の直列回路と、ＦＥＴ３１及び３２のオン／オフを制御する制御部４とを備える。一次巻線１１は、他端が端子Ａに接続されている。ＦＥＴ３１及び３２は、バイポーラトランジスタ、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）等の他のスイッチング素子であってもよい。 The DC / DC converter 100 also includes an Nch-type MOSFET (Metal Oxide Semiconductor Connector Field Effect Transistor: hereinafter referred to as an FET) 31 (corresponding to a switching element) connected between one end of the primary winding 11 of the transformer 10 and the terminal B. ), A series circuit of the FET 32 and the capacitor 22 connected between one end of the primary winding 11 and the terminal A, and a control unit 4 for controlling on / off of the FETs 31 and 32. The other end of the primary winding 11 is connected to the terminal A. The FETs 31 and 32 may be other switching elements such as a bipolar transistor and an IGBT (Insulated Gate Bipolar Transistor).
　ＦＥＴ３１は、ドレインが一次巻線１１の一端に接続され、ソースが端子Ｂに接続され、ゲートが制御部４に接続されている。ＦＥＴ３２は、ドレインがキャパシタ２２の一端に接続され、ソースが一次巻線１１の一端に接続され、ゲートが制御部４に接続されている。キャパシタ２２の他端は、端子Ａに接続されている。ＦＥＴ３１及び３２の夫々は、両端に逆並列に接続されたボディダイオードを有する。アクティブクランプ回路を構成するＦＥＴ３２及びキャパシタ２２は、直列に接続する順序を入れ換えてもよい。 The FET 31 has a drain connected to one end of the primary winding 11, a source connected to the terminal B, and a gate connected to the control unit 4. The FET 32 has a drain connected to one end of the capacitor 22, a source connected to one end of the primary winding 11, and a gate connected to the control unit 4. The other end of the capacitor 22 is connected to the terminal A. Each of the FETs 31 and 32 has a body diode connected in anti-parallel at both ends. The order in which the FET 32 and the capacitor 22 constituting the active clamp circuit are connected in series may be changed.
　トランス１０の二次巻線１２は、一端にダイオード５１のカソードが接続され、他端にダイオード５２のカソードが接続されている。ダイオード５２のカソードは、更に、チョークコイルとしてのインダクタ６に含まれる導電体６１を介してキャパシタ２１の一端及び端子Ｃに接続されている。ダイオード５１及び５２のアノードは、インダクタ６に含まれる導電体６２を介してキャパシタ２１の他端及び端子Ｄに接続されている。 The secondary winding 12 of the transformer 10 has one end connected to the cathode of the diode 51 and the other end connected to the cathode of the diode 52. The cathode of the diode 52 is further connected to one end of the capacitor 21 and the terminal C via a conductor 61 included in the inductor 6 as a choke coil. The anodes of the diodes 51 and 52 are connected to the other end of the capacitor 21 and the terminal D via a conductor 62 included in the inductor 6.
　インダクタ６は、一対のコア及び導電体６１，６２を含んで一体化されている。なお、回路図上は、インダクタ６はコアにコイルが巻回されたものであるかのように表されているが、本実施形態１では、導電体６１，６２がコイルに相当する。インダクタ６の詳細については後述する。 The inductor 6 is integrated including the pair of cores and the conductors 61 and 62. In the circuit diagram, the inductor 6 is represented as if a coil is wound around a core. However, in the first embodiment, the conductors 61 and 62 correspond to the coil. Details of the inductor 6 will be described later.
　上述の構成を有するＤＣ／ＤＣコンバータ１００は、いわゆる１石式のフォワードコンバータであり、端子Ａ及びＢから供給される所定電圧を｛（ＦＥＴ３１のデューティ比）／（トランス１０の巻数比）｝倍に変換した電圧を端子Ｃ及びＤから出力する。ＤＣ／ＤＣコンバータ１００は、１石式に限定されず、多石式のプッシュプル方式、ハーフブリッジ方式及びフルブリッジ方式の何れかであってもよい。多石式の例については、方式そのものが公知であるため、記載を省略する。 The DC / DC converter 100 having the above-described configuration is a so-called single-rock type forward converter, and multiplies a predetermined voltage supplied from the terminals A and B by {(duty ratio of the FET 31) / (turn ratio of the transformer 10)}. Are output from terminals C and D. The DC / DC converter 100 is not limited to a single-stone type, and may be any of a multi-stone type push-pull type, a half-bridge type, and a full-bridge type. The description of the example of the multiple stone type is omitted since the type itself is known.
　本実施形態１では、ＦＥＴ３１を所定の周期でＰＷＭ（Ｐｕｌｓｅ　Ｗｉｄｔｈ　Ｍｏｄｕｌａｔｉｏｎ）制御することにより、電圧変換を行う。そこで、先ずＤＣ／ＤＣコンバータ１００の電圧変換動作について説明する。以下の図２及び３では、キャパシタ２０、制御部４、及び端子Ｃ，Ｄの図示を省略する。 In the first embodiment, voltage conversion is performed by performing PWM (Pulse Width Modulation) control on the FET 31 at a predetermined cycle. Therefore, the voltage conversion operation of the DC / DC converter 100 will be described first. 2 and 3, the illustration of the capacitor 20, the control unit 4, and the terminals C and D is omitted.
　図２は、トランス１０の一次側から二次側に電力を伝達する期間での動作状態の一例を示す説明図である。この期間では、制御部４の制御によってＦＥＴ３１がオンとなり、ＦＥＴ３２はオフとなる。そして、端子Ａ及びＢからトランス１０の一次巻線１１に所定電圧が印加されて二次巻線１２に一定の電圧が誘起し、ダイオード５１が導通してインダクタ６に直線的に増加する負荷電流が流れる。この間に、二次巻線１２（所定の電流源に相当）から導電体６１を介してキャパシタ２１及び負荷に流れる電流（実質的な出力電流）を流出電流とし、キャパシタ２１及び負荷から導電体６２を介して二次巻線１２に戻る電流（所謂リターンパスを流れる電流）を戻り電流とする。流出電流及び戻り電流の大きさは同じである。 FIG. 2 is an explanatory diagram illustrating an example of an operation state during a period in which power is transmitted from the primary side to the secondary side of the transformer 10. During this period, the FET 31 is turned on and the FET 32 is turned off under the control of the control unit 4. Then, a predetermined voltage is applied to the primary winding 11 of the transformer 10 from the terminals A and B to induce a constant voltage in the secondary winding 12, the diode 51 conducts, and the load current that increases linearly in the inductor 6. Flows. During this time, a current (substantial output current) flowing from the secondary winding 12 (corresponding to a predetermined current source) to the capacitor 21 and the load via the conductor 61 is set as an outflow current, and the conductor 62 is transferred from the capacitor 21 and the load. (Current flowing through a so-called return path) that returns to the secondary winding 12 via the control circuit is defined as a return current. The magnitudes of the outflow current and the return current are the same.
　一方、一次巻線１１には、負荷電流（より正確には、二次側の負荷電流の大きさをトランス１０の巻数比で除した大きさの電流）及び励磁電流を足し合わせた電流が直線的に増加するように流れる。一次巻線１１及び二次巻線１２夫々に流れる負荷電流による磁束はお互いに打消し合うのに対し、励磁電流はトランス１０のコア内に磁束を作る。キャパシタ２２には、現在のＰＷＭ周期に至るまでの間に、ＦＥＴ３２のドレイン側を正とする電圧が充電されている。以下では、説明上、一次巻線１１の一端に対して他端の電位が高い場合を正の電圧とする。また、一次巻線１１の他端から一端に流れる電流を正の電流とする。 On the other hand, a current obtained by adding the load current (more precisely, the current obtained by dividing the magnitude of the load current on the secondary side by the turns ratio of the transformer 10) and the exciting current is applied to the primary winding 11 in a straight line. Flows to increase gradually. The magnetic flux due to the load current flowing through each of the primary winding 11 and the secondary winding 12 cancels each other, while the exciting current creates a magnetic flux in the core of the transformer 10. The capacitor 22 is charged with a voltage that makes the drain side of the FET 32 positive until the current PWM cycle. Hereinafter, for the sake of explanation, a case where the potential of the other end is higher than the one end of the primary winding 11 is defined as a positive voltage. The current flowing from the other end of the primary winding 11 to one end is defined as a positive current.
　図３は、トランス１０の二次側で負荷電流が還流する期間での動作状態の一例を示す説明図である。この期間の初めにＦＥＴ３１がオフとなり、ＦＥＴ３１に負荷電流及び励磁電流が流れなくなって、ＦＥＴ３２のボディダイオードに正の励磁電流が転流する（実線参照）。転流した励磁電流は直線的に減少するが、励磁電流の向きが正である間はキャパシタ２２が充電される。一方の二次巻線１２にダイオード５１を介して流れていた負荷電流は、ダイオード５２を介して流れるように還流する。 FIG. 3 is an explanatory diagram showing an example of an operation state during a period in which the load current flows on the secondary side of the transformer 10. At the beginning of this period, the FET 31 is turned off, the load current and the exciting current stop flowing through the FET 31, and the positive exciting current commutates to the body diode of the FET 32 (see the solid line). Although the commutated exciting current decreases linearly, the capacitor 22 is charged while the direction of the exciting current is positive. The load current flowing through one secondary winding 12 via the diode 51 flows back through the diode 52.
　その後、制御部４の制御によってＦＥＴ３２がオンとなり、ＦＥＴ３２のボディダイオードに流れていた励磁電流は、チャネル領域を流れるようになるが、励磁電流は依然として減少し続ける。図３に示す期間の全期間を通じてキャパシタ２２から一次巻線１１に負の電圧が印加されるため、励磁電流は、直線的に減少して上記全期間の中程で極性が正から負に反転する（破線参照）。この時にキャパシタ２２が放電に転じる。そして、ＦＥＴ３２がオンである期間の終了時点でトランス１０に蓄えられたエネルギーの放出が終了する。トランス１０の二次側の負荷電流は、依然としてダイオード５２を介して還流し続ける。 (4) Thereafter, the FET 32 is turned on by the control of the control unit 4, and the exciting current flowing through the body diode of the FET 32 flows through the channel region, but the exciting current continues to decrease. Since a negative voltage is applied from the capacitor 22 to the primary winding 11 throughout the period shown in FIG. 3, the exciting current decreases linearly and the polarity is inverted from positive to negative in the middle of the entire period. (See broken line). At this time, the capacitor 22 starts discharging. Then, at the end of the period in which the FET 32 is on, the release of the energy stored in the transformer 10 ends. The load current on the secondary side of the transformer 10 continues to flow back through the diode 52.
　次に、インダクタ６の詳細について説明する。図４は、実施形態１に係るインダクタ６を斜め上方から見た斜視図であり、図５は、実施形態１に係るインダクタ６の組み立て後の状態を模式的に示す縦断面図である。インダクタ６は、例えば断面がＵ字状の一対のコア６３，６４の突き合わせ面Ｘ－Ｘに沿って貫通孔６０が形成されており、該貫通孔６０に一対の導電体６１，６２が重なるように挿通されている。一対の導電体６１，６２のうちの一方を第１導電体６１といい、他方を第２導電体６２という。導電体６１，６２の上下関係は、図４及び５に示すものと逆であってもよい。 Next, details of the inductor 6 will be described. FIG. 4 is a perspective view of the inductor 6 according to the first embodiment viewed obliquely from above, and FIG. 5 is a longitudinal sectional view schematically illustrating a state after the assembly of the inductor 6 according to the first embodiment. In the inductor 6, for example, a through hole 60 is formed along a mating surface XX of a pair of cores 63 and 64 having a U-shaped cross section, and the pair of conductors 61 and 62 overlap the through hole 60. Has been inserted. One of the pair of conductors 61, 62 is referred to as a first conductor 61, and the other is referred to as a second conductor 62. The vertical relationship between the conductors 61 and 62 may be opposite to that shown in FIGS.
　第１導電体６１を流れる電流を第１電流といい、第２導電体６２を流れる電流を第２電流という。ここでは、第１電流は、流出電流であり、第２電流は、戻り電流である。第２電流は、第１電流が、インダクタ６外部の回路素子である負荷を経由して、インダクタ６に戻る電流である。また、第１電流は、第２電流が、インダクタ６外部の回路素子である二次巻線１２又はダイオード５２を経由して、インダクタ６に戻る電流であると考えてもよい。 電流 A current flowing through the first conductor 61 is called a first current, and a current flowing through the second conductor 62 is called a second current. Here, the first current is an outflow current, and the second current is a return current. The second current is a current in which the first current returns to the inductor 6 via a load which is a circuit element outside the inductor 6. Further, the first current may be considered to be a current that returns to the inductor 6 via the secondary winding 12 or the diode 52 that is a circuit element outside the inductor 6.
　コア（磁性コア）６３，６４は、磁性体を含む。コア６３，６４は、一対のコア部材６３，６４を突き合せて構成されている。一対のコア部材６３，６４のうちの一方を第１コア部材６３といい、他方を第２コア部材という。なお、以下では、第１コア部材６３を単にコア６３と呼び、第２コア部材６４を単にコア６４と呼ぶことがある。さらに、一対のコア部材６３，６４を一対のコア６３，６４と呼ぶことがある。一対のコア６３，６４は、突き合わせることによって貫通孔が形成されるものであれば、断面及び外形がどのような形状であってもよい。 The cores (magnetic cores) 63 and 64 include a magnetic material. The cores 63 and 64 are configured by abutting a pair of core members 63 and 64. One of the pair of core members 63 and 64 is referred to as a first core member 63, and the other is referred to as a second core member. Hereinafter, the first core member 63 may be simply referred to as a core 63, and the second core member 64 may be simply referred to as a core 64. Further, the pair of core members 63 and 64 may be referred to as a pair of cores 63 and 64. The pair of cores 63 and 64 may have any shape in cross section and outer shape as long as a through hole is formed by abutting the cores.
　導電体６１，６２は、断面が矩形状の平角銅線又はバスバーであり、アスペクト比（長辺と短辺の比率）は、例えば２：１から２０：１の範囲内であるが、これに限定されるものではない。このように断面を矩形状にしてアスペクト比を大きくすることにより、導電体６１，６２の放熱が容易となる。 The conductors 61 and 62 are rectangular copper wires or bus bars having a rectangular cross section, and the aspect ratio (the ratio of the long side to the short side) is, for example, in the range of 2: 1 to 20: 1. It is not limited. By thus increasing the aspect ratio by making the cross section rectangular, heat dissipation of the conductors 61 and 62 becomes easy.
　コア６３，６４は、材料が、磁性体を焼結して形成したフェライト又は磁性体を含む粉末を加圧して形成した圧粉形成体であるため、高周波特性が良好である。つまり、コア６３，６４は、フェライトコア又は圧粉コアである。コア６３，６４の材料はこれらに限定されず、例えば、軟質磁性体の粉末及び樹脂を含む複合材料であってもよいし、板状の磁性体を積層した積層体であってもよい。コア６３，６４は、ナノ結晶軟磁性材料コアであってもよいし、アモルファスコアであってもよい。 (4) Since the cores 63 and 64 are made of a powder compact formed by pressing a powder containing a ferrite or a magnetic material formed by sintering a magnetic material, the cores 63 and 64 have good high-frequency characteristics. That is, the cores 63 and 64 are ferrite cores or dust cores. The material of the cores 63 and 64 is not limited to these, and may be, for example, a composite material containing a powder of a soft magnetic material and a resin, or may be a laminate in which plate-like magnetic materials are laminated. The cores 63 and 64 may be nanocrystalline soft magnetic material cores or amorphous cores.
　導電体６１，６２の間には、絶縁層６５が配されている。導電体６１，６２とコア６３，６４との間には、絶縁層６６が配されている。絶縁層６５，６６の材料が、例えばシリコンシート等の放熱材料である場合は、導電体６１，６２の放熱が良好となる。ここでは、導電体６１，６２と絶縁層６６との間に、すなわち、導電体６１，６２とコア６３，６４との間に、例えばカーボンシート等の伝熱材料を含む伝熱層６７，６７を更に設けてある。導電体６１，６２の間に、伝熱層（不図示）を更に設けてもよい。 絶 縁 An insulating layer 65 is provided between the conductors 61 and 62. An insulating layer 66 is provided between the conductors 61 and 62 and the cores 63 and 64. When the material of the insulating layers 65 and 66 is a heat dissipation material such as a silicon sheet, the heat dissipation of the conductors 61 and 62 is improved. Here, between the conductors 61, 62 and the insulating layer 66, that is, between the conductors 61, 62 and the cores 63, 64, for example, the heat transfer layers 67, 67 containing a heat transfer material such as a carbon sheet. Is further provided. A heat transfer layer (not shown) may be further provided between the conductors 61 and 62.
　インダクタ６の組み立て段階では、コア６３，６４を突き合わせる前に、コア６４における貫通孔６０が形成されるべき位置に導電体６１，６２が載置され、その後、コア６４にコア６３が突き合わされて組み立てられる。インダクタ６を周辺回路と接続する場合は、導電体６１に流れる流出電流及び導電体６２に流れる戻り電流が、貫通孔６０の貫通方向に対して同一方向に流れるように考慮される。 In the step of assembling the inductor 6, the conductors 61 and 62 are placed at positions where the through holes 60 are to be formed in the core 64 before butting the cores 63 and 64, and then the core 63 is butted against the core 64. Assembled. When the inductor 6 is connected to the peripheral circuit, it is considered that the outflow current flowing through the conductor 61 and the return current flowing through the conductor 62 flow in the same direction as the through-hole 60.
　次に、上記のように構成されたインダクタ６の適用範囲と性能について説明する。一般的にフォワード型のＤＣ／ＤＣコンバータのチョークコイルは、必要とされるインダクタンスがスイッチング周波数に反比例し、スイッチング周波数が低い場合はコイルを巻形状ではない導体に置き換えることができなくなる。このため、本実施形態１では、制御部４によるＦＥＴ３１，３２のスイッチング周波数を３００ｋＨｚ～３ＭＨｚの範囲内と想定し、インダクタ６に必要なインダクタンスを０．１μＨ～３μＨの範囲内と想定する。 Next, the applicable range and performance of the inductor 6 configured as described above will be described. Generally, in a choke coil of a forward type DC / DC converter, required inductance is inversely proportional to a switching frequency, and when the switching frequency is low, the coil cannot be replaced with a conductor having no winding shape. Therefore, in the first embodiment, it is assumed that the switching frequency of the FETs 31 and 32 by the control unit 4 is in the range of 300 kHz to 3 MHz, and that the inductance required for the inductor 6 is in the range of 0.1 μH to 3 μH.
　導電体６１，６２夫々に流れる流出電流及び戻り電流の大きさは、３０Ａ～２５０Ａの範囲内と想定する。このような大電流が流れる場合であっても、インダクタ６の導電体６１，６２を巻形状にする必要がないため、放熱が比較的容易である。 (4) It is assumed that the magnitude of the outflow current and return current flowing through each of the conductors 61 and 62 is in the range of 30A to 250A. Even when such a large current flows, the conductors 61 and 62 of the inductor 6 do not need to be formed in a winding shape, so that heat radiation is relatively easy.
ここで、一般的に漏れ磁束がない単層のソレノイドコイルのインダクタンスＬは、以下の式（１）で表されることが知られている。 Here, it is generally known that the inductance L of a single-layer solenoid coil having no leakage magnetic flux is represented by the following equation (1).
 
Ｌ＝μＳＮ２／１・・・・・・・・・・・・・・・・・・・・・・・・（１）
但し、
μ：透磁率
Ｓ：コイルの断面積
Ｎ：コイルの巻数
ｌ：コイルの磁路長
L = μSN 2/1 ························ ( 1)
However,
μ: magnetic permeability S: cross-sectional area of coil N: number of turns of coil l: magnetic path length of coil
　式（１）より、コア６３，６４の形状及び大きさが一定の場合、インダクタ６のインダクタンスは、導電体６１，６２による巻数、即ち、貫通孔６０に挿通される導電体６１及び６２の数（＝２）の二乗に比例する。従って、貫通孔６０に１つの導電体を挿通する場合と比較して、インダクタ６のインダクタンスは略４倍になり、導電体６１，６２を巻形状にせずに済むスイッチング周波数を１／４に引き下げることができる。 From the equation (1), when the shapes and sizes of the cores 63 and 64 are constant, the inductance of the inductor 6 is determined by the number of turns of the conductors 61 and 62, that is, the number of the conductors 61 and 62 inserted into the through hole 60. It is proportional to the square of (= 2). Therefore, the inductance of the inductor 6 is substantially four times as large as the case where one conductor is inserted into the through hole 60, and the switching frequency at which the conductors 61 and 62 do not need to be wound is reduced to 1/4. be able to.
　なお、本実施形態１では、導電体６１，６２とコア６３，６４との間に絶縁層６６を配したが、貫通孔６０に挿通される筒状部と、貫通孔６０の両開口部の開口面に沿う鍔状の鍔部とを有する絶縁体からなるボビンに導電体６１，６２を挿通させてもよい。また、導電体６１，６２を、多層配線基板の異なる内層又は外層における導体パターンで形成してもよい。この場合、エポキシ樹脂及びガラス繊維を含むプリプレグで絶縁層６５及び絶縁層６６の一部を置き換えたり、基板表面のレジスト層で絶縁層６６の一部を置き換えたりすることができる。 In the first embodiment, the insulating layer 66 is disposed between the conductors 61 and 62 and the cores 63 and 64. However, the cylindrical portion inserted into the through hole 60 and the two openings of the through hole 60 are formed. The conductors 61 and 62 may be inserted through a bobbin made of an insulator having a flange-shaped flange along the opening surface. Further, the conductors 61 and 62 may be formed by conductor patterns in different inner layers or outer layers of the multilayer wiring board. In this case, a part of the insulating layer 65 and the insulating layer 66 can be replaced with a prepreg containing epoxy resin and glass fiber, or a part of the insulating layer 66 can be replaced with a resist layer on the substrate surface.
　以上のように本実施形態１によれば、磁性体を含む一対のコア６３，６４を突き合わせた突き合わせ面Ｘ－Ｘに沿って貫通孔６０が形成されており、貫通孔６０に挿通された一対の導電体６１，６２は、トランス１０の二次巻線１２からの流出電流及び二次巻線１２への戻り電流が、貫通孔６０の貫通方向に対して同一方向に流れるように周辺回路と接続されている。これにより、コア６３，６４の貫通孔６０に１つの導電体を挿通する場合と比較して、起磁力Ｆが２倍となり、インダクタンスが略４倍になる。従って、コア６３，６４に挿通する導体を巻形状にしない場合であっても必要なインダクタンスを確保することが可能となる。 As described above, according to the first embodiment, the through-hole 60 is formed along the butting surface XX where the pair of cores 63 and 64 including the magnetic material is butted. Conductors 61 and 62 are connected to peripheral circuits so that the outflow current from the secondary winding 12 of the transformer 10 and the return current to the secondary winding 12 flow in the same direction as the penetration direction of the through hole 60. It is connected. Thereby, the magnetomotive force F is doubled and the inductance is substantially quadrupled as compared with the case where one conductor is inserted into the through holes 60 of the cores 63 and 64. Therefore, even when the conductor inserted into the cores 63 and 64 is not wound, it is possible to secure necessary inductance.
　また、実施形態１によれば、一対の導電体６１，６２夫々の断面が矩形状であるため、断面の短辺方向の厚さを抑えることができ、インダクタ６の高さを抑えることができる。また、一対の導電体６１，６２夫々の断面積に対する表面積が大きいため、放熱性が良好となる。 Further, according to the first embodiment, since the cross section of each of the pair of conductors 61 and 62 is rectangular, the thickness of the cross section in the short side direction can be suppressed, and the height of the inductor 6 can be suppressed. . Further, since the surface area with respect to the cross-sectional area of each of the pair of conductors 61 and 62 is large, the heat dissipation is improved.
　更に、実施形態１によれば、多層配線基板の異なる内層又は外層に含まれる導体パターンを一対の導電体６１，６２として用いる場合は、周辺回路を含めて一対の導電体６１，６２を容易に形成することができる。 Further, according to the first embodiment, when the conductor patterns included in different inner layers or outer layers of the multilayer wiring board are used as the pair of conductors 61 and 62, the pair of conductors 61 and 62 including the peripheral circuit can be easily formed. Can be formed.
　更に、実施形態１によれば、コア６３，６４の材料にフェライト又は圧粉形成体を用いるため、高周波特性が良好である。 According to the first embodiment, since the ferrite or the compact is used as the material of the cores 63 and 64, the high frequency characteristics are good.
　更に、実施形態１によれば、一対の導電体６１，６２とコア６３，６４との間に伝熱層６７，６７が介装されているため、導電体６１，６２で発生した熱が貫通孔６０の外部に好適に伝熱される。一対の導電体６１，６２の間にも伝熱層を配した場合は、更に伝熱性が向上する。 Furthermore, according to the first embodiment, since the heat transfer layers 67, 67 are interposed between the pair of conductors 61, 62 and the cores 63, 64, the heat generated in the conductors 61, 62 penetrates. Heat is preferably transferred to the outside of the hole 60. When a heat transfer layer is also provided between the pair of conductors 61 and 62, the heat transfer is further improved.
　更に、実施形態１によれば、トランス１０の一次巻線１１にＦＥＴ３１が直列に接続され、トランス１０の二次巻線１２に対する流出電流及び戻り電流夫々がインダクタ６の一対の導電体６１，６２に流れる。これにより、ＦＥＴ３１がオン／オフしたときにトランス１０の二次巻線１２に電流が誘起し、この電流が上述のインダクタ６における一対の導電体６１，６２に流れるため、出力電流を効果的に平滑することができる。 Further, according to the first embodiment, the FET 31 is connected in series to the primary winding 11 of the transformer 10, and the outflow current and the return current to the secondary winding 12 of the transformer 10 are each a pair of conductors 61 and 62 of the inductor 6. Flows to As a result, when the FET 31 is turned on / off, a current is induced in the secondary winding 12 of the transformer 10, and this current flows through the pair of conductors 61 and 62 of the inductor 6, thereby effectively reducing the output current. Can be smoothed.
（実施形態２）
　実施形態１は、一対のコア６３，６４を突き合わせた状態で１つの貫通孔６０が形成される形態であるのに対し、実施形態２は、一対のコア６３ｂ，６４ｂを突き合わせた状態で２つの貫通孔６０１，６０２が形成される形態である。実施形態２に係るＤＣ／ＤＣコンバータのブロック構成は、実施形態１に係るＤＣ／ＤＣコンバータ１００と同様であるため、図示を省略すると共に、実施形態１に対応する箇所には同様の符号を付してその説明を省略する。 (Embodiment 2)
In the first embodiment, one through hole 60 is formed in a state where a pair of cores 63 and 64 are abutted, whereas in the second embodiment, two through holes 60 are formed in a state where a pair of cores 63b and 64b are butted. In this embodiment, through holes 601 and 602 are formed. Since the block configuration of the DC / DC converter according to the second embodiment is the same as that of the DC / DC converter 100 according to the first embodiment, the illustration is omitted, and the portions corresponding to the first embodiment are denoted by the same reference numerals. The description is omitted.
　図６は、実施形態２に係るインダクタ６ｂを斜め上方から見た斜視図であり、図７は、インダクタ６ｂの組み立て後の状態を模式的に示す縦断面図である。また、図８Ａ，図８Ｂは、実施形態２に係る貫通孔６０１，６０２の双方に挿通された導電体６１ｂ及び６２ｂを各別に示す平面図である。図８Ａは第１導電体６１ｂを示し、図８Ｂは第２導電体６２ｂを示す。インダクタ６ｂは、ＥＥ型のコア６３ｂ，６４ｂの突き合わせ面Ｘｂ－Ｘｂに沿って貫通方向が同一方向に揃った貫通孔６０１，６０２が形成されており、該貫通孔６０１，６０２夫々に一対の導電体６１ｂ，６２ｂの双方が重なるように挿通されている。導電体６１ｂ，６２ｂの上下関係は、図６及び７に示すものと逆であってもよい。一対のコア６３ｂ，６４ｂは、例えばＥＩ型、ＥＲ型等の他の形状を有するものであってもよい。 6 is a perspective view of the inductor 6b according to the second embodiment viewed obliquely from above, and FIG. 7 is a vertical cross-sectional view schematically showing a state after the inductor 6b is assembled. 8A and 8B are plan views respectively showing the conductors 61b and 62b inserted into both the through holes 601 and 602 according to the second embodiment. FIG. 8A shows the first conductor 61b, and FIG. 8B shows the second conductor 62b. In the inductor 6b, through holes 601 and 602 whose through directions are aligned in the same direction are formed along the abutting surfaces Xb-Xb of the EE- type cores 63b and 64b, and a pair of conductive holes are respectively formed in the through holes 601 and 602. The bodies 61b and 62b are inserted so as to overlap each other. The vertical relationship between the conductors 61b and 62b may be opposite to that shown in FIGS. The pair of cores 63b and 64b may have another shape such as, for example, an EI type or an ER type.
　第１導電体６１ｂは、貫通孔６０１，６０２に挿通された部位及びこれらの部位を接続する部位を含む第１Ｕ字状部６１ｂｕを有する。同様に、第２導電体６２ｂは、貫通孔６０１，６０２に挿通された部位及びこれらの部位を接続する部位を含む第２Ｕ字状部６２ｂｕを有する。図６，図８Ａ及び図８Ｂに示す例では、導電体６１ｂ，６２ｂの夫々について、電流が流れる方向の一端及び他端を含む部位同士が貫通孔６０１，６０２と交差する方向へ互いに逆向きに折り曲げられているが、このように折り曲げられていなくてもよい。以下では、このように折り曲げられた部位を一端部及び他端部という。 The first conductor 61b has a first U-shaped portion 61bu including a portion inserted into the through holes 601 and 602 and a portion connecting these portions. Similarly, the second conductor 62b has a second U-shaped portion 62bu including a portion inserted into the through holes 601 and 602 and a portion connecting these portions. In the examples shown in FIGS. 6, 8A and 8B, for each of the conductors 61 b and 62 b, portions including one end and the other end in the direction in which current flows are opposite to each other in a direction intersecting the through holes 601 and 602. Although it is bent, it may not be bent in this way. Hereinafter, the portions bent in this manner are referred to as one end and the other end.
　図８Ａ，８Ｂに示すように、導電体６１ｂ，６２ｂは、平面視にて線対称の単純な形状となる。更に、導電体６１ｂ，６２ｂの夫々について、貫通孔６０１及び６０２に挿通された部位に流れる電流が、必然的に互いに逆方向となり、貫通孔６０１及び６０２の間のコア内で磁束が打ち消し合うことがない。従って、一対のコア６３ｂ，６４ｂの大きさが、実施形態１に係る一対のコア６３，６４を２組だけ横に並べた大きさと略等しければ、インダクタ６ｂのインダクタンスは、インダクタ６のインダクタンスの略２倍となる。 導電 As shown in FIGS. 8A and 8B, the conductors 61b and 62b have a simple line-symmetric shape in plan view. Further, with respect to each of the conductors 61b and 62b, the current flowing through the portions inserted into the through holes 601 and 602 is necessarily in the opposite direction, and the magnetic flux cancels out in the core between the through holes 601 and 602. There is no. Therefore, if the size of the pair of cores 63b and 64b is substantially equal to the size of two pairs of the cores 63 and 64 according to the first embodiment arranged side by side, the inductance of the inductor 6b is substantially equal to the inductance of the inductor 6. Double.
　導電体６１ｂ，６２ｂの間には、絶縁層６５が配されている。導電体６１ｂ，６２ｂとコア６３ｂ，６４ｂとの間には、絶縁層６６が配されている。ここでは、導電体６１ｂ，６２ｂと絶縁層６６との間に、伝熱層６７，６７を更に設けてある。導電体６１ｂ，６２ｂの間に、伝熱層（不図示）を更に設けてもよい。 絶 縁 An insulating layer 65 is provided between the conductors 61b and 62b. An insulating layer 66 is provided between the conductors 61b and 62b and the cores 63b and 64b. Here, heat transfer layers 67, 67 are further provided between the conductors 61b, 62b and the insulating layer 66. A heat transfer layer (not shown) may be further provided between the conductors 61b and 62b.
　インダクタ６ｂの組み立て段階では、コア６３ｂ，６４ｂを突き合わせる前に、コア６４ｂにおける貫通孔６０１，６０２夫々が形成されるべき位置に導電体６１ｂ，６２ｂが載置され、その後、コア６４ｂにコア６３ｂが突き合わされて組み立てられる。インダクタ６ｂを周辺回路と接続する場合は、導電体６１ｂに流れる流出電流及び導電体６２ｂに流れる戻り電流が、貫通孔６０１の貫通方向に対して同一方向に流れるように、且つ貫通孔６０２の貫通方向に対しても同一方向に流れるように考慮される。 At the stage of assembling the inductor 6b, the conductors 61b and 62b are placed at positions where the through holes 601 and 602 are to be formed in the core 64b before the cores 63b and 64b are abutted. Are assembled together. When the inductor 6b is connected to a peripheral circuit, the outflow current flowing through the conductor 61b and the return current flowing through the conductor 62b flow in the same direction as the through direction of the through-hole 601 and pass through the through-hole 602. It is taken into consideration that the fluid flows in the same direction.
　この場合、図８Ａ，８Ｂに示すようにＵ字状部６１ｂｕ，６２ｂｕが互いに逆向きになるようにしてあるため、導電体６１ｂ，６２ｂの一端同士、及び導電体６１ｂ，６２ｂの他端同士が、貫通孔６０１，６０２の貫通方向の両側に離隔されることとなり、周辺回路との接続が容易となる。具体的に図１及び６に示す例では、二次巻線１２の他端からの電路が、流出電流が流れ込む導電体６１ｂの一端に接続され、戻り電流が流れ出す導電体６２ｂの一端がダイオード５１，５２のアノードに接続される。また、流出電流が流れ出す導電体６１ｂの他端が、端子Ｃへの電路に接続され、端子Ｄからの電路が、戻り電流が流れ込む導電体６２ｂの他端に接続される。 In this case, as shown in FIGS. 8A and 8B, since the U-shaped portions 61bu and 62bu are configured to be opposite to each other, one ends of the conductors 61b and 62b and the other ends of the conductors 61b and 62b are connected to each other. , The through holes 601 and 602 are separated on both sides in the penetrating direction, thereby facilitating connection with peripheral circuits. Specifically, in the examples shown in FIGS. 1 and 6, an electric path from the other end of the secondary winding 12 is connected to one end of a conductor 61 b into which an outflow current flows, and one end of a conductor 62 b from which a return current flows is a diode 51. , 52 are connected to the anodes. The other end of the conductor 61b from which the outflow current flows is connected to the electric path to the terminal C, and the electric path from the terminal D is connected to the other end of the electric conductor 62b into which the return current flows.
　なお、本実施形態２にあっては、Ｕ字状部６１ｂｕ，６２ｂｕが貫通孔６０１，６０２の貫通方向に対して互いに逆向きなるようにしたが、これらが同一方向を向くようにした場合であっても、周辺回路との接続に多少の変更が必要になるものの、インダクタ６ｂとしては同様の効果を奏する。 In the second embodiment, the U-shaped portions 61bu and 62bu are configured to be opposite to each other with respect to the direction in which the through holes 601 and 602 penetrate. Even if there is some change in the connection with the peripheral circuit, a similar effect can be obtained as the inductor 6b.
　以上のように本実施形態２によれば、貫通方向がコア６３ｂ，６４ｂの突き合わせ面Ｘｂ－Ｘｂに沿った同一方向に揃っている２つの貫通孔６０１，６０２がコア６３ｂ，６４ｂに形成されており、一対の導電体６１ｂ，６２ｂの一方及び他方の夫々は、隣り合う２つの貫通孔６０１及び６０２に挿通された部位に流れる電流が互いに逆方向になるように構成されている。従って、隣り合う貫通孔６０１及び６０２の間のコア内で磁束が打ち消し合うことがなく、貫通孔６０１，６０２の数に略比例してインダクタンスを更に増大させることができる。 As described above, according to the second embodiment, two through holes 601 and 602 whose through directions are aligned in the same direction along the abutting surface Xb-Xb of the cores 63b and 64b are formed in the cores 63b and 64b. Each of one and the other of the pair of conductors 61b, 62b is configured such that currents flowing in portions inserted into two adjacent through holes 601 and 602 are in opposite directions. Therefore, the magnetic flux does not cancel out in the core between the adjacent through holes 601 and 602, and the inductance can be further increased substantially in proportion to the number of the through holes 601 and 602.
　また、実施形態２によれば、一対の導電体６１ｂ，６２ｂの夫々について、隣り合う２つの貫通孔６０１及び６０２に挿通された部位及びこれらの部位を接続する部位がＵ字状をなしている。従って、一対の導電体６１ｂ，６２ｂの夫々を、平面視にて線対称の比較的単純な形状とすることができる。 Further, according to the second embodiment, for each of the pair of conductors 61b and 62b, a portion inserted into two adjacent through holes 601 and 602 and a portion connecting these portions have a U-shape. . Therefore, each of the pair of conductors 61b and 62b can have a relatively simple shape that is line-symmetric in plan view.
　更に、実施形態２によれば、一対の導電体６１ｂ，６２ｂ夫々におけるＵ字状部６１ｂｕ，６２ｂｕが互いに逆向きに構成されている。従って、一対の導電体６１ｂ，６２ｂの一端同士及び他端同士が貫通孔６０１，６０２の貫通方向の両側に離隔されるため、二次巻線１２及び端子Ｃ，Ｄとの接続を容易に行うことができる。 According to the second embodiment, the U-shaped portions 61bu and 62bu of the pair of conductors 61b and 62b are configured to be opposite to each other. Therefore, one end and the other end of the pair of conductors 61b, 62b are separated on both sides in the through direction of the through holes 601 and 602, so that the connection with the secondary winding 12 and the terminals C and D is easily performed. be able to.
　更に、実施形態２によれば、突き合わせた状態で２つの貫通孔６０１，６０２を有するＥＥ型、ＥＩ型又はＥＲ型のコアを用いるため、広く普及しているコアを利用することができる。 According to the second embodiment, an EE-type, EI-type, or ER-type core having two through holes 601 and 602 in abutted state can be used.
（変形例１）
　実施形態２は、一対のコア６３ｂ，６４ｂを突き合わせた状態で２つの貫通孔６０１，６０２が形成される形態であるのに対し、変形例１は、一対のコア６３ｃ，６４ｃを突き合わせた状態で３つの貫通孔６０１，６０２，６０３が形成される形態である。変形例１に係る一対のコア６３ｃ，６４ｃの構成は、貫通方向が同一方向に揃った貫通孔６０１，６０２，６０３が形成される点を除いて実施形態２の場合と同様であるため、詳細な説明を省略する。一対のコアに形成される貫通孔の数が４以上の場合についても、実施形態２又は本変形例１の場合と同様である。 (Modification 1)
Embodiment 2 is a mode in which two through holes 601 and 602 are formed in a state where a pair of cores 63b and 64b are abutted, whereas Modification 1 is a state where a pair of cores 63c and 64c are abutted. In this embodiment, three through holes 601, 602, and 603 are formed. The configuration of the pair of cores 63c and 64c according to the first modification is the same as that of the second embodiment except that the through- holes 601, 602, and 603 are formed in the same direction. Detailed description is omitted. The case where the number of through holes formed in the pair of cores is four or more is the same as in the case of the second embodiment or the first modification.
　図９Ａ，９Ｂは、変形例１に係る貫通孔６０１，６０２，６０３の全てに挿通された導電体６１ｃ及び６２ｃを各別に示す平面図である。図９Ａは第１導電体６１ｃを示し、図９Ｂは第２導電体６２ｃを示す。第１導電体６１ｃは、貫通孔６０１，６０２に挿通された部位及びこれらの部位を接続する部位を含む第１Ｕ字状部６１ｃｕと、貫通孔６０２，６０３に挿通された部位及びこれらの部位を接続する部位を含む第１Ｕ字状部６１ｃｕとを有する。２つのＵ字状部６１ｃｕは、一部が重複している。同様に、第２導電体６２ｃは、貫通孔６０１，６０２に挿通された部位及びこれらの部位を接続する部位を含む第２Ｕ字状部６２ｃｕと、貫通孔６０２，６０３に挿通された部位及びこれらの部位を接続する部位を含む第２Ｕ字状部６２ｃｕとを有する。 FIGS. 9A and 9B are plan views respectively showing the conductors 61c and 62c inserted into all of the through holes 601, 602, and 603 according to the first modification. FIG. 9A shows the first conductor 61c, and FIG. 9B shows the second conductor 62c. The first conductor 61c includes a first U-shaped portion 61cu including a portion inserted into the through holes 601 and 602 and a portion connecting these portions, a portion inserted into the through holes 602 and 603, and these portions. And a first U-shaped portion 61cu including a portion to be connected. The two U-shaped portions 61cu partially overlap. Similarly, the second conductor 62c includes a second U-shaped portion 62cu including a portion inserted into the through holes 601 and 602 and a portion connecting these portions, a portion inserted into the through holes 602 and 603, and And a second U-shaped portion 62cu including a portion connecting the portions.
　このように、導電体６１ｃ，６２ｃは、平面視にて点対称の単純な形状となる。更に、導電体６１ｃ，６２ｃの夫々について、隣り合う貫通孔６０１及び６０２に挿通された部位に流れる電流が、必然的に互いに逆方向となり、貫通孔６０１及び６０２の間のコア内で磁束が打ち消し合うことがない。同様に、隣り合う貫通孔６０２及び６０３に挿通された部位に流れる電流が、必然的に互いに逆方向となり、貫通孔６０２及び６０３の間のコア内で磁束が打ち消し合うことがない。従って、一対のコア６３ｃ，６４ｃの大きさが、実施形態１に係る一対のコア６３，６４を３組だけ横に並べた大きさと略等しければ、変形例１に係るインダクタのインダクタンスは、実施形態１に係るインダクタ６のインダクタンスの略３倍となる。 Thus, the conductors 61c and 62c have a simple point-symmetrical shape in plan view. Further, for each of the conductors 61c and 62c, the current flowing in the portion inserted into the adjacent through- holes 601 and 602 is necessarily in the opposite direction, and the magnetic flux cancels out in the core between the through- holes 601 and 602. It doesn't fit. Similarly, the currents flowing in the portions inserted into the adjacent through holes 602 and 603 are necessarily in opposite directions, and the magnetic flux does not cancel out in the core between the through holes 602 and 603. Therefore, if the size of the pair of cores 63c and 64c is substantially equal to the size of three pairs of the cores 63 and 64 according to the first embodiment arranged side by side, the inductance of the inductor according to the first modification is the same as that of the first embodiment. This is approximately three times the inductance of the inductor 6 according to (1).
　更に、実施形態２の場合と同様に、対応するＵ字状部６１ｃｕ，６２ｃｕが互いに逆向きになるようにしてあるため、導電体６１ｃ，６２ｃの一端同士、及び導電体６１ｃ，６２ｃの他端同士が、貫通孔６０１，６０２，６０３の貫通方向の両側に離隔されることとなり、周辺回路との接続が容易となる。具体的には、二次巻線１２の他端からの電路が、導電体６１ｃの一端に接続され、導電体６２ｃの一端がダイオード５１，５２のアノードに接続される。また、導電体６１ｃの他端が、端子Ｃへの電路に接続され、端子Ｄからの電路が、導電体６２ｃの他端に接続される。 Further, as in the case of the second embodiment, the corresponding U-shaped portions 61cu and 62cu are configured to be opposite to each other, so that one ends of the conductors 61c and 62c and the other ends of the conductors 61c and 62c are opposite to each other. These are separated from each other on both sides of the through- holes 601, 602, and 603 in the direction of penetration, so that connection with peripheral circuits is facilitated. Specifically, an electric path from the other end of the secondary winding 12 is connected to one end of the conductor 61c, and one end of the conductor 62c is connected to anodes of the diodes 51 and 52. The other end of the conductor 61c is connected to the electric path to the terminal C, and the electric path from the terminal D is connected to the other end of the electric conductor 62c.
　以上のように本変形例１によれば、貫通方向がコア６３ｃ，６４ｃの突き合わせ面に沿った同一方向に揃っている３つの貫通孔６０１，６０２，６０３がコア６３ｃ，６４ｃに形成されており、一対の導電体６１ｃ，６２ｃの一方及び他方の夫々は、隣り合う２つの貫通孔６０１及び６０２（又は貫通孔６０２及び６０３）に挿通された部位に流れる電流が互いに逆方向になるように構成されている。従って、隣り合う貫通孔６０１及び６０２（又は貫通孔６０２及び６０３）の間のコア内で磁束が打ち消し合うことがなく、貫通孔６０１，６０２，６０３の数に略比例してインダクタンスを更に増大させることができる。 As described above, according to the first modification, three through holes 601, 602, and 603 whose through directions are aligned in the same direction along the abutting surfaces of the cores 63 c and 64 c are formed in the cores 63 c and 64 c. One and the other of the pair of conductors 61c, 62c are configured such that currents flowing in portions inserted into two adjacent through holes 601 and 602 (or through holes 602 and 603) are in opposite directions. Have been. Accordingly, the magnetic flux does not cancel out in the core between the adjacent through holes 601 and 602 (or the through holes 602 and 603), and the inductance is further increased substantially in proportion to the number of the through holes 601, 602, and 603. be able to.
　また、変形例１によれば、一対の導電体６１ｃ，６２ｃの夫々について、隣り合う２つの貫通孔６０１及び６０２（又は貫通孔６０２及び６０３）に挿通された部位及びこれらの部位を接続する部位がＵ字状をなしている。従って、一対の導電体６１ｃ，６２ｃの夫々を、平面視にて点対称の比較的単純な形状とすることができる。 According to the first modification, for each of the pair of conductors 61c and 62c, a portion inserted into two adjacent through holes 601 and 602 (or through holes 602 and 603) and a portion connecting these portions. Are U-shaped. Therefore, each of the pair of conductors 61c and 62c can have a relatively simple shape that is point-symmetric in plan view.
　更に、変形例１によれば、一対の導電体６１ｃ，６２ｃ夫々におけるＵ字状部６１ｃｕ，６２ｃｕが互いに逆向きに構成されている。従って、一対の導電体６１ｃ，６２ｃの一端同士及び他端同士が貫通孔６０１，６０２，６０３の貫通方向の両側に離隔されるため、二次巻線１２及び端子Ｃ，Ｄとの接続を容易に行うことができる。 According to the first modification, the U-shaped portions 61cu and 62cu of the pair of conductors 61c and 62c are configured to be opposite to each other. Therefore, one end and the other end of the pair of conductors 61c, 62c are separated from each other on both sides of the through- holes 601, 602, 603 in the penetrating direction. Can be done.
（変形例２）
　実施形態２は、一対の導電体６１ｂ，６２ｂを周辺回路とは別に形成する形態であるのに対し、変形例２は、一対の導電体６１ｄ，６２ｄを周辺回路と一体的に形成する形態である。変形例２に係る一対のコア６３ｂ，６４ｂの構成は、実施形態２の場合と全く同様である。 (Modification 2)
Embodiment 2 is a form in which the pair of conductors 61b and 62b are formed separately from the peripheral circuit, whereas Modification 2 is a form in which the pair of conductors 61d and 62d are formed integrally with the peripheral circuit. is there. The configuration of the pair of cores 63b and 64b according to the second modification is exactly the same as that of the second embodiment.
　図１０Ａ，１０Ｂは、変形例２に係る一対の導電体６１ｄ，６２ｄを模式的に示す平面図である。導電体６１ｄは、実施形態２に係る導電体６１ｂと比較して、一端部がトランス１０のワンターンの二次巻線１２と一体的に形成され、更に他端部が端子Ｃと一体的に形成されている。導電体６１ｄが端子Ｃと一体化されていなくてもよい。一方の導電体６２ｄは、実施形態２に係る導電体６２ｂと比較して、他端部が端子Ｄと一体的に形成されているが、必ずしもこのように一体化されていなくてもよい。 FIGS. 10A and 10B are plan views schematically showing a pair of conductors 61d and 62d according to the second modification. One end of the conductor 61d is formed integrally with the one-turn secondary winding 12 of the transformer 10, and the other end is formed integrally with the terminal C, as compared with the conductor 61b according to the second embodiment. Have been. The conductor 61d may not be integrated with the terminal C. The other conductor 62d has the other end formed integrally with the terminal D as compared with the conductor 62b according to the second embodiment, but does not necessarily have to be so integrated.
　なお、本変形例２にあっては、実施形態２の図６に示す導電体６１ｂを二次巻線１２及び端子Ｃと一体化し、導電体６２ｂを端子Ｄと一体化する場合を例示したが、これに限定されない。例えば、実施形態１の図４に示す導電体６１を二次巻線１２及び端子Ｃと一体化し、導電体６２を端子Ｄと一体化してもよいし、変形例１の図９Ａに示す導電体６１ｃを二次巻線１２及び端子Ｃと一体化し、図９Ｂに示す導電体６２ｃを端子Ｄと一体化してもよい。 In the second modification, the conductor 61b of the second embodiment illustrated in FIG. 6 is integrated with the secondary winding 12 and the terminal C, and the conductor 62b is integrated with the terminal D. , But is not limited to this. For example, the conductor 61 shown in FIG. 4 of the first embodiment may be integrated with the secondary winding 12 and the terminal C, and the conductor 62 may be integrated with the terminal D, or the conductor shown in FIG. 9C may be integrated with the secondary winding 12 and the terminal C, and the conductor 62c shown in FIG.
　以上のように本変形例２によれば、導電体６１ｄがトランス１０の二次巻線１２及び端子Ｃと一体的に形成され、導電体６２ｄが端子Ｄと一体的に形成されるため、部品間の接合箇所を削減することができる。 As described above, according to the second modification, the conductor 61d is formed integrally with the secondary winding 12 and the terminal C of the transformer 10, and the conductor 62d is formed integrally with the terminal D. The number of joints between them can be reduced.
（変形例３）
　実施形態２は、インダクタ６ｂの取り付け方法を明示しない形態であるのに対し、変形例３は、インダクタ６ｃを筐体７へ取り付ける形態である。変形例３に係る一対のコア６３ｂ，６４ｂの構成は、実施形態２の場合と全く同様である。 (Modification 3)
Embodiment 2 is a mode in which the mounting method of the inductor 6b is not specified, whereas Modification 3 is a mode in which the inductor 6c is mounted on the housing 7. The configuration of the pair of cores 63b and 64b according to the third modification is completely the same as that of the second embodiment.
　図１１は、変形例３に係るインダクタ６ｃを斜め上方から見た斜視図であり、図１２は、筐体７に取り付けたインダクタ６ｃを模式的に示す側面図である。インダクタ６ｃは、実施形態２に係るインダクタ６ｂと比較して、導電体６１ｂを導電体６１ｅに置き換えたものであり、一対のコア６３ｂ，６４ｂ及び導電体６２ｂは、実施形態２の場合と共通である。 FIG. 11 is a perspective view of the inductor 6c according to the third modification viewed from obliquely above, and FIG. 12 is a side view schematically showing the inductor 6c attached to the housing 7. The inductor 6c is different from the inductor 6b according to the second embodiment in that the conductor 61b is replaced by a conductor 61e, and the pair of cores 63b and 64b and the conductor 62b are common to those in the second embodiment. is there.
　仮に実施形態２に係るインダクタ６ｂを平面上に平置きした場合、導電体６２ｂの下面よりも導電体６１ｂの下面の方が高くなる（図６，７参照）。そこで、本変形例３では、図１１に示すように、互いに逆向きに折り曲げられた導電体６１ｅの一端部及び他端部を、導電体６２ｂと重ならない位置で厚さ方向に階段状に折り曲げてある。これにより、コア６４ｂを下側にしてインダクタ６ｃを筐体７に平置きした場合、導電体６１ｅの一端部及び他端部の下面と、導電体６２ｂの一端部及び他端部の下面とで、筐体７からの高さが一致するようになる。 If the inductor 6b according to the second embodiment is laid flat on a plane, the lower surface of the conductor 61b is higher than the lower surface of the conductor 62b (see FIGS. 6 and 7). Therefore, in the third modification, as shown in FIG. 11, one end and the other end of the conductor 61e bent in opposite directions are bent stepwise in a thickness direction at a position not overlapping with the conductor 62b. It is. Thus, when the inductor 6c is placed flat on the housing 7 with the core 64b facing down, the lower surface of one end and the other end of the conductor 61e and the lower surface of the one end and the other end of the conductor 62b. , And the height from the housing 7 becomes the same.
　図１２に示すように、筐体７の上面には、高さが同じ突出部７１，７２が設けられている。突出部７１は、導電体６２ｂの一端部及び他端部と重なる位置に配されている。突出部７２は、導電体６１ｅの一端部及び他端部と重なる位置に配されている。突出部７１の上面と、導電体６２ｂの一端部及び他端部の下面との間には、絶縁層６８が設けられている。突出部７２の上面と、導電体６１ｅの一端部及び他端部の下面との間には、絶縁層６９が設けられている。導電体６１ｅと導電体６２ｂとが重なる部分の間には、絶縁層６５が設けられている。 突出 As shown in FIG. 12, projecting portions 71 and 72 having the same height are provided on the upper surface of the housing 7. The protrusion 71 is disposed at a position overlapping one end and the other end of the conductor 62b. The protrusion 72 is disposed at a position overlapping one end and the other end of the conductor 61e. An insulating layer 68 is provided between the upper surface of the protrusion 71 and the lower surfaces of the one end and the other end of the conductor 62b. An insulating layer 69 is provided between the upper surface of the protrusion 72 and the lower surfaces of the one end and the other end of the conductor 61e. An insulating layer 65 is provided between portions where the conductor 61e and the conductor 62b overlap.
　以上のように、本変形例３によれば、インダクタ６ｃを筐体７に容易に取り付けることができる。 As described above, according to the third modification, the inductor 6c can be easily attached to the housing 7.
（実施形態３）
　実施形態１は、一対のコア６３，６４を一対のみ備える形態であるのに対し、実施形態３は、一対のコア６３，６４を複数対備える形態である。換言すれば、本実施形態３は、一対のコア６３，６４を突き合わせて形成される貫通孔６０に一対の導電体６１，６２が挿通されたインダクタ６を複数含む複合インダクタを備える形態である。図１３は、実施形態３に係るＤＣ／ＤＣコンバータ１００ｂの構成例を示すブロック図である。ＤＣ／ＤＣコンバータ１００ｂは、入力側の端子Ａ及びＢの電位と出力側の端子Ｃ及びＤの電位とを分離するトランス１０と、一対の導電体６１，６２と、端子Ｃ及びＤ間に接続されたキャパシタ２１と、導電体６１，６２間に接続されたキャパシタ２３とを備える。 (Embodiment 3)
Embodiment 1 is a mode in which only a pair of cores 63 and 64 are provided, whereas Embodiment 3 is a mode in which a plurality of pairs of cores 63 and 64 are provided. In other words, the third embodiment is a form including a composite inductor including a plurality of inductors 6 in which a pair of conductors 61 and 62 are inserted into a through hole 60 formed by abutting a pair of cores 63 and 64. FIG. 13 is a block diagram illustrating a configuration example of a DC / DC converter 100b according to the third embodiment. The DC / DC converter 100b is connected between the transformer 10 for separating the potentials of the input-side terminals A and B and the potentials of the output-side terminals C and D, a pair of conductors 61 and 62, and between the terminals C and D. And a capacitor 23 connected between the conductors 61 and 62.
　トランス１０の二次巻線１２は、一端にＦＥＴ５１ｂのドレインが接続され、他端にＦＥＴ５２ｂのドレインが接続されている。ＦＥＴ５２ｂのドレインは、更に、一方のインダクタ（以下、第１のインダクタと言う）６に含まれる導電体６１を介してキャパシタ２３の一端に接続されている。キャパシタ２３の一端は、更に、他方のインダクタ（以下、第２のインダクタと言う）６に含まれる導電体６１を介してキャパシタ２１の一端及び端子Ｃに接続されている。ＦＥＴ５１ｂ及び５２ｂのソースは、第１のインダクタ６に含まれる導電体６２を介してキャパシタ２３の他端に接続されている。キャパシタ２３の他端は、更に、第２のインダクタ６に含まれる導電体６２を介してキャパシタ２１の他端及び端子Ｄに接続されている。ＦＥＴ５１ｂ及び５２ｂのゲートは、制御部４に接続されている。 The secondary winding 12 of the transformer 10 has one end connected to the drain of the FET 51b and the other end connected to the drain of the FET 52b. The drain of the FET 52b is further connected to one end of the capacitor 23 via a conductor 61 included in one inductor (hereinafter, referred to as a first inductor) 6. One end of the capacitor 23 is further connected to one end of the capacitor 21 and a terminal C via a conductor 61 included in the other inductor (hereinafter, referred to as a second inductor) 6. The sources of the FETs 51 b and 52 b are connected to the other end of the capacitor 23 via a conductor 62 included in the first inductor 6. The other end of the capacitor 23 is further connected to the other end of the capacitor 21 and the terminal D via a conductor 62 included in the second inductor 6. The gates of the FETs 51b and 52b are connected to the control unit 4.
　その他、実施形態１に対応する箇所には同様の符号を付してその説明を省略する。なお、ＦＥＴ５１ｂ，５２ｂは、実施形態１で用いたダイオード５１，５２に置き換えてもよい。インダクタ６の数は２つに限定されず、３つ以上であってもよい。 In addition, the same reference numerals are given to portions corresponding to the first embodiment, and description thereof will be omitted. Note that the FETs 51b and 52b may be replaced with the diodes 51 and 52 used in the first embodiment. The number of inductors 6 is not limited to two, and may be three or more.
　上述のインダクタ６，６が複合インダクタ６００に相当する。各インダクタ６は、２端子対回路と見なされ、これらの２端子対回路が縦続接続されている。複合インダクタ６００に含まれる導電体６１には流出電流が流れ、導電体６２には戻り電流が流れる。第１のインダクタ６による２端子対回路の一方の端子対にはキャパシタが接続されていないが、ここにキャパシタを接続してもよい。キャパシタ２３は、第１のインダクタ６による２端子対回路の他方の端子対に接続されていると見なしてもよいし、第２のインダクタ６による２端子対回路の一方の端子対に接続されていると見なしてもよい。キャパシタ２１を削除して外部の負荷に含めるようにしてもよい。インダクタ６，６，・・による隣り合う２端子対回路の接続部位では、導電体６１，６２の間に必ずしもキャパシタを接続しなくてもよい。 The above-described inductors 6 and 6 correspond to the composite inductor 600. Each inductor 6 is regarded as a two-port pair circuit, and these two-port pair circuits are cascaded. Outflow current flows through the conductor 61 included in the composite inductor 600, and return current flows through the conductor 62. Although a capacitor is not connected to one terminal pair of the two-terminal pair circuit formed by the first inductor 6, a capacitor may be connected here. The capacitor 23 may be regarded as being connected to the other terminal pair of the two-terminal pair circuit formed by the first inductor 6 or connected to one terminal pair of the two-terminal pair circuit formed by the second inductor 6. May be considered. The capacitor 21 may be deleted and included in an external load. It is not always necessary to connect a capacitor between the conductors 61 and 62 at the connection portion of the two-terminal pair circuit adjacent by the inductors 6, 6,.
　次に、導体パターンを用いてインダクタ６，６を形成する例について説明する。図１４は、実施形態３に係るＤＣ／ＤＣコンバータ１００ｂの印刷配線基板８上に形成されたトランス１０及びインダクタ６，６を模式的に示す平面図である。印刷配線基板８には、内層が４層である６層の多層基板を用いているが、内層の数が３以下又は５以上であってもよい。トランス１０には所謂ＰＱ型のコアを、インダクタ６，６には断面がコの字状のコアを用いているが、これに限定されるものではない。 Next, an example in which the inductors 6 and 6 are formed using a conductor pattern will be described. FIG. 14 is a plan view schematically showing the transformer 10 and the inductors 6 and 6 formed on the printed wiring board 8 of the DC / DC converter 100b according to the third embodiment. The printed wiring board 8 uses a six-layer multi-layer substrate having four inner layers, but the number of inner layers may be three or less or five or more. Although a so-called PQ type core is used for the transformer 10 and a U-shaped core is used for the inductors 6 and 6, the present invention is not limited to this.
　トランス１０は、印刷配線基板８の長手方向の一端部にて長手方向と交差する方向に等間隔に設けられた３つの開口部にＰＱ型のコアの３つの脚部が各別に挿通されている。第１のインダクタ６は、印刷配線基板８の長手方向の略中央部にて長手方向に設けられた２つの開口部に断面がコの字状のコア６３，６４の２つの脚部が各別に挿通されている。第２のインダクタ６は、印刷配線基板８の長手方向の他端部にて長手方向に設けられた２つの開口部に断面がコの字状のコア６３，６４の２つの脚部が各別に挿通されている。 In the transformer 10, three legs of a PQ-type core are separately inserted into three openings provided at equal intervals in a direction intersecting the longitudinal direction at one longitudinal end of the printed wiring board 8. . In the first inductor 6, two legs of cores 63 and 64 having a U-shaped cross section are separately provided in two openings provided in the longitudinal direction substantially at the center of the printed wiring board 8 in the longitudinal direction. It has been inserted. In the second inductor 6, two legs of cores 63 and 64 having a U-shaped cross section are separately provided in two openings provided in the longitudinal direction at the other end of the printed wiring board 8 in the longitudinal direction. It has been inserted.
　印刷配線基板８の一方の外層には、インダクタ６，６夫々の貫通孔６０，６０に挿通する導電体６１が導体パターンによって形成されている。この導体パターンは、トランス１０の１ターンの二次巻線１２及び端子Ｃと一体化されている。印刷配線基板８の特定の内層には、インダクタ６，６夫々の貫通孔６０，６０に挿通する導電体６２が導体パターン（破線で示す）によって形成されている。この導体パターンの一端部、中央部及び他端部夫々は、ビアホール部６２１、６２２及び６２３を介して一方の外層に形成された相異なる導体パターンに電気的に接続されている。このように上記特定の内層及び一方の外層に形成されて電気的に接続された導体パターンの全体が導電体６２に相当する。なお、導電体６２のうち、印刷配線基板８の長手方向の他端部にて一方の外層に形成された導体パターンは、端子Ｄと一体化されている。 (4) On one outer layer of the printed wiring board 8, a conductor 61 inserted into the through holes 60, 60 of the inductors 6, 6 is formed by a conductor pattern. This conductor pattern is integrated with the one-turn secondary winding 12 of the transformer 10 and the terminal C. In a specific inner layer of the printed wiring board 8, a conductor 62 inserted into the through holes 60, 60 of the inductors 6, 6 is formed by a conductor pattern (shown by a broken line). One end, the center, and the other end of the conductor pattern are electrically connected to different conductor patterns formed in one outer layer via via holes 621, 622, and 623, respectively. The entirety of the conductor pattern formed on the specific inner layer and one outer layer and electrically connected in this way corresponds to the conductor 62. The conductor pattern formed on one outer layer of the conductor 62 at the other end in the longitudinal direction of the printed wiring board 8 is integrated with the terminal D.
　トランス１０の一次巻線１１は、印刷配線基板８の内層に形成されている。一次巻線１１は、例えば任意の内層に形成された渦巻き状の導体パターンにより、ターン数（巻数）が２以上となるようにしてもよいし、１つの内層に形成された任意のターン数の巻線を、内層間を接続するビアホールによって直列に接続してもよい。なお、一次巻線１１は、導電体６１及び二次巻線１２との重なり部位を除いて破線で示す。また、導電体６２は、導電体６１との重なり部位を含めて破線で示す。 The primary winding 11 of the transformer 10 is formed in an inner layer of the printed wiring board 8. The number of turns (number of turns) of the primary winding 11 may be two or more, for example, by a spiral conductor pattern formed on an arbitrary inner layer. The windings may be connected in series by via holes connecting the inner layers. In addition, the primary winding 11 is shown by a broken line except for an overlapping portion with the conductor 61 and the secondary winding 12. The conductor 62 is indicated by a broken line including a portion where the conductor 62 overlaps the conductor 62.
　トランス１０及び第１のインダクタ６の間の部位における二次巻線１２及び外層の導電体６２の間には、ＦＥＴ５１ｂが表面実装されている。トランス１０及び第１のインダクタ６の間の部位における導電体６１及び外層の導電体６２の間には、ＦＥＴ５２ｂが表面実装されている。インダクタ６，６の間の部位における導電体６１及び外層の導電体６２の間には、キャパシタ２３が表面実装されている。キャパシタ２３は３つのキャパシタを並列に接続したものであるが、これに限定されず、例えば１つのキャパシタであってもよい。第２のインダクタ６よりも端子Ｃ及びＤ側の部位における導電体６１及び外層の導電体６２の間には、キャパシタ２１が表面実装されている。キャパシタ２１は３つのキャパシタを並列に接続したものであるが、これに限定されず、例えば１つのキャパシタであってもよい。キャパシタ２１，２３は、積層セラミックコンデンサであるが、例えばリードタイプのセラミックコンデンサ又はフィルムコンデンサを用いてもよい。 (4) The FET 51b is surface-mounted between the secondary winding 12 and the outer conductor 62 at a location between the transformer 10 and the first inductor 6. An FET 52b is surface-mounted between a conductor 61 and an outer conductor 62 at a portion between the transformer 10 and the first inductor 6. The capacitor 23 is surface-mounted between the conductor 61 and the outer conductor 62 at a portion between the inductors 6 and 6. The capacitor 23 is formed by connecting three capacitors in parallel, but is not limited to this. For example, one capacitor may be used. The capacitor 21 is surface-mounted between the conductor 61 and the conductor 62 in the outer layer at a portion closer to the terminals C and D than the second inductor 6. The capacitor 21 is formed by connecting three capacitors in parallel, but is not limited to this. For example, one capacitor may be used. Although the capacitors 21 and 23 are multilayer ceramic capacitors, for example, a lead type ceramic capacitor or a film capacitor may be used.
　本実施形態３にあっては、一対の導電体６１，６２を印刷配線基板８の導体パターンで形成したので、部品点数の増加、接続ポイントの増加、加工工程の増加等を抑制して、ノイズ低減効果の高いＤＣ／ＤＣコンバータを容易に作製できるという効果が得られる。例えば一対の導電体６１，６２にバスバーを用いることもできる。但し、この場合は、導電体６１，６２及びキャパシタ２３の間と、導電体６１，６２及びキャパシタ２１の間とを、印刷配線基板８上での接続によらずに、別途半田付け又は溶接を用いて接続しなければならず、接続ポイントの数や工数が増える。 In the third embodiment, since the pair of conductors 61 and 62 are formed by the conductor pattern of the printed wiring board 8, an increase in the number of components, an increase in connection points, an increase in processing steps, and the like are suppressed, and noise is reduced. An effect is obtained that a DC / DC converter having a high reduction effect can be easily manufactured. For example, a bus bar can be used for the pair of conductors 61 and 62. However, in this case, soldering or welding is separately performed between the conductors 61 and 62 and the capacitor 23 and between the conductors 61 and 62 and the capacitor 21 without depending on the connection on the printed wiring board 8. Connection and the number of connection points and man-hours increase.
　以上のように本実施形態３によれば、１対のコア６３，６４の２対分によって複合インダクタ６００のインダクタンスが２つのインダクタ６，６に分散されるため、各対のコア６３，６４の容積を低減することができる。 As described above, according to the third embodiment, the inductance of the composite inductor 600 is distributed to the two inductors 6 and 6 by two pairs of the pair of cores 63 and 64. The volume can be reduced.
　また、実施形態３によれば、一対のコア６３，６４の貫通孔６０に一対の導電体６１，６２が挿通されて形成される各インダクタ６が２つのインダクタンス要素を含む２端子対回路と見なされ、各２端子対回路が縦続接続されている。従って、第１のインダクタ６の出力を第２のインダクタ６の入力に引き継ぐことができる。 According to the third embodiment, each inductor 6 formed by inserting a pair of conductors 61 and 62 into a through hole 60 of a pair of cores 63 and 64 is regarded as a two-terminal pair circuit including two inductance elements. The two terminal pair circuits are cascaded. Therefore, the output of the first inductor 6 can be taken over by the input of the second inductor 6.
　更に、実施形態３によれば、トランス１０の一次巻線１１にＦＥＴ３１が直列に接続され、トランス１０の二次巻線１２に対する流出電流及び戻り電流が複合インダクタ６００の一対の導電体６１，６２に流れる。これにより、ＦＥＴ３１がオン／オフしたときにトランス１０の二次巻線１２に電流が誘起し、この電流が上述の複合インダクタ６００における一対の導電体６１，６２に流れるため、出力電流を効果的に平滑することができる。 Further, according to the third embodiment, the FET 31 is connected in series to the primary winding 11 of the transformer 10, and the outflow current and return current to the secondary winding 12 of the transformer 10 are controlled by the pair of conductors 61 and 62 of the composite inductor 600. Flows to As a result, when the FET 31 is turned on / off, a current is induced in the secondary winding 12 of the transformer 10, and this current flows through the pair of conductors 61 and 62 in the composite inductor 600, so that the output current is effectively reduced. Can be smoothed.
（実施形態４）
　実施形態３は、複合インダクタ６００が実施形態１に係るインダクタ６，６を含む形態であるのに対し、実施形態４は、複合インダクタ６００ｂが実施形態２に係るインダクタ６ｂ，６ｂを含む形態である。実施形態４に係るＤＣ／ＤＣコンバータ１００ｂのブロック図は、実施形態３の図１３に示すものと同様であり、複合インダクタ６００及びインダクタ６の符号が変わるだけであるため、図示を省略する。その他、実施形態３に対応する箇所には同様の符号を付してその説明を省略する。 (Embodiment 4)
The third embodiment is a form in which the composite inductor 600 includes the inductors 6 and 6 according to the first embodiment, whereas the fourth embodiment is a form in which the composite inductor 600b includes the inductors 6b and 6b according to the second embodiment. . The block diagram of the DC / DC converter 100b according to the fourth embodiment is the same as that shown in FIG. 13 of the third embodiment, and only the signs of the composite inductor 600 and the inductor 6 are changed. In addition, the same reference numerals are given to the portions corresponding to the third embodiment, and the description is omitted.
　各インダクタ６ｂは、２端子対回路と見なされ、これらの２端子対回路が縦続接続されている。複合インダクタ６００ｂに含まれる導電体６１には流出電流が流れ、導電体６２には戻り電流が流れる。図１５は、実施形態４に係るＤＣ／ＤＣコンバータ１００ｂの印刷配線基板８ｂ上に形成されたトランス１０及びインダクタ６ｂ，６ｂを模式的に示す平面図である。トランス１０には所謂ＰＱ型のコアを、インダクタ６ｂ，６ｂにはＥＩ型のコアを用いているが、これに限定されるものではない。 Each inductor 6b is regarded as a two-terminal pair circuit, and these two-terminal pair circuits are connected in cascade. Outflow current flows through the conductor 61 included in the composite inductor 600b, and return current flows through the conductor 62. FIG. 15 is a plan view schematically showing the transformer 10 and the inductors 6b, 6b formed on the printed wiring board 8b of the DC / DC converter 100b according to the fourth embodiment. Although a so-called PQ type core is used for the transformer 10 and an EI type core is used for the inductors 6b and 6b, the present invention is not limited to this.
　トランス１０は、印刷配線基板８ｂの長手方向の一端部にて長手方向と交差する方向に等間隔に設けられた３つの開口部にＰＱ型のコアの３つの脚部が各別に挿通されている。第１のインダクタ６ｂは、印刷配線基板８ｂの長手方向の略中央部にて長手方向に等間隔に設けられた３つの開口部にＥＩ型のコア６３ｂ，６４ｂの３つの脚部が各別に挿通されている。第２のインダクタ６ｂは、印刷配線基板８ｂの長手方向の他端部にて長手方向に等間隔に設けられた３つの開口部にＥＩ型のコア６３ｂ，６４ｂの３つの脚部が各別に挿通されている。 In the transformer 10, three legs of a PQ-type core are separately inserted into three openings provided at equal intervals in a direction intersecting the longitudinal direction at one longitudinal end of the printed wiring board 8b. . In the first inductor 6b, three legs of the EI- type cores 63b and 64b are separately inserted into three openings provided at equal intervals in the longitudinal direction at substantially the center in the longitudinal direction of the printed wiring board 8b. Have been. In the second inductor 6b, three legs of the EI type cores 63b and 64b are separately inserted into three openings provided at equal intervals in the longitudinal direction at the other end in the longitudinal direction of the printed wiring board 8b. Have been.
　印刷配線基板８ｂの一方の外層には、インダクタ６ｂ，６ｂ夫々の２つの貫通孔６０１，６０２に挿通する導電体６１が導体パターンによって形成されている。この導体パターンは、トランス１０の１ターンの二次巻線１２及び端子Ｃと一体化されている。印刷配線基板８ｂの特定の内層には、インダクタ６ｂ，６ｂ夫々の２つの貫通孔６０１，６０２に挿通する導電体６２が導体パターン（破線で示す）によって形成されている。この導体パターンの一端部、中央部及び他端部夫々は、ビアホール部６２１、６２２及び６２３を介して一方の外層に形成された相異なる導体パターンに電気的に接続されている。ビアホール部６２１，６２２及び６２３は、上記特定の内層及び一方の外層の間を接続するビアホールの集合体である。このように上記特定の内層及び一方の外層に形成されて電気的に接続された導体パターンの全体が導電体６２に相当する。なお、導電体６２のうち、印刷配線基板８ｂの長手方向の他端部にて一方の外層に形成された導体パターンは、端子Ｄと一体化されている。 {Circle around (2)} On one outer layer of the printed wiring board 8b, a conductor 61 to be inserted into the two through holes 601 and 602 of the inductors 6b and 6b is formed by a conductor pattern. This conductor pattern is integrated with the one-turn secondary winding 12 of the transformer 10 and the terminal C. In a specific inner layer of the printed wiring board 8b, a conductor 62 inserted into the two through holes 601 and 602 of the inductors 6b and 6b is formed by a conductor pattern (shown by a broken line). One end, the center, and the other end of the conductor pattern are electrically connected to different conductor patterns formed in one outer layer via via holes 621, 622, and 623, respectively. The via hole portions 621, 622, and 623 are an aggregate of via holes connecting between the specific inner layer and one of the outer layers. The entirety of the conductor pattern formed on the specific inner layer and one outer layer and electrically connected in this way corresponds to the conductor 62. In the conductor 62, a conductor pattern formed on one outer layer at the other end in the longitudinal direction of the printed wiring board 8b is integrated with the terminal D.
　トランス１０の一次巻線１１は、印刷配線基板８の内層に渦巻き状に形成されている。なお、一次巻線１１は、導電体６１及び二次巻線１２との重なり部位を除いて破線で示す。また、導電体６２は、導電体６１との重なり部位を含めて破線で示す。 The primary winding 11 of the transformer 10 is spirally formed in the inner layer of the printed wiring board 8. In addition, the primary winding 11 is shown by a broken line except for an overlapping portion with the conductor 61 and the secondary winding 12. The conductor 62 is indicated by a broken line including a portion where the conductor 62 overlaps the conductor 62.
　トランス１０及び第１のインダクタ６ｂの間の部位における二次巻線１２及び外層の導電体６２の間には、ＦＥＴ５１ｂが表面実装されている。トランス１０及び第１のインダクタ６ｂの間の部位における導電体６１及び外層の導電体６２の間には、ＦＥＴ５２ｂが表面実装されている。インダクタ６ｂ，６ｂの間の部位における導電体６１及び外層の導電体６２の間には、キャパシタ２３が表面実装されている。第２のインダクタ６ｂよりも端子Ｃ及びＤ側の部位における導電体６１及び外層の導電体６２の間には、キャパシタ２１が表面実装されている。 The FET 51b is surface-mounted between the secondary winding 12 and the outer conductor 62 at a location between the transformer 10 and the first inductor 6b. An FET 52b is surface-mounted between a conductor 61 and an outer conductor 62 at a portion between the transformer 10 and the first inductor 6b. The capacitor 23 is surface-mounted between the conductor 61 and the outer conductor 62 in a portion between the inductors 6b, 6b. The capacitor 21 is surface-mounted between the conductor 61 and the outer conductor 62 at a portion closer to the terminals C and D than the second inductor 6b.
　次に、本実施形態４に係るＤＣ／ＤＣコンバータ１００ｂによるノイズ低減の効果と、実施形態２に係るＤＣ／ＤＣコンバータ１００によるノイズ低減の効果とを、シミュレーションによって比較検証した結果について説明する。図１６Ａは、実施形態２に係るＤＣ／ＤＣコンバータ１００によるスイッチングノイズの周波数成分を示すグラフである。図１６Ｂは、実施形態４に係るＤＣ／ＤＣコンバータ１００ｂによるスイッチングノイズの周波数成分を示すグラフである。図１６Ａ及び１６Ｂの縦軸はノイズレベル（ｄＢμＶ）を表し、横軸はスイッチング周波数（基本波）に対する相対的周波数を表す。図中に一点鎖線で示す折れ線は、ノイズの基本波及び高調波のピークを連ねたものである。 Next, the result of comparing and verifying the effect of noise reduction by the DC / DC converter 100b according to the fourth embodiment and the effect of noise reduction by the DC / DC converter 100 according to the second embodiment by simulation will be described. FIG. 16A is a graph illustrating frequency components of switching noise caused by the DC / DC converter 100 according to the second embodiment. FIG. 16B is a graph illustrating frequency components of switching noise caused by the DC / DC converter 100b according to the fourth embodiment. 16A and 16B, the vertical axis represents the noise level (dBμV), and the horizontal axis represents the relative frequency to the switching frequency (fundamental wave). A broken line indicated by a dashed line in the drawing is a series of peaks of a fundamental wave and a harmonic wave of noise.
　シミュレーションで用いたコア６３ｂ，６４ｂの容積、インダクタ６ｂのインダクタンス及びキャパシタ２１，２３のキャパシタンスは以下のとおりである。
（ａ）実施形態２に係るＤＣ／ＤＣコンバータ１００
コア６３ｂ，６４ｂの容積＝Ｌｍｌ（Ｌは定数）
インダクタ６ｂのインダクタンス＝ＭμＨ（Ｍは定数）
キャパシタ２１のキャパシタンス＝ＮμＦ（Ｎは定数）
（ｂ）実施形態４に係るＤＣ／ＤＣコンバータ１００ｂ
コア６３ｂ，６４ｂの容積＝０．２５Ｌｍｌ
インダクタ６ｂのインダクタンス＝０．２ＭμＨ
キャパシタ２１，２３のキャパシタンス＝０．４ＮμＦ The volumes of the cores 63b and 64b, the inductance of the inductor 6b, and the capacitances of the capacitors 21 and 23 used in the simulation are as follows.
(A) DC / DC converter 100 according to Embodiment 2
Volume of cores 63b and 64b = Lml (L is a constant)
Inductance of inductor 6b = MμH (M is a constant)
Capacitance of capacitor 21 = NμF (N is a constant)
(B) DC / DC converter 100b according to the fourth embodiment
Volume of cores 63b and 64b = 0.25Lml
Inductance of inductor 6b = 0.2MμH
Capacitance of capacitors 21 and 23 = 0.4 NμF
　図１６Ｂに示すように、実施形態４に係るＤＣ／ＤＣコンバータ１００ｂによれば、図１６Ａに示す実施形態２に係るＤＣ／ＤＣコンバータ１００と比較して、スイッチング周波数の２倍波及び３倍波（２次高調波及び３次高調波）夫々に相当する周波数におけるノイズレベルが１０ｄＢ及び２０ｄＢ程度下回っている。即ち、実施形態４に係るＤＣ／ＤＣコンバータ１００ｂによれば、実施形態２に係るコア６３ｂ，６４ｂに対して容積比で１／４程度の大きさのコア６３ｂ，６４ｂを用いた場合であっても、高調波のノイズレベルを１０ｄＢ～２０ｄＢ又はそれ以上低減することができる。このような効果は、インダクタ６ｂ，６ｂを含む２つの２端子対回路が縦続接続されているため、第１のインダクタ６ｂ及びキャパシタ２３と、第２のインダクタ６ｂ及びキャパシタ２１とによって実現される２つの低域通過フィルタの減衰量が加算されることによるものと言える。 As shown in FIG. 16B, according to the DC / DC converter 100b according to the fourth embodiment, as compared with the DC / DC converter 100 according to the second embodiment shown in FIG. (Second harmonic and third harmonic) Noise levels at frequencies corresponding to the respective harmonics are lower by about 10 dB and 20 dB. That is, according to the DC / DC converter 100b according to the fourth embodiment, the cores 63b and 64b according to the second embodiment use the cores 63b and 64b having a volume ratio of about 1/4. Also, the noise level of harmonics can be reduced by 10 dB to 20 dB or more. Such an effect is realized by the first inductor 6b and the capacitor 23 and the second inductor 6b and the capacitor 21 because the two two-terminal pair circuits including the inductors 6b and 6b are cascaded. This is due to the fact that the attenuations of the two low-pass filters are added.
　以上のように本実施形態４によれば、１対のコア６３ｂ，６４ｂの２対分によって複合インダクタ６００ｂのインダクタンスが２つのインダクタ６ｂ，６ｂに分散されるため、各対のコア６３ｂ，６４ｂの容積を低減することができる。 As described above, according to the fourth embodiment, the inductance of the composite inductor 600b is distributed to the two inductors 6b and 6b by the two pairs of the pair of cores 63b and 64b. The volume can be reduced.
　また、実施形態４によれば、一対のコア６３ｂ，６４ｂの２つの貫通孔６０１，６０２に一対の導電体６１，６２が挿通されて形成される各インダクタ６ｂが２つのインダクタンス要素を含む２端子対回路と見なされ、各２端子対回路が縦続接続されている。従って、第１のインダクタ６ｂの出力を第２のインダクタ６ｂの入力に引き継ぐことができる。 According to the fourth embodiment, each of the inductors 6b formed by inserting the pair of conductors 61 and 62 into the two through holes 601 and 602 of the pair of cores 63b and 64b has two terminals including two inductance elements. It is regarded as a pair circuit, and each two-terminal pair circuit is cascaded. Therefore, the output of the first inductor 6b can be taken over by the input of the second inductor 6b.
　更に、実施形態４によれば、縦続接続された２つの２端子対回路の出力側の端子対夫々にキャパシタ２３，２１が接続されているため、２段の低域通過フィルタを形成することができる。 Further, according to the fourth embodiment, since the capacitors 23 and 21 are connected to the output-side terminal pairs of the two cascade-connected two-port pair circuits, a two-stage low-pass filter can be formed. it can.
　更に、実施形態３及び４によれば、導電体６１がトランス１０の二次巻線１２及び端子Ｃと一体的に形成され、導電体６２が端子Ｄと一体的に形成されるため、部品間の接合箇所を削減することができる。 Furthermore, according to the third and fourth embodiments, since the conductor 61 is formed integrally with the secondary winding 12 and the terminal C of the transformer 10 and the conductor 62 is formed integrally with the terminal D, Can be reduced.
（実施形態５）
　図１７は、実施形態５に係るＤＣ／ＤＣコンバータ１００の構成例を示す回路図である。実施形態５において、インダクタ６は、トランス１０の入力側（一次巻線１１側）に設けられている。実施形態５のインダクタ６の詳細については、前述のインダクタ６と同様である。実施形態４のインダクタ６においても、前述のインダクタ６と同程度のインダクタンス（例えば、１から３μＨ）が必要とされる。 (Embodiment 5)
FIG. 17 is a circuit diagram illustrating a configuration example of the DC / DC converter 100 according to the fifth embodiment. In the fifth embodiment, the inductor 6 is provided on the input side (the primary winding 11 side) of the transformer 10. The details of the inductor 6 of the fifth embodiment are the same as those of the inductor 6 described above. Also in the inductor 6 of the fourth embodiment, the same inductance (for example, 1 to 3 μH) as the above-described inductor 6 is required.
　実施形態５に係るＤＣ／ＤＣコンバータ１００は、フルブリッジ方式であり、トランス１０の入力側（一次巻線１１側）に、フルブリッジを構成する４つのスイッチング素子３５，３６，３７，３８が設けられている。フルブリッジは、直列接続されたスイッチング素子３５，３６と、直列接続されたスイッチング素子３７，３８と、を並列接続して構成されている。 The DC / DC converter 100 according to the fifth embodiment is of a full-bridge type, and four switching elements 35, 36, 37, and 38 forming a full bridge are provided on the input side (primary winding 11 side) of a transformer 10. Have been. The full bridge is configured by connecting switching elements 35 and 36 connected in series and switching elements 37 and 38 connected in series.
　実施形態１から実施形態４のインダクタ６は、ＤＣ／ＤＣコンバータ１００が備えるトランス１０の出力側（二次巻線１２側）に設けられていた。実施形態１から実施形態４のインダクタ６は、交流電流を平滑化して直流に変換するために用いられていた。これに対して、実施形態５においては、インダクタ６は、ＤＣ／ＤＣコンバータ１００が備えるトランス１０の入力側（一次巻線１１側）に設けられている。実施形態５のインダクタ６は、共振現象により、ＺＶＳ（Ｚｅｒｏ　Ｖｏｌｔａｇｅ　Ｓｗｉｔｃｈｉｎｇ）動作をさせるために用いられる。 The inductors 6 according to the first to fourth embodiments are provided on the output side (the secondary winding 12 side) of the transformer 10 included in the DC / DC converter 100. The inductors 6 according to the first to fourth embodiments are used to smooth an AC current and convert it to a DC. On the other hand, in the fifth embodiment, the inductor 6 is provided on the input side (the primary winding 11 side) of the transformer 10 included in the DC / DC converter 100. The inductor 6 of the fifth embodiment is used for performing a ZVS (Zero Voltage Switching) operation due to a resonance phenomenon.
　実施形態５において、第１導電体６１の一端は、直列接続されたスイッチング素子３５とスイッチング素子３６との間に接続されている。第１導電体６１の他端は、トランス１０の一次巻線１１の一端に接続されている。したがって、スイッチング素子３５、第１導電体６１（インダクタ６）、及び一次巻線１１は、直列接続されている。 In the fifth embodiment, one end of the first conductor 61 is connected between the switching element 35 and the switching element 36 connected in series. The other end of the first conductor 61 is connected to one end of the primary winding 11 of the transformer 10. Therefore, the switching element 35, the first conductor 61 (the inductor 6), and the primary winding 11 are connected in series.
　また、第２導電体の一端は、直列接続されたスイッチング素子３５とスイッチング素子３６との間に接続されている。第２導電体６２の他端は、トランス１０の一次巻線１１の他端に接続されている。したがって、スイッチング素子３７、第２導電体６２（インダクタ６）、及び一次巻線１１は、直列接続されている。 {Circle around (2)} One end of the second conductor is connected between the switching element 35 and the switching element 36 connected in series. The other end of the second conductor 62 is connected to the other end of the primary winding 11 of the transformer 10. Therefore, the switching element 37, the second conductor 62 (the inductor 6), and the primary winding 11 are connected in series.
　スイッチング素子３５、第１導電体６１、第１巻線１１、第２導電体６２、及びスイッチング素子３８は、直列接続されている。したがって、スイッチング素子３５及びスイッチング素子３８がオンになると、スイッチング素子３５から、第１導電体６１、第１巻線１１、第２導電体６２の順で、スイッチング素子３８へ電流が流れる。この場合、第１電流は、第１導電体６１を流れ、インダクタ６外部の回路素子である一次巻線１１へ向かう。第２電流は、第１電流が一次巻線１１を経由して、第２導電体６２に戻る電流である。 The switching element 35, the first conductor 61, the first winding 11, the second conductor 62, and the switching element 38 are connected in series. Therefore, when the switching element 35 and the switching element 38 are turned on, a current flows from the switching element 35 to the switching element 38 in the order of the first conductor 61, the first winding 11, and the second conductor 62. In this case, the first current flows through the first conductor 61 and goes to the primary winding 11 which is a circuit element outside the inductor 6. The second current is a current that returns to the second conductor 62 via the primary winding 11.
　また、スイッチング素子３７、第２導電体６２、第１巻線１１、第１導電体６１、及びスイッチング素子３６は、直列接続されている。したがって、スイッチング素子３７及びスイッチング素子３６がオンになると、スイッチング素子３７から、第２導電体６２、第１巻線１１、第１導電体６１の順で、スイッチング素子３６へ電流が流れる。この場合、第２電流は、第２導電体６２を流れ、インダクタ６の外部の回路素子である一次巻線１１へ向かう。第１電流は、第２電流が一次巻線１１を経由して、第１導電体６１へ戻る電流である。 The switching element 37, the second conductor 62, the first winding 11, the first conductor 61, and the switching element 36 are connected in series. Therefore, when the switching element 37 and the switching element 36 are turned on, a current flows from the switching element 37 to the switching element 36 in the order of the second conductor 62, the first winding 11, and the first conductor 61. In this case, the second current flows through the second conductor 62 and goes to the primary winding 11 which is a circuit element outside the inductor 6. The first current is a current in which the second current returns to the first conductor 61 via the primary winding 11.
　実施形態５において、第１導電体６１及び第２導電体６２を流れる電流の大きさは、５～２０Ａの範囲内と想定され、比較的小電流である。ただし、実施形態５においては、表皮効果又は近接効果などの交流電流に起因する損出（いわゆるＡＣ損）がある。したがって、実施形態５においても、図５等に示す伝熱層６７による放熱性の確保が有効である。 In the fifth embodiment, the magnitude of the current flowing through the first conductor 61 and the second conductor 62 is assumed to be in the range of 5 to 20 A, and is a relatively small current. However, in the fifth embodiment, there is loss (so-called AC loss) due to an alternating current such as a skin effect or a proximity effect. Therefore, also in the fifth embodiment, it is effective to secure the heat dissipation by the heat transfer layer 67 shown in FIG.
１００、１００ｂ　ＤＣ／ＤＣコンバータ
１０　トランス
１１　一次巻線
１２　二次巻線
２０、２１、２２、２３　キャパシタ
３１、３２、３５、３６、３７、３８　ＦＥＴ
４　制御部
５１、５２　ダイオード
５１ｂ、５２ｂ　ＦＥＴ
６、６ｂ、６ｃ　インダクタ
６０、６０１、６０２、６０３　貫通孔
６１、６１ｂ、６１ｃ、６１ｄ、６１ｅ、６２、６２ｂ、６２ｃ、６２ｄ　導電体
６１ｂｕ、６１ｃｕ、６２ｂｕ、６２ｃｕ　Ｕ字状部
６３、６３ｂ、６３ｃ、６４、６４ｂ、６４ｃ　コア
６５、６６、６８、６９　絶縁層
６７　伝熱層
６００、６００ｂ　複合インダクタ
７　筐体
７１、７２　突出部
８、８ｂ 　印刷配線基板
Ａ、Ｂ、Ｃ、Ｄ　端子

  100, 100b DC / DC converter 10 Transformer 11 Primary winding 12 Secondary winding 20, 21, 22, 23 Capacitors 31, 32, 35, 36, 37, 38 FET
4 Controllers 51, 52 Diodes 51b, 52b FET
6, 6b, 6c Inductors 60, 601, 602, 603 Through holes 61, 61b, 61c, 61d, 61e, 62, 62b, 62c, 62d Conductors 61bu, 61cu, 62bu, 62cu U-shaped portions 63, 63b, 63c , 64, 64b, 64c Cores 65, 66, 68, 69 Insulation layer 67 Heat transfer layer 600, 600b Composite inductor 7 Housing 71, 72 Projection 8, 8b Printed wiring boards A, B, C, D terminals

Claims (18)

  1. 　インダクタであって、
    　第１貫通孔を有するコアと、
    　前記第１貫通孔に挿通された部位を有し、第１電流が流れる第１導電体と、
    　前記第１貫通孔に挿通された部位を有し、第２電流が流れる第２導電体と、
    　を備え、
    　前記第１電流及び前記第２電流のうちの一方の電流は、他方の電流が前記インダクタ外部を経由して前記インダクタへ戻る電流であり、
    　前記第１貫通孔内における前記第１電流及び前記第２電流の向きは、前記第１貫通孔の貫通方向に対して同一である
    　インダクタ。     An inductor,
    A core having a first through hole;
    A first conductor having a portion inserted into the first through hole, through which a first current flows;
    A second conductor having a portion inserted through the first through hole, through which a second current flows;
    With
    One of the first current and the second current is a current in which the other current returns to the inductor via the outside of the inductor,
    The direction of the first current and the second current in the first through hole is the same as the direction of the first through hole.
  2. 　前記コアは、前記第１貫通孔と同一方向に貫通する第２貫通孔を更に備え、
    　前記第１導電体は、前記第２貫通孔に挿通された部位を更に有し、
    　前記第２導電体は、前記第２貫通孔に挿通された部位を更に有し、
    　前記第２貫通孔内における前記第１電流及び前記第２電流の向きは、前記第２貫通孔の貫通方向に対して同一であり、前記第１貫通孔内における前記第１電流及び前記第２電流の向きとは逆である
    　請求項１に記載のインダクタ。     The core further includes a second through hole penetrating in the same direction as the first through hole,
    The first conductor further has a portion inserted into the second through-hole,
    The second conductor further has a portion inserted into the second through-hole,
    The directions of the first current and the second current in the second through-hole are the same with respect to the direction of penetration of the second through-hole, and the first current and the second current in the first through-hole. The inductor according to claim 1, wherein the direction of the current is opposite to the direction of the current.
  3. 　前記第１導電体は、第１Ｕ字状部を有し、
    　前記第１Ｕ字状部は、前記第１導電体が前記第１貫通孔に挿通された前記部位及び前記第２貫通孔に挿通された前記部位を含む
    　請求項２に記載のインダクタ。     The first conductor has a first U-shaped portion,
    The inductor according to claim 2, wherein the first U-shaped portion includes the portion where the first conductor is inserted through the first through hole and the portion where the first conductor is inserted through the second through hole.
  4. 　前記第２導電体は、前記第１Ｕ字状部に対して逆向きになるように配置された第２Ｕ字状部を有し、
    　前記第２Ｕ字状部は、前記第２導電体が前記第１貫通孔に挿通された前記部位及び前記第２貫通孔に挿通された前記部位を含む
    　請求項３に記載のインダクタ。     The second conductor has a second U-shaped portion disposed to be opposite to the first U-shaped portion,
    The inductor according to claim 3, wherein the second U-shaped portion includes the portion where the second conductor is inserted into the first through hole and the portion where the second conductor is inserted into the second through hole.
  5. 　前記コアは、ＥＥ型、ＥＩ型及びＥＲ型の何れかである請求項２から請求項４の何れか１項に記載のインダクタ。 The inductor according to any one of claims 2 to 4, wherein the core is any of an EE type, an EI type, and an ER type.
  6. 　前記第１導電体及び前記第２導電体の夫々は、断面が矩形状をなしている請求項１から請求項５の何れか１項に記載のインダクタ。 6. The inductor according to claim 1, wherein each of the first conductor and the second conductor has a rectangular cross section. 7.
  7. 　前記第１導電体及び前記第２導電体は、多層配線基板の異なる層に含まれる導体パターンである請求項６に記載のインダクタ。 7. The inductor according to claim 6, wherein the first conductor and the second conductor are conductor patterns included in different layers of a multilayer wiring board.
  8. 　前記コアは、フェライトコア又は圧粉コアである請求項１から請求項７の何れか１項に記載のインダクタ。 The inductor according to any one of claims 1 to 7, wherein the core is a ferrite core or a dust core.
  9. 　伝熱材料を含む伝熱層を更に備え、
    　前記伝熱層は、
    　　前記第１導電体と、前記第２導電体と、の間、及び
    　　前記第１導電体及び前記第２導電体と、前記コアと、の間
    　の少なくとも何れか一方に配置されている
    　請求項１から請求項８の何れか１項に記載のインダクタ。     Further comprising a heat transfer layer including a heat transfer material,
    The heat transfer layer,
    2. The device is disposed between at least one of the first conductor and the second conductor, and between the first conductor and the second conductor, and the core. 3. The inductor according to any one of claims 1 to 8.
  10. 　前記コアは、互いに突き合わせ可能な一対のコア部材を備え、
    　前記第１貫通孔は、前記一対のコア部材を突き合せた状態で突合せ面に沿った方向に貫通している
    　請求項１から９のいずれか１項に記載のインダクタ。     The core includes a pair of core members that can abut each other,
    The inductor according to any one of claims 1 to 9, wherein the first through-hole penetrates in a direction along an abutting surface in a state where the pair of core members abut each other.
  11. 　請求項１から請求項９の何れか１項に記載のインダクタを含む複合インダクタであって、
    　前記第１導電体及び前記第２導電体が前記第１貫通孔に挿通された前記コアを複数備える複合インダクタ。     A composite inductor including the inductor according to any one of claims 1 to 9,
    A composite inductor comprising a plurality of the cores each having the first conductor and the second conductor inserted through the first through hole.
  12. 　各コアの前記第１貫通孔に前記第１導電体及び第２導電体が挿通されることによって形成されるインダクタによる２端子対回路が縦続接続となるようにしてある請求項１１に記載の複合インダクタ。 12. The composite according to claim 11, wherein a two-terminal pair circuit composed of inductors formed by inserting the first conductor and the second conductor into the first through-hole of each core is cascaded. 13. Inductor.
  13. 　少なくとも１つの前記２端子対回路における一方の端子対にキャパシタを接続してある請求項１２に記載の複合インダクタ。 The composite inductor according to claim 12, wherein a capacitor is connected to one terminal pair of the at least one two-terminal pair circuit.
  14. 　請求項１から請求項１０の何れか１項に記載のインダクタと、
    　スイッチング素子と、
    　一次巻線が前記スイッチング素子に直列に接続されたトランスと
    　を備え、
    　前記第１導電体は、前記トランスの二次巻線から外部へ流出する流出電流が前記第１電流として流れるように接続され、前記第２導電体は、外部から前記二次巻線に戻る戻り電流が前記第２電流として流れるように接続されているＤＣ／ＤＣコンバータ。     An inductor according to any one of claims 1 to 10,
    A switching element;
    A transformer having a primary winding connected in series with the switching element,
    The first conductor is connected such that an outflow current flowing out of the secondary winding of the transformer to the outside flows as the first current, and the second conductor returns from the outside to the secondary winding. A DC / DC converter connected so that current flows as the second current.
  15. 　請求項１１から請求項１３の何れか１項に記載の複合インダクタと、
    　スイッチング素子と、
    　一次巻線が前記スイッチング素子に直列に接続されたトランスと
    　を備え、
    　前記第１導電体は、前記トランスの二次巻線から外部へ流出する流出電流が前記第１電流として流れるよう接続され、前記第２導電体は、外部から前記二次巻線に戻る戻り電流が前記第２電流として流れるように接続されているＤＣ／ＤＣコンバータ。     A composite inductor according to any one of claims 11 to 13,
    A switching element;
    A transformer having a primary winding connected in series with the switching element,
    The first conductor is connected such that an outflow current flowing out of the secondary winding of the transformer to the outside flows as the first current, and the second conductor is a return current returning from the outside to the secondary winding. Is connected to flow as the second current.
  16. 　前記第１導電体は、
    　前記二次巻線と一体的に形成されており、
    　前記第１導電体及び前記第２導電体の少なくとも一方が出力側の電路と一体的に形成されている
    　請求項１４又は請求項１５に記載のＤＣ／ＤＣコンバータ。     The first conductor is
    Being formed integrally with the secondary winding,
    16. The DC / DC converter according to claim 14, wherein at least one of the first conductor and the second conductor is formed integrally with an output-side electric circuit.
  17. 　請求項１から請求項１０の何れか１項に記載のインダクタと、
    　スイッチング素子と、
    　一次巻線を有するトランスと、
    　を備え、
    　少なくとも、前記スイッチング素子と、前記インダクタと、前記一次巻線と、が直列接続されているＤＣ／ＤＣコンバータ。     An inductor according to any one of claims 1 to 10,
    A switching element;
    A transformer having a primary winding;
    With
    A DC / DC converter in which at least the switching element, the inductor, and the primary winding are connected in series.
  18. 　請求項１から請求項１０の何れか１項に記載のインダクタと、
    　前記インダクタ外部において、前記第１導電体及び前記第２導電体に直列接続された回路素子と、
    を備える回路。

          An inductor according to any one of claims 1 to 10,
    A circuit element connected in series to the first conductor and the second conductor outside the inductor;
    A circuit comprising:

PCT/JP2019/024706 2018-07-30 2019-06-21 Inductor, composite inductor, dc/dc converter, and circuit WO2020026641A1 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5822579A (en) * 1981-08-04 1983-02-09 Hitachi Metals Ltd Switching power source
JPS6481661A (en) * 1987-09-22 1989-03-27 Dx Antenna Constant-voltage power circuit
JP2007097390A (en) * 2005-08-31 2007-04-12 Tdk Corp Switching power supply equipment
JP2014120559A (en) * 2012-12-14 2014-06-30 Kitagawa Kogyo Co Ltd Magnetic material core
US20170047155A1 (en) * 2011-11-22 2017-02-16 Volterra Semiconductor LLC Coupled Inductor Arrays And Associated Methods
US20170178795A1 (en) * 2015-12-21 2017-06-22 Infineon Technologies Austria Ag Through-Hole Inductor for Placement Over a Power Stage of a Power Converter

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5822579A (en) * 1981-08-04 1983-02-09 Hitachi Metals Ltd Switching power source
JPS6481661A (en) * 1987-09-22 1989-03-27 Dx Antenna Constant-voltage power circuit
JP2007097390A (en) * 2005-08-31 2007-04-12 Tdk Corp Switching power supply equipment
US20170047155A1 (en) * 2011-11-22 2017-02-16 Volterra Semiconductor LLC Coupled Inductor Arrays And Associated Methods
JP2014120559A (en) * 2012-12-14 2014-06-30 Kitagawa Kogyo Co Ltd Magnetic material core
US20170178795A1 (en) * 2015-12-21 2017-06-22 Infineon Technologies Austria Ag Through-Hole Inductor for Placement Over a Power Stage of a Power Converter

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