WO2020015084A1 - 一种阵列基板的制备方法及阵列基板 - Google Patents

一种阵列基板的制备方法及阵列基板 Download PDF

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WO2020015084A1
WO2020015084A1 PCT/CN2018/104467 CN2018104467W WO2020015084A1 WO 2020015084 A1 WO2020015084 A1 WO 2020015084A1 CN 2018104467 W CN2018104467 W CN 2018104467W WO 2020015084 A1 WO2020015084 A1 WO 2020015084A1
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layer
metal layer
plane area
via hole
plane
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PCT/CN2018/104467
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English (en)
French (fr)
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吕晓文
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/203,785 priority Critical patent/US10665622B2/en
Publication of WO2020015084A1 publication Critical patent/WO2020015084A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present invention relates to the field of display, and in particular, to a method for preparing an array substrate and an array substrate.
  • FIG. 1 is a schematic structural diagram of a conventional array substrate having a hole digging process.
  • a partial structure diagram of a TFT using a back channel etching (BCE) structure is shown, which mainly shows that it includes a first metal layer 11 ′ sequentially deposited on a glass substrate 10 ′.
  • the connection of 15 ′ with the second metal layer 13 ′ and the first metal layer 11 ′ is achieved by performing a hole digging process after the passivation layer is deposited to form deep and shallow holes.
  • a step of digging the gate insulating layer is added, that is, digging holes in the gate insulating layer and the passivation layer respectively, so that the situation of deep and shallow holes does not occur.
  • FIG. 2 a partial structural schematic diagram of an existing array substrate with two boring processes is shown.
  • this method can solve the problem of residual via holes in the plane, in the splicing screen shown in Figure 3 below, the upper half screen (AA-1) and the lower half screen (AA-2) are respectively bound to the binding area.
  • the technical problem to be solved by the present invention is to provide a method for preparing an array substrate and an array substrate, which can improve the performance of products out of the plane and in the plane, and increase the product yield.
  • an aspect of an embodiment of the present invention provides a method for manufacturing an array substrate, including steps:
  • a gate insulating layer is deposited on the base substrate and the first metal layer, and a first via is formed in an in-plane area of the gate insulating layer, and the first via directly reaches the first metal in the plane.
  • a second metal layer is deposited on the in-plane area and the out-plane area of the gate insulation layer, respectively, wherein the second metal layer located in the in-plane area fills the first via hole;
  • a third via hole is formed in the out-of-plane region of the layer directly to the surface of the second metal layer, and a fourth via hole is formed in the out-of-plane region of the passivation layer directly to the surface of the first metal layer in the out-of-plane region;
  • a transparent conductive layer is deposited in the in-plane area and the out-plane area of the passivation layer, respectively.
  • the transparent conductive layer located in the in-plane area is filled with the second via; the transparent conductive layer located in the out-of-plane area is filled with the third via. Hole and fourth via.
  • the gate insulating layer is made of SiOx material or SiOx / SiNx laminated composite material, and the transparent conductive layer is an ITO thin film layer.
  • the first via is directly opposite and located on the first metal layer in the in-plane area
  • the second via is directly opposite and located on the second metal layer in the in-plane area
  • the third via is The fourth via is directly opposite and located on the second metal layer in the out-of-plane area
  • the fourth via is directly opposite and located on the first metal layer in the out-of-plane area.
  • first via hole and the second via hole are staggered from each other.
  • the second via, the third via, and the fourth via are obtained by using the same mask.
  • the present invention also provides an array substrate, which at least includes:
  • a first via is formed at a position in the in-plane area of the gate insulating layer on the first metal layer, and the first via is directly to the surface of the first metal layer;
  • a passivation layer is deposited on the second metal layer and the gate insulation layer; a second region directly on the surface of the second metal layer is formed at a position in the in-plane region of the passivation layer on the second metal layer.
  • a transparent conductive layer is deposited in the in-plane area of the passivation layer, wherein the transparent conductive layer located in the in-plane area fills the second via hole.
  • a first metal layer is deposited on the out-of-plane area of the base substrate
  • a third via is formed in the out-of-plane region of the passivation layer directly to the surface of the second metal layer, and an out-of-plane region of the passivation layer is formed on the surface of the first metal layer.
  • a transparent conductive layer is deposited in an out-of-plane area of the passivation layer, and the transparent conductive layer fills the third via hole and the fourth via hole.
  • the gate insulating layer is made of SiOx material or SiOx / SiNx laminated composite material, and the transparent conductive layer is an ITO thin film layer.
  • first via hole and the second via hole are staggered from each other.
  • the second via, the third via, and the fourth via are obtained by using the same mask.
  • the invention provides a method for preparing an array substrate and an array substrate.
  • a via hole for digging holes in the gate insulating layer and the passivation layer in the plane the depth of each hole can be more conveniently controlled because there are no deep and shallow holes.
  • Etching time to avoid coke residues caused by too long shallow hole etching time, so that the in-plane contact impedance can be normal and normal display effect can be obtained.
  • the separate out-of-plane area of the upper and lower half screens does not need to use a separate gate insulation layer for digging and drying processes, so it is not easy to accumulate static electricity, thereby avoiding There is a pressure difference between the upper and lower half-screen charges at the joint of the common electrode layer, thereby forming the probability of occurrence of electrostatic discharge, which can improve product yield and reduce production costs.
  • FIG. 1 is a schematic structural diagram of an array substrate having a hole digging process in the prior art
  • FIG. 2 is a schematic structural diagram of an array substrate having two digging processes in the prior art
  • FIG. 3 is a schematic structural diagram of a splicing screen in the prior art
  • FIG. 4 is a schematic flowchart of an embodiment of a method for manufacturing an array substrate provided by the present invention.
  • FIG. 5 is a structural schematic diagram corresponding to each step of FIG. 4.
  • FIG. 4 a schematic diagram of a main process of an embodiment of a method for manufacturing an array substrate according to the present invention is shown, and a structural schematic diagram corresponding to each step of the manufacturing method shown in FIG. 5 is combined together.
  • the preparation method includes the following steps:
  • a gate insulating layer 12 is deposited on the base substrate 10 and the first metal layer 11, and a first via hole is formed at a position on the first metal layer 11 in an in-plane area of the gate insulating layer 12. 120, the first via hole 120 directly reaches the surface of the first metal layer 11; wherein the gate insulating layer 12 is made of SiOx material or SiOx / SiNx laminated composite material;
  • a second metal layer 13 is deposited on the in-plane area and the out-plane area of the gate insulation layer 12, respectively.
  • the second metal layer 13 located in the in-plane area fills the first via hole 120, so that the first The two metal layers 13 are electrically connected to the first metal layer 11; the first vias 120 are directly opposite and located on the in-plane first metal layer 11.
  • a passivation layer 14 is deposited on the second metal layer 13 and the gate insulating layer 12, and a passivation layer 14 is formed on the second metal layer 13 at a position in an in-plane region of the passivation layer 14.
  • step S13 Form a fourth via 142 directly to the surface of the first metal layer 11 at a position where the out-of-plane area of the passivation layer 14 is located on the first metal layer 11; wherein the first via 120 And the second via hole 140 are staggered from each other; and in step S13, the second via hole 140, the third via hole 141, and the fourth via hole 142 are obtained through the same mask; and
  • the hole 140 is directly opposite and located on the second metal layer 13 in the plane;
  • the third via hole 141 is directly opposite and located on the second metal layer 13 out of the plane, and the fourth via 142 is directly opposite and located Above the out-of-plane first metal layer 11.
  • a transparent conductive layer 15 is deposited in the in-plane area and the out-plane area of the passivation layer 14, respectively.
  • the transparent conductive layer 15 located in the in-plane area fills the second via hole 140, so that the transparent conductive layer 15 and The second metal layer 13 is electrically connected; the transparent conductive layer 15 located in the out-of-plane area fills the third via hole 141 and the fourth via hole 142, so that the transparent conductive layer 15 and the second metal layer 13 and the first metal layer 11 to achieve electrical connection.
  • the transparent conductive layer 15 may be an ITO thin film layer.
  • the "in-plane area” refers to the display area of the liquid crystal panel
  • the "out-plane area” refers to the non-display area of the liquid crystal panel provided around the aforementioned display area.
  • First metal layers 11 are deposited on the in-plane area and the out-plane area of the base substrate 10, respectively;
  • a gate insulating layer 12 is deposited on the base substrate 10 and the first metal layer 11;
  • a first via hole 120 is formed at a position in the in-plane region of the gate insulating layer 12 on the first metal layer 11, and the first via hole 120 reaches directly to the surface of the first metal 11 layer; wherein the gate
  • the insulating layer 12 is made of SiOx material or SiOx / SiNx laminated composite material;
  • a second metal layer 13 is deposited on the in-plane area and the out-plane area of the gate insulating layer 12, respectively, wherein the second metal layer 13 located in the in-plane area fills the first via hole 120;
  • a passivation layer 14 is deposited on the second metal layer 13 and the gate insulation layer 12; a position in the in-plane region of the passivation layer 14 on the second metal layer 13 is directly formed to the first metal layer 13.
  • a second via hole 140 on the surface of the two metal layer 13, the second via hole 140 and the first via hole 120 are staggered from each other; an out-of-plane area of the passivation layer 14 is located on the second metal layer 13
  • a third via 141 is formed at a position directly to the surface of the second metal layer 13, and a direct access to the first metal is formed at a position outside the plane of the passivation layer 14 on the first metal layer 11
  • the fourth via 142 on the surface of the layer 11; in one example, the second via 140, the third via 141, and the fourth via 142 are obtained by using the same mask;
  • the array substrate provided by the present invention is difficult to accumulate static electricity due to the design of digging shallow and deep holes at the same time when the passivation layer is still used in the out-of-plane via holes.
  • the pressure difference between the upper and lower half screen charges at the splicing place of the common electrode layer can prevent the occurrence of electrostatic discharge, thereby improving the product yield of the splicing screen.
  • the invention provides a method for preparing an array substrate and an array substrate.
  • a via hole for digging holes in the gate insulating layer and the passivation layer in the plane the depth of each hole can be more conveniently controlled because there are no deep and shallow holes.
  • Etching time to avoid coke residues caused by too long shallow hole etching time, so that the in-plane contact impedance can be normal and normal display effect can be obtained.

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Abstract

提供一种阵列基板的制备方法及阵列基板。制备方法包括步骤：在衬底基板（10）上沉积第一金属层（11）；在衬底基板（10）及第一金属层（11）上沉积一层栅绝缘层（12），并在其面内区域形成第一过孔（120）；在栅绝缘层（12）的面内区域及面外区域分别沉积第二金属层（13），其中，位于面内区域的第二金属层（13）充满第一过孔（120）；在第二金属层（13）、栅绝缘层（12）上沉积钝化层（14），并在钝化层（14）的面内区域上形成第二过孔（140）；在钝化层（14）的面外区域上分别形成第三过孔（141）、第四过孔（142）；在钝化层（14）的面内区域及面外区域分别沉积透明导电层（15），位于面内区域的透明导电层（15）充满第二过孔（140）；位于面外区域的透明导电层充满第三过孔（141）和第四过孔（142）。可以提高产品良率。

Description

一种阵列基板的制备方法及阵列基板
本申请要求于2018年7月17日提交中国专利局、申请号为201810784374.5、发明名称为“一种阵列基板的制备方法及阵列基板”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示领域，特别涉及一种阵列基板的制备方法及阵列基板。
背景技术
在薄膜晶体管液晶显示器(TFT-LCD)的阵列基板中，对于TFT中的有源层，目前应用较为广泛的是高迁移率的IGZO(铟镓锌氧化物)材料，同时拼接屏也越来越广泛的应用于我们的生活中。IGZO有源层的栅绝缘层材料一般采用SiOx或者SiOx/SiNx复合材料，相对SiNx来说，SiOx的刻蚀速率较低，刻蚀时间较长。如图1示出了现有的一种具有一道挖孔制程的阵列基板的结构示意图。在图1中，其采用了背沟道刻蚀型(Back channel etching,BCE)结构的TFT的局部结构示意图，主要示出了其包括依次在玻璃基板10’上沉积的第一金属层11’、栅绝缘层12’、第二金属层13’(形成IGZO有源层和源漏极)、钝化层14’和ITO(铟锡氧化物)层15’，从中可以看出，其中ITO层15’与第二金属层13’及第一金属层11’的连接，是通过在沉积钝化层后进行一次挖孔制程，形成深浅孔而实现。但是这样的制程会存在不足之处，因为为配合深孔刻蚀，浅孔刻蚀时间过长会出现过孔焦化残留，从而导致过孔接触阻抗过大而传导性能不佳，可能会导致显示异常。这种情形一般发生在面内小孔处。
为解决面内过孔残留的问题，在一些制程中会增加一道栅绝缘层挖孔步骤，即在栅绝缘层和钝化层分别进行挖孔，这样不会出现深浅孔的情形。如图2所示，示出了现有的一种具有两道挖孔制程的阵列基板的局部结构示意图。但是这种方法虽然可以解决面内过孔残留的问题，但是在如下图3所示 的拼接屏中，其中上半屏(AA-1)和下半屏(AA-2)分别与绑定区17’连接，但因为上下半屏在制程中会存在电荷不匹配，如果此时上下半屏的面外区域都采用栅绝缘层挖孔制程，则在干燥过程中易累计静电，使上下半屏电荷在公共电极层16’(COM)的中间分屏位置有压差存在形成静电释放(ESD)，造成显示面板无法正常显示，甚至因为ESD造成薄膜剥落(Peeling)，无法进行后续制程。
发明内容
本发明所要解决的技术问题在于，提供一种阵列基板的制备方法及阵列基板，可以改善面外及面内的产品性能，提高产品良率。
为了解决上述技术问题，本发明的实施例的一方面提供一种阵列基板的制备方法，包括步骤：
在衬底基板的面内区域及面外区域上分别沉积有第一金属层；
在所述衬底基板及第一金属层上沉积一层栅绝缘层，在所述栅绝缘层的面内区域形成第一过孔，所述第一过孔直达面内的所述第一金属层表面；
在所述栅绝缘层的面内区域及面外区域分别沉积有第二金属层，其中，位于面内区域的第二金属层充满所述第一过孔；
在所述第二金属层、栅绝缘层上沉积钝化层，并在所述钝化层的面内区域形成直达面内区域的第二金属层表面的第二过孔；在所述钝化层的面外区域形成直达面外区域的第二金属层表面的第三过孔，在所述钝化层的面外区域形成直达面外区域的第一金属层表面的第四过孔；
在所述钝化层的面内区域及面外区域分别沉积透明导电层，位于面内区域的透明导电层充满所述第二过孔；位于面外区域的透明导电层充满所述第三过孔和第四过孔。
其中，所述栅绝缘层采用SiOx材料，或SiOx/SiNx叠层复合材料，所述透明导电层为ITO薄膜层。
其中，所述第一过孔正对且位于面内区域的第一金属层之上，所述第二过孔正对且位于面内区域的第二金属层之上；所述第三过孔正对且位于面外区域的第二金属层之上，所述第四过孔正对且位于面外区域的第一金属层之 上。
其中，所述第一过孔和所述第二过孔相互错开。
其中，所述第二过孔、第三过孔、第四过孔采用同一道光罩获得。
相应地，本发明还提供一种阵列基板，其至少包括：
衬底基板；
在衬底基板的面内区域沉积有第一金属层；
在所述衬底基板及第一金属层上沉积有一层栅绝缘层；
在所述栅绝缘层的面内区域位于第一金属层上的位置形成有第一过孔，所述第一过孔直达所述第一金属层表面；
在所述栅绝缘层的面内区域沉积有第二金属层，其中，位于面内区域的第二金属层充满所述第一过孔；
在所述第二金属层、栅绝缘层上沉积有一层钝化层；在所述钝化层的面内区域位于所述第二金属层上的位置形成有直达第二金属层表面的第二过孔；
在所述钝化层的面内区域沉积有透明导电层，其中，位于面内区域的透明导电层充满所述第二过孔。
其中，在衬底基板的面外区域上沉积有第一金属层；
在所述栅绝缘层的面外区域沉积有第二金属层；
在所述钝化层的面外区域形成有直达面外的第二金属层表面的第三过孔，在所述钝化层的面外区域上形成有直达面外的第一金属层表面的第四过孔；
在所述钝化层的面外区域沉积有透明导电层，所述透明导电层充满所述第三过孔和第四过孔。
其中，所述栅绝缘层采用SiOx材料，或SiOx/SiNx叠层复合材料，所述透明导电层为ITO薄膜层。
其中，所述第一过孔和所述第二过孔相互错开。
其中，所述第二过孔、第三过孔、第四过孔采用同一道光罩获得。
实施本发明实施例，具有如下有益效果：
本发明提供的一种阵列基板的制备方法及阵列基板，通过在面内在栅绝 缘层和钝化层分别挖孔的过孔设计，由于不存在深浅孔，可以更方便地控制每一孔的刻蚀时间，避免出现浅孔刻蚀时间过长而出现的焦化残留，从而可以保证面内接触阻抗正常，获得正常显示效果。
同时，在面外的过孔处仍使用钝化层时同时挖深浅孔设计，此时上下半屏的面外区域无需采用单独的栅绝缘层挖孔及干燥制程，故不易累计静电，从而避免上下半屏电荷在公共电极层的拼接处存在压差从而形成静电释放的发生概率，从而可以提高产品良率，降低生产成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是现有技术中一种具有一道挖孔制程的阵列基板的结构示意图；
图2是现有技术中一种具有两道挖孔制程的阵列基板的结构示意图；
图3是现有技术中一种拼接屏的结构示意图；
图4是本发明提供的一种阵列基板的制备方法一个实施例的主流程示意图；
图5是对应于图4各步骤形成的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚完整地描述，显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了与本发明关系不大的其他细节。
如图4所示，示出了本发明提供的一种阵列基板的制备方法一个实施例的主流程示意图，一并结合图5所示的制备方法各步骤所对应的结构示意图。在该实施例中，所述制备方法包括如下步骤：
步骤S10，在衬底基板10的面内区域及面外区域上分别沉积第一金属层11，所述衬底基板10可以玻璃基板或PI基板；
步骤S11，在所述衬底基板10及第一金属层11上沉积一层栅绝缘层12，在所述栅绝缘层12的面内区域位于第一金属层11上的位置形成第一过孔120，所述第一过孔120直达所述第一金属层11表面；其中，所述栅绝缘层12采用SiOx材料，或SiOx/SiNx叠层复合材料；
步骤S12，在所述栅绝缘层12的面内区域及面外区域分别沉积第二金属层13，其中，位于面内区域的第二金属层13充满所述第一过孔120，从而使第二金属层13与第一金属层11实现电连接；所述第一过孔120正对且位于面内的第一金属层11之上。
步骤S13，在所述第二金属层13、栅绝缘层12上沉积钝化层14，并在所述钝化层14的面内区域位于所述第二金属层13上的位置形成直达所述第二金属层13表面的第二过孔140；在所述钝化层14的面外区域位于所述第二金属层13上的位置形成直达所述第二金属层13表面的第三过孔141，在所述钝化层14的面外区域位于所述第一金属层11上的位置形成直达所述第一金属层11表面的第四过孔142；其中，所述第一过孔120和所述第二过孔140相互错开；且在步骤S13中，所述第二过孔140、第三过孔141、第四过孔142通过同一个光罩获得；且，所述第二过孔140正对且位于面内的第二金属层13之上；所述第三过孔141正对且位于面外的第二金属层13之上，所述第四过孔142正对且位于面外的第一金属层11之上。
步骤S14，在所述钝化层14的面内区域及面外区域分别沉积透明导电层15，位于面内区域的透明导电层15充满所述第二过孔140，从而使透明导电层15与第二金属层13实现电连接；位于面外区域的透明导电层15充满所述第三过孔141和第四过孔142，从而使透明导电层15与第二金属层13、第一金属层11实现电连接。在一个例子中，所述透明导电层15具体可以是ITO薄膜层。
需要说明的是，本发明中“面内区域”是指液晶面板的显示区域，“面外区域”是指围绕前述显示区域而设的液晶面板的非显示区域。
相应地，本发明实施例还提供一种阵列基板，其应用于拼接屏中，其包括：
衬底基板10；
在衬底基板10的面内区域及面外区域上分别沉积有第一金属层11；
在所述衬底基板10及第一金属层11上沉积有一层栅绝缘层12；
在所述栅绝缘层12的面内区域位于第一金属层11上的位置形成有第一过孔120，所述第一过孔120直达所述第一金属11层表面；其中，所述栅绝缘层12采用SiOx材料，或SiOx/SiNx叠层复合材料；
在所述栅绝缘层12的面内区域及面外区域分别沉积有第二金属层13，其中，位于面内区域的第二金属层13充满所述第一过孔120；
在所述第二金属层13、栅绝缘层12上沉积有一层钝化层14；在所述钝化层14的面内区域位于所述第二金属层13上的位置形成有直达所述第二金属层13表面的第二过孔140，所述第二过孔140与所述第一过孔120相互错开；在所述钝化层14的面外区域位于所述第二金属层13上的位置形成有直达所述第二金属层13表面的第三过孔141，在所述钝化层14的面外区域位于所述第一金属层11上的位置形成有直达所述第一金属层11表面的第四过孔142；在一个例子中，所述第二过孔140、第三过孔141、第四过孔142采用同一道光罩获得；
在所述钝化层14的面内区域及面外区域分别沉积有ITO金属层15，其中，位于面内区域的ITO金属层15充满所述第二过孔140；位于面外区域的ITO金属层15充满所述第三过孔141和第四过孔142。
可以理解的是，本发明提供的阵列基板，由于面外的过孔处仍使用钝化层时同时挖深浅孔设计，由于无需采用单独的栅绝缘层挖孔及干燥制程，故不易累计静电，在应用于上下屏的拼接屏中时，可以避免上下半屏电荷在公共电极层的拼接处存在压差从而形成静电释放的发生概率，从而可以提高拼接屏的产品良率。
更详细的细节，请参考前述对图4和图5的描述，在此不进行详述。
实施本发明实施例，具有如下有益效果：
本发明提供的一种阵列基板的制备方法及阵列基板，通过在面内在栅绝缘层和钝化层分别挖孔的过孔设计，由于不存在深浅孔，可以更方便地控制每一孔的刻蚀时间，避免出现浅孔刻蚀时间过长而出现的焦化残留，从而可以保证面内接触阻抗正常，获得正常显示效果。
同时，在面外的过孔处仍使用钝化层时同时挖深浅孔设计，此时上下半屏的面外区域无需采用单独的栅绝缘层挖孔及干燥制程，故不易累计静电，从而避免上下半屏电荷在公共电极层的拼接处存在压差从而形成静电释放的发生概率，从而可以提高产品良率，降低生产成本。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (10)

  1. 一种阵列基板的制备方法，其中，包括步骤：
    在衬底基板的面内区域及面外区域上分别沉积有第一金属层；
    在所述衬底基板及第一金属层上沉积一层栅绝缘层，在所述栅绝缘层的面内区域形成第一过孔，所述第一过孔直达面内区域的所述第一金属层表面；
    在所述栅绝缘层的面内区域及面外区域分别沉积有第二金属层，其中，位于面内区域的第二金属层充满所述第一过孔；
    在所述第二金属层、栅绝缘层上沉积钝化层，并在所述钝化层的面内区域形成直达面内区域的所述第二金属层表面的第二过孔；在所述钝化层的面外区域形成直达面外区域的所述第二金属层表面的第三过孔，在所述钝化层的面外区域形成直达面外区域的所述第一金属层表面的第四过孔；
    在所述钝化层的面内区域及面外区域分别沉积透明导电层，位于面内区域的透明导电层充满所述第二过孔；位于面外区域的透明导电层充满所述第三过孔和第四过孔。
  2. 如权利要求1所述的制备方法，其中，所述栅绝缘层采用SiOx材料，或SiOx/SiNx叠层复合材料，所述透明导电层为ITO薄膜层。
  3. 如权利要求1所述的特备方法，其中，所述第一过孔正对且位于面内区域的第一金属层之上，所述第二过孔正对且位于面内区域的第二金属层之上；所述第三过孔正对且位于面外区域的第二金属层之上，所述第四过孔正对且位于面外区域的第一金属层之上。
  4. 如权利要求3所述的制备方法，其中，所述第一过孔和所述第二过孔相互错开。
  5. 如权利要求4所述的制备方法，其中，所述第二过孔、第三过孔、第四过孔采用同一道光罩获得。
  6. 一种阵列基板，其中，至少包括：
    衬底基板；
    在衬底基板的面内区域沉积有第一金属层；
    在所述衬底基板及第一金属层上沉积有一层栅绝缘层；
    在所述栅绝缘层的面内区域位于第一金属层上的位置形成有第一过孔，所述第一过孔直达所述第一金属层表面；
    在所述栅绝缘层的面内区域沉积有第二金属层，其中，位于面内区域的第二金属层充满所述第一过孔；
    在所述第二金属层、栅绝缘层上沉积有一层钝化层；在所述钝化层的面内区域位于所述第二金属层上的位置形成有直达所述第二金属层表面的第二过孔；
    在所述钝化层的面内区域沉积有透明导电层，其中，位于面内区域的透明导电层充满所述第二过孔。
  7. 如权利要求6所述的阵列基板，其中，其中，
    在衬底基板的面外区域上沉积有第一金属层；
    在所述栅绝缘层的面外区域沉积有第二金属层；
    在所述钝化层的面外区域形成有直达面外区域的第二金属层表面的第三过孔，在所述钝化层的面外区域上形成有直达面外区域的第一金属层表面的第四过孔；
    在所述钝化层的面外区域沉积有透明导电层，所述透明导电层充满所述第三过孔和第四过孔。
  8. 如权利要求7所述的阵列基板，其中，所述栅绝缘层采用SiOx材料，或SiOx/SiNx叠层复合材料，所述透明导电层为ITO薄膜层。
  9. 如权利要求8所述的阵列基板，其中，所述第一过孔和所述第二过孔相互错开。
  10. 如权利要求9所述的阵列基板，其中，所述第二过孔、第三过孔、第四过孔采用同一道光罩获得。
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