WO2020007091A1 - 显示面板及其制备方法,显示装置 - Google Patents
显示面板及其制备方法,显示装置 Download PDFInfo
- Publication number
- WO2020007091A1 WO2020007091A1 PCT/CN2019/082482 CN2019082482W WO2020007091A1 WO 2020007091 A1 WO2020007091 A1 WO 2020007091A1 CN 2019082482 W CN2019082482 W CN 2019082482W WO 2020007091 A1 WO2020007091 A1 WO 2020007091A1
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- WIPO (PCT)
- Prior art keywords
- substrate
- display panel
- insulating layer
- wiring
- groove
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 92
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000010410 layer Substances 0.000 claims description 80
- 239000005022 packaging material Substances 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 13
- 239000011521 glass Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 abstract description 7
- 230000005856 abnormality Effects 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000010147 laser engraving Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Definitions
- the present disclosure relates to the field of display technology, and in particular, to a display panel and a manufacturing method thereof, and a display device.
- the spacing between wirings in display panels also tends to decrease.
- the display panel may also need to undergo high-temperature processing processes such as glass frit packaging. During these processes, adjacent wiring may be in contact with each other due to the melting of the wiring, which may cause a short circuit and cause abnormal display.
- a display panel including: a substrate; an insulating layer provided on the substrate, the insulating layer having a plurality of grooves on a surface of the side away from the substrate; and a plurality of The wirings are respectively disposed in the plurality of grooves, and the plurality of wirings are located in a non-display area of the display panel.
- the orthographic projection of the groove on the substrate covers the orthographic projection of the wiring on the substrate.
- a depth of the groove in a direction perpendicular to the substrate is equal to or greater than a height of the wiring in a direction perpendicular to the substrate.
- a depth of the groove in a direction perpendicular to the substrate is equal to or smaller than a height of the insulating layer in a direction perpendicular to the substrate.
- the display panel further includes a packaging material disposed on a surface of the insulating layer and the wiring side away from the substrate.
- the packaging material includes a glass frit.
- a gap is formed between the groove and the wiring, and the packaging material is filled into the gap.
- the wiring includes a source-drain line.
- the substrate includes: a base substrate; a thin film transistor disposed on the base substrate and located in a display area of the display panel; and an interlayer insulation layer, the interlayer insulation A layer is disposed on a side of the thin film transistor remote from the base substrate, wherein the interlayer insulating layer is made in the same layer as the insulating layer.
- a display device including the display panel according to the above aspect of the present disclosure.
- a method of preparing a display panel including: forming a substrate; forming an insulating layer on the substrate; and forming a plurality of surfaces of the insulating layer on a surface of the side away from the substrate. A groove; and forming a plurality of wirings in the groove, respectively, wherein the plurality of wirings are located in a non-display area of the display panel.
- the orthographic projection on the substrate covers the orthographic projection of the wiring on the substrate.
- a depth of the groove in a direction perpendicular to the substrate is formed to be equal to or greater than a height of the wiring in a direction perpendicular to the substrate.
- a depth of the groove in a direction perpendicular to the substrate is equal to or smaller than a height of the insulating layer in a direction perpendicular to the substrate.
- the method further includes: forming a packaging material over the insulating layer and the wiring.
- a gap is formed between the groove and the wiring, and the packaging material is formed to fill the gap.
- the forming a substrate includes forming a base substrate; forming a thin film transistor on the base substrate such that the thin film transistor is located in a display area of the display panel; and in the thin film An interlayer insulating layer is formed on a side of the transistor far from the base substrate, wherein the interlayer insulating layer is made in the same layer as the insulating layer.
- a display panel includes: a substrate; an insulating layer provided on the substrate and having a plurality of grooves; and a plurality of wirings provided in the plurality of grooves.
- FIG. 1A is a schematic diagram of a display device according to an embodiment of the present disclosure.
- FIG. 1B is a partial cross-sectional view of a display panel according to an embodiment of the present disclosure
- FIG. 2 is an enlarged structural diagram of a portion A in FIG. 1B;
- 3A-3E are flowcharts of a method of preparing a display panel according to an embodiment of the present disclosure.
- an embodiment of the present disclosure provides a display device.
- the display device may include a display panel 100.
- the display panel 100 includes a display area PA and a peripheral area 100a.
- a packaging material 150 for example, frit
- the peripheral area 100a is located below the glass cover in the display panel, and is therefore shown by a dotted line.
- the arrangement manner of the peripheral area 100a is not limited to that shown in the drawings.
- the display device includes a display panel including: a substrate 110; an insulating layer 120 provided on the substrate 110 and having a plurality of grooves 130; and a plurality of wirings 140 provided in the plurality of grooves 130, The plurality of wirings are located in a non-display area (for example, the peripheral area 100a) of the display panel.
- the substrate 110 is used to carry and support a wiring structure.
- a wiring structure used as a signal line for example, a source-drain line configured to provide an electric signal to a driving circuit in a display area
- a wiring structure used as a signal line may be formed in a thin film transistor (TFT) and an organic light emitting diode. (OLED) and extends into the non-display area
- the substrate 110 for a wiring structure for carrying and supporting a signal line may be an array substrate in which a thin film transistor (TFT) is formed.
- the substrate 110 may include a base substrate 110a and a TFT layer 110b formed on the base substrate, and the insulating layer 120 may be disposed on the TFT layer 110b.
- the TFT layer 110b may be formed with a TFT in a portion corresponding to a display area, and may not be formed in a portion corresponding to a non-display area (for example, the TFT layer 110b may be a gate insulating layer in this case).
- the gate insulating layer in the TFT structure is made in the same process).
- the insulating layer 120 may be formed on the TFT and extended into the non-display area.
- the array substrate on which the thin film transistors are formed is a structure commonly used by those skilled in the art in organic light emitting diode displays (OLED displays), so the specific structure of the array substrate will not be described repeatedly here.
- OLED displays organic light emitting diode displays
- the present disclosure is not limited to the aforementioned array substrate.
- the substrate 110 may be other supporting substrates for carrying and supporting the wiring structure.
- the insulating layer 120 is disposed on the substrate 110 so as to electrically insulate the substrate 110 from other structures disposed thereon.
- the insulating layer 120 may be an interlayer insulating layer, and is made by the same process as the interlayer insulating layer in the display area PA.
- two layers made in the same process may be referred to as two layers made in the same layer.
- an interlayer insulation layer also called an interlayer dielectric layer ILD
- ILD interlayer dielectric layer
- the present disclosure is not limited to the aforementioned interlayer insulating layer.
- the insulating layer 120 may be other for electrically insulating the substrate 110 from other structures provided above it. Insulation structure.
- the insulating layer 120 may be formed integrally with the substrate 110 so as to be formed as a part of the substrate 110.
- the insulating layer 120 may have a single-layer or multi-layer structure, and embodiments of the present disclosure have no particular limitation on this.
- the groove 130 is formed in the insulating layer 120.
- the groove 130 may be formed on a surface of the insulating layer 120 remote from the substrate 110.
- the groove 130 may be formed in the insulating layer 120 by etching a part of the insulating layer 120. More specifically, a groove 130 may be formed on a surface of the insulating layer 120 by forming a mask on the surface of the insulating layer 120 and removing a part of the insulating layer 120 by etching using the mask.
- the step of forming a mask may include steps of coating a photoresist, exposing, and developing, which will not be described in detail here.
- the groove 130 may be formed in the insulating layer 120 by other methods, such as laser engraving, ion beam bombardment, etc., and will not be described here. To repeat.
- the wiring 140 is provided in the groove 130. As shown in FIGS. 1B and 2, the wiring 140 is disposed in the middle portion of the groove 130, and the width W1 of the wiring is smaller than the width W2 of the groove 130. In one embodiment of the present disclosure, the width W2 of the groove 130 is larger than the width W1 of the wiring by about 1.6-3 ⁇ m, that is, the distance between the side surface of the wiring and the inner surface of the groove 130 may be about 0.8-1.5 ⁇ m. between.
- the orthographic projection of the groove 130 on the substrate covers the orthographic projection of the wiring on the substrate.
- the depth D of the groove 130 may be equal to or greater than the height H of the wiring 140 so that the wiring 140 can be completely received in the groove 130.
- the depth of the groove 130 in a direction perpendicular to the substrate is equal to or greater than the height of the wiring 140 in a direction perpendicular to the substrate.
- the depth H of the groove may be between about 0.7-1 ⁇ m.
- the depth D of the groove 130 may be equal to or smaller than the thickness of the insulating layer 120. That is, a depth of the groove in a direction perpendicular to the substrate is equal to or smaller than a height of the insulating layer in a direction perpendicular to the substrate.
- the depth of the groove may be equal to the thickness of the insulating layer 120 (for example, through the insulating layer 120), the field is not limited to this, and in practical applications In one embodiment, the depth of the groove may be smaller than the thickness of the insulating layer 120, that is, it extends only into a part of the insulating layer 120.
- the arrangement according to the present disclosure can ensure that even if the wirings 140 are melted in the high-temperature processing process, the melted wirings 140 can be prevented from contacting each other, thereby avoiding display abnormalities due to short circuits.
- the wiring 140 may be a wiring structure for forming a signal line (for example, a source-drain line).
- a signal line for example, a source-drain line
- the wiring 140 may be other wiring structures that may be affected by high temperature.
- the display panel may further include a packaging material 150 disposed on a surface of the insulating layer 120 and the wiring 140 away from the substrate.
- the packaging material 150 may be formed of frit to isolate the display panel from the external environment, thereby preventing external substances such as oxygen and moisture from entering the display panel and causing deterioration of the display panel.
- the packaging material 150 may be filled into a gap between the groove 130 and the wiring 140 so as to cover the wiring structure and prevent the wiring 140 from being affected by external oxygen or the like.
- a multi-level packaging material is formed from the outside to the inside, extending the path of water and oxygen invasion, thereby better blocking external moisture or oxygen Go inside the display panel.
- a display panel includes: a substrate; an insulating layer provided on the substrate and having a plurality of grooves; and a plurality of wirings provided in the plurality of grooves. Therefore, even if the wirings are melted in the high-temperature processing process, the melted wirings can be prevented from contacting each other, thereby preventing display abnormalities due to short circuits.
- 3A to 3E illustrate a method of manufacturing a display panel according to an embodiment of the present disclosure.
- the method includes forming a substrate 110 and forming an insulating layer 120 on the substrate 110.
- a plurality of grooves 130 are formed in the insulating layer 120, wherein the plurality of wirings are located in a non-display area of the display panel.
- a plurality of wirings 140 are formed in the groove 130.
- the step of forming the wiring 140 may include: depositing a metal layer 140 a on the structure of FIG. 3B, and then patterning the metal layer 140 a to form a plurality of wirings 140.
- the step of patterning the metal layer 140a may use any patterning technique known in the art, and will not be described again here.
- the method may further include forming a packaging material 150 over the insulating layer 120 and the wiring 140.
- the packaging material 150 may be formed to fill a gap between the groove 130 and the wiring 140.
- the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance; the term “plurality” means two or more.
- the specific meanings of the above terms in the present disclosure can be understood according to specific situations.
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
Description
Claims (20)
- 一种显示面板,包括:基板;绝缘层,设置在所述基板上,所述绝缘层远离所述基板的一侧表面上具有多个凹槽;以及多条布线,分别设置在所述多个凹槽中,其中,所述多条布线位于所述显示面板的非显示区中。
- 根据权利要求1所述的显示面板,其中,所述凹槽在所述基板上的正投影覆盖所述布线在所述基板上的正投影。
- 根据权利要求1所述的显示面板,其中,所述凹槽在垂直于所述基板的方向上的深度等于或大于所述布线在垂直于所述基板的方向上的高度。
- 根据权利要求1所述的显示面板,其中,所述凹槽在垂直于所述基板的方向上的深度等于或小于所述绝缘层在垂直于所述基板的方向上的厚度。
- 根据权利要求1所述的显示面板,其中,所述布线的宽度小于所述凹槽的宽度。
- 根据权利要求5所述的显示面板,其中,所述布线的侧表面与所述凹槽的内表面之间的距离在大约0.8-1.5μm之间。
- 根据权利要求1所述的显示面板,还包括:封装材料,设置在所述绝缘层以及所述布线远离所述基板一侧的表面上。
- 根据权利要求7所述的显示面板,其中,所述封装材料包括玻璃料。
- 根据权利要求7所述的显示面板,其中,所述凹槽与所述布线之间形成有间隙,所述封装材料填充至所述间隙中。
- 根据权利要求1所述的显示面板,其中,所述布线包括源漏线。
- 根据权利要求1所述的显示面板,其中,所述基板包括:衬底基板;薄膜晶体管,设置在所述衬底基板上并位于所述显示面板的显示区中;以及层间绝缘层,所述层间绝缘层设置在所述薄膜晶体管远离所述衬底基板一侧上,其中所述层间绝缘层与所述绝缘层同层制作。
- 一种显示装置,包括根据权利要求1-11任一项所述的显示面板。
- 一种制备显示面板的方法,包括:形成基板;在所述基板上形成绝缘层,并在所述绝缘层远离所述基板的一侧表面上形成多个凹槽;以及在所述凹槽中分别形成多条布线,其中,所述多条布线位于所述显示面板的非显示区中。
- 根据权利要求13所述的方法,其中,在所述基板上的正投影覆盖所述布线在所述基板上的正投影。
- 根据权利要求13所述的方法,其中,所述凹槽在垂直于所述基板的方向上的深度被形成为等于或大于所述布线在垂直于所述基板的方向上的高度。
- 根据权利要求13所述的方法,其中,所述凹槽在垂直于所述基板的方向上的深度等于或小于所述绝缘层在垂直于所述基板的方向上的厚度。
- 根据权利要求13所述的方法,其中,所述布线的宽度小于所述凹槽的宽度。
- 根据权利要求17所述的方法,其中,所述布线的侧表面与所述凹槽的内表面之间的距离在大约0.8-1.5μm之间。
- 根据权利要求18所述的方法,还包括:在所述绝缘层以及所述布线远离所述基板一侧的表面上形成封装材料,所述封装材料填充至所述凹槽与所述布线之间形成的间隙中。
- 根据权利要求13所述的方法,其中,所述形成基板包括:形成衬底基板;在所述衬底基板上形成薄膜晶体管,使得所述薄膜晶体管位于所述显示面板的显示区中;以及在所述薄膜晶体管远离所述衬底基板一侧上形成层间绝缘层,其中所述层间绝缘层与所述绝缘层同层制作。
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CN201810737833.4A CN108899330A (zh) | 2018-07-06 | 2018-07-06 | 显示面板及其制备方法,显示装置 |
CN201810737833.4 | 2018-07-06 |
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CN108899330A (zh) * | 2018-07-06 | 2018-11-27 | 京东方科技集团股份有限公司 | 显示面板及其制备方法,显示装置 |
KR20200137070A (ko) * | 2019-05-28 | 2020-12-09 | 삼성디스플레이 주식회사 | 디스플레이 장치 |
CN114122009A (zh) * | 2021-11-05 | 2022-03-01 | Tcl华星光电技术有限公司 | 显示面板及其制备方法与移动终端 |
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2019
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CN107994058A (zh) * | 2017-11-27 | 2018-05-04 | 京东方科技集团股份有限公司 | 显示基板及其制造方法、显示面板及其封装方法 |
CN207441753U (zh) * | 2017-11-27 | 2018-06-01 | 京东方科技集团股份有限公司 | 显示基板、显示面板及显示装置 |
CN108899330A (zh) * | 2018-07-06 | 2018-11-27 | 京东方科技集团股份有限公司 | 显示面板及其制备方法,显示装置 |
CN208336230U (zh) * | 2018-07-06 | 2019-01-04 | 京东方科技集团股份有限公司 | 显示面板及显示装置 |
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