WO2020007091A1 - 显示面板及其制备方法，显示装置 - Google Patents

显示面板及其制备方法，显示装置 Download PDF

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Publication number
WO2020007091A1
WO2020007091A1 PCT/CN2019/082482 CN2019082482W WO2020007091A1 WO 2020007091 A1 WO2020007091 A1 WO 2020007091A1 CN 2019082482 W CN2019082482 W CN 2019082482W WO 2020007091 A1 WO2020007091 A1 WO 2020007091A1
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WIPO (PCT)
Prior art keywords
substrate
display panel
insulating layer
wiring
groove
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PCT/CN2019/082482
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English (en)
French (fr)
Inventor
李子华
刘静
问智博
蔡璐
刘恒博
***
金文强
高鑫鹏
王强
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Publication of WO2020007091A1 publication Critical patent/WO2020007091A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a manufacturing method thereof, and a display device.
  • the spacing between wirings in display panels also tends to decrease.
  • the display panel may also need to undergo high-temperature processing processes such as glass frit packaging. During these processes, adjacent wiring may be in contact with each other due to the melting of the wiring, which may cause a short circuit and cause abnormal display.
  • a display panel including: a substrate; an insulating layer provided on the substrate, the insulating layer having a plurality of grooves on a surface of the side away from the substrate; and a plurality of The wirings are respectively disposed in the plurality of grooves, and the plurality of wirings are located in a non-display area of the display panel.
  • the orthographic projection of the groove on the substrate covers the orthographic projection of the wiring on the substrate.
  • a depth of the groove in a direction perpendicular to the substrate is equal to or greater than a height of the wiring in a direction perpendicular to the substrate.
  • a depth of the groove in a direction perpendicular to the substrate is equal to or smaller than a height of the insulating layer in a direction perpendicular to the substrate.
  • the display panel further includes a packaging material disposed on a surface of the insulating layer and the wiring side away from the substrate.
  • the packaging material includes a glass frit.
  • a gap is formed between the groove and the wiring, and the packaging material is filled into the gap.
  • the wiring includes a source-drain line.
  • the substrate includes: a base substrate; a thin film transistor disposed on the base substrate and located in a display area of the display panel; and an interlayer insulation layer, the interlayer insulation A layer is disposed on a side of the thin film transistor remote from the base substrate, wherein the interlayer insulating layer is made in the same layer as the insulating layer.
  • a display device including the display panel according to the above aspect of the present disclosure.
  • a method of preparing a display panel including: forming a substrate; forming an insulating layer on the substrate; and forming a plurality of surfaces of the insulating layer on a surface of the side away from the substrate. A groove; and forming a plurality of wirings in the groove, respectively, wherein the plurality of wirings are located in a non-display area of the display panel.
  • the orthographic projection on the substrate covers the orthographic projection of the wiring on the substrate.
  • a depth of the groove in a direction perpendicular to the substrate is formed to be equal to or greater than a height of the wiring in a direction perpendicular to the substrate.
  • a depth of the groove in a direction perpendicular to the substrate is equal to or smaller than a height of the insulating layer in a direction perpendicular to the substrate.
  • the method further includes: forming a packaging material over the insulating layer and the wiring.
  • a gap is formed between the groove and the wiring, and the packaging material is formed to fill the gap.
  • the forming a substrate includes forming a base substrate; forming a thin film transistor on the base substrate such that the thin film transistor is located in a display area of the display panel; and in the thin film An interlayer insulating layer is formed on a side of the transistor far from the base substrate, wherein the interlayer insulating layer is made in the same layer as the insulating layer.
  • a display panel includes: a substrate; an insulating layer provided on the substrate and having a plurality of grooves; and a plurality of wirings provided in the plurality of grooves.
  • FIG. 1A is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 1B is a partial cross-sectional view of a display panel according to an embodiment of the present disclosure
  • FIG. 2 is an enlarged structural diagram of a portion A in FIG. 1B;
  • 3A-3E are flowcharts of a method of preparing a display panel according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a display device.
  • the display device may include a display panel 100.
  • the display panel 100 includes a display area PA and a peripheral area 100a.
  • a packaging material 150 for example, frit
  • the peripheral area 100a is located below the glass cover in the display panel, and is therefore shown by a dotted line.
  • the arrangement manner of the peripheral area 100a is not limited to that shown in the drawings.
  • the display device includes a display panel including: a substrate 110; an insulating layer 120 provided on the substrate 110 and having a plurality of grooves 130; and a plurality of wirings 140 provided in the plurality of grooves 130, The plurality of wirings are located in a non-display area (for example, the peripheral area 100a) of the display panel.
  • the substrate 110 is used to carry and support a wiring structure.
  • a wiring structure used as a signal line for example, a source-drain line configured to provide an electric signal to a driving circuit in a display area
  • a wiring structure used as a signal line may be formed in a thin film transistor (TFT) and an organic light emitting diode. (OLED) and extends into the non-display area
  • the substrate 110 for a wiring structure for carrying and supporting a signal line may be an array substrate in which a thin film transistor (TFT) is formed.
  • the substrate 110 may include a base substrate 110a and a TFT layer 110b formed on the base substrate, and the insulating layer 120 may be disposed on the TFT layer 110b.
  • the TFT layer 110b may be formed with a TFT in a portion corresponding to a display area, and may not be formed in a portion corresponding to a non-display area (for example, the TFT layer 110b may be a gate insulating layer in this case).
  • the gate insulating layer in the TFT structure is made in the same process).
  • the insulating layer 120 may be formed on the TFT and extended into the non-display area.
  • the array substrate on which the thin film transistors are formed is a structure commonly used by those skilled in the art in organic light emitting diode displays (OLED displays), so the specific structure of the array substrate will not be described repeatedly here.
  • OLED displays organic light emitting diode displays
  • the present disclosure is not limited to the aforementioned array substrate.
  • the substrate 110 may be other supporting substrates for carrying and supporting the wiring structure.
  • the insulating layer 120 is disposed on the substrate 110 so as to electrically insulate the substrate 110 from other structures disposed thereon.
  • the insulating layer 120 may be an interlayer insulating layer, and is made by the same process as the interlayer insulating layer in the display area PA.
  • two layers made in the same process may be referred to as two layers made in the same layer.
  • an interlayer insulation layer also called an interlayer dielectric layer ILD
  • ILD interlayer dielectric layer
  • the present disclosure is not limited to the aforementioned interlayer insulating layer.
  • the insulating layer 120 may be other for electrically insulating the substrate 110 from other structures provided above it. Insulation structure.
  • the insulating layer 120 may be formed integrally with the substrate 110 so as to be formed as a part of the substrate 110.
  • the insulating layer 120 may have a single-layer or multi-layer structure, and embodiments of the present disclosure have no particular limitation on this.
  • the groove 130 is formed in the insulating layer 120.
  • the groove 130 may be formed on a surface of the insulating layer 120 remote from the substrate 110.
  • the groove 130 may be formed in the insulating layer 120 by etching a part of the insulating layer 120. More specifically, a groove 130 may be formed on a surface of the insulating layer 120 by forming a mask on the surface of the insulating layer 120 and removing a part of the insulating layer 120 by etching using the mask.
  • the step of forming a mask may include steps of coating a photoresist, exposing, and developing, which will not be described in detail here.
  • the groove 130 may be formed in the insulating layer 120 by other methods, such as laser engraving, ion beam bombardment, etc., and will not be described here. To repeat.
  • the wiring 140 is provided in the groove 130. As shown in FIGS. 1B and 2, the wiring 140 is disposed in the middle portion of the groove 130, and the width W1 of the wiring is smaller than the width W2 of the groove 130. In one embodiment of the present disclosure, the width W2 of the groove 130 is larger than the width W1 of the wiring by about 1.6-3 ⁇ m, that is, the distance between the side surface of the wiring and the inner surface of the groove 130 may be about 0.8-1.5 ⁇ m. between.
  • the orthographic projection of the groove 130 on the substrate covers the orthographic projection of the wiring on the substrate.
  • the depth D of the groove 130 may be equal to or greater than the height H of the wiring 140 so that the wiring 140 can be completely received in the groove 130.
  • the depth of the groove 130 in a direction perpendicular to the substrate is equal to or greater than the height of the wiring 140 in a direction perpendicular to the substrate.
  • the depth H of the groove may be between about 0.7-1 ⁇ m.
  • the depth D of the groove 130 may be equal to or smaller than the thickness of the insulating layer 120. That is, a depth of the groove in a direction perpendicular to the substrate is equal to or smaller than a height of the insulating layer in a direction perpendicular to the substrate.
  • the depth of the groove may be equal to the thickness of the insulating layer 120 (for example, through the insulating layer 120), the field is not limited to this, and in practical applications In one embodiment, the depth of the groove may be smaller than the thickness of the insulating layer 120, that is, it extends only into a part of the insulating layer 120.
  • the arrangement according to the present disclosure can ensure that even if the wirings 140 are melted in the high-temperature processing process, the melted wirings 140 can be prevented from contacting each other, thereby avoiding display abnormalities due to short circuits.
  • the wiring 140 may be a wiring structure for forming a signal line (for example, a source-drain line).
  • a signal line for example, a source-drain line
  • the wiring 140 may be other wiring structures that may be affected by high temperature.
  • the display panel may further include a packaging material 150 disposed on a surface of the insulating layer 120 and the wiring 140 away from the substrate.
  • the packaging material 150 may be formed of frit to isolate the display panel from the external environment, thereby preventing external substances such as oxygen and moisture from entering the display panel and causing deterioration of the display panel.
  • the packaging material 150 may be filled into a gap between the groove 130 and the wiring 140 so as to cover the wiring structure and prevent the wiring 140 from being affected by external oxygen or the like.
  • a multi-level packaging material is formed from the outside to the inside, extending the path of water and oxygen invasion, thereby better blocking external moisture or oxygen Go inside the display panel.
  • a display panel includes: a substrate; an insulating layer provided on the substrate and having a plurality of grooves; and a plurality of wirings provided in the plurality of grooves. Therefore, even if the wirings are melted in the high-temperature processing process, the melted wirings can be prevented from contacting each other, thereby preventing display abnormalities due to short circuits.
  • 3A to 3E illustrate a method of manufacturing a display panel according to an embodiment of the present disclosure.
  • the method includes forming a substrate 110 and forming an insulating layer 120 on the substrate 110.
  • a plurality of grooves 130 are formed in the insulating layer 120, wherein the plurality of wirings are located in a non-display area of the display panel.
  • a plurality of wirings 140 are formed in the groove 130.
  • the step of forming the wiring 140 may include: depositing a metal layer 140 a on the structure of FIG. 3B, and then patterning the metal layer 140 a to form a plurality of wirings 140.
  • the step of patterning the metal layer 140a may use any patterning technique known in the art, and will not be described again here.
  • the method may further include forming a packaging material 150 over the insulating layer 120 and the wiring 140.
  • the packaging material 150 may be formed to fill a gap between the groove 130 and the wiring 140.
  • the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance; the term “plurality” means two or more.
  • the specific meanings of the above terms in the present disclosure can be understood according to specific situations.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种显示面板及其制备方法，以及一种显示装置。显示面板包括：基板（110）；绝缘层（120）设置在该基板（110）上，该绝缘层（120）远离该基板（110）的一侧表面上具有多个凹槽（130）；以及多条布线（140），分别设置在该多个凹槽（130）中，其中，该多条布线（140）位于该显示面板的非显示区中。即使在高温处理工艺中布线（140）熔融，也能够避免熔融后的布线（140）彼此接触，从而避免了由于产生短路而导致显示异常。

Description

显示面板及其制备方法，显示装置
相关申请的交叉引用
本申请要求于2018年07月06日递交的中国专利申请第201810737833.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及其制备方法，以及一种显示装置。
背景技术
随着显示装置的小型化、窄边框的发展趋势，显示面板中的布线之间的间距也趋于减小。在形成布线图案后，显示面板可能还需要经受例如玻璃料封装等高温处理工艺，在这些处理过程中，可能由于布线熔融而导致相邻的布线彼此接触，从而产生短路而导致显示异常。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一方面，提供了一种显示面板，包括：基板；绝缘层，设置在所述基板上，所述绝缘层远离所述基板的一侧表面上具有多个凹槽；以及多条布线，分别设置在所述多个凹槽中，其中，所述多条布线位于所述显示面板的非显示区中。
在本公开的一个方面中，所述凹槽在所述基板上的正投影覆盖所述布线在所述基板上的正投影。
在本公开的一个方面中，所述凹槽在垂直于所述基板的方向上的深度等于或大于所述布线在垂直于所述基板的方向上的高度。
在本公开的一个方面中，所述凹槽在垂直于所述基板的方向上的深度等于或小于所述绝缘层在垂直于所述基板的方向上的高度。
在本公开的一个方面中，所述显示面板还包括：封装材料，设置在所述绝缘层以及所述布线远离所述基板一侧的表面上。
在本公开的一个方面中，所述封装材料包括玻璃料。
在本公开的一个方面中，所述凹槽与所述布线之间形成有间隙，所述封装材料填充至所述间隙中。
在本公开的一个方面中，所述布线包括源漏线。
在本公开的一个方面中，所述基板包括：衬底基板；薄膜晶体管，设置在所述衬底基板上并位于所述显示面板的显示区中；以及层间绝缘层，所述层间绝缘层设置在所述薄膜晶体管远离所述衬底基板一侧上，其中所述层间绝缘层与所述绝缘层同层制作。
根据本公开的另一方面，提供了一种显示装置，包括根据本公开的上述方面的显示面板。
根据本公开的又一方面，提供了一种制备显示面板的方法，包括：形成基板；在所述基板上形成绝缘层，并在所述绝缘层远离所述基板的一侧表面上形成多个凹槽；以及在所述凹槽中分别形成多条布线，其中，所述多条布线位于所述显示面板的非显示区中。
在本公开的一个方面中，在所述基板上的正投影覆盖所述布线在所述基板上的正投影。
在本公开的一个方面中，所述凹槽在垂直于所述基板的方向上的深度被形成为等于或大于所述布线在垂直于所述基板的方向上的高度。
在本公开的一个方面中，所述凹槽在垂直于所述基板的方向上的深度等于或小于所述绝缘层在垂直于所述基板的方向上的高度。
在本公开的一个方面中，所述方法还包括：在所述绝缘层以及所述布线上方形成封装材料。
在本公开的一个方面中，所述凹槽与所述布线之间形成有间隙，所述封装材料被形成为填充至所述间隙中。
在本公开的一个方面中，所述形成基板包括：形成衬底基板； 在所述衬底基板上形成薄膜晶体管，使得所述薄膜晶体管位于所述显示面板的显示区中；以及在所述薄膜晶体管远离所述衬底基板一侧上形成层间绝缘层，其中所述层间绝缘层与所述绝缘层同层制作。
根据本公开的各方面，显示面板包括：基板；绝缘层，设置在所述基板上，并具有多个凹槽；以及多条布线，设置在所述多个凹槽中。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
本节提供本公开中描述的技术的各种实现或示例的概述，并不是所公开技术的全部范围或所有特征的全面公开。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1A是根据本公开一个实施例的显示装置的示意图；
图1B是根据本公开一个实施例的显示面板的局部剖视图；
图2是图1B中A部的放大结构示意图；
图3A-图3E是根据本公开一个实施例的制备显示面板的方法的流程图。
具体实施方式
为了可以更清楚地理解本公开的上述目的、特征和优点，下面结合附图和具体实施方式对本公开进行进一步的详细描述。需要说明的是，在不冲突的情况下，本申请的实施例及实施例中的特征可以相互组合。
在下面的描述中阐述了很多具体细节以便于充分理解本公开，但是，本公开还可以采用其他不同于在此描述的其他方式来实施，因此，本公开的保护范围并不受下面公开的具体实施例的限制。
如图1A至图2所示，本公开的实施例提供了一种显示装置，显 示装置可以包括显示面板100。
在本公开的一个实施例中，如图1A所示，显示面板100包括显示区域PA以及外周区域100a，在外周区域100a中可以形成封装材料150(例如玻璃料)，以用于密封显示面板100。还应指出的是，如附图所示，在本实施例中，外周区域100a位于显示面板中玻璃盖板的下方，因此用虚线示出。然而本领域技术人员应当理解，外周区域100a的布置方式不限于附图中所示的方式。
显示装置包括显示面板，显示面板包括：基板110；绝缘层120，设置在所述基板110上，并具有多个凹槽130；以及多条布线140，设置在所述多个凹槽130中，其中，所述多条布线位于所述显示面板的非显示区(例如***区域100a)中。
根据本公开的一个方面，基板110用于承载和支撑布线结构。例如，在有机发光显示装置中，用作信号线(例如，源漏线，其被配置为向显示区中的驱动电路提供电信号)的布线结构可以形成在薄膜晶体管(TFT)以及有机发光二极管(OLED)之间并延伸至非显示区域中，因此在这种情况下，用于承载和支撑信号线的布线结构的基板110可以是其中形成有薄膜晶体管(TFT)的阵列基板。例如，基板110可以包括衬底基板110a以及形成在衬底基板上的TFT层110b，绝缘层120可以设置在该TFT层110b上。在一个实施例中，TFT层110b在对应于显示区域的部分中可以形成有TFT，在对应于非显示区域的部分中可以不形成TFT(例如，在此情况下TFT层110b可以为栅绝缘层，由TFT结构中的栅绝缘层同一道工序制成)，绝缘层120可以形成在TFT上并延伸至非显示区域中。其中形成有薄膜晶体管的阵列基板是本领域技术人员在有机发光二极管显示器(OLED display)中常用的结构，因此在这里将不再重复描述阵列基板的具体结构。本领域技术人员应当理解的是，本公开不限于前述阵列基板，针对不同的布线结构，基板110可以是用于承载和支撑该布线结构的其它支撑基板。
绝缘层120设置在基板110上，以使基板110与设置在其上方的其它结构之间彼此电绝缘。仍然以有机发光显示装置为例，绝缘层 120可以为层间绝缘层，并与显示区域PA中的层间绝缘层由同一道工艺制成。在本公开中，在同一道工艺中制成的两个层可以被称作“同层制作”的两个层。通常，在阵列基板与有机发光二极管之间设置层间绝缘层(或称为层间介电层ILD)，以使阵列基板中形成的TFT结构与OLED之间电绝缘，并通过在层间绝缘层之间形成过孔来使驱动晶体管的漏极连接到OLED的阳极。本领域技术人员应当理解的是，本公开不限于前述层间绝缘层，针对不同的布线结构，绝缘层120可以是用于使基板110与设置在其上方的其它结构之间彼此电绝缘的其它绝缘层结构。在一些实施方式中，绝缘层120可以与基板110一体地形成，从而被形成为基板110的一部分。绝缘层120可以是单层或多层结构，本公开的实施例对此没有特别的限制。
凹槽130形成在绝缘层120中。凹槽130可以形成在绝缘层120的远离基板110一侧的表面上。可以通过蚀刻绝缘层120的一部分来在绝缘层120中形成凹槽130。更具体地，可以通过在绝缘层120的表面上形成掩模，并利用该掩模进行蚀刻来去除绝缘层120的一部分，从而在其表面上形成凹槽130。在一个实施例中，形成掩模的步骤可以包括涂覆光致抗蚀剂、曝光、显影等步骤，在这里将不再具体阐述。另外，本领域技术人员应当理解的是，本公开不限于前述方式，例如，也可以通过其他方式来在绝缘层120中形成凹槽130，例如激光雕刻、离子束轰击等，在这里将不再赘述。
布线140设置在凹槽130中。如图1B和图2所示，布线140设置在凹槽130的中间部分，且布线的宽度W1小于凹槽130的宽度W2。在本公开的一个实施例中，凹槽130的宽度W2比布线的宽度W1大大约1.6-3μm，即布线的侧表面与凹槽130的内表面之间的距离可以在大约0.8-1.5μm之间。例如，凹槽130在基板上的正投影覆盖布线在所述基板上的正投影。凹槽130的深度D可以等于或大于布线140的高度H，使得布线140能够被完全容纳在凹槽130中。例如，凹槽130在垂直于所述基板的方向上的深度等于或大于所述布线140在垂直于所述基板的方向上的高度。例如，根据布线140的高度，凹槽的深度H可以在大约0.7-1μm之间。在本实施例中，应当 理解的是，凹槽130的深度D可以等于或小于绝缘层120的厚度。即，所述凹槽在垂直于所述基板的方向上的深度等于或小于所述绝缘层在垂直于所述基板的方向上的高度。更具体地说，本领域技术人员应当理解，虽然在附图中示出了凹槽的深度可能等于绝缘层120的厚度(例如贯穿绝缘层120)，但本领域并非局限于此，在实际应用中，凹槽的深度可以小于绝缘层120的厚度，即只延伸到绝缘层120的一部分中。根据本公开的设置可以保证即使在高温处理工艺中布线140发生熔融，也能够避免熔融后的布线140彼此接触，从而避免了由于产生短路而导致显示异常。
在前述显示面板为有机发光显示面板的示例中，布线140可以是用于形成信号线(例如源漏线)的布线结构。然而本公开不限于此，在本公开的其它实施例中，布线140可以是其它可能受到高温影响的布线结构。
根据本公开的一个实施例，如图1B和图2所示，显示面板还可以包括封装材料150，设置在绝缘层120以及布线140远离所述基板一侧的表面上。
封装材料150可以由玻璃料(frit)形成，以用于将显示面板与外部环境隔离，从而避免诸如氧气、湿气等外部物质进入显示面板而造成显示面板的劣化。封装材料150可以填充至凹槽130与布线140之间的间隙中，从而包覆所述布线结构并防止布线140受到外部氧气等的影响。此外，由于封装材料150填充至凹槽130与布线140之间的间隙中，因此形成了从外向内的多级封装材料，延长了水氧入侵的路径，从而更好地阻止外部湿气或氧气进入到显示面板的内部。
根据本公开的实施例，显示面板包括：基板；绝缘层，设置在所述基板上，并具有多个凹槽；以及多条布线，设置在所述多个凹槽中。因此，即使在高温处理工艺中布线熔融，也能够避免熔融后的布线彼此接触，从而避免了由于产生短路而导致显示异常。
图3A至图3E示出了根据本公开实施例的制造显示面板的方法。参见图3A，该方法包括：形成基板110，以及在基板110的上形成绝缘层120。参见图3B，在绝缘层120中形成多个凹槽130，其中， 所述多条布线位于所述显示面板的非显示区中。
参见图3C和图3D，在凹槽130中形成多条布线140。其中形成布线140的步骤可以包括：在图3B的结构上沉积金属层140a，然后将金属层140a图案化以形成多条布线140。图案化金属层140a的步骤可以使用本领域公知的任何图案化技术，在这里将不再赘述。
参见图3E，该方法还可以包括在绝缘层120以及布线140上方形成封装材料150。其中，封装材料150可以被形成为填充至凹槽130与布线140之间的间隙中。
关于本实施例中各个步骤的具体细节已经在前面参照图1A至图2描述的实施例中进行了具体说明，因此在这里将不再赘述。
在本公开中，术语“第一”、“第二”仅用于描述的目的，而不能理解为指示或暗示相对重要性；术语“多个”表示两个或两个以上。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种显示面板，包括：
    基板；
    绝缘层，设置在所述基板上，所述绝缘层远离所述基板的一侧表面上具有多个凹槽；以及
    多条布线，分别设置在所述多个凹槽中，
    其中，所述多条布线位于所述显示面板的非显示区中。
  2. 根据权利要求1所述的显示面板，其中，所述凹槽在所述基板上的正投影覆盖所述布线在所述基板上的正投影。
  3. 根据权利要求1所述的显示面板，其中，所述凹槽在垂直于所述基板的方向上的深度等于或大于所述布线在垂直于所述基板的方向上的高度。
  4. 根据权利要求1所述的显示面板，其中，所述凹槽在垂直于所述基板的方向上的深度等于或小于所述绝缘层在垂直于所述基板的方向上的厚度。
  5. 根据权利要求1所述的显示面板，其中，所述布线的宽度小于所述凹槽的宽度。
  6. 根据权利要求5所述的显示面板，其中，所述布线的侧表面与所述凹槽的内表面之间的距离在大约0.8-1.5μm之间。
  7. 根据权利要求1所述的显示面板，还包括：
    封装材料，设置在所述绝缘层以及所述布线远离所述基板一侧的表面上。
  8. 根据权利要求7所述的显示面板，其中，所述封装材料包括玻璃料。
  9. 根据权利要求7所述的显示面板，其中，所述凹槽与所述布线之间形成有间隙，所述封装材料填充至所述间隙中。
  10. 根据权利要求1所述的显示面板，其中，所述布线包括源漏线。
  11. 根据权利要求1所述的显示面板，其中，所述基板包括：
    衬底基板；
    薄膜晶体管，设置在所述衬底基板上并位于所述显示面板的显示区中；以及
    层间绝缘层，所述层间绝缘层设置在所述薄膜晶体管远离所述衬底基板一侧上，
    其中所述层间绝缘层与所述绝缘层同层制作。
  12. 一种显示装置，包括根据权利要求1-11任一项所述的显示面板。
  13. 一种制备显示面板的方法，包括：
    形成基板；
    在所述基板上形成绝缘层，并在所述绝缘层远离所述基板的一侧表面上形成多个凹槽；以及
    在所述凹槽中分别形成多条布线，
    其中，所述多条布线位于所述显示面板的非显示区中。
  14. 根据权利要求13所述的方法，其中，在所述基板上的正投影覆盖所述布线在所述基板上的正投影。
  15. 根据权利要求13所述的方法，其中，所述凹槽在垂直于所述基板的方向上的深度被形成为等于或大于所述布线在垂直于所述基板的方向上的高度。
  16. 根据权利要求13所述的方法，其中，所述凹槽在垂直于所述基板的方向上的深度等于或小于所述绝缘层在垂直于所述基板的方向上的厚度。
  17. 根据权利要求13所述的方法，其中，所述布线的宽度小于所述凹槽的宽度。
  18. 根据权利要求17所述的方法，其中，所述布线的侧表面与所述凹槽的内表面之间的距离在大约0.8-1.5μm之间。
  19. 根据权利要求18所述的方法，还包括：
    在所述绝缘层以及所述布线远离所述基板一侧的表面上形成封装材料，所述封装材料填充至所述凹槽与所述布线之间形成的间隙中。
  20. 根据权利要求13所述的方法，其中，所述形成基板包括：
    形成衬底基板；
    在所述衬底基板上形成薄膜晶体管，使得所述薄膜晶体管位于所述显示面板的显示区中；以及
    在所述薄膜晶体管远离所述衬底基板一侧上形成层间绝缘层，
    其中所述层间绝缘层与所述绝缘层同层制作。
PCT/CN2019/082482 2018-07-06 2019-04-12 显示面板及其制备方法，显示装置 WO2020007091A1 (zh)

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