WO2020000616A1 - 一种有源混频器 - Google Patents

一种有源混频器 Download PDF

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Publication number
WO2020000616A1
WO2020000616A1 PCT/CN2018/101970 CN2018101970W WO2020000616A1 WO 2020000616 A1 WO2020000616 A1 WO 2020000616A1 CN 2018101970 W CN2018101970 W CN 2018101970W WO 2020000616 A1 WO2020000616 A1 WO 2020000616A1
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drain
nmos tube
tube
source
gate
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PCT/CN2018/101970
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English (en)
French (fr)
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樊璠
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樊璠
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Priority to DE212018000151.0U priority Critical patent/DE212018000151U1/de
Publication of WO2020000616A1 publication Critical patent/WO2020000616A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1441—Balanced arrangements with transistors using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential

Definitions

  • the invention belongs to the field of radio frequency integrated circuits and relates to an active mixer, in particular to a mixer with high conversion gain, high linearity, low noise and high isolation.
  • the radio frequency receiver is an important module of wireless communication, and its performance index affects the entire wireless communication system, so the design of the radio frequency integrated circuit must develop toward miniaturization, low cost, low power consumption, high performance, and high integration.
  • the mixer is the core module of the radio frequency receiver, which realizes the conversion from radio frequency to intermediate frequency. Active mixers have lower requirements on the power of the local oscillator, and they can provide higher gains, reducing the noise requirements of the mixer's subsequent circuits. Therefore, in the design of the mixer, performance indicators such as conversion gain, noise, linearity, power consumption, and isolation need to be comprehensively considered.
  • the purpose of the present invention is to provide an active mixer circuit.
  • the technical problem to be solved is that improving the performance of the mixer on the basis of low power consumption is limited.
  • An active mixer circuit includes a transconductance stage, a switching stage, and a load stage.
  • the transconductance stage module adopts the third-order transconductance coefficient correction current mirror technology, noise cancellation technology, and degenerate inductor structure of the source. It is connected to an external input device and connected to the RF voltage signal to convert the RF voltage signal into a RF current signal.
  • the switch stage The local oscillator signal is connected, and the MOS tube is turned on in turn under the control of the local oscillator large signal, and the current is switched and modulated to achieve frequency conversion.
  • the load-level RC circuit is responsible for converting the frequency-converted intermediate frequency current signal into an output. Voltage signal.
  • the beneficial effect of the present invention is that the transconductance stage is composed of a third-order transconductance coefficient correction current mirror technology (M1-M10), so that the conversion gain and linearity of the mixer are improved.
  • M1-M10 third-order transconductance coefficient correction current mirror technology
  • the source degenerate inductor structure is used.
  • the inductors L4 and L5 provide better input matching characteristics and also improve the linearity of the circuit.
  • a noise cancellation technique is used in the transconductance stage.
  • the circuit has an inductor L1 connected in parallel at the common source node of the two switching stages to eliminate the effects of parasitic capacitance on noise and linearity.
  • the circuit uses an improved dynamic current injection technique to reduce flicker noise.
  • the present invention can also be improved as follows.
  • the transconductance stage includes NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, NMOS tube M9, NMOS tube M10, PMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, inductance L1, inductance L2, L3, L4 and L5.
  • One end of the inductor L2 is connected to the positive terminal RF + of the RF voltage signal, and the other end is connected to the gate of the NMOS tube M1; the source of the NMOS tube M1 is connected to the source of the NMOS tube M2, and the drain is connected to the drain of the NMOS tube M9.
  • the gate and drain of the NMOS tube M9 are connected, the source is connected to the gate of the NMOS tube M1; the gate of the NMOS tube M2 is connected to the gate of the NMOS tube M1, and the source is connected to the source of the NMOS tube M1,
  • the drain is connected to the drain of the PMOS tube M6; one end of the inductor L4 is connected to the source of the NMOS tube M1, and the other end is grounded; the drain of the PMOS tube M5 is connected to the drain of the NMOS tube M1, and the gate is connected to the drain of the PMOS tube M6.
  • the gate is connected, the source is connected to the bias voltage V0; the gate and drain of the PMOS tube M6 are connected, and the source is connected to the bias voltage V0;
  • One end of the inductor L3 is connected to the negative terminal of the RF voltage signal, and the other end is connected to the gate of the NMOS tube M3; the source of the NMOS tube M3 is connected to the source of the NMOS tube M4, and the drain is connected to the drain of the NMOS tube M10.
  • the gate and drain of the NMOS tube M10 are connected, the source is connected to the gate of the NMOS tube M3; the gate of the NMOS tube M4 is connected to the gate of the NMOS tube M3, and the source is connected to the source of the NMOS tube M3,
  • the drain is connected to the drain of the PMOS tube M7; one end of the inductor L5 is connected to the source of the NMOS tube M3, and the other end is grounded; the drain of the PMOS tube M8 is connected to the drain of the NMOS tube M3, and the gate is connected to the PMOS tube M7.
  • the gate is connected, the source is connected to the bias voltage V0; the gate and drain of the PMOS tube M7 are connected, and the source is connected to the bias voltage V0; one end of the inductor L1 is connected to the drain of the NMOS tube M1, and the other of the inductor L1 The drain of one end NMOS tube M3 is connected;
  • the transconductance stage uses NMOS tubes M1 and M2, and the current mirrors M5 and M6 form a third-order transconductance coefficient correction current mirror pair circuit.
  • the output current signal is injected into the switching stage for frequency conversion.
  • the linearity of the mixer can be improved.
  • some people use resistors, capacitors, and inductors as feedback devices to improve the linearity of the mixer. However, if a resistor is used, it will cause additional resistance thermal noise, which will reduce the noise performance of the mixer. If the capacitor or inductor is used as negative feedback, the noise performance will not be reduced.
  • the present invention uses the inductors L4 and L5 as a feedback device.
  • L2-L5 forms a better impedance matching circuit and also improves the linearity of the circuit.
  • an inductor L1 is connected in series between the transconductance stage and the switching stage, so that the linearity of the mixer is improved.
  • the NMOS transistors M9 and M10 are used in the transconductance stage to form the input noise cancellation circuit.
  • the switching stage includes an NMOS tube M11, an NMOS tube M12, an NMOS tube M13, and an NMOS tube M14.
  • the gate of the NMOS transistor M11 is connected to the positive terminal LO + of the local oscillator signal
  • the source stage is connected to the drain of the NMOS transistor M1, and the drain is connected to one end of the load stage resistor R1;
  • the gate of the NMOS transistor M12 is connected to the local oscillator signal.
  • the negative terminal of the NMOS tube is connected to the source of the NMOS tube M11, and the drain is connected to the drain of the NMOS tube M14.
  • the gate of the NMOS tube M13 is connected to the negative terminal of the local oscillator signal LO- It is connected to the drain of NMOS tube M3, and the drain is connected to the drain of NMOS tube M11; the gate of NMOS tube M14 is connected to the negative terminal LO + of the local oscillator signal, and its source is connected to the drain of NMOS tube M3. Connected to one end of load-level resistor R1;
  • the switch stage is connected to the local oscillator signal, and the MOS tube is turned on in turn under the control of the local oscillator large signal, and the current is switched and modulated to realize the frequency conversion;
  • the load stage includes a resistor R1, a resistor R2, a capacitor C1, and a capacitor C2.
  • One end of R1 is connected to the drain of the NMOS tube M11 and the other end is connected to the power supply voltage VDD; one end of the capacitor C1 is connected to the drain of the NMOS tube M11 and the other end is connected to the power supply voltage VDD; one end of R2 is connected to the The drain is connected, the other end is connected to the power supply voltage VDD; one end of the capacitor C2 is connected to the drain of the NMOS tube M14, and the other end is connected to the power supply voltage VDD.
  • the improved current injection technology includes a PMOS tube M15, a PMOS tube M16, and a PMOS tube M17.
  • the gate of the PMOS tube M15 is connected to the DC bias voltage V1, the source is connected to the power supply voltage VDD, and the drain is connected to the source of the PMOS tube M16;
  • the gate of the PMOS tube M16 is connected to the drain of the PMOS tube M17, and the drain
  • the electrode is connected to the drain of the NMOS tube M1;
  • the gate of the PMOS tube M17 is connected to the drain of the PMOS tube M16, the drain is connected to the drain of the NMOS tube M3, and the source is connected to the source of the PMOS tube M16;
  • a beneficial effect of the further solution a current pulse is generated at the moment when the two switching tubes are simultaneously turned on or switched on.
  • the switch pair When one pair of MOS tubes in the switch pair is turned on, the other pair of MOS tubes is turned off, and the current flowing through the MOS tubes is determined by the current across the conduit, which does not contribute to noise. Therefore, a dynamic current injection technology can be adopted.
  • the switch to the NMOS tube When the switch to the NMOS tube is turned on at the same time, the voltage at the common source node of the switch stage reaches the lowest level, and the PMOS transistors M16 and M17 are turned on to draw the current from the switch to the common source node.
  • FIG. 1 is a schematic diagram of a circuit in the present invention
  • FIG. 2 is a simulation diagram of the change of the conversion gain with the power of the local oscillator in the present invention
  • FIG. 3 is a simulation diagram of a change in conversion gain with output frequency in the present invention.
  • FIG. 4 is a simulation result diagram of a noise figure of the present invention.
  • FIG. 5 is a graph of linearity simulation results of the present invention.
  • An active mixer circuit includes a transconductance stage, a switching stage, and a load stage.
  • the transconductance stage module adopts the third-order transconductance coefficient correction current mirror technology, noise cancellation technology, and degenerate inductor structure of the source. It is connected to an external input device and connected to the RF voltage signal to convert the RF voltage signal into a RF current signal.
  • the switch stage The local oscillator signal is connected, and the MOS tube is turned on in turn under the control of the local oscillator large signal, and the current is switched and modulated to achieve frequency conversion.
  • the load-level RC circuit is responsible for converting the frequency-converted intermediate frequency current signal into an output. Voltage signal.
  • the transconductance stage includes NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, NMOS tube M9, NMOS tube M10, PMOS tube M5, NMOS tube M6, and NMOS tube.
  • One end of the inductor L2 is connected to the positive terminal RF + of the RF voltage signal, and the other end is connected to the gate of the NMOS tube M1; the source of the NMOS tube M1 is connected to the source of the NMOS tube M2, and the drain is connected to the drain of the NMOS tube M9.
  • the gate and drain of the NMOS tube M9 are connected, the source is connected to the gate of the NMOS tube M1; the gate of the NMOS tube M2 is connected to the gate of the NMOS tube M1, and the source is connected to the source of the NMOS tube M1,
  • the drain is connected to the drain of the PMOS tube M6; one end of the inductor L4 is connected to the source of the NMOS tube M1, and the other end is grounded; the drain of the PMOS tube M5 is connected to the drain of the NMOS tube M1, and the gate is connected to the drain of the PMOS tube M6.
  • the gate is connected, the source is connected to the bias voltage V0; the gate and drain of the PMOS tube M6 are connected, and the source is connected to the bias voltage V0;
  • One end of the inductor L3 is connected to the negative terminal of the RF voltage signal, and the other end is connected to the gate of the NMOS tube M3; the source of the NMOS tube M3 is connected to the source of the NMOS tube M4, and the drain is connected to the drain of the NMOS tube M10.
  • the gate and drain of the NMOS tube M10 are connected, the source is connected to the gate of the NMOS tube M3; the gate of the NMOS tube M4 is connected to the gate of the NMOS tube M3, and the source is connected to the source of the NMOS tube M3,
  • the drain is connected to the drain of the PMOS tube M7; one end of the inductor L5 is connected to the source of the NMOS tube M3, and the other end is grounded; the drain of the PMOS tube M8 is connected to the drain of the NMOS tube M3, and the gate is connected to the PMOS tube M7.
  • the gate is connected, the source is connected to the bias voltage V0; the gate and drain of the PMOS tube M7 are connected, and the source is connected to the bias voltage V0; one end of the inductor L1 is connected to the drain of the NMOS tube M1, and the other of the inductor L1 The drain of one end NMOS tube M3 is connected;
  • the fully differential transconductance stage uses a third-order transconductance coefficient to modify the current mirror pair circuit.
  • the MOS tube operates in different regions, and its transconductance is different.
  • the bias voltage of the auxiliary MOS tube is adjusted to work in the sub-threshold region, the third-order transconductance coefficient of the third-order transconductance coefficient and the third-order transconductance coefficient of the main amplifier tube can be cancelled each other, thereby improving the linearity of the circuit.
  • the series feedback of the transconductance MOS transistors M1 and M3 of the mixer constitutes a series feedback to improve the linearity of the mixer.
  • L2-L5 forms a better impedance matching circuit and also improves the linearity of the circuit.
  • an inductor L1 is connected in series between the transconductance stage and the switching stage, so that the linearity of the mixer is improved.
  • the NMOS transistors M9 and M10 are used to form the input noise cancellation circuit in the transconductance stage.
  • the NMOS transistors M9 and M10 work in the deep linear region and can be equivalent to resistors.
  • MOS Any noise between the two ends of the tube that can be equivalent to a current source can be eliminated by this structure.
  • the flicker noise caused by the MOS tube itself cannot be completely eliminated, and only the inflow part can be eliminated, while the outflow part cannot. Even so, this structure still has great advantages in obtaining low noise.
  • the switching stage includes an NMOS tube M11, an NMOS tube M12, an NMOS tube M13, and an NMOS tube M14.
  • the gate of the NMOS transistor M11 is connected to the positive terminal LO + of the local oscillator signal
  • the source stage is connected to the drain of the NMOS transistor M1, and the drain is connected to one end of the load stage resistor R1;
  • the gate of the NMOS transistor M12 is connected to the local oscillator signal.
  • the negative terminal of the NMOS tube is connected to the source of the NMOS tube M11, and the drain is connected to the drain of the NMOS tube M14.
  • the gate of the NMOS tube M13 is connected to the negative terminal of the local oscillator signal LO- It is connected to the drain of NMOS tube M3, and the drain is connected to the drain of NMOS tube M11; the gate of NMOS tube M14 is connected to the negative terminal LO + of the local oscillator signal, and its source is connected to the drain of NMOS tube M3. Connected to one end of the load stage resistor R1.
  • the switch stage is connected to the local oscillator signal, and the MOS tube is turned on in turn under the control of the large local oscillator signal, and the current is switched and modulated to achieve frequency conversion.
  • the load stage includes a resistor R1, a resistor R2, a capacitor C1, and a capacitor C2.
  • R1 is connected to the drain of the NMOS tube M11, the other end of R1 is connected to the power supply voltage VDD;
  • one end of the capacitor C1 is connected to the drain of the NMOS tube M11, and the other end of the capacitor C1 is connected to the power supply voltage VDD;
  • one end of R2 Connected to the drain of the NMOS tube M14, the other end of R2 is connected to the power supply voltage VDD;
  • one end of the capacitor C2 is connected to the drain of the NMOS tube M14, and the other end of the capacitor C2 is connected to the power supply voltage VDD.
  • the impedance values of the capacitors C1 and C2 are AC ground, which can provide the load required for the conversion gain.
  • the improved current injection technology includes a PMOS tube M15, a PMOS tube M16, and a PMOS tube M17.
  • the gate of the PMOS tube M15 is connected to the DC bias voltage V1, the source is connected to the power supply voltage VDD, and the drain is connected to the source of the PMOS tube M16; the gate of the PMOS tube M16 is connected to the drain of the PMOS tube M17, and the drain
  • the electrode is connected to the drain of the NMOS tube M1; the gate of the PMOS tube M17 is connected to the drain of the PMOS tube M16, the drain is connected to the drain of the NMOS tube M3, and the source is connected to the source of the PMOS tube M16.
  • a dynamic current injection technology is used, and a current pulse will be generated at the moment when two switching tubes are turned on at the same time or the switching action is performed.
  • the other pair of MOS tubes is turned off, and the current flowing through the MOS tubes is determined by the current across the conduit, which does not contribute to noise. Therefore, a dynamic current injection technology can be adopted.
  • the conversion gain of the mixer is improved.
  • the resonance frequency is selected at 2 ⁇ RF , the parasitic capacitance impedance is reduced to 1/3 of the original, so that the nonlinearity of the second harmonic caused by the parasitic capacitance is minimized.
  • the invention adopts TSMC 0.18um CMOS process parameters and simulates the circuit in Cadence Spectre.
  • the size parameters of the circuit are shown in Table 1.
  • the comparative references are:
  • circuit structure of the present invention is simple, the conversion gain is high, the linearity is good, the noise is low, and the port isolation is high.

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Abstract

一种有源混频器，属于混频器技术领域。该混频器包括跨导级（1）、开关级（2）和负载级（3）三部分；跨导级（1）采用第三阶跨导系数修正电流镜对电路，将输入的射频差分电压信号转换成电流信号；开关级（2）MOS管在本振大信号的控制下轮流导通；负载级（3）电阻将开关级转换后的电流信号转换成电压信号；该混频器采用了改进型的动态电流注入技术，减小了混频器的闪烁噪声；结构简单、转换增益高、线性度好、噪声低、端口隔离度好。

Description

一种有源混频器 技术领域
本发明属于射频集成电路领域，涉及一种有源混频器，具体为高转换增益、高线性度、低噪声、高隔离度的混频器。
背景技术
随着无线通信的高速发展，Wi f i、蓝牙广泛应用于人们的工作于生活中，无线通信的迅速发展使得人们对通信设备需求不断增加，并且对其性能提出了更高的要求。射频接收机是无线通信的重要模块，它的性能指标影响着整个无线通信***，所以射频集成电路的设计必须向着小型化、低成本、低功耗、高性能、高集成度方向发展。混频器是射频接收机的核心模块，它实现射频到中频的转换。有源混频器对本振功率要求较低，而且可以提供较高的增益，降低混频器后级电路的噪声要求。因此，在混频器的设计中，需要对转换增益、噪声、线性度、功耗、隔离度等性能指标进行综合考虑。
发明内容
本发明的目的是提供一种有源混频器电路，所要解决的技术问题是：在低功耗的基础上提高混频器的性能受到限制。
本发明解决上述技术问题的技术方案如下：一种有源混频器电路，包括跨导级、开关级和负载级。跨导级模块采用第三阶跨导系数修正电流镜技术、噪声消除技术和源简并电感结构，与外部输入设备连接，接入射频电压信号，将射频电压信号转化为射频电流信号；开关级接入本振信号，采用MOS管在本振大信号的控制下轮流导通，对电流进行切换调制，来实现频率的转换； 所述负载级RC电路负责把变频后的中频电流信号转换成输出电压信号。
本发明的有益效果是：跨导级由第三阶跨导系数修正电流镜技术(M1-M10)构成，使得混频器的转换增益和线性度得到了改善。同时采用源简并电感结构，电感L4、L5提供了较好的输入匹配特性，还提高了电路的线性度。为降低输入级的噪声，在跨导级采用了噪声消除技术。电路在两个开关级的共源节点处并联了一个电感L1，用来消除寄生电容对噪声和线性度的影响。为了提高混频器的转换增益，电路采用了改进型的动态电流注入技术用来减小闪烁噪声。
在上述技术方案的基础上，本发明还可以做如下改进。
进一步，跨导级包括NMOS管M1、NMOS管M2、NMOS管M3、NMOS管M4、NMOS管M9、NMOS管M10，PMOS管M5、NMOS管M6、NMOS管M7、NMOS管M8，电感L1、电感L2、电感L3、电感L4和电感L5。其中电感L2的一端与射频电压信号的正极端RF+连接，另一端与NMOS管M1的栅极连接；NMOS管M1的源级与NMOS管M2的源级连接，漏极与NMOS管M9的漏极连接；NMOS管M9的栅极和漏极连接，源级与NMOS管M1的栅极连接；NMOS管M2的栅极与NMOS管M1的栅极连接，源级与NMOS管M1的源级连接，漏极与PMOS管M6的漏极连接；电感L4的一端与NMOS管M1的源级连接，另一端接地；PMOS管M5的漏极与NMOS管M1的漏极连接，栅极与PMOS管M6的栅极连接，源级与偏置电压V0连接；PMOS管M6的栅极和漏极连接，源级与偏置电压V0连接；
电感L3的一端与射频电压信号的负极端RF-连接，另一端与NMOS管M3的栅极连接；NMOS管M3的源级与NMOS管M4的源级连接，漏极与NMOS管M10的漏极连接；NMOS管M10的栅极和漏极连接，源级与NMOS管M3的栅极连接；NMOS管M4的栅极与NMOS管M3的栅极连接，源级与NMOS管M3的源级连接，漏极与PMOS管M7的漏极连接；电感L5的一端与NMOS管M3的源 级连接，另一端接地；PMOS管M8的漏极与NMOS管M3的漏极连接，栅极与PMOS管M7的栅极连接，源级与偏置电压V0连接；PMOS管M7的栅极和漏极连接，源级与偏置电压V0连接；电感L1的一端与NMOS管M1的漏极连接，电感L1的另一端NMOS管M3的漏极连接；
进一步方案的有益效果：跨导级采用了NMOS管M1、M2，电流镜M5、M6构成了第三阶跨导系数修正电流镜对电路。输出的电流信号注入到开关级进行频率转换。通过在混频器的跨导级MOS管M1、M3的源级串联无源器件构成串联反馈可以提高混频器的线性度。在一些文献中有人采用电阻、电容、电感作为反馈器件，来提高混频器的线性度。但若采用电阻时，会引起额外的电阻热噪声，使得混频器的噪声性能降低。若采用电容或者电感作为负反馈则不会使噪声性能降低。但使用电容作为反馈器件时需要增加额外的直流通路，所以使用本发明采用电感L4、L5作为反馈器件。L2-L5形成了较好的阻抗匹配电路，还提高了电路的线性度。为了消除寄生电容的影响，在跨导级和开关级之间串联了一个电感L1，使得混频器的线性度得到了提高。为降低输入级的噪声，在跨导级采用了NMOS管M9、M10构成了输入噪声消除电路。
进一步，开关级包括NMOS管M11、NMOS管M12、NMOS管M13、NMOS管M14。其中NMOS管M11的栅极与本振信号的正极端LO+连接，其源级与NMOS管M1的漏极连接，漏极与负载级电阻R1的一端连接；NMOS管M12的栅极与本振信号的负极端LO-连接，其源级与NMOS管M11的源极连接，漏极与NMOS管M14的漏极连接；NMOS管M13的栅极与本振信号的负极端LO-连接，其源级与NMOS管M3的漏极连接，漏极与NMOS管M11的漏极连接；NMOS管M14的栅极与本振信号的负极端LO+连接，其源级与NMOS管M3的漏极连接，漏极与负载级电阻R1的一端连接；
进一步方案的有益效果：开关级接入本振信号，采用MOS管在本振大信 号的控制下轮流导通，对电流进行切换调制，来实现频率的转换；
进一步，负载级包括电阻R1、电阻R2、电容C1和电容C2。其中R1的一端与NMOS管M11的漏极连接，另一端与电源电压VDD连接；电容C1的一端与NMOS管M11的漏极连接，另一端与电源电压VDD连接；R2的一端与NMOS管M14的漏极连接，另一端与电源电压VDD连接；电容C2的一端与NMOS管M14的漏极连接，另一端与电源电压VDD连接。
进一步方案的有益效果：当输入差模信号时，电容C1、C2阻抗值是交流接地，可以提供转换增益所需的负载。
进一步，改进型电流注入技术包括PMOS管M15、PMOS管M16、PMOS管M17。其中PMOS管M15的栅极与直流偏置电压V1连接，源极与电源电压VDD连接，漏极与PMOS管M16的源极连接；PMOS管M16的栅极与PMOS管M17的漏极连接，漏极与NMOS管M1的漏极连接；PMOS管M17的栅极与PMOS管M16的漏极连接，漏极与NMOS管M3的漏极连接，源级与PMOS管M16的源极连接；
进一步方案的有益效果：在两个开关管同时导通或者开关动作的瞬间，会产生电流脉冲。当开关对中一对MOS管导通时,另一对MOS管截止,流过MOS管的电流由跨导管的电流决定，对噪声没有贡献。因此,可以采用一种动态的电流注入技术，当开关对NMOS管同时导通时，开关级共源节点处的电压达到最低，PMOS管M16、M17导通，将开关对共源节点的电流抽走，当开关对中的NMOS管没有同时导通时，共源节点处的电压很高，PMOS管M16、M17截止，不抽走电流。这种方案可以有效地降低了噪声电流脉冲的幅度,从而降低1/f噪声，也不会像静态电流注入那样引起额外的热噪声，由于只有开关瞬间抽取电流，因此基本不会引入热噪声。
附图说明
图1为本发明中电路原理图；
图2为本发明中转换增益随本振功率变化的仿真图；
图3为本发明中转换增益随输出频率变化的仿真图；
图4为本发明噪声系数仿真结果图；
图5为本发明线性度仿真结果图；
附图中，各标号所代表的部件列表如下：
1、跨导级，2、开关级，3、负载级，4、电流注入电路。
具体实施方式
以下结合附图对本发明的原理和特征进行描述，所举实例只用于解释本发明，并非用于限定本发明的范围。
一种有源混频器电路，包括跨导级、开关级和负载级。跨导级模块采用第三阶跨导系数修正电流镜技术、噪声消除技术和源简并电感结构，与外部输入设备连接，接入射频电压信号，将射频电压信号转化为射频电流信号；开关级接入本振信号，采用MOS管在本振大信号的控制下轮流导通，对电流进行切换调制，来实现频率的转换；所述负载级RC电路负责把变频后的中频电流信号转换成输出电压信号。
可选的，作为本发明的一个实施例：跨导级包括NMOS管M1、NMOS管M2、NMOS管M3、NMOS管M4、NMOS管M9、NMOS管M10，PMOS管M5、NMOS管M6、NMOS管M7、NMOS管M8，电感L1、电感L2、电感L3、电感L4和电感L5。其中电感L2的一端与射频电压信号的正极端RF+连接，另一端与NMOS管M1的栅极连接；NMOS管M1的源级与NMOS管M2的源级连接，漏极与NMOS管M9的漏极连接；NMOS管M9的栅极和漏极连接，源级与NMOS管M1的栅极连接；NMOS管M2的栅极与NMOS管M1的栅极连接，源级与NMOS管M1的源级 连接，漏极与PMOS管M6的漏极连接；电感L4的一端与NMOS管M1的源级连接，另一端接地；PMOS管M5的漏极与NMOS管M1的漏极连接，栅极与PMOS管M6的栅极连接，源级与偏置电压V0连接；PMOS管M6的栅极和漏极连接，源级与偏置电压V0连接；
电感L3的一端与射频电压信号的负极端RF-连接，另一端与NMOS管M3的栅极连接；NMOS管M3的源级与NMOS管M4的源级连接，漏极与NMOS管M10的漏极连接；NMOS管M10的栅极和漏极连接，源级与NMOS管M3的栅极连接；NMOS管M4的栅极与NMOS管M3的栅极连接，源级与NMOS管M3的源级连接，漏极与PMOS管M7的漏极连接；电感L5的一端与NMOS管M3的源级连接，另一端接地；PMOS管M8的漏极与NMOS管M3的漏极连接，栅极与PMOS管M7的栅极连接，源级与偏置电压V0连接；PMOS管M7的栅极和漏极连接，源级与偏置电压V0连接；电感L1的一端与NMOS管M1的漏极连接，电感L1的另一端NMOS管M3的漏极连接；
上述实施例中，全差分跨导级采用第三阶跨导系数修正电流镜对电路，MOS管工作在不同的区域，其跨导都不同。当调节辅助MOS管的偏置电压使其工作在亚阈值区，可以使其第三阶跨导系数与主放大管的第三阶跨导系数相互抵消，以此来提高电路的线性度。通过在混频器的跨导级MOS管M1、M3的源级串联电感构成串联反馈提高了混频器的线性度。L2-L5形成了较好的阻抗匹配电路，还提高了电路的线性度。为了消除寄生电容的影响，在跨导级和开关级之间串联了一个电感L1，使得混频器的线性度得到了提高。为降低输入级的噪声，在跨导级采用了NMOS管M9、M10构成了输入噪声消除电路，使NMOS管M9、M10工作在深线性区，可以等效成电阻，对于该噪声消除结构，MOS管两端之间任何能等效为电流源的噪声都能被该结构消除。但是MOS管本身引起的闪烁噪声却不能完全消除，只能消除对流入的那部分，而流出那部分则不能。即便如此，这种结构仍然在获得低噪声方面具有很大 的优势。
可选的，作为本发明的一个实施例：开关级包括NMOS管M11、NMOS管M12、NMOS管M13、NMOS管M14。其中NMOS管M11的栅极与本振信号的正极端LO+连接，其源级与NMOS管M1的漏极连接，漏极与负载级电阻R1的一端连接；NMOS管M12的栅极与本振信号的负极端LO-连接，其源级与NMOS管M11的源极连接，漏极与NMOS管M14的漏极连接；NMOS管M13的栅极与本振信号的负极端LO-连接，其源级与NMOS管M3的漏极连接，漏极与NMOS管M11的漏极连接；NMOS管M14的栅极与本振信号的负极端LO+连接，其源级与NMOS管M3的漏极连接，漏极与负载级电阻R1的一端连接。
上述实例中，开关级接入本振信号，采用MOS管在本振大信号的控制下轮流导通，对电流进行切换调制，来实现频率的转换。
可选的，作为本发明的一个实施例负载级包括电阻R1、电阻R2、电容C1和电容C2。其中R1的一端与NMOS管M11的漏极连接，R1的另一端与电源电压VDD连接；电容C1的一端与NMOS管M11的漏极连接，电容C1的另一端与电源电压VDD连接；R2的一端与NMOS管M14的漏极连接，R2的另一端与电源电压VDD连接；电容C2的一端与NMOS管M14的漏极连接，电容C2的另一端与电源电压VDD连接。
上述实例中，当输入差模信号时，电容C1、C2阻抗值是交流接地，可以提供转换增益所需的负载。
可选的，作为本发明的一个实施例：改进型电流注入技术包括PMOS管M15、PMOS管M16、PMOS管M17。其中PMOS管M15的栅极与直流偏置电压V1连接，源极与电源电压VDD连接，漏极与PMOS管M16的源极连接；PMOS管M16的栅极与PMOS管M17的漏极连接，漏极与NMOS管M1的漏极连接；PMOS管M17的栅极与PMOS管M16的漏极连接，漏极与NMOS管M3的漏极连接，源级与PMOS管M16的源极连接。
上述实例中，采用了动态电流注入技术，在两个开关管同时导通或者开关动作的瞬间，会产生电流脉冲。当开关对中一对MOS管导通时,另一对MOS管截止,流过MOS管的电流由跨导管的电流决定，对噪声没有贡献。因此,可以采用一种动态的电流注入技术，当开关对NMOS管同时导通时，开关级共源节点处的电压达到最低，PMOS管M16、M17导通，将开关对共源节点的电流抽走，当开关对中的NMOS管没有同时导通时，共源节点处的电压很高，PMOS管M16、M17截止，不抽走电流。这种方案可以有效地降低了噪声电流脉冲的幅度,从而降低1/f噪声，也不会像静态电流注入那样引起额外的热噪声，由于只有开关瞬间抽取电流，因此基本不会引入热噪声。我们通过设置合理的电感L1值，使其与寄生电容发生谐振。当谐振频率谐振在ω RF时，混频器的转换增益得到了改善。当谐振频率点选择在2ω RF时，寄生电容阻抗减小到原来的1/3，使寄生电容引起的二次谐波非线性减小到最小。从以上的分析可以看出，当谐振点在不同的频率时，线性度或增益性能在特定的频率能达到很好的优化。本实例中，通过选择合适的电感L1，使得与共源节点处的总寄生电容谐振频率介于射频基波和射频二次谐波之间，混频器的转换增益、噪声、线性度性能参数都能得到提高。
本发明采用TSMC 0.18um CMOS工艺参数，在Cadence Spectre中对电路就行仿真，电路的尺寸参数如表1所示。
表1电路的尺寸参数
器件 参数 器件 参数 器件 参数
M1、M3 40u/0.18u M11、M12 120u/0.18u C1、C2 500p
M2、M4 80u/0.18u M13、M14 120u/0.18u L1 5n
M5、M8 27u/0.4u M15 60u/0.4 L2、L3 3n
M6、M7 3u/0.4u M16、M17 8u/0.4u L4、L5 2n
M9、M10 256u/0.4u R1、R2 167    
本发明的有源混频器与近几年发表的混频器性能进行比较，如表2所示。
表2本发明的有源混频器
Figure PCTCN2018101970-appb-000001
对比的参考文献分别为：
[1]Wei K C,Ramiah H,Vitee N.A 0.12-,2.4-GHz CMOS Inductorless High Isolation Subharmonic Mixer With Effective Current-Reuse Transconductance[J].IEEE Transactions on Microwave Theory&Techniques,2015,63(8):2427-2437.
[2]姜梅,张兴,王新安,等.一款工作于2.4GHz频段的带有源负载的高性能双平衡有源混频器[J].北京大学学报:自然科学版,2012,48(4):538-544.
[3]Yoon J,Kim H,Park C,et al.A New RF CMOS Gilbert Mixer With Improved Noise Figure and Linearity[J].IEEE Transactions on Microwave Theory&Techniques,2008,56(3):626-631.
由上述分析可知，本发明电路结构简单、转换增益高、线性度好、噪声低、端口隔离度高。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (5)

  1. 一种混频器电路，其特征在于：包括依次电连接的跨导级、开关级和负载级，所述跨导级采用第三阶跨导系数修正电流镜对电路和源简并电感结构，跨导级与外部输入设备连接，接入射频电压，将射频电压转化为射频电流；
    所述开关级接入本振信号，采用MOS管在本振大信号的控制下轮流导通，对电流进行切换调制，来实现频率的转换；
    所述负载级电阻负责把变频后的中频电流信号转换成输出电压信号。
  2. 根据权利要求1所述的混频器，其特征在于：所述跨导级包括NMOS管M1、NMOS管M2、NMOS管M3、NMOS管M4、NMOS管M9、NMOS管M10，PMOS管M5、NMOS管M6、NMOS管M7、NMOS管M8，电感L1、电感L2、电感L3、电感L4和电感L5；所述电感L2的一端与射频电压信号的正极端RF+连接，另一端与NMOS管M1的栅极连接；NMOS管M1的源级与NMOS管M2的源级连接，漏极与NMOS管M9的漏极连接；NMOS管M9的栅极和漏极连接，源级与NMOS管M1的栅极连接；NMOS管M2的栅极与NMOS管M1的栅极连接，源级与NMOS管M1的源级连接，漏极与PMOS管M6的漏极连接；电感L4的一端与NMOS管M1的源级连接，另一端接地；PMOS管M5的漏极与NMOS管M1的漏极连接，栅极与PMOS管M6的栅极连接，源级与偏置电压V0连接；PMOS管M6的栅极和漏极连接，源级与偏置电压V0连接；
    电感L3的一端与射频电压信号的负极端RF-连接，另一端与NMOS管M3的栅极连接；NMOS管M3的源级与NMOS管M4的源级连接，漏极与NMOS管M10的漏极连接；NMOS管M10的栅极和漏极连接，源级与NMOS管M3的栅极连接；NMOS管M4的栅极与NMOS管M3的栅极连接，源级与NMOS管M3的源级连接，漏极与PMOS管M7的漏极连接；电感L5的一端与NMOS管M3的源 级连接，另一端接地；PMOS管M8的漏极与NMOS管M3的漏极连接，栅极与PMOS管M7的栅极连接，源级与偏置电压V0连接；PMOS管M7的栅极和漏极连接，源级与偏置电压V0连接；电感L1的一端与NMOS管M1的漏极连接，电感L1的另一端NMOS管M3的漏极连接。
  3. 根据权利要求2所述的混频器，其特征在于：所述开关级包括NMOS管M11、NMOS管M12、NMOS管M13、NMOS管M14；所述NMOS管M11的栅极与本振信号的正极端LO+连接，其源级与NMOS管M1的漏极连接，漏极与负载级电阻R1的一端连接；NMOS管M12的栅极与本振信号的负极端LO-连接，其源级与NMOS管M11的源极连接，漏极与NMOS管M14的漏极连接；NMOS管M13的栅极与本振信号的负极端LO-连接，其源级与NMOS管M3的漏极连接，漏极与NMOS管M11的漏极连接；NMOS管M14的栅极与本振信号的负极端LO+连接，其源级与NMOS管M3的漏极连接，漏极与负载级电阻R2的一端连接。
  4. 根据权利要求3所述的混频器，其特征在于：所述负载级包括电阻R1、电阻R2、电容C1和电容C2；所述电阻R1的一端与NMOS管M11的漏极连接，R1的另一端与电源电压VDD连接；电容C1的一端与NMOS管M11的漏极连接，另一端与电源电压VDD连接；所述电阻R2的一端与NMOS管M14的漏极连接，R2的另一端与电源电压VDD连接；电容C2的一端与NMOS管M14的漏极连接，另一端与电源电压VDD连接。
  5. 根据权利要求4所述的混频器，其特征在于：所述改进型电流注入技术包括PMOS管M15、PMOS管M16、PMOS管M17；所述PMOS管M15的栅极与直流偏置电压V1连接，源极与电源电压VDD连接，漏极与PMOS管M16的源极连接；PMOS管M16的栅极与PMOS管M17的漏极连接，漏极与NMOS管M1的漏极连接；PMOS管M17的栅极与PMOS管M16的漏极连接，漏极与NMOS管M3的漏极连接，源级与PMOS管M16的源极连接。
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