WO2020000593A1 - 一种阵列基板及显示面板 - Google Patents

一种阵列基板及显示面板 Download PDF

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Publication number
WO2020000593A1
WO2020000593A1 PCT/CN2018/100230 CN2018100230W WO2020000593A1 WO 2020000593 A1 WO2020000593 A1 WO 2020000593A1 CN 2018100230 W CN2018100230 W CN 2018100230W WO 2020000593 A1 WO2020000593 A1 WO 2020000593A1
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Prior art keywords
layer
insulating layer
gate
array substrate
region
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PCT/CN2018/100230
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English (en)
French (fr)
Inventor
赵瑜
Original Assignee
武汉华星光电半导体显示技术有限公司
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Priority to US16/094,478 priority Critical patent/US20210226137A1/en
Publication of WO2020000593A1 publication Critical patent/WO2020000593A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a display panel, and a method for manufacturing the array substrate, a display, and an electronic device.
  • OLED display panels have become a very popular emerging flat display device product at home and abroad. This is because OLED display devices have self-emission, wide viewing angle, short response time, high light-emitting efficiency, Wide color gamut, low operating voltage, thin thickness, large-scale and flexible panels can be made, and simple manufacturing process. It also has the potential of low cost.
  • the inorganic insulating layer (such as the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer) generally covers the flexible substrate in its entirety. Therefore, when the display panel is folded, inorganic substances are easily broken, and Causes device failure.
  • the inorganic insulating layer including the buffer layer, the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer
  • all parts of the inorganic insulating layer that do not have an insulating effect are removed, and only The necessary part that plays an insulating role is retained, thereby effectively preventing the inorganic objects from being broken when a display panel having the array substrate is folded, so as to increase the flexibility of the display panel.
  • the present application first provides an array substrate having a first region and a second region.
  • the array substrate includes: a flexible substrate; a first layer; the first layer is provided on the flexible substrate and is located on the first region; a second layer; the second layer is provided On the flexible substrate and on the first region; and an inorganic insulating layer, the inorganic insulating layer is provided between the first layer and the second layer, and is located on the first layer On one region but not on the second region; wherein one of the first layer and the second layer is a metal layer; the first layer includes an active layer; the second layer The layer includes a first gate; and the inorganic insulating layer includes a first gate insulating layer disposed on the active layer and the first gate.
  • the first layer further includes a second gate
  • the inorganic insulating layer further includes a second gate insulation disposed between the first gate and the second gate. Floor.
  • the array substrate further includes an organic dielectric layer.
  • the organic dielectric layer includes a first portion located in the second region and a second portion located on the inorganic insulating layer.
  • the second layer further includes a source / drain, and the source / drain passes through the first gate insulating layer and the second gate insulating layer and is connected to the active layer.
  • the inorganic insulating layer further includes an interlayer insulating layer provided between the second gate and the source / drain, and a second portion of the organic dielectric layer is located between the source / drain and the source / drain; Between the interlayer insulation layers.
  • the second area includes a curved portion corresponding to a non-display area of a display panel
  • the first area includes a functional portion corresponding to the display area of the display panel and adjacent to the curved portion
  • the array substrate is provided with a groove adjacent to a boundary between the curved portion and the display portion, the groove penetrates the organic dielectric layer and exposes the first gate insulating layer and the second gate Electrode insulation layer and said interlayer insulation layer.
  • the array substrate further includes a buffer layer between the flexible substrate and the active layer, and the source / drain penetrates the active layer and the buffer layer.
  • the array substrate includes a functional area corresponding to a display area of a display panel, and the functional area includes the first area and the second area.
  • the present application also provides an array substrate having a first region and a second region.
  • the array substrate includes: a flexible substrate; a first layer provided on the flexible substrate; the first layer is located on the first region; a first layer provided on the flexible substrate; A second layer, the second layer being located on the first region; and an inorganic insulating layer provided between the first layer and the second layer; wherein the inorganic insulating layer is located on the first region; On the first zone and not on the second zone.
  • the array substrate further includes an organic dielectric layer, and the organic dielectric layer includes a first portion located in the second region.
  • the organic medium layer further includes a second portion on the inorganic insulating layer.
  • one of the first layer and the second layer is a metal layer.
  • the first layer includes an active layer
  • the second layer includes a first gate
  • the inorganic insulating layer includes a layer disposed on the active layer and the first gate.
  • a first gate insulating layer is first insulating layer.
  • the first layer further includes a second gate
  • the inorganic insulating layer further includes a second gate insulating layer disposed between the first gate and the second gate.
  • the second layer further includes a source / drain, and the source / drain passes through the first gate insulating layer and the second gate insulating layer and is connected to the active layer.
  • the inorganic insulating layer further includes an interlayer insulating layer provided between the second gate and the source / drain, and a second portion of the organic dielectric layer is located between the source / drain and the source / drain. Between the interlayer insulation layers.
  • the second region includes a curved portion corresponding to a non-display region of a display panel
  • the first region includes a display region corresponding to the display panel and is adjacent to the curve.
  • a functional part of a portion, the array substrate is provided with a groove adjacent to a boundary between the curved portion and the display portion, the groove penetrates the organic dielectric layer and exposes the first gate insulation Layer, the second gate insulating layer, and the interlayer insulating layer.
  • the array substrate further includes a buffer layer between the flexible substrate and the active layer, and the source / drain penetrates the active layer and the buffer layer.
  • the array substrate includes a functional area corresponding to a display area of a display panel, and the functional area includes the first area and the second area.
  • the present application also provides a method for manufacturing a display panel, which includes the above-mentioned array substrate.
  • the array substrate includes a first region and a second region, and the manufacturing method includes:
  • S1 providing a flexible substrate and a first layer disposed on the flexible substrate, the first layer being located on the first region;
  • the second area includes a curved portion corresponding to a non-display area of a display panel
  • the first area includes a functional portion corresponding to a display area of the display panel and is adjacent to the curved portion.
  • a groove is provided on the array substrate adjacent to a boundary between the curved portion and the display portion, the groove penetrates the organic dielectric layer and exposes the first gate insulating layer and the second A gate insulating layer and the interlayer insulating layer.
  • the present application also provides a display panel including a first region and a second region.
  • the display panel includes: a flexible substrate; a first layer disposed on the flexible substrate; The first layer is located on the first region; a second layer is provided on the flexible substrate, the second layer is located on the first region; and, the first layer is provided on the first layer; An inorganic insulating layer between the second layer and the second layer; wherein the inorganic insulating layer is located on the first region and not on the second region.
  • the present application further provides a display panel including the above-mentioned array substrate or an array substrate manufactured by the above-mentioned manufacturing method.
  • the display panel includes, but is not limited to, OLED, QLED, LED, Micro LED, and the like.
  • OLED is taken as an example for detailed description in this specification.
  • the present application also provides an application of the above array substrate in a display panel, such as but not limited to OLED, QLED, LED, and Micro LED.
  • the present application also provides a display.
  • the display includes an array substrate described above, or includes a display panel described above.
  • the present application also provides an electronic device, which includes an array substrate as described above or a display panel as described above.
  • the electronic device is a terminal device with a display panel, such as, but not limited to, a mobile phone, a smart phone, a notebook computer, a digital broadcast receiver, a PDA (Personal Digital Assistant), a PAD (Tablet Computer), and a PMP (Portable Multimedia Player) Device), navigation device, etc.
  • first region is defined as a region where the inorganic insulating layer is required to be insulated
  • second region is defined as a region where the inorganic insulating layer may not be required.
  • the array substrate of the present application has at least the following structure: an active layer, a first gate insulating layer, a first A gate, a second gate insulating layer, a second gate, an interlayer insulating layer, an organic dielectric layer, and a source / drain
  • the first region is in the first gate insulating layer A region that covers and only covers the active layer, and covers and only covers the first gate in the second gate insulating layer (of course, it also includes a non-display region formed together with the first gate) Area of the gate line and the gate pad portion), the interlayer insulation layer and only the second gate (of course, also includes the second gate formed in the non-display area) Gate line and gate pad part).
  • the second region is all regions of the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer except the first region.
  • the inorganic insulating layer further includes a buffer layer formed between the active layer and the flexible substrate.
  • the buffer layer is also located in the first region. That is, the buffer layer is provided only between the active layer and the flexible substrate.
  • the present application also provides an array substrate including: a flexible substrate including a curved portion and a functional portion; at least one patterned functional layer, the patterned functional layer being disposed on the flexible On the substrate; and, an inorganic insulating layer disposed on the patterned functional layer; wherein the pattern of the inorganic insulating layer corresponds to the pattern of the patterned functional layer .
  • the patterned functional layer is an active layer, a first patterned metal layer, or a second patterned metal layer.
  • the first patterned metal layer includes a plurality of first gate electrodes located in a display area of the display panel, a plurality of gate pads located in a non-display area of the display panel, and a connection. A gate line of the first gate and the gate pad.
  • the second patterned metal layer includes a plurality of second gates located in a display area of the display panel, a plurality of gate pads located in a non-display area of the display panel, and a connection to the second gate. With the gate line of the gate pad.
  • the array substrate further includes an organic dielectric layer, the organic dielectric layer is disposed on the inorganic insulating layer and completely covers the flexible substrate; wherein the organic dielectric layer is in A groove is formed at an interface between the curved portion and the functional portion, and the groove penetrates the organic medium layer to expose the flexible substrate.
  • the array substrate further includes a buffer layer, the buffer layer is disposed on the flexible substrate and is in contact with the flexible substrate, wherein the pattern of the buffer layer and the pattern The pattern of the functional layer corresponds.
  • inorganic insulation is formed on and only on the active layer, the first gate (and / or the second gate) and its traces, and the source / drain and its traces. Layer for insulation.
  • the present application also provides a method for manufacturing the above-mentioned array substrate, including: S1: providing a flexible substrate, the flexible substrate including a curved portion and a functional portion; S2: forming a patterned function on the flexible substrate And S3: forming an inorganic insulating layer on the patterned functional layer, and patterning the inorganic insulating layer so that the pattern of the inorganic insulating layer corresponds to the pattern of the patterned functional layer And remove the rest of the inorganic insulating layer.
  • the manufacturing method further includes: S4: forming a comprehensively covered organic dielectric layer so that the organic dielectric layer is positioned above the inorganic insulating layer and contacts the flexible substrate; and patterning the organic dielectric layer so that the organic dielectric layer The organic medium layer forms a groove at the boundary between the curved portion and the functional portion, and the groove penetrates the organic medium layer to expose the flexible substrate.
  • the manufacturing method further includes: S5: forming a third patterned metal layer on the organic dielectric layer, the third patterned metal layer including a plurality of source electrodes and a plurality of drain electrodes.
  • the manufacturing method further includes: the manufacturing method further includes: between S1 and S2: S1-2: forming a buffer layer on the flexible substrate, and patterning the buffer layer so that The pattern of the buffer layer corresponds to the pattern of the patterned functional layer.
  • a method for forming an active layer on a buffer layer is: depositing an amorphous silicon layer on the buffer layer, and performing molecular laser annealing treatment on the amorphous silicon layer, so that the amorphous silicon After the layer is crystallized, it is converted into a polysilicon layer, and the polysilicon layer is patterned by a yellow light and etching process to form a polysilicon segment, and then the source contact regions and The drain contact region.
  • the material forming the first and second gates may be a conventional metal material forming a gate in the art.
  • the material forming the inorganic insulating layer may be a conventional inorganic material forming a gate insulating layer (or a barrier gate) in the art, for example, a metal oxide (such as silicon oxide, aluminum oxide, tin oxide, zinc oxide, indium tin oxide).
  • a metal oxide such as silicon oxide, aluminum oxide, tin oxide, zinc oxide, indium tin oxide.
  • metal nitrides such as silicon nitride, aluminum nitride, boron nitride
  • metal oxynitrides such as aluminum nitride, silicon oxynitride, boron oxynitride
  • metal carbonization Materials such as tungsten carbide, boron carbide, silicon carbide
  • metal boron oxides such as zirconia boron oxide, titanium borooxide, etc.
  • a photomask is used to form a first contact hole and a second contact hole, which saves the number of photomasks in the manufacturing process and simplifies the manufacturing process.
  • the structure of the inorganic insulating layer of the buffer layer, the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer, which play an insulating role, is adjusted.
  • a groove is formed on the organic dielectric layer, the flat layer, and the pixel defining layer at a boundary between a display area and a non-display area of the flexible substrate, so as to expose all
  • the flexible substrate further prevents device failure caused by moisture being transmitted into the display area through organic matter.
  • FIG. 1 is a schematic structural diagram of a display panel according to the present application.
  • step 1 of a method for manufacturing a display panel according to the present application is a schematic diagram of step 1 of a method for manufacturing a display panel according to the present application
  • step 2 of the method for manufacturing a display panel according to the present application is a schematic diagram of step 2 of the method for manufacturing a display panel according to the present application.
  • 4A and 4B are schematic diagrams of step 3 of the method for manufacturing a display panel according to the present application.
  • step 4 is a schematic diagram of step 4 of the method for manufacturing a display panel according to the present application.
  • step 5 is a schematic diagram of step 5 of the method for manufacturing a display panel according to the present application.
  • step 7 is a schematic diagram of step 7 of the method for manufacturing a display panel according to the present application.
  • step 8 is a schematic diagram of step 8 of the method for manufacturing a display panel according to the present application.
  • step 9 is a schematic diagram of step 9 of the method for manufacturing a display panel according to the present application.
  • FIG. 10 is a schematic diagram of step 10 of the method for manufacturing a display panel according to the present application.
  • the "first” or “lower” of the first feature may include the first and second features in direct contact, and may also include the first and second features. Not directly, but through another characteristic contact between them.
  • the first feature is “above”, “above”, and “above” the second feature, including that the first feature is directly above and obliquely above the second feature, or merely indicates that the first feature is higher in level than the second feature.
  • the first feature is “below”, “below”, and “below” of the second feature, including the fact that the first feature is directly below and obliquely below the second feature, or merely indicates that the first feature is less horizontal than the second feature.
  • a display panel is first provided, and the array substrate described in this application is applied.
  • an OLED display panel is taken as an example for description.
  • the array substrate described in this application can also be applied to other types of display panels, such as but not limited to OLED, QLED, LED, and Micro LED, and are formed on the array substrate during application.
  • the other structures of the display panel are sufficient.
  • the display panel has a flexible substrate 10.
  • the flexible substrate 10 includes a display area 101 and a non-display area 102.
  • the display panel includes: a buffer layer 11 provided in the flexible substrate display area 101, and an active layer 12 provided on the buffer layer 11; a first gate Electrode insulating layer 13 and a first gate electrode 131 disposed on the first gate insulating layer; a second gate insulating layer 14 and a second gate electrode disposed on the second gate insulating layer 14 An electrode 141; an interlayer insulating layer 15 provided on the second gate electrode 141; an organic dielectric layer 16 provided on the interlayer insulating layer 15; a source provided on the organic dielectric layer 16 An electrode 171 and a drain 172; a flat layer covering the source 171 and the drain 172; an anode 181 provided on the flat layer 18; a pixel defining layer 19 provided on the anode 18 A spacer 20 formed on the pixel
  • the spacer 20 is used to support the box thickness of the OLED display panel.
  • the flexible substrate 10 is made of polyimide (PI).
  • the inorganic insulating layer (including the buffer layer 11, the first gate insulating layer 13, and the All parts of the second gate insulating layer 14 and the interlayer insulating layer 15) that do not have an insulating effect (ie, the second region), and only the parts that play an insulating role (ie, the first region) are retained, thereby being effective
  • the ground prevents the inorganic material from being broken when the display panel is folded. That is, in this embodiment, in the area shown in FIG. 1, only the first area retains an inorganic insulating layer corresponding to the active layer, the first gate, and the second gate, and plays an insulating role. (The first gate insulating layer 13, the second gate insulating layer 14, and the interlayer insulating layer 15), the inorganic insulating layer in the remaining portion (ie, the second region) is completely removed.
  • the manufacturing method of the display panel described in this embodiment specifically includes the following steps.
  • Step S1 Provide a flexible substrate 10, as shown in FIG. 2, the flexible substrate 10 includes a display area 101 and a non-display area 102; a buffer layer 11 is formed on the flexible substrate 10.
  • the buffer layer 11 can be formed in a known manner, for example, using a chemical vapor deposition method. And, the composition of the buffer layer 11 is a known composition.
  • Step S2 forming a polysilicon layer (not shown) on the buffer layer, and patterning the polysilicon layer and the buffer layer 11 to obtain an active layer 12 as shown in FIG. 3 Only a portion of the buffer layer 11 corresponding to the active layer 12 is retained. As shown in FIG. 3, the rest of the buffer layer 11 is removed, so that the flexible substrate 10 is completely exposed in the rest except the active layer 11. As shown in FIG. 3, the active layer 12 includes a source contact region 121, a drain contact region 122, and a trench between the source contact region 121 and the drain contact region 122. Road District 123.
  • forming the active layer 12 on the buffer layer 11 is to deposit an amorphous silicon layer on the buffer layer 11 and perform molecular laser annealing treatment on the amorphous silicon layer so that the amorphous silicon layer After crystallization, it is converted into the polysilicon layer, and the polysilicon layer is patterned through a yellow light and etching process to form a polysilicon segment, and then the source contact regions are formed at both ends of the polysilicon segment by a deposition, yellow light, and etching process 121 and the drain contact region 122.
  • Step S3 as shown in FIG. 4A, first forming the first gate insulating layer 13 on the active layer 12 and forming the first gate 131 on the first gate insulating layer 13;
  • the second gate insulating layer 14 is formed on the first gate 131 and the second gate 141 is formed on the second gate insulating layer 14.
  • the first gate insulating layer 13 covers the active layer 12 and the flexible substrate 10, and the first gate 131 is located above the active layer 12,
  • the second gate insulating layer 14 covers the first gate 131 and the first gate insulating layer 13, and the second gate 141 is located above the first gate 131.
  • Step S4 An interlayer insulating layer 15 is formed on the second gate 141. As shown in FIG. 5, the interlayer insulating layer 15 covers the second gate 141 and the second gate insulation. Layer 14.
  • the interlayer insulating layer 15 may be formed in a known manner, for example, using a chemical vapor deposition method. And, the composition of the interlayer insulating layer 15 is a known composition.
  • Step S5 Etching the interlayer insulating layer 15, the second gate insulating layer 14, and the first insulating layer 13 with a photomask to form a first contact hole 151 as shown in FIG. And a second contact hole 152, and as shown in FIG. 6, in this step, "the area requiring the inorganic insulating layer for insulation" is defined as the first area, and "the area where the inorganic insulating layer may not be required” is defined It is the second area, wherein the division of the first area and the second area is performed in a top view. For example, in a front view, as shown in FIG.
  • the first region includes the first gate insulating layer 13 and the second gate insulating layer 13 that happen to cover the active layer 12, the first gate 131, and the second gate 141 in FIG. 6.
  • the second region includes other portions on the left and right sides of the portion.
  • the interlayer insulating layer 15, the first gate insulating layer 13 and the second gate insulating layer 14 are etched by using a photomask to retain the first region as shown in FIG. 6.
  • the widths of the first gate insulating layer 13, the second gate insulating layer 14, and the interlayer insulating layer 15 in FIG. 6 remain the same, and are slightly wider than those of the active layer 12. The width. This is due to the use of a photomask for etching. Such a width design will not affect the technical effects described in this application.
  • first gate insulating layer 13, the second gate insulating layer 14, and the interlayer insulating layer 15 can also be etched through multiple photomasks, so that the first A gate insulating layer 13 covers and covers only the active layer 12, and the second gate insulating layer 14 covers and covers only the first gate 131 (of course, it also includes common with the first gate 131 The gate lines and pads formed), the interlayer insulating layer covers and covers only the second gate 141 (of course, the gate lines and pads formed together with the second gate 141).
  • the first contact hole 151 penetrates the source electrode of the interlayer insulating layer 15, the second gate insulating layer 14, the first gate insulating layer 13, and the active layer 12.
  • the second contact hole 152 penetrates the interlayer insulating layer 15, the second gate insulating layer 14, the first gate insulating layer 13, The drain contact region of the active layer 12 and the buffer layer 11 are exposed to expose the flexible substrate 10.
  • Step S6 forming an organic dielectric layer 16 on the interlayer insulating layer 15 so that the organic dielectric layer 16 covers the interlayer insulating layer 15 and the non-display area 102 of the flexible substrate 10.
  • the organic medium layer 16 can be formed in a known manner, for example, using a chemical vapor deposition method.
  • Step S7 The organic dielectric layer 16 is etched with a light to form a third contact hole 161, a fourth contact hole 162, and a first groove 163 as shown in FIG.
  • the third contact hole 161 corresponds to the first contact hole 151
  • the fourth contact hole 162 corresponds to the second contact hole 152
  • the first groove 163 is provided in
  • the interface between the display area 101 and the non-display area 102 of the flexible substrate 10 is to expose the flexible substrate 10. Since the organic medium layer 16 is made of an organic material, its anti-permeability is not as good as that of an inorganic material, and water vapor can easily penetrate into the display panel through the organic medium layer 16 and make a device such as a driving TFT ineffective.
  • the groove 163 located at the boundary between the display area and the non-display area of the flexible substrate 10 can prevent the failure of the device caused by the moisture transmitted into the display area through organic substances.
  • Step S8 forming a source electrode 171 and a drain electrode 172 on the organic dielectric layer 16.
  • a method for forming the source electrode 171 and the drain electrode 172 includes: depositing a metal layer forming the source electrode 171 and the drain electrode 172 on the organic dielectric layer 16 by using a physical vapor deposition method, and then applying a metal layer to the metal layer Graphic processing is performed to obtain a source electrode 171 and a drain electrode 172 as shown in FIG. 8.
  • the source electrode 171 is in contact with the flexible substrate 10 through the third contact hole 161 and the first contact hole 151 shown in FIG. 7, and the drain electrode 172 is contacted with the flexible substrate 10 through FIG. 7.
  • the fourth contact hole 162 and the second contact hole 152 are shown in contact with the flexible substrate 10.
  • Step 9 A flat layer 18 is formed on the source electrode 171 and the drain electrode 172, an anode 181 is formed on the flat layer 18, and a pixel defining layer 19 is formed on the anode 181.
  • the flat layer 18 forms a second groove 182 at a position corresponding to the first groove 163, and the pixel defining layer 19 forms a second groove 182.
  • a third groove 191 is formed at the position of the groove 181 to expose the flexible substrate 10.
  • a via hole 183 is formed on the flat layer 18, and the via hole 183 corresponds to the drain electrode 172 shown in FIG. 8, so that the anode 181 and the drain electrode 172 pass through the via hole 183. Phase contact.
  • a blank area 192 is formed on the pixel defining layer 19 at a position corresponding to the anode 181 to expose the anode 181.
  • Step 10 As shown in FIG. 10, at least one spacer 20 is further formed on the pixel defining layer 19, and the spacer 20 is used to support a box thickness of the OLED display panel.
  • the anode 181 also has a light-emitting layer 30 required for an OLED device.
  • the present application also provides a display panel including a first region and a second region.
  • the display panel includes: a flexible substrate; a first layer disposed on the flexible substrate; The first layer is located on the first region; the second layer is provided on the flexible substrate; the second layer is located on the first region; and The inorganic insulating layer between the second layers; wherein the inorganic insulating layer is located on the first region and not on the second region.
  • the first region and the second region may not only be disposed on the array substrate, but may also be located in other structures of the display panel. This can improve the flexibility of the display panel.
  • the present application also provides a display, which includes the above-mentioned array substrate, or includes an OLED, QLED, LED, and Micro LED display panel made from the above-mentioned array substrate.
  • the present application further provides an electronic device including the above-mentioned array substrate or the above-mentioned display panel.
  • the electronic device includes, for example, but is not limited to, a mobile phone, a smart phone, a notebook computer, a digital broadcast receiver, a PDA (Personal Digital Assistant), a PAD (Tablet Computer), a PMP (Portable Multimedia Player), a navigation device, and the like. Terminal device.
  • the first contact hole and the second contact hole are formed by a photomask, which saves the number of photomasks in the manufacturing process and simplifies the manufacturing process.
  • the structure of the inorganic insulating layer of the buffer layer, the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer, which play an insulating role, is adjusted.
  • the inorganic insulating layer Only the parts of the inorganic insulating layer that play an insulating role are retained, and the remaining parts are all etched to remove the inorganic insulating layers (including the buffer layer, the All non-essential parts of the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer (that is, not in contact with the active layer, patterning the first metal layer, etc.) do not have an insulating effect. Part of the display panel), thereby minimizing the inorganic insulating layer in the curved portion (display area) of the display panel, and effectively preventing the inorganic material from cracking when the display panel is folded.
  • a groove is formed on the organic medium layer, the flat layer, and the pixel defining layer at a boundary between a display area and a non-display area of the flexible substrate, so as to expose all
  • the flexible substrate prevents the failure of the device caused by the moisture transmitted into the display area through the organic matter.

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Abstract

一种阵列基板，具有一显示区(101)及一非显示区(102)，包括：一柔性衬底(10)，设于所述柔性衬底(10)之上并且位于所述显示区(101)上的一有源层(12)，设于所述柔性衬底(10)之上并且位于所述显示区(101)上的一第一栅极(131)，一无机的第一栅极绝缘层(13)，所述第一栅极绝缘层(13)设于所述有源层(12)与所述第一栅极(131)之间，并且位于所述显示区(101)上而不位于所述非显示区(102)上。该阵列基板去除了无机绝缘层中所有不起到绝缘作用的部分，从而有效地防止了显示面板在折叠时发生的无机物碎裂。

Description

一种阵列基板及显示面板 技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板及显示面板，以及该阵列基板的制造方法、显示器及电子装置。
 背景技术
近年来，有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板成为国内外非常热门的新兴平面显示装置产品，这是因为OLED显示装置具有自发光、广视角、短反应时间、高发光效率、广色域、低工作电压、薄厚度、可制作大尺寸与可挠曲的面板及制程简单等特性，而且它还具有低成本的潜力。
 技术问题
现有柔性OLED中，无机绝缘层（例如第一栅绝缘层、第二栅绝缘层、层间绝缘层）一般全面覆盖柔性衬底，因而在显示面板进行折叠时易发生无机物碎裂，而导致器件失效。
因此，有必要提供一种新的阵列基板及应用该阵列基板的显示面板、显示面板的制造方法、显示器及电子装置，以克服上述缺陷。
 技术解决方案
在本申请的阵列基板中，去除了所述无机绝缘层（包括缓冲层、第一栅极绝缘层、第二栅极绝缘层及层间绝缘层）中所有不起到绝缘作用的部分而仅保留起到绝缘作用的必要部分，从而有效地防止了具有所述阵列基板的一显示面板在折叠时发生的无机物碎裂，以增加显示面板的柔软性。
为了达到上述目的，本申请首先提供一阵列基板，具有一第一区和一第二区。所述阵列基板包括：一柔性衬底；一第一层，所述第一层设于所述柔性衬底之上并且位于所述第一区上；一第二层，所述第二层设于所述柔性衬底之上并且位于所述第一区上；以及，一无机绝缘层，所述无机绝缘层设于所述第一层与所述第二层之间，并且位于所述第一区上而不位于所述第二区上；其中，所述第一层与所述第二层之中有一层是一金属层；所述第一层包括一有源层；所述第二层包括一第一栅极；并且，所述无机绝缘层包括设于所述有源层和所述第一栅极的一第一栅极绝缘层。
在一实施例中，所述第一层还包括一第二栅极，所述无机绝缘层还包括设于所述第一栅极和所述第二栅极之间的一第二栅极绝缘层。
在一实施例中，所述阵列基板还包括一有机介质层，所述有机介质层包括位于所述第二区的一第一部分和位于所述无机绝缘层上的一第二部分。
在一实施例中，所述第二层还包括源/漏极，所述源/漏极穿过所述第一栅极绝缘层和所述第二栅极绝缘层并连接于所述有源层；所述无机绝缘层还包括设于所述第二栅极和所述源/漏极之间的一层间绝缘层，所述有机介质层的第二部分位于所述源/漏极与所述层间绝缘层之间。
在一实施例中，所述第二区包括对应于一显示面板的非显示区的弯曲部分，所述第一区包括对应于所述显示面板的显示区并邻近所述弯曲部分的功能部分，所述阵列基板上设有邻近所述弯曲部分和所述显示部分的交界处的凹槽，所述凹槽贯穿所述有机介质层并暴露所述第一栅极绝缘层、所述第二栅极绝缘层和所述层间绝缘层。
在一实施例中，所述阵列基板还包括位于所述柔性衬底与所述有源层之间的一缓冲层，所述源/漏极贯穿所述有源层和所述缓冲层。
在一实施例中，所述阵列基板包括对应于一显示面板的显示区的功能区，所述功能区包括所述第一区和所述第二区。
本申请还提供一阵列基板，具有一第一区和一第二区。所述阵列基板包括：一柔性衬底；设于所述柔性衬底之上的一第一层，所述第一层位于所述第一区上；设于所述柔性衬底之上的一第二层，所述第二层位于所述第一区上；以及，设于所述第一层和所述第二层之间的一无机绝缘层；其中，所述无机绝缘层位于所述第一区上，而不位于所述第二区上。
在一实施例中，所述阵列基板还包括一有机介质层，所述有机介质层包括位于所述第二区的一第一部分。
在一实施例中，所述有机介质层还包括位于所述无机绝缘层上的一第二部分。
在一实施例中，所述第一层与所述第二层之中有一层是一金属层。
在一实施例中，所述第一层包括一有源层，所述第二层包括一第一栅极，所述无机绝缘层包括设于所述有源层和所述第一栅极的一第一栅极绝缘层。
在一实施例中，所述第一层还包括第二栅极，所述无机绝缘层还包括设于所述第一栅极和所述第二栅极之间的一第二栅极绝缘层。
在一实施例中，所述第二层还包括源/漏极，所述源/漏极穿过所述第一栅极绝缘层和所述第二栅极绝缘层并连接于所述有源层，所述无机绝缘层还包括设于所述第二栅极和所述源/漏极之间的一层间绝缘层，所述有机介质层的第二部分位于所述源/漏极与所述层间绝缘层之间。
在本申请一实施例中，所述第二区包括对应于一显示面板的一非显示区的一弯曲部分，所述第一区包括对应于所述显示面板的一显示区并邻近所述弯曲部分的一功能部分，所述阵列基板上设有邻近所述弯曲部分和所述显示部分的交界处的一凹槽，所述凹槽贯穿所述有机介质层并暴露所述第一栅极绝缘层、所述第二栅极绝缘层和所述层间绝缘层。
在本申请一实施例中，所述阵列基板还包括位于所述柔性衬底与所述有源层之间的一缓冲层，所述源/漏极贯穿所述有源层和所述缓冲层。
在本申请一实施例中，所述阵列基板包括对应于一显示面板的一显示区的一功能区，所述功能区包括所述第一区和所述第二区。
本申请还提供一显示面板的制造方法，所述显示面板包括上述的阵列基板。所述阵列基板包括一第一区和一第二区，所述制造方法包括：
S1: 提供一柔性衬底和设于所述柔性衬底之上的一第一层，所述第一层位于所述第一区上；
提供设于所述柔性衬底之上的一第二层，所述第二层位于所述第一区上；
S2：在所述柔性衬底上形成一有源层，所述有源层位于所述第一区上；
S3：在所述有源层上形成一第一栅极绝缘层，所述第一栅极绝缘层位于所述第一区上而不位于所述第二区上；
S4：在所述第一栅极绝缘层上形成一第一栅极，所述第一栅极位于所述第一区上；
S5：在所述第一栅极上形成一第二栅极绝缘层，所述第二栅极绝缘层位于所述第一区上而不位于所述第二区上；
S6：在所述第二栅极绝缘层上形成一第二栅极，所述第二栅极位于所述第一区上；
S7：在所述第二栅极上形成一层间绝缘层，所述层间绝缘层位于所述第一区上而不位于所述第二区上；
S8：在所述层间绝缘层上形成一有机介质层，所述有机介质层包括位于所述第二区的第一部分和位于所述层间绝缘层上的第二部分；以及，
S9：在所述有机介质层上形成源/漏极，所述源/漏极穿过所述第一栅极绝缘层和所述第二栅极绝缘层并连接于所述有源层，并且，所述源/漏极位于所述有机介质层的第二部分之上；
其中，所述第二区包括对应于一显示面板的一非显示区的一弯曲部分，所述第一区包括对应于所述显示面板的一显示区并邻近所述弯曲部分的一功能部分，所述阵列基板上设有邻近所述弯曲部分和所述显示部分的交界处的一凹槽，所述凹槽贯穿所述有机介质层并暴露所述第一栅极绝缘层、所述第二栅极绝缘层和所述层间绝缘层。
本申请还提供一种显示面板，所述显示面板包括一第一区和一第二区，所述显示面板包括：一柔性衬底；设于所述柔性衬底之上的一第一层，所述第一层位于所述第一区上；设于所述柔性衬底之上的一第二层，所述第二层位于所述第一区上；以及，设于所述第一层和所述第二层之间的一无机绝缘层；其中，所述无机绝缘层位于所述第一区上，而不位于所述第二区上。
本申请还提供一种显示面板，所述显示面板包括一上述的阵列基板，或者，由上述制造方法制造的一阵列基板。所述显示面板包括但不限于OLED、QLED、LED、Micro LED等。为便于说明，本说明书中以OLED为例进行详细说明。本领域技术人员应当理解的是，本申请所述的阵列基板在应用于其他类型(例如LED、Micro LED)的显示面板时，在所述阵列基板上形成该显示面板的其他相应结构即可。也就是说，本申请还提供一种上述阵列基板在显示面板中的应用，该显示面板例如但不限于OLED、QLED、LED、Micro LED。
本申请还提供一种显示器，所述显示器包括一上述的阵列基板，或者，包括一上述的显示面板。
本申请还提供一种电子装置，所述电子装置包括一上述的阵列基板，或者，包括一上述的显示面板。所述电子装置为一具有一显示面板的终端装置，例如但不限于移动电话、智能电话、笔记本电脑、数字广播接收器、PDA(个人数字助理)、PAD（平板电脑）、PMP(便携式多媒体播放器)、导航装置等。
在本申请中，定义术语“第一区”为需要所述无机绝缘层进行绝缘的区域，定义术语“第二区”为可以不需要所述无机绝缘层的区域。
例如，当本申请的所述阵列基板具有至少以下结构时：依次形成于柔性衬底上的一有源层、一第一栅极绝缘层、一第一栅极、一层间绝缘层、一有机介质层和源/漏极，所述第一区为：所述第一栅极绝缘层中覆盖且仅覆盖所述有源层的区域、所述层间绝缘层中覆盖且仅覆盖所述第一栅极（当然也包括与所述第一栅极一并形成的位于非显示区的栅极线及栅极焊盘部分）的区域。而所述第二区则为所述第一栅极绝缘层与所述层间绝缘层除去所述第一区之外的全部区域。当本申请的所述阵列基板具有双栅极结构是，即，所述阵列基板具有至少以下结构时：依次形成于柔性衬底上的一有源层、一第一栅极绝缘层、一第一栅极、一第二栅极绝缘层、一第二栅极、一层间绝缘层、一有机介质层和源/漏极，所述第一区为：所述第一栅极绝缘层中覆盖且仅覆盖所述有源层的区域、所述第二栅极绝缘层中覆盖且仅覆盖所述第一栅极（当然也包括与所述第一栅极一并形成的位于非显示区的栅极线及栅极焊盘部分）的区域、所述层间绝缘层中覆盖且仅覆盖所述第二栅极（当然也包括与所述第二栅极一并形成的位于非显示区的栅极线及栅极焊盘部分）。而所述第二区则为所述第一栅极绝缘层、所述第二栅极绝缘层及所述层间绝缘层中除去所述第一区之外的全部区域。
当然，所述无机绝缘层还包括形成于所述有源层与柔性衬底之间的一缓冲层。所述缓冲层也位于所述第一区。即，所述缓冲层仅设置于所述有源层与所述柔性衬底之间。
本申请还提供一种阵列基板，包括：一柔性衬底，所述柔性衬底包括一弯曲部分和一功能部分；至少一图案化的功能层，所述图案化的功能层设置于所述柔性衬底之上；以及，一无机绝缘层，所述无机绝缘层设置于所述图案化的功能层之上；其中，所述无机绝缘层的图案与所述图案化的功能层的图案相对应。
需要说明的是，“所述无机绝缘层的图案与所述图案化的功能层的图案相对应”的表述是指：所述无机绝缘层仅覆盖所述图案化的功能层，即所述无机绝缘层的图案与所述图案化的功能层的图案完全相同且空间上完全重叠，当然，工程上的误差是不可避免的。
在本申请一实施例中，所述图案化的功能层为一有源层，一第一图案化金属层或一第二图案化金属层。本领域技术人员可以理解的是，所述第一图案化金属层包括：位于显示面板显示区域内的复数个第一栅极、位于显示面板非显示区域内的复数个栅极焊盘，以及连接所述第一栅极与所述栅极焊盘的栅极线。类似的，所述第二图案化金属层包括：位于显示面板显示区域内的复数个第二栅极、位于显示面板非显示区域内的复数个栅极焊盘，以及连接所述第二栅极与所述栅极焊盘的栅极线。
在本申请一实施例中，所述阵列基板还包括一有机介质层，所述有机介质层设置于所述无机绝缘层上，并完全覆盖所述柔性衬底；其中，所述有机介质层在所述弯曲部分和所述功能部分的交界处形成一凹槽，所述凹槽贯穿所述有机介质层以暴露所述柔性衬底。
在本申请一实施例中，所述阵列基板还包括一第三图案化金属层，所述第三图案化金属层包含复数个源极和复数个漏极。本领域技术人员可以理解的是，所述第三图案化金属层包括位于显示面板显示区域内的复数个源极和复数个漏极，以及位于非显示区域内的扫描线及其他走线。
在本申请一实施例中，所述阵列基板还包括一缓冲层，所述缓冲层设置于柔性衬底之上并与所述柔性衬底接触，其中，所述缓冲层的图案与所述图案化的功能层的图案相对应。
也就是说，在上述阵列基板中，在且仅在所述有源层、第一栅极(和/或第二栅极)及其走线、源/漏极及其走线上形成无机绝缘层，以进行绝缘。
本申请还提供上述阵列基板的制造方法，包括：S1: 提供一柔性衬底，所述柔性衬底包括一弯曲部分和一功能部分；S2: 在所述柔性衬底上形成一图案化的功能层；以及，S3: 在所述图案化的功能层上形成一无机绝缘层，图案化所述无机绝缘层，以使所述无机绝缘层的图案与所述图案化的功能层的图案相对应，并去除所述无机绝缘层的其余部分。
所述制造方法还包括：S4: 形成一全面覆盖的有机介质层，使得有机介质层位于所述无机绝缘层之上并接触所述柔性衬底；图案化所述有机介质层，以使所述有机介质层在所述弯曲部分和所述功能部分的交界处形成一凹槽，所述凹槽贯穿所述有机介质层以暴露所述柔性衬底。
所述制造方法还包括：S5: 在所述有机介质层上形成一第三图案化金属层，所述第三图案化金属层包含复数个源极和复数个漏极。
所述制造方法还包括：所述制造方法在所述S1与所述S2之间还包括：S1-2：在所述柔性衬底之上形成一缓冲层，图案化所述缓冲层以使所述缓冲层的图案与所述图案化的功能层的图案相对应。
在本申请一实施例中，所述柔性衬底由聚酰亚胺制成。
本领域技术人员可以理解的是，在本申请中，以本领域已知的方式形成各层。例如，在本申请一实施例中，在缓冲层上形成一有源层的方法是：在缓冲层上沉积非晶硅层，并对非晶硅层进行分子激光退火处理，使得该非晶硅层结晶后转变为多晶硅层，并通过黄光、蚀刻制程对该多晶硅层进行图案化处理以形成多晶硅段，接着通过沉积、黄光、蚀刻制程在多晶硅段两端形成所述源极接触区及所述漏极接触区。形成所述第一栅极和第二栅极的材料可以是本领域中形成栅极的常规金属材料。形成所述无机绝缘层的材料可以是本领域中形成栅极绝缘层（或屏障栅极）的常规无机材料，例如金属氧化物（诸如氧化硅、氧化铝、氧化锡、氧化锌、氧化铟锡、氧化铟锌、氧化铝锌等）、金属氮化物（诸如氮化硅、氮化铝、氮化硼）、金属氮氧化物（诸如氮氧化铝、氮氧化硅、氮氧化硼）、金属碳化物（诸如碳化钨、碳化硼、碳化硅）、金属硼氧化物（诸如硼氧化锆、硼氧化钛等）和其组合。
 有益效果
在本申请中，以一道光罩形成一第一接触孔及一第二接触孔，节省了制程中的光罩数量并简化了制程。此外，在本申请中，对起到绝缘作用的所述缓冲层、所述第一栅极绝缘层、所述第二栅极绝缘层及所述层间绝缘层的无机绝缘层结构进行调整，只保留该些无机绝缘层中起到绝缘作用的部分，而将其余部分全部蚀刻，以去除在所述柔性衬底显示区与非显示区内无机绝缘层（包括所述缓冲层、所述第一栅极绝缘层、所述第二栅极绝缘层及所述层间绝缘层）的所有非必要部分（即不接触所述有源层、图案化第一金属层等不起到绝缘作用的部分），从而最大程度地降低了显示面板弯曲部分（显示区）内的无机绝缘层，有效地防止了所述显示面板在折叠时发生的无机物碎裂。再者，在本申请中，通过在所述有机介质层、所述平坦层及所述像素界定层上位于所述柔性衬底的显示区与非显示区的交界处形成凹槽，以暴露所述柔性衬底，进而防止了水分通过有机物传输进入显示区所造成的器件失效。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请所述显示面板的结构示意图；
图2是本申请所述显示面板的制造方法的步骤1的示意图；
图3是本申请所述显示面板的制造方法的步骤2的示意图；
图4A和图4B是本申请所述显示面板的制造方法的步骤3的示意图；
图5是本申请所述显示面板的制造方法的步骤4的示意图；
图6是本申请所述显示面板的制造方法的步骤5的示意图；
图7是本申请所述显示面板的制造方法的步骤7的示意图；
图8是本申请所述显示面板的制造方法的步骤8的示意图；
图9是本申请所述显示面板的制造方法的步骤9的示意图；
图10是本申请所述显示面板的制造方法的步骤10的示意图。
 本发明的最佳实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
在本实施例中，首先提供一种显示面板，应用了本申请所述的阵列基板。在本实施例中，以OLED显示面板为例进行说明。当然，本领域技术人员可以理解的是，本申请所述的阵列基板也可以适用于其他类型的显示面板，例如但不限于OLED、QLED、LED、Micro LED，应用时在所述阵列基板上形成相应显示面板的其他结构即可。
所述显示面板结构如图1所示。如图1所示的，所述显示面板具有一柔性衬底10，所述柔性衬底10包括一显示区101及一非显示区102。如图1所示的，所述显示面板包括：设于所述柔性衬底显示区内101的缓冲层11，以及一设于所述缓冲层11上的一有源层12；一第一栅极绝缘层13及设置于所述第一栅极绝缘层上的一第一栅极131；一第二栅极绝缘层14及设置于所述第二栅极绝缘层14上的一第二栅极141；一设于所述第二栅极141上的层间绝缘层15；一设于所述层间绝缘层15上的有机介质层16；设于所述有机介质层16上的一源极171和一漏极172；覆盖所述源极171及所述漏极172的平坦层；设置于所述平坦层18上的一阳极181；一设于所述阳极18上的像素界定层19；形成于所述像素界定层19上的隔垫物20；以及设于在所述阳极181上的一OLED器件所需的发光层30。
所述隔垫物20用于支撑OLED显示面板的盒厚。所述柔性衬底10由聚酰亚胺（PI）制成。
如图1所示的，在本实施例所述的显示面板中，去除了所述柔性衬底10中无机绝缘层（包括所述缓冲层11、所述第一栅极绝缘层13、所述第二栅极绝缘层14及所述层间绝缘层15）中所有不起到绝缘作用的部分（即第二区），而仅保留起到绝缘作用的部分（即第一区），从而有效地防止了所述显示面板在折叠时发生的无机物碎裂。也就是说，本实施例中，在如图1中显示区域内，仅在第一区保留与所述有源层、第一栅极及第二栅极对应的起到绝缘作用的无机绝缘层（所述第一栅极绝缘层13、所述第二栅极绝缘层14及所述层间绝缘层15），其余部分（即第二区）的无机绝缘层全部去除。
以下结合图2至图10详细介绍所述显示面板的制造方法。
本实施例所述显示面板的制造方法具体包括以下步骤。
步骤S1：提供一柔性衬底10，如图2所示的，所述柔性衬底10包括一显示区101和一非显示区102；在所述柔性衬底10上形成一缓冲层11。所述缓冲层11可以以已知的方式形成，例如采用化学气相沉积法形成。并且，所述缓冲层11的组分为已知组分。
步骤S2：在所述缓冲层上形成一多晶硅层(图中未示出)，对所述多晶硅层及所述缓冲层11进行图形化处理，以获得如图3所示的一有源层12并只保留所述缓冲层11与所述有源层12相对应的部分。如图3所示的，所述缓冲层11的其余部分均被去除，使得所述柔性衬底10在除了所述有源层11以外的其余部分全部暴露。如图3所示的，所述有源层12包括一源极接触区121、一漏极接触区122和一位于所述源极接触区121与所述漏极接触区122之间的一沟道区123。本领域技术人员可以理解的是，在缓冲层11上形成有源层12是在缓冲层11上沉积一非晶硅层，并对非晶硅层进行分子激光退火处理，使得该非晶硅层结晶后转变为所述多晶硅层，并通过黄光、蚀刻制程对该多晶硅层进行图案化处理以形成多晶硅段，接着通过沉积、黄光、蚀刻制程在多晶硅段两端形成所述源极接触区121及所述漏极接触区122。
步骤S3：如图4A所示的，首先在所述有源层12形成所述第一栅极绝缘层13并在第一栅极绝缘层13上形成所述第一栅极131；接着如图4B所示的，在所述第一栅极131上形成所述第二栅极绝缘层14并在所述第二栅极绝缘层14上形成所述第二栅极141。如图4A和6B所示的，所述第一栅极绝缘层13覆盖所述有源层12及所述柔性衬底10，所述第一栅极131位于所述有源层12的上方，所述第二栅极绝缘层14覆盖所述第一栅极131及所述第一栅极绝缘层13，所述第二栅极141位于所述第一栅极131上方。
步骤S4：在所述第二栅极141上形成一层间绝缘层15，如图5所示的，所述层间绝缘层15覆盖所述第二栅极141及所述第二栅极绝缘层14。所述层间绝缘层15可以以已知的方式形成，例如采用化学气相沉积法形成。并且，所述层间绝缘层15的组分为已知组分。
步骤S5：以一道光罩对所述层间绝缘层15、所述第二栅极绝缘层14及所述第一绝缘层13进行蚀刻，以形成如图6所示的一第一接触孔151和一第二接触孔152，并且如图6所示的，在本步骤中，将“需要无机绝缘层进行绝缘的区域”定义为第一区，将“可以不需要无机绝缘层的区域”定义为第二区，其中所述第一区和第二区的划分，是在俯视视角下进行的。例如，在正视视角下，如图6中，第一区包括图6中恰巧覆盖所述有源层12、第一栅极131、第二栅极141的第一栅极绝缘层13、第二栅极绝缘层14及层间绝缘层15所在的部分，第二区包括位于该部分的左侧及右侧的其他的部分。通过所述以一道光罩对所述层间绝缘层15、所述第一栅极绝缘层13及所述第二栅极绝缘层14进行蚀刻，以保留如图6所示的第一区。
本领域技术人员可以理解的是，图6中所述第一栅极绝缘层13、第二栅极绝缘层14及层间绝缘层15的宽度保持一致，且略宽于所述有源层12的宽度。这是因为采用了一道光罩进行蚀刻而造成的。这种宽度的设计不会对获得本申请所述技术效果造成影响。然而，本领域技术人员可以理解的是，也可以通过多道光罩分别对所述第一栅极绝缘层13、第二栅极绝缘层14及层间绝缘层15进行蚀刻，以使得所述第一栅极绝缘层13覆盖且仅覆盖所述有源层12、所述第二栅极绝缘层14覆盖且仅覆盖所述第一栅极131（当然也包括与所述第一栅极131共同形成的栅极线及焊盘）、所述层间绝缘层覆盖且仅覆盖所述第二栅极141（当然也包括与所述第二栅极141共同形成的栅极线及焊盘）。
如图6所示的，所述第一接触孔151贯穿所述层间绝缘层15、第二栅极绝缘层14、第一栅极绝缘层13、所述有源层12的所述源极接触区及所述缓冲层11以暴露所述柔性衬底10；所述第二接触孔152贯穿所述层间绝缘层15、第二栅极绝缘层14、第一栅极绝缘层13、所述有源层12的所述漏极接触区及所述缓冲层11以暴露所述柔性衬底10。
步骤S6：在所述层间绝缘层15上形成一有机介质层16，使所述有机介质层16覆盖所述层间绝缘层15及所述柔性衬底10的非显示区102。所述有机介质层16可以以已知的方式形成，例如采用化学气相沉积法形成。
步骤S7：以一道光对所述有机介质层16进行蚀刻，以形成如图7所示的一第三接触孔161、一第四接触孔162和一第一凹槽163。如图7所示的，所述第三接触孔161对应于所述第一接触孔151，所述第四接触孔162对应于所述第二接触孔152，所述第一凹槽163设置于所述柔性衬底10的显示区101与非显示区102的交界处，以暴露所述柔性衬底10。由于所述有机介质层16由有机材料制成，其防渗透性不如无机材质，水汽很容易通过所述有机介质层16而渗入到显示面板内，使诸如驱动TFT的器件失效。而位于所述柔性衬底10的显示区与非显示区的交界处的凹槽163则可以防止水分通过有机物传输进入显示区所造成的器件失效。
步骤S8：在所述有机介质层16上形成一源极171和一漏极172。形成所述源极171与所述漏极172的方法包括：采用物理气相沉积法在所述有机介质层16上沉积形成所述源极171与漏极172的金属层，随后对所述金属层进行图形化处理，以获得如图8所示的源极171和漏极172。如图7及图8所示的，所述源极171通过图7中所示第三接触孔161及第一接触孔151与所述柔性衬底10接触，所述漏极172通过图7中所示第四接触孔162及第二接触孔152与所述柔性衬底10接触。
步骤9：在所述源极171和所述漏极172上形成一平坦层18，在所述平坦层18上形成一阳极181并在所述阳极181上形成一像素界定层19。如图8及图9所示的，所述平坦层18在对应于所述第一凹槽163的位置上形成一第二凹槽182，所述像素界定层19在对应于所述第二凹槽181的位置上形成一第三凹槽191，以暴露所述柔性衬底10。在所述平坦层18上形成一过孔183，所述过孔183对应于图8中所示的所述漏极172，以使所述阳极181经由所述过孔183与所述漏极172相接触。并且，如图9所示的，在所述像素界定层19上对应于所述阳极181的位置上形成一空白区192，以暴露所述阳极181。
步骤10：如图10所示的，在所述像素界定层19上还形成至少一隔垫物20，所述隔垫物20用于支撑OLED显示面板的盒厚。当然，在所述阳极181上还具有一OLED器件所需的发光层30。
本申请还提供一种显示面板，所述显示面板包括一第一区和一第二区，所述显示面板包括：一柔性衬底；设于所述柔性衬底之上的第一层，所述第一层位于所述第一区上；设于所述柔性衬底之上的第二层，所述第二层位于所述第一区上；以及，设于所述第一层和所述第二层之间的无机绝缘层；其中，所述无机绝缘层位于所述第一区上，而不位于所述第二区上。在本实施例中，第一区和第二区可以不仅仅设置在阵列基板上，还可以位于显示面板的其他结构中。这样可以改善显示面板的柔性性能。
本申请还提供一种显示器，所述显示器包括上述的阵列基板，或者包含以上述阵列基板制得的OLED、QLED、LED、Micro LED显示面板。
本申请还提供一种电子装置，所述电子装置包括上述的阵列基板，或者，包括上述的显示面板。所述电子装置例如但不限于移动电话、智能电话、笔记本电脑、数字广播接收器、PDA(个人数字助理)、PAD（平板电脑）、PMP(便携式多媒体播放器)、导航装置等具有显示面板的终端装置。
在本申请中，以一道光罩形成所述第一接触孔及所述第二接触孔，节省了制程中的光罩数量并简化了制程。此外，在本申请中，对起到绝缘作用的所述缓冲层、所述第一栅极绝缘层、所述第二栅极绝缘层及所述层间绝缘层的无机绝缘层结构进行调整，只保留该些无机绝缘层中起到绝缘作用的部分，而将其余部分全部蚀刻，以去除在所述柔性衬底显示区与非显示区内的无机绝缘层（包括所述缓冲层、所述第一栅极绝缘层、所述第二栅极绝缘层及所述层间绝缘层）的所有非必要部分（即不接触所述有源层、图案化第一金属层等不起到绝缘作用的部分），从而最大程度地降低了显示面板弯曲部分（显示区）内的无机绝缘层，有效地防止了所述显示面板在折叠时发生的无机物碎裂。再者，在本申请中，通过在所述有机介质层、所述平坦层及所述像素界定层上位于所述柔性衬底的显示区与非显示区的交界处形成凹槽，以暴露所述柔性衬底，进而防止了水分通过有机物传输进入显示区所造成的器件失效。
本申请已由上述相关实施例加以描述，然而上述实施例仅为实施本申请的范例。必需指出的是，已公开的实施例并未限制本申请的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本申请的范围内。

Claims (20)

  1. 一种阵列基板，具有一第一区和一第二区，包括：
    一柔性衬底；
    一第一层，所述第一层设于所述柔性衬底之上并且位于所述第一区上；
    一第二层，所述第二层设于所述柔性衬底之上并且位于所述第一区上；以及，
    一无机绝缘层，所述无机绝缘层设于所述第一层与所述第二层之间，并且位于所述第一区上而不位于所述第二区上；
    其中，所述第一层与所述第二层之中有一层是一金属层；
    所述第一层包括一有源层；
    所述第二层包括一第一栅极；并且，
    所述无机绝缘层包括设于所述有源层和所述第一栅极的一第一栅极绝缘层。
  2. 如权利要求1所述的阵列基板，其中，所述第一层还包括一第二栅极，所述无机绝缘层还包括设于所述第一栅极和所述第二栅极之间的一第二栅极绝缘层。
  3. 如权利要求2所述的阵列基板，其中，所述阵列基板还包括一有机介质层，所述有机介质层包括位于所述第二区的一第一部分和位于所述无机绝缘层上的一第二部分。
  4. 如权利要求3所述的阵列基板，其中，所述第二层还包括源/漏极，所述源/漏极穿过所述第一栅极绝缘层和所述第二栅极绝缘层并连接于所述有源层；
    所述无机绝缘层还包括设于所述第二栅极和所述源/漏极之间的一层间绝缘层，所述有机介质层的第二部分位于所述源/漏极与所述层间绝缘层之间。
  5. 如权利要求4所述的阵列基板，其中，所述第二区包括对应于一显示面板的非显示区的弯曲部分，所述第一区包括对应于所述显示面板的显示区并邻近所述弯曲部分的功能部分，所述阵列基板上设有邻近所述弯曲部分和所述显示部分的交界处的凹槽，所述凹槽贯穿所述有机介质层并暴露所述第一栅极绝缘层、所述第二栅极绝缘层和所述层间绝缘层。
  6. 如权利要求5所述的阵列基板，其中，所述阵列基板还包括位于所述柔性衬底与所述有源层之间的一缓冲层，所述源/漏极贯穿所述有源层和所述缓冲层。
  7. 如权利要求1所述的阵列基板，其中，所述阵列基板包括对应于一显示面板的显示区的功能区，所述功能区包括所述第一区和所述第二区。
  8. 一种阵列基板，所述阵列基板包括一第一区和一第二区，其中，所述阵列基板还包括：
    一柔性衬底；
    设于所述柔性衬底之上的以第一层，所述第一层位于所述第一区上；
    设于所述柔性衬底之上的一第二层，所述第二层位于所述第一区上；以及，
    设于所述第一层和所述第二层之间的一无机绝缘层，所述无机绝缘层位于所述第一区上，而不位于所述第二区上。
  9. 如权利要求8所述的阵列基板，其中，所述阵列基板还包括一有机介质层，所述有机介质层包括位于所述第二区的第一部分。
  10. 如权利要求9所述的阵列基板，其中，所述有机介质层还包括位于所述无机绝缘层上的第二部分。
  11. 如权利要求10所述的阵列基板，其中，所述第一层与所述第二层之中有一层是一金属层。
  12. 如权利要求10所述的阵列基板，其中，所述第一层包括一有源层，所述第二层包括一第一栅极，所述无机绝缘层包括设于所述有源层和所述第一栅极的第一栅极绝缘层。
  13. 如权利要求12所述的阵列基板，其中，所述第一层还包括第二栅极，所述无机绝缘层还包括设于所述第一栅极和所述第二栅极之间的第二栅极绝缘层。
  14. 如权利要求13所述的阵列基板，其中，所述第二层还包括源/漏极，所述源/漏极穿过所述第一栅极绝缘层和所述第二栅极绝缘层并连接于所述有源层，所述无机绝缘层还包括设于所述第二栅极和所述源/漏极之间的层间绝缘层，所述有机介质层的第二部分位于所述源/漏极与所述层间绝缘层之间。
  15. 如权利要求14所述的阵列基板，其中，所述第二区包括对应于一显示面板的非显示区的弯曲部分，所述第一区包括对应于所述显示面板的显示区并邻近所述弯曲部分的功能部分，所述阵列基板上设有邻近所述弯曲部分和所述显示部分的交界处的凹槽，所述凹槽贯穿所述有机介质层并暴露所述第一栅极绝缘层、所述第二栅极绝缘层和所述层间绝缘层。
  16. 如权利要求14所述的阵列基板，其中，所述阵列基板还包括位于所述柔性衬底与所述有源层之间的缓冲层，所述源/漏极贯穿所述有源层和所述缓冲层。
  17. 如权利要求8所述的阵列基板，其中，所述阵列基板包括对应于一显示面板的显示区的功能区，所述功能区包括所述第一区和所述第二区。
  18. 一种显示面板，具有一第一区和一第二区，包括：
    一柔性衬底；
    设于所述柔性衬底之上的一第一层，所述第一层位于所述第一区上；
    设于所述柔性衬底之上的一第二层，所述第二层位于所述第一区上；以及，
    设于所述第一层和所述第二层之间的一无机绝缘层，所述无机绝缘层位于所述第一区上，而不位于所述第二区上；
    其中，所述第一层与所述第二层之中有一层是一金属层；
    所述第一层包括一有源层；
    所述第二层包括一第一栅极；并且，
    所述无机绝缘层包括设于所述有源层和所述第一栅极的一第一栅极绝缘层。
  19. 如权利要求18所述的显示面板，其中，所述第一层还包括一第二栅极，所述无机绝缘层还包括设于所述第一栅极和所述第二栅极之间的一第二栅极绝缘层。
  20. 如权利要求19所述的显示面板，其中，所述阵列基板还包括一有机介质层，所述有机介质层包括位于所述第二区的一第一部分和位于所述无机绝缘层上的一第二部分。
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