WO2019242213A1 - 显示面板及其应用的显示装置 - Google Patents

显示面板及其应用的显示装置 Download PDF

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Publication number
WO2019242213A1
WO2019242213A1 PCT/CN2018/115403 CN2018115403W WO2019242213A1 WO 2019242213 A1 WO2019242213 A1 WO 2019242213A1 CN 2018115403 W CN2018115403 W CN 2018115403W WO 2019242213 A1 WO2019242213 A1 WO 2019242213A1
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WO
WIPO (PCT)
Prior art keywords
area
layer
display panel
transmission line
wiring
Prior art date
Application number
PCT/CN2018/115403
Other languages
English (en)
French (fr)
Inventor
黄世帅
Original Assignee
惠科股份有限公司
重庆惠科金渝光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 惠科股份有限公司, 重庆惠科金渝光电科技有限公司 filed Critical 惠科股份有限公司
Priority to US16/313,096 priority Critical patent/US20190393247A1/en
Publication of WO2019242213A1 publication Critical patent/WO2019242213A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present application relates to the technical field of wiring of a display panel, and in particular, to a display panel and a display device to which the display panel is applied.
  • the display driving method includes: the system motherboard transmits color (for example: R / G / B / Red / Green / Blue / Green / Blue) compression signals, control signals, and power to the control board. After the signal is processed by the timing controller on the control board, it is transmitted to the source circuit and gate circuit of the printed circuit board. The necessary data and power are transmitted through the gate line, data line, power supply and other lines on the substrate.
  • the display area so that the display obtains the power and signals required to present the picture. At present, the borders of products on the market are getting narrower and narrower, and the space for routing in the fan-out area is becoming more and more limited.
  • the difference in length between the outermost trace and the middle trace becomes larger, the difference in resistance becomes larger, and impedance such as traces cannot be achieved.
  • the parasitic capacitance above the outermost trace and the middle trace will also be different.
  • the difference in the resistance and capacitance of the fanout area leads to the resistance and capacitance delay of the signal transmitted to the source line through the two traces. This delay can cause problems such as unequal fanout trace signals and signal delays.
  • the display panel is lit and displayed on the screen, there is also a problem of display differences in the uneven display area.
  • An object of the present application is to provide a display panel including, but not limited to, achieving a purpose of adjusting a phase shift signal delay of a fan-out trace.
  • a display panel including:
  • the first substrate includes a display area and a peripheral wiring area.
  • the wiring area has a fan-out area.
  • a plurality of signal lines are provided in the display area.
  • a plurality of active switches and a plurality of pixels are provided in the display area of the substrate.
  • a unit, the plurality of pixel units are respectively coupled to the plurality of active switches, and the plurality of active switches are respectively electrically coupled to the plurality of signal lines;
  • a driving unit disposed in the wiring area
  • a transmission line is disposed in the fan-out area, and the transmission line is electrically coupled between the driving unit and the plurality of signal lines;
  • An isolation layer disposed at a position of the second substrate relative to the fan-out area
  • an electrode layer is provided on the surface of the isolation layer, and when the electrode layer is electrically coupled to a common electrode voltage line, the electrode layer and the transmission line form a capacitance.
  • Another object of the present application is to provide a display panel including:
  • the first substrate includes a display area and a peripheral wiring area.
  • the wiring area has a fan-out area.
  • a plurality of signal lines are provided in the display area.
  • a plurality of active switches and a plurality of pixels are provided in the display area of the substrate.
  • a unit, the plurality of pixel units are respectively coupled to the plurality of active switches, and the plurality of active switches are respectively electrically coupled to the plurality of signal lines;
  • a second substrate opposite to the first substrate, and the second substrate is provided with an insulating layer
  • a driving unit disposed in the wiring area
  • a transmission line is disposed in the fan-out area, and the transmission line is electrically coupled between the driving unit and the plurality of signal lines, and the transmission line has wiring according to the shape setting of the fan-out area And a diagonal region, the wiring region is disposed between the diagonal region and the driving unit, and the diagonal region is routed in a narrow to wide manner toward the display region and connects the plurality of signal lines;
  • the electrode layer is disposed on the surface of the insulation layer, the electrode layer on the insulation layer forms a capacitance with the transmission line, and the insulation
  • the layer setting covers the fan-out area, the oblique line area, the oblique line area and a part of the wiring area, or the wiring area and a part of the oblique area;
  • the insulation layer includes a color resist layer With at least one of the black matrices.
  • Another object of the present application is to provide a display device including:
  • the first substrate includes a display area and a peripheral wiring area.
  • the wiring area has a fan-out area.
  • a plurality of signal lines are provided in the display area.
  • a plurality of active switches and a plurality of pixels are provided in the display area of the substrate.
  • a unit, the plurality of pixel units are respectively coupled to the plurality of active switches, and the plurality of active switches are respectively electrically coupled to the plurality of signal lines;
  • a second substrate opposite to the first substrate, and the second substrate is provided with an insulating layer
  • a driving unit is disposed in the wiring area;
  • a transmission line is disposed in the fan-out area, and the transmission line is electrically coupled between the driving unit and the plurality of signal lines;
  • the position of the insulation layer is relative to the position of the fan-out area
  • the electrode layer is disposed on the surface of the insulation layer
  • the electrode layer on the insulation layer forms a capacitor with the transmission line.
  • the display panel provided by the embodiment of the present application can make the phase shift signals of the traces have similar delays through the capacitance above the fan-out traces without substantially changing the existing production process, which can avoid the problem of unequal fan-out trace signals.
  • FIG. 1a is a schematic structural diagram of an exemplary display device
  • FIG. 1b is a schematic diagram of an exemplary pixel unit configuration
  • 1c is a schematic wiring diagram of a fan-out area of an exemplary display device
  • 2a is a schematic wiring diagram of a display panel according to an embodiment of the present application.
  • 2b is a schematic wiring diagram of a display panel according to an embodiment of the present application.
  • 3a is a schematic wiring diagram of a display panel according to another embodiment of the present application.
  • 3b is a schematic wiring diagram of a display panel according to another embodiment of the present application.
  • 3c is a schematic wiring diagram of a display panel according to another embodiment of the present application.
  • 3d is a schematic wiring diagram of a display panel according to another embodiment of the present application.
  • 4a is a schematic wiring diagram of a display panel according to another embodiment of the present application.
  • 4b is a schematic wiring diagram of a display panel according to another embodiment of the present application.
  • 5a is a schematic wiring diagram of a display panel according to another embodiment of the present application.
  • 5b is a schematic wiring diagram of a display panel according to another embodiment of the present application.
  • 5c is a schematic wiring diagram of a display panel according to another embodiment of the present application.
  • FIG. 5d is a schematic wiring diagram of a display panel according to another embodiment of the present application.
  • FIG. 6 is a schematic diagram of a transmission line wiring of a display panel according to another embodiment of the present application.
  • FIG. 1 a is a schematic structural diagram of an exemplary display device.
  • a display device 100 includes: a control board 101, which includes a timing module (TCON) 102; a printed circuit board 104, and a flexible flat cable (flexible flat cable) between the control board 101 and the control board 101 FFC) 103 are connected; the source driving unit 120 and the gate driving unit 130 are arranged in the wiring area, and are respectively connected to the source line 121 and the gate line 131 in the display area 111.
  • the gate driving unit 130 and the source driving unit 120 include, but are not limited to, a flip-chip thin film.
  • the driving method of the display device 100 includes: the system motherboard provides color (eg, R / G / B) compression signals, control signals, and power transmission to the control board 101.
  • the timing controller (TCON) 102 on the control board 101 and the processing of these signals are transmitted to the printed circuit board through a flexible flat cable (FFC) 103 together with the power processed by the driving circuit.
  • the gate driving unit 130 and the source driving unit 120 of the 104, the gate driving unit 130 and the source driving unit 120 transmit necessary data and power to the display area 111, so that the display device 100 obtains the power required for displaying the picture, signal.
  • FIG. 1b is a schematic diagram of an exemplary pixel unit configuration. Please cooperate with Figure 1a to facilitate understanding.
  • the gate driving unit 130 supplies the scanning signals to the gate lines 131 row by row, and provides the scanning signals to the row of gate lines 131 every scanning period.
  • the source line 121 of the display panel is opened one by one, and the source driving unit 120 provides data to the pixel unit P through the source line 121.
  • FIG. 1c is a schematic wiring diagram of a fan-out area of an exemplary display device. Please cooperate with FIG. 1a and FIG. 1b to facilitate understanding.
  • the gate driving unit 130 and the source driving unit 120 are configured in a flip-chip thin film manner.
  • a corresponding integrated circuit (IC) is configured on the flip-chip film, and the integrated circuits are electrically coupled to each other through a connection line 150.
  • the integrated circuit is connected to the conductive lines of the display area 111 through the transmission lines 160 of the fan-out area 112, respectively.
  • the conductive lines connected are also different.
  • the gate integrated circuit is connected to the scan line (gate line 131), and the source integrated circuit is connected to the data line (source line 121).
  • the resistance value of the middle trace of the transmission line 160 is small. As the distance from the middle trace increases, the resistance value of the corresponding trace also increases. In particular, the length difference between the outermost trace and the middle trace of the transmission line 160 is relatively large, and the difference in resistance is also high, so that the impedance such as the trace cannot be achieved. At the same time, the parasitic capacitance of the outermost trace and the middle trace of the transmission line 160 will also be different. The difference in the resistance and capacitance of the traces in the fan-out area 112 will cause a delay in the resistance and capacitance of the signal transmitted to the source line through the two traces. This delay can cause problems such as unequal fanout trace signals and signal delays. When the display panel is lit and displayed on the screen, there is also a problem of display differences in the uneven display area.
  • FIG. 2a is a schematic wiring diagram of a display panel according to an embodiment of the present application.
  • a display panel includes: a first substrate 110, including a display area 111 and a peripheral wiring area, the wiring area has a fan-out area 112, and a plurality of signal lines 311 are arranged In the display area 111, a plurality of active switches T and a plurality of pixel units P are provided in the display area 111 of the first substrate 110.
  • the plurality of pixel units P are respectively coupled to the plurality of active switches T, and the plurality of active switches T are electrically Is coupled to a plurality of signal lines 311; a second substrate 210 is disposed opposite to the first substrate 110; a driving unit 310 is disposed in the wiring area; a transmission line 160 is disposed in the fan-out area 112; the transmission line 160 is electrically coupled to the driver Between the unit 310 and the plurality of signal lines 311; the isolation layer 320 is disposed above the transmission line 160; wherein, the surface of the isolation layer 320 is provided with an electrode layer 330. When the electrode layer 330 is electrically coupled to a shared voltage, the electrode layer 330 and The transmission line 160 forms a capacitor.
  • the setting of the transmission line 160 includes a single-layer metal wiring method
  • the electrode layer 330 is, for example, a metal layer or an indium tin oxide semiconductor layer, which is not limited herein.
  • the setting of the transmission line 160 includes a two-layer metal wiring method
  • the electrode layer 330 is, for example, an indium tin oxide semiconductor layer, which is not limited herein.
  • the electrode layer 330 when the electrode layer 330 is a metal layer, it may be designed and configured as a single-layer or double-layer metal layer or a metal oxide layer, which is not limited herein.
  • FIG. 2b is a schematic diagram showing a wiring of a display panel according to an embodiment of the method of the present application.
  • the first substrate 110 is a multilayer circuit board.
  • the first substrate 110 includes a first layer board 110a and a second layer board 110b.
  • the transmission line 160 is disposed on a surface of the first layer board 110a.
  • the electrode layer 330 is disposed on the surface of the second layer plate 110b.
  • the second layer 110 b is the insulation layer 320.
  • the configuration range of the electrode layer 330 covers a part or all of the wiring range of the transmission line 160.
  • the capacitance value of the capacitor corresponds to the range of the electrode layer 330 covering the transmission line 160.
  • FIG. 3a is a schematic wiring diagram of a display panel according to an embodiment of the present application.
  • the electrode layer configuration covers the entire wiring area, so that the transmission line 160 is covered by the electrode layer.
  • FIG. 3b is a schematic wiring diagram of a display panel according to an embodiment of the present application.
  • the electrode layer 330 is configured to cover the wiring area.
  • FIG. 3c is a schematic wiring diagram of a display panel according to an embodiment of the present application.
  • the electrode layer 330 is configured to cover the oblique line region.
  • FIG. 3d is a schematic wiring diagram of a display panel according to an embodiment of the present application.
  • the electrode layer 330 is configured to cover the entire oblique line area and the local wiring area.
  • the electrode layer 330 may cover only the lines in the wiring area in a targeted manner.
  • the electrode layer 330 is electrically coupled to the shared voltage line 132. As shown in FIG. 3b, when the electrode layer 330 is configured to cover the wiring area, the beginning of the wiring area is electrically coupled to the shared voltage line 132. As shown in FIG. 3c, when the electrode layer 330 is configured to cover the oblique line region, the ends of the oblique line region are electrically coupled to the shared voltage line 132.
  • the plurality of signal lines 311 include a plurality of gate lines 131 and a plurality of source lines 121
  • the driving unit 310 includes at least one of a gate driving unit 130 and a source driving unit 120.
  • the gate driving unit 130 is electrically coupled to the plurality of gate lines 131
  • the source driving unit 120 is electrically coupled to the plurality of source lines 121.
  • an embodiment of the present application provides a display panel including a first substrate 110 including a display area 111 and a peripheral wiring area, the wiring area has a fan-out area 112, and a plurality of signal lines 311 are disposed on In the display area 111, a plurality of active switches T and a plurality of pixel units P are provided in the display area 111 of the substrate.
  • the plurality of pixel units P are respectively coupled to the plurality of active switches T, and the plurality of active switches T are electrically coupled to a plurality of each.
  • the signal line 311; the second substrate 210 is disposed opposite to the first substrate 110; the driving unit 310 is disposed in the wiring area; the transmission line 160 is disposed in the fan-out area 112; the transmission line 160 is electrically coupled to the driving unit 310 and more Between the signal lines 311, the transmission line 160 has a wiring area and a diagonal line area according to the shape of the fan-out area 112. The wiring area is disposed between the diagonal area and the driving unit 310.
  • an isolation layer 320 is disposed above the transmission line 160; wherein an electrode layer 330 is disposed on the surface of the isolation layer 320, and the electrode layer 330 is electrically coupled to the shared voltage when the electrode layer 330 is electrically coupled With transmission line 1 60 forms a capacitor, and the electrode layer 330 is configured to cover the fan-out area 112, the wiring area, the oblique line area, or a partial oblique line area and a local wiring area.
  • the display device 100 includes: a control module 101 that provides a control signal and an operating voltage, and the operating voltage includes a shared voltage; a display panel controlled by the control module 101 and including: a first substrate 110 including a display Area 111 and its peripheral wiring area.
  • the wiring area has a fan-out area 112.
  • a plurality of signal lines 311 are arranged in the display area 111.
  • a plurality of active switches T and a plurality of pixel units P are provided in the display area 111 of the substrate.
  • the unit P is respectively coupled to a plurality of active switches T, and each of the plurality of active switches T is electrically coupled to a plurality of signal lines 311; a second substrate 210 is disposed opposite to the first substrate 110; a driving unit 310 is disposed in the wiring area; The transmission line 160 is disposed in the fan-out area 112. The transmission line 160 is electrically coupled between the driving unit 310 and the plurality of signal lines 311.
  • the isolation layer 320 is disposed above the transmission line 160. The surface of the isolation layer 320 is provided. There is an electrode layer 330. When the electrode layer 330 is electrically coupled to a shared voltage, the electrode layer 330 and the transmission line 160 form a capacitor.
  • FIG. 4a is a schematic wiring diagram of a display panel according to an embodiment of the present application.
  • a display panel includes: a first substrate 110, including a display area 111 and a peripheral wiring area, the wiring area having a fan-out area 112, and a plurality of signal lines 311 configured In the display area 111, a plurality of active switches T and a plurality of pixel units P are provided in the display area 111 of the substrate.
  • the plurality of pixel units P are respectively coupled to the plurality of active switches T, and the plurality of active switches T are electrically coupled to each other.
  • the transmission line 160 is provided in a single-layer or double-layer metal wiring manner.
  • the electrode layer 330 is, for example, a metal layer or an indium tin oxide semiconductor layer, which is not limited herein.
  • FIG. 4b is a schematic diagram showing a wiring of a display panel according to an embodiment of the present application.
  • an isolation layer 320 is disposed on the second substrate 210 with respect to the fan-out region 112, and an electrode layer 330 is disposed on a surface of the isolation layer 320.
  • the isolation layer 320 includes at least one of a color resist layer and a black matrix.
  • the configuration range of the isolation layer 320 covers a part or all of the wiring range of the transmission line 160.
  • the capacitance value of the capacitor corresponds to the range that the isolation layer 320 covers the transmission line 160.
  • FIG. 5a is a schematic wiring diagram of a display panel according to an embodiment of the present application.
  • the color resist layer 320 is configured to cover the entire fan-out area, so that the transmission line 160 is covered by the electrode layer 330 on the surface of the color resist layer 320.
  • FIG. 5b is a schematic wiring diagram of a display panel according to an embodiment of the present application.
  • the color resist layer 320 is configured to cover the wiring area, so that the wiring area is covered by the electrode layer 330 on the surface of the color resist layer 320.
  • FIG. 5c is a schematic wiring diagram of a display panel according to an embodiment of the present application.
  • the color resist layer 320 is configured to cover the oblique line region, so that the oblique line region is covered by the electrode layer 330 on the surface of the color resist layer 320.
  • FIG. 5d is a schematic wiring diagram of a display panel according to an embodiment of the present application.
  • the color resist layer 320 is configured to cover the entire oblique line area and the local wiring area, so that the local oblique line area and the local wiring area are covered by the electrode layer 330 on the surface of the color resist layer 320. .
  • the color resist layer 320 may be specifically covered only over the lines of the wiring region 112.
  • FIG. 6 is a schematic diagram of a transmission line wiring of a display panel according to an embodiment of the present application. As shown in FIG. 6, in one embodiment, the wiring in the wiring area is provided by a continuously curved bow wire.
  • the display panel includes a first substrate 110 including a display area 111 and a peripheral wiring area.
  • the wiring area has a fan-out area 112.
  • a plurality of signal lines 311 are disposed in the display area 111.
  • 111 is provided with a plurality of active switches T and a plurality of pixel units P, the plurality of pixel units P are respectively coupled to the plurality of active switches T, and the plurality of active switches T are respectively electrically coupled to the plurality of signal lines 311;
  • the second substrate 210 Opposite the first substrate 110, the second substrate 210 is provided with an isolation layer 320;
  • the driving unit 310 is disposed in the wiring area;
  • the transmission line 160 is disposed in the fan-out area 112, and the transmission line 160 is electrically coupled to the driving unit 310 and Between the plurality of signal lines 311, the transmission line 160 has a wiring area and a diagonal line area according to the shape of the fan-out area 112.
  • the wiring area is disposed between the diagonal area and the driving unit 310, and the diagonal area faces the display area 111.
  • An electrode layer 330 disposed covering 112 fan out area, shaded area, local area and the hatched wiring region, and termination region or the local region hatched; insulation layer 320 comprises a color resist layer, at least one of the black matrix.
  • the display device 100 includes: a control module including, but not limited to, the aforementioned control board 101; a display panel controlled by the control module, a first substrate 110, including a display area 111 and a peripheral wiring area thereof;
  • the wiring area has a fan-out area 112, a plurality of signal lines 311 are arranged in the display area 111, a plurality of active switches T and a plurality of pixel units P are provided in the display area 111 of the substrate, and the plurality of pixel units P are respectively coupled to a plurality of Active switch T, each of which is electrically coupled to multiple signal lines 311;
  • the second substrate 210 is disposed opposite to the first substrate 110, and the second substrate 210 is provided with an insulation layer 320;
  • the drive unit 310 is provided in the wiring Transmission line 160 is disposed in the fan-out area 112, and the transmission line 160 is electrically coupled between the driving unit 310 and the plurality of signal lines 311; wherein the position of the insulation layer 320 is relative to the position
  • the display panel further includes any one of the previous embodiments.
  • the display panel of the present application may be, for example, a liquid crystal display panel, but it is not limited thereto. It may also be an OLED (Organic Light Emitting Diode) display panel. Emitting Diode white light organic electroluminescence diode (OLED) display panel, QLED (Quantum Dot Light Emitting Diodes quantum dot light emitting diode) display panel, plasma display panel, curved display panel or other type of display panel.
  • OLED Organic Light Emitting Diode
  • the capacitors above the fan-out traces make the phase-shifted signals of the traces have similar delays, which can avoid the problem of unequal fan-out trace signals. Because there is no need to significantly adjust the production process, there are no special process requirements and difficulties, and it will not increase higher costs. It is highly competitive in the market. Moreover, this application is applicable to a variety of display panel designs today, and of course it is also applicable to the narrow bezel design of the panel, which is in line with market and technology trends.

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Abstract

一种显示面板，包括：第一基板(110)，包括显示区(111)及其***的布线区，所述布线区具有扇出区(112)；第二基板(210)，与第一基板(110)相对设置；传输线路(160)，设置于扇出区(112)，传输线路(160)电性耦接于驱动单元(310)与多条信号线(311)之间；隔绝层(320)设置于第二基板(210)相对于扇出区(112)的位置；隔绝层(320)的表面设置有电极层(330)，电极层(330)电性耦接公共电极电压线(132)与传输线路(160)形成电容。

Description

显示面板及其应用的显示装置
本申请要求于2018年06月22日提交中国专利局，申请号为2018106507018，发明名称为“显示面板及其应用的显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及一种显示面板的布线技术领域，特别涉及一种显示面板及其应用的显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。显示面板正常显示时，需要栅级驱动线路、源极驱动线路，结合基板上纵横交错的栅极线、数据线以控制各个像素，实现图像的显示。
显示器驱动方式包括：***主板将颜色(例如：R/G/B Red/Green/Blue红/绿/蓝)压缩信号、控制信号及电源传输至控制板。信号经过控制板上的时序控制器处理后，传输至印刷电路板的源极电路及栅极电路，通过基板上的栅极线、数据线、电源等线路，将必要性的数据与电源传输于显示区，从而使得显示器获得呈现画面需求的电源、信号。目前市场上的产品边框越做越窄，扇出区走线的空间也越来越有限。当扇出区空间较小时，最外面一条走线和中间一根条线的长度差异会变大，阻值差异变大，无法实现走线等阻抗。同时最外面一条走线和中间一条走线上方的寄生电容也会有差异。扇出区走线的电阻电容的差异会导致通过两条走线线传输到源极线上的信号出现电阻电容延迟。这种延迟会产生扇出走线信号不均等、信号延迟等问题。在显示面板在画面点亮及显示时，也会有区域性显示不均的显示差异问题。
申请内容
本申请的一个目的在于提供一种显示面板，包括但不限于实现调整扇出走线的相移信号延迟的目的。
为实现上述目的，本申请实施例采用的技术方案是：一种显示面板，包括：
第一基板，包括显示区及其***的布线区，所述布线区具有扇出区，多条信号线设置于所述显示区，在所述基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线；
第二基板，与所述第一基板相对设置；
驱动单元，设置于所述布线区；
传输线路，设置于所述扇出区，所述传输线路电性耦接于所述驱动单元与所述多条信号线之间；
隔绝层，设置于所述第二基板相对于所述扇出区的位置；
其中，所述隔绝层的表面设置有电极层，所述电极层电性耦接公共电极电压线时，所述电极层与所述传输线路形成电容。
本申请的另一目的为提供一种显示面板，其包括：
第一基板，包括显示区及其***的布线区，所述布线区具有扇出区，多条信号线设置于所述显示区，在所述基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线；
第二基板，与所述第一基板相对设置，所述第二基板设置有隔绝层；
驱动单元，设置于所述布线区；
传输线路，设置于所述扇出区，所述传输线路电性耦接于所述驱动单元与所述多条信号线之间，所述传输线路依据所述扇出区的形状设置而具有接线区与斜线区，所述接线区设置于所述斜线区与所述驱动单元之间，所述斜线区朝向所述显示区以窄至宽方式布线且连接所述多条信号线；
其中，所述隔绝层的位置相对于所述扇出区的位置，电极层设置于所述隔绝层的表面，所述隔绝层上的所述电极层与所述传输线路形成电容，所述隔绝层设置涵盖所述扇出区、所述斜线区、所述斜线区及局部的所述接线区、或所述接线区及局部的所述斜线区；所述隔绝层包括色阻层与黑色矩阵中至少其一。
本申请的又一目的为提供一种显示装置，其包括：
第一基板，包括显示区及其***的布线区，所述布线区具有扇出区，多条信号线设置于所述显示区，在所述基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线；
第二基板，与所述第一基板相对设置，所述第二基板设置有隔绝层；
驱动单元，设置于所述布线区；传输线路，设置于所述扇出区，所述传输线路电性耦接于所述驱动单元与所述多条信号线之间；
其中，所述隔绝层的位置相对于所述扇出区的位置，电极层设置于所述隔绝层的表面，所述隔绝层上的所述电极层与所述传输线路形成电容。
本申请实施例提供的显示面板可以不大幅改变现有生产流程的前提下，通过扇出走线上方的电容，使得走线的相移信号延迟相近，较能避免扇出走线信号不均等的问题。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1a为示例性的显示装置的架构示意图；
图1b为示例性的像素单元配置示意图；
图1c为示例性的显示装置的扇出区的布线示意图；
图2a为本申请一个实施例提供的显示面板的布线示意图；
图2b为本申请一个实施例提供的显示面板的布线示意图；
图3a为本申请另一个实施例提供的显示面板的布线示意图；
图3b为本申请另一个实施例提供的显示面板的布线示意图；
图3c为本申请另一个实施例提供的显示面板的布线示意图；
图3d为本申请另一个实施例提供的显示面板的布线示意图；
图4a为本申请再一个实施例提供的显示面板的布线示意图；
图4b为本申请再一个实施例提供的显示面板的布线示意图；
图5a为本申请又一个实施例提供的显示面板的布线示意图；
图5b为本申请又一个实施例提供的显示面板的布线示意图；
图5c为本申请又一个实施例提供的显示面板的布线示意图；
图5d为本申请又一个实施例提供的显示面板的布线示意图；
图6为本申请又一个实施例提供的显示面板的传输线路布线示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以直接在另一个部件上或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本专利的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所述的技术方案，以下结合具体附图及实施例进行详细说明。
图1a为示例性的显示装置的架构示意图。请参照图1a，一种显示装置100，包括：控制板101，控制板101包括时序模块(Timing Controller，TCON)102；印刷电路板104，与控制板101之间通过柔性扁平电缆(Flexible Flat Cable，FFC)103相连接；源极驱动单元120与栅极驱动单元130配置于布线区，分别与显示区111内的源极线121及栅极线131连接。在一些实施例中，栅极驱动单元130及源极驱动单元120包括但不限制为覆晶薄膜形式。
在一个实施例中，显示装置100的驱动方式包括：***主板提供颜色(例如：R/G/B)压缩信号、控制信号及电源传输至控制板101。控制板101上的时序控制器(Timing Controller，TCON)102与处理此等信号后，连同被驱动电路处理的电源，通过柔性扁平电缆(Flexible Flat Cable，FFC)103，一并传输至印刷电路板104的栅极驱动单元130及源极驱动单元120，栅极驱动单元130及源极驱动单元120将必要性的数据与电源传输于显示区111，从而使得显示装置100获得呈现画面需求的电源、信号。
图1b为示例性的像素单元配置示意图。请配合图1a以利于了解。栅极驱动单元130是逐行提供扫描信号给栅极线131，每一扫描周期提供扫描信号给一行栅极线131。显示面板的源极线121会被逐行打开，源极驱动单元120通过源极线121提供数据至像素单元P。
图1c为示例性的显示装置的扇出区的布线示意图，请配合图1a及图1b以利于了解。如1c所绘示，在某些实施例中，栅极驱动单元130及源极驱动单元120以覆晶薄膜方式配置。覆晶薄膜上配置有对应的集成电路(IC)，集成电路彼此之间是通过连接线路150电性耦接。在一个实施例中，集成电路通过扇出区112的传输线路160分别与显示区111的导电线路相连接。依据集成电路的不同，所连接的导电线路亦不相同。如栅极集成电路即连接扫描线(栅极线131)，如源极集成电路即连接数据线(源极线121)。
然而，当扇出区112空间较小时，传输线路160其中间走线的阻值较小，随着与中间走线距离的增大，对应走线的阻值也随之增大。特别的，传输线路160最外面一条走线和中间一根条线的长度差异相对较大，阻值差异也较高，无法实现走线等阻抗。同时传输线路160最外面一条走线和中间一条走线的寄生电容也会有差异。扇出区112走线的电阻电容的差异，会导致通过此两条走线线传输到源极线上的信号出现电阻电容延迟。这种延迟会产生扇出走线信号不均等、信号延迟等问题。在显示面板在画面点亮及显示时，也会有区域性显示不均的显示差异问题。
图2a为本申请一实施例的显示面板的布线示意图。显示面板组件配置请配合图1a至图1c以利于理解。请参照图2a，在本申请一实施例中，一种显示面板，包括：第一基板110，包括显示区111及其***的布线区，布线区具有扇出区112，多条信号线311配置于显示区111，在第一基板110的显示区111设置多个主动开关T和多个像素单元P，多个像素单元P分别耦接于多个主动开关T，多个主动开关T分别电性耦接多条信号线311；第二基板210，与第一基板110相对设置；驱动单元310，配置于布线区；传输线路160，设置于扇出区112，传输线路160电性耦接于驱动单元310与多条信号线311之间；隔绝层320，设置于传输线路160上方；其中，隔绝层320的表面设置有电极层330，电极层330电性耦接共享电压时，电极层330与传输线路160形成电容。
在一个实施例中，传输线路160的设置包括单层金属布线方式，电极层330例如为金属层或铟锡氧化物半导体层，在此不做限定。
在一个实施例中，传输线路160的设置包括双层金属布线方式，电极层330例如为铟锡氧化物半 导体层，在此不做限定。
在一个实施例中，电极层330为金属层时，可设计配置为单层或双层金属层或金属氧化物层，在此不做限制。
图2b为显示依据本申请的方法，一实施例的显示面板的布线示意图。显示面板组件配置请配合图1a至图1c以利于理解。请参照图2b，在一个实施例中，第一基板110为多层电路板，第一基板110包括第一层板110a与第二层板110b，传输线路160配置于第一层板110a的表面，电极层330配置于第二层板110b的表面。
在一个实施例中，第二层板110b即为隔绝层320。
在一个实施例中，电极层330的配置范围涵盖局部或全部的传输线路160的布线范围。
在一个实施例中，电容的电容值对应电极层330涵盖传输线路160的范围。
图3a为本申请一实施例的显示面板的布线示意图。显示面板组件配置请配合图1a至图2b以利于理解。请参照图3a，电极层配置涵盖整个布线区，以使传输线路160被涵盖在电极层的范围内。
图3b为本申请一实施例的显示面板的布线示意图。显示面板组件配置请配合图1a至图2b以利于理解。请参照图3b，电极层330配置涵盖接线区。
图3c为本申请一实施例的显示面板的布线示意图。显示面板组件配置请配合图1a至图2b以利于理解。请参照图3c，电极层330配置涵盖斜线区。
图3d为本申请一实施例的显示面板的布线示意图。显示面板组件配置请配合图1a至图2b以利于理解。请参照图3d，电极层330配置涵盖整个局部的斜线区及局部的接线区。
在一个实施例中，电极层330可针对性的仅覆盖在布线区的线路上方。
在一个实施例中，电极层330电性耦接共享电压线132。如图3b所示，电极层330配置涵盖接线区时，接线区的始端电性耦接共享电压线132。如图3c所示，电极层330配置涵盖斜线区时，斜线区的末端电性耦接共享电压线132。
在一个实施例中，多条信号线311包括多条栅极线131与多条源极线121，驱动单元310包括栅极驱动单元130与源极驱动单元120中至少其一，栅极驱动单元130电性耦接多条栅极线131，源极驱动单元120电性耦接多条源极线121。
在一个实施例中，本申请实施例提供一种显示面板，其包括：第一基板110，包括显示区111及其***的布线区，布线区具有扇出区112，多条信号线311配置于显示区111，在基板的显示区111设置多个主动开关T和多个像素单元P，多个像素单元P分别耦接于多个主动开关T，多个主动开关T分别电性耦接多条信号线311；第二基板210，与第一基板110相对设置；驱动单元310，配置于布线区；传输线路160，设置于扇出区112，传输线路160电性耦接于驱动单元310与多条信号线311之间，传输线路160依据扇出区112的形状设置而具有接线区与斜线区，接线区设置于斜线区与驱动单元310之间， 斜线区朝向显示区111以窄至宽方式布线且连接多条信号线311；隔绝层320，设置于传输线路160上方；其中，隔绝层320的表面设置有电极层330，电极层330电性耦接共享电压时，电极层330与传输线路160形成电容，电极层330配置涵盖扇出区112、接线区、斜线区、或局部的斜线区及局部的接线区。
在本申请一实施例中，显示装置100包括：控制模块101，提供控制信号与工作电压，工作电压包括共享电压；显示面板，为控制模块101所控制的，包括：第一基板110，包括显示区111及其***的布线区，布线区具有扇出区112，多条信号线311配置于显示区111，在基板的显示区111设置多个主动开关T和多个像素单元P，多个像素单元P分别耦接于多个主动开关T，多个主动开关T分别电性耦接多条信号线311；第二基板210，与第一基板110相对设置；驱动单元310，配置于布线区；传输线路160，设置于扇出区112，传输线路160电性耦接于驱动单元310与多条信号线311之间；隔绝层320，设置于传输线路160上方；其中，隔绝层320的表面设置有电极层330，电极层330电性耦接共享电压时，电极层330与传输线路160形成电容。
图4a为本申请一实施例的显示面板的布线示意图。相关显示面板组件配置请配合图1a至图2b以利于理解。请参照图4a，在本申请一实施例中，一种显示面板，包括：第一基板110，包括显示区111及其***的布线区，布线区具有扇出区112，多条信号线311配置于显示区111，在基板的显示区111设置多个主动开关T和多个像素单元P，多个像素单元P分别耦接于多个主动开关T，多个主动开关T分别电性耦接多条信号线311；第二基板210，与第一基板110相对设置；驱动单元310，配置于布线区；传输线路160，设置于扇出区112，传输线路160电性耦接于驱动单元310与多条信号线311之间；其中，第二基板210相对于扇出区112的表面设置有电极层330，电极层330与传输线路160形成电容。
在一个实施例中，传输线路160的设置包括单层或双层金属布线方式，电极层330例如为金属层或铟锡氧化物半导体层，在此不做限定。
图4b为显示依据本申请一实施例的显示面板的布线示意图。相关显示面板组件配置请配合图1a至图1c、及图4a以利于理解。请参照图4b，在一个实施例中，第二基板210相对于扇出区112的位置设置有隔绝层320，电极层330配置于隔绝层320的表面。
在一个实施例中，隔绝层320包括色阻层与黑色矩阵中至少其一。
在一个实施例中，隔绝层320的配置范围涵盖局部或全部的传输线路160的布线范围。
在一个实施例中，电容的电容值对应隔绝层320涵盖传输线路160的范围。
图5a为本申请一实施例的显示面板的布线示意图。显示面板组件配置请配合图1a至图1c、及图4b以利于理解。请参照图5a，色阻层320配置涵盖整个扇出区，以使传输线路160被涵盖在色阻层320表面的电极层330的范围内。
图5b为本申请一实施例的显示面板的布线示意图。显示面板组件配置请配合图1a至图1c、及图 4b以利于理解。请参照图5b，色阻层320配置涵盖接线区，以使接线区被涵盖在色阻层320表面的电极层330的范围内。
图5c为本申请一实施例的显示面板的布线示意图。显示面板组件配置请配合图1a至图1c、及图4b以利于理解。请参照图5c，色阻层320配置涵盖斜线区，以使斜线区被涵盖在色阻层320表面的电极层330的范围内。
图5d为本申请的一实施例的显示面板的布线示意图。显示面板组件配置请配合图1a至图1c、及图4b以利于理解。请参照图5d，色阻层320配置涵盖整个局部的斜线区及局部的接线区，以使局部的斜线区及局部的接线区被涵盖在色阻层320表面的电极层330的范围内。
在一个实施例中，色阻层320可针对性的仅覆盖在布线区112的线路上方。
图6为本申请的一实施例的显示面板的传输线路布线示意图。如图6所示，在一个实施例中，接线区的线路是以连续弯曲的弓型线设置。
在一个实施例中，显示面板包括：第一基板110，包括显示区111及其***的布线区，布线区具有扇出区112，多条信号线311配置于显示区111，在基板的显示区111设置多个主动开关T和多个像素单元P，多个像素单元P分别耦接于多个主动开关T，多个主动开关T分别电性耦接多条信号线311；第二基板210，与第一基板110相对设置，第二基板210配置有隔绝层320；驱动单元310，配置于布线区；传输线路160，设置于扇出区112，传输线路160电性耦接于驱动单元310与多条信号线311之间，传输线路160依据扇出区112的形状设置而具有接线区与斜线区，接线区设置于斜线区与驱动单元310之间，斜线区朝向显示区111以窄至宽方式布线且连接多条信号线；其中，隔绝层320的位置相对于扇出区112的位置，电极层330配置于隔绝层320的表面，隔绝层320表面的电极层330与传输线路160形成电容，电极层330配置涵盖扇出区112、斜线区、斜线区及局部的接线区、或接线区及局部的斜线区；隔绝层320包括色阻层与黑色矩阵中至少其一。
在本申请一实施例中，显示装置100包括：控制模块，其包括但不限于前述控制板101；为控制模块所控制的显示面板，第一基板110，包括显示区111及其***的布线区，布线区具有扇出区112，多条信号线311配置于显示区111，在基板的显示区111设置多个主动开关T和多个像素单元P，多个像素单元P分别耦接于多个主动开关T，多个主动开关T分别电性耦接多条信号线311；第二基板210，与第一基板110相对设置，第二基板210配置有隔绝层320；驱动单元310，配置于布线区；传输线路160，设置于扇出区112，传输线路160电性耦接于驱动单元310与多条信号线311之间；其中，隔绝层320的位置相对于扇出区112的位置，电极层330配置于隔绝层320的表面，隔绝层320上的电极层330与传输线路160形成电容。
在一个实施例中，显示面板更包括先前任一种实施方式。
在某些实施例中，本申请显示面板可例如为液晶显示面板，然不限于此，其亦可为OLED(Organic  Light Emitting Diode有机电致发光二极管)显示面板，W-OLED(White-Organic Light Emitting Diode白光有机电致发光二极管)显示面板，QLED(Quantum Dot Light Emitting Diodes量子点发光二极管)显示面板，等离子体显示面板，曲面型显示面板或其他类型显示面板。
本申请通过扇出走线上方的电容，使得走线的相移信号延迟相近，较能避免扇出走线信号不均等的问题。因不需大幅调整生产流程，较没有特别的制程要求与难度，亦不会提升较高成本，极具备市场竞争性。而且，本申请适用于现今多种的显示面板设计，当然也适用于面板窄边框设计，符合市场及技术趋势。
以上仅为本申请的可选实施例而已，并不用于限制本申请。对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (18)

  1. 一种显示面板，其中，包括：
    第一基板，包括显示区及其***的布线区，所述布线区具有扇出区，多条信号线设置于所述显示区；
    第二基板，与所述第一基板相对设置；
    驱动单元，设置于所述布线区；
    传输线路，设置于所述扇出区，所述传输线路电性耦接于所述驱动单元与所述多条信号线之间；
    隔绝层，设置于所述第二基板相对于所述扇出区的位置；
    其中，所述隔绝层的表面设置有电极层，所述电极层电性耦接公共电极电压线，所述电极层与所述传输线路形成电容。
  2. 如权利要求1所述的显示面板，其中，所述传输线路包括单层金属布线，所述电极层为金属层。
  3. 如权利要求1所述的显示面板，其中，所述传输线路包括单层金属布线，所述电极层为铟锡氧化物半导体层。
  4. 如权利要求1所述的显示面板，其中，所述传输线路包括双层金属布线，所述电极层为金属层。
  5. 如权利要求1所述的显示面板，其中，所述传输线路包括双层金属布线，所述电极层为铟锡氧化物半导体层。
  6. 如权利要求1所述的显示面板，其中，所述隔绝层的设置范围涵盖局部或全部的所述传输线路的布线范围。
  7. 如权利要求1所述的显示面板，其中，所述电容的电容值对应所述隔绝层涵盖所述传输线路的范围。
  8. 如权利要求1所述的显示面板，其中，所述电容的电容值对应所述电极层涵盖所述传输线路的范围。
  9. 如权利要求1所述的显示面板，其中，所述多条信号线包括多条栅极线，所述驱动单元包括栅极驱动单元，所述栅极驱动单元电性耦接所述多条栅极线。
  10. 如权利要求1所述的显示面板，其中，所述多条信号线包括多条源极线，所述驱动单元包括源极驱动单元，所述源极驱动单元电性耦接所述多条源极线。
  11. 如权利要求1所述的显示面板，其中，所述第一基板包括第一层板与第二层板，所述传输线路设置于所述第一层板的表面，所述电极层设置于所述第二层板的表面。
  12. 如权利要求11所述的显示面板，其中，所述第二层板为所述隔绝层。
  13. 如权利要求1所述的显示面板，其中，所述电极层的设置范围涵盖局部或全部的所述传输线路的布线范围。
  14. 一种显示面板，其中，包括：
    第一基板，包括显示区及其***的布线区，所述布线区具有扇出区，多条信号线设置于所述显示区，在所述基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线；
    第二基板，与所述第一基板相对设置；
    驱动单元，设置于所述布线区；
    传输线路，设置于所述扇出区，所述传输线路电性耦接于所述驱动单元与所述多条信号线之间，所述传输线路依据所述扇出区的形状设置而具有接线区与斜线区，所述接线区设置于所述斜线区与所述驱动单元之间，所述斜线区朝向所述显示区以窄至宽方式布线且连接所述多条信号线；
    隔绝层，设置于所述第二基板，所述隔绝层的位置相对于所述扇出区的位置；
    其中，电极层设置于所述隔绝层的表面，所述隔绝层上的所述电极层与所述传输线路形成电容，所述隔绝层设置涵盖所述扇出区、所述斜线区、所述斜线区及局部的所述接线区或所述接线区及局部的所述斜线区；所述隔绝层包括色阻层与黑色矩阵中至少其一。
  15. 如权利要求14所述的显示面板，其中，所述电极层设置涵盖所述接线区。
  16. 如权利要求14所述的显示面板，其中，所述电极层设置涵盖所述斜线区。
  17. 如权利要求14所述的显示面板，其中，所述接线区的线路设置为连续弯曲的弓型线。
  18. 一种显示装置，其中，包括：
    第一基板，包括显示区及其***的布线区，所述布线区具有扇出区，多条信号线设置于所述显示区，在所述基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线；
    第二基板，与所述第一基板相对设置；
    驱动单元，设置于所述布线区；
    传输线路，设置于所述扇出区，所述传输线路电性耦接于所述驱动单元与所述多条信号线之间；
    隔绝层，设置于所述第二基板，所述隔绝层的位置相对于所述扇出区的位置；
    其中，电极层设置于所述隔绝层的表面，所述隔绝层上的所述电极层与所述传输线路形成电容。
PCT/CN2018/115403 2018-06-22 2018-11-14 显示面板及其应用的显示装置 WO2019242213A1 (zh)

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