WO2019237283A1 - Loop output circuit, tv tuner and radio frequency receiving system - Google Patents

Loop output circuit, tv tuner and radio frequency receiving system Download PDF

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Publication number
WO2019237283A1
WO2019237283A1 PCT/CN2018/091090 CN2018091090W WO2019237283A1 WO 2019237283 A1 WO2019237283 A1 WO 2019237283A1 CN 2018091090 W CN2018091090 W CN 2018091090W WO 2019237283 A1 WO2019237283 A1 WO 2019237283A1
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WO
WIPO (PCT)
Prior art keywords
loop
output
circuit
buffer
input
Prior art date
Application number
PCT/CN2018/091090
Other languages
French (fr)
Chinese (zh)
Inventor
莫秉轩
侯斌
金香菊
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201880094527.1A priority Critical patent/CN112262531B/en
Priority to CN202210291522.6A priority patent/CN114827508A/en
Priority to PCT/CN2018/091090 priority patent/WO2019237283A1/en
Publication of WO2019237283A1 publication Critical patent/WO2019237283A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/50—Tuning indicators; Automatic tuning control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/12—Neutralising, balancing, or compensation arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/18—Input circuits, e.g. for coupling to an antenna or a transmission line
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H04N21/42607—Internal components of the client ; Characteristics thereof for processing the incoming bitstream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/148—Video amplifiers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45—Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/12—Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal

Definitions

  • the present application relates to the field of circuit technology, and in particular, to a loop-through output circuit, a television tuner, and a radio frequency receiving system.
  • Loop-through output refers to sending one video signal to multiple devices for use when the video signal is being output.
  • the loop-through output of video can be applied in various scenarios, such as the loop-through output of surveillance video and the loop-through output of satellite TV video signals.
  • a television tuner (TV tuner) can amplify, filter, and convert analog signals to radio frequency signals.
  • the television device can then perform video playback according to the signal output after the above processing.
  • a loop-through output circuit is often introduced before the RF signal is amplified or after the RF signal is amplified.
  • the loop-through output circuit can include multiple channels, and the signal output by each channel in the multiple channels can be used for video playback through television equipment.
  • the transmitted video signal still needs to be amplified, filtered, and analog-to-digital converted.
  • the signal after the signal passes through the loop-through output, it still generally needs a certain degree of amplification, and the amplification gain is required to be adjustable. Therefore, each path after the loop-through output needs to realize the gain range and gain range of the signal amplification, thereby making the hardware implementation of the loop-through output circuit more complicated and increasing the power consumption of the loop-through output circuit.
  • the embodiments of the present application disclose a loop-through output circuit, a television tuner, and a set-top box, which can reduce the complexity of the implementation scheme of the loop-through output circuit and reduce power consumption.
  • an embodiment of the present application provides a television tuner.
  • the television tuner includes a radio frequency receiving circuit and a loop-through output circuit.
  • the radio frequency receiving circuit includes a low noise amplifier, a first filter, and a first mode.
  • a digital converter for sequentially low-noise amplification, filtering, and analog-to-digital conversion of the received signal;
  • the loop-through output circuit includes a first loop-through buffer, and the first loop-through buffer includes a voltage buffer circuit and A feedback circuit, the voltage buffer circuit is configured to perform voltage buffering on a signal output at an input terminal of the first filter or a signal output at an output terminal of the first filter, and an output terminal of the voltage buffer circuit
  • the output signal is used for loop-through output, and the feedback circuit is used to feed back the signal output from the output end of the voltage buffer circuit to the input end of the voltage buffer circuit to improve the loop gain of the voltage buffer circuit .
  • a voltage buffer circuit and a feedback circuit may be designed to sequentially perform a signal output at the input end of the first filter or a signal output at the output end of the first filter.
  • Voltage buffering and signal feedback The feedback circuit in the loop-through buffer can increase the loop gain of the voltage buffer circuit and reduce the output impedance of the loop-through output circuit, thereby providing the loop-through output circuit with high input impedance and low output impedance, which can improve the loop-through output circuit.
  • the drive capability of the loop-through output circuit has better linearity performance. The condition that the signal output at the input end of the first filter or the signal output at the output end of the first filter is loop-through can be satisfied.
  • the signal of the input loop-through output circuit is amplified by the variable gain amplifier in the RF receiving circuit according to the principle that the input power of the analog-to-digital converter is a constant power value
  • the signal of the input loop-through output circuit It can ensure that the input power of the analog-to-digital converter in the loop-through output circuit is a constant power value, and there is no need to set different gain ranges and gain ranges for the low-noise amplifier and the variable gain amplifier in the loop-through output circuit. This reduces the complexity of the loop-through output circuit structure and reduces the power consumption of the loop-through output circuit.
  • the voltage buffer circuit includes a source follower, and the feedback circuit includes a current mirror and a first transistor; wherein: a drain of the first transistor is coupled to an input terminal of the current mirror An output end of the current mirror is coupled to a source of the source follower; the current mirror and the first transistor are configured to feed back a signal output from the output end of the source follower to the source An input terminal of the electrode follower and provides a current bias for the source of the source follower.
  • the structure of the source follower, the current mirror, and the first transistor can provide the loop-through output circuit with high input impedance and low output impedance, and can improve the driving ability of the loop-through output circuit.
  • the feedback circuit composed of the current mirror and the first transistor can improve the loop gain of the voltage buffer circuit and reduce the output impedance of the loop-through output circuit.
  • the loop-through output circuit has better linearity performance, which can meet the The condition that the signal output at the input end of the filter or the signal output at the output end of the first filter performs loop-through output reduces the complexity of the loop-through output circuit structure.
  • the voltage buffer circuit is configured to perform voltage buffering on a signal output at an input end of the first filter, and the loop-through output circuit further includes a second filter and a second modulus.
  • the voltage buffer circuit is used for voltage buffering a signal output at an output end of the first filter
  • the loop-through output circuit further includes a third analog-to-digital converter for Performing analog-to-digital conversion on a signal output by the first loop-through buffer.
  • the radio frequency receiving circuit may be a narrow-band radio frequency receiving circuit or a full-band radio frequency receiving circuit.
  • the gain of the first amplifier may be adjustable to ensure that the power of the analog signal received by the first analog-to-digital converter is constant.
  • the first amplifier may be a PGA.
  • the first filter may be an anti-aliasing filter AAF or a low-pass filter LPF.
  • the first filter and the second filter may be low-pass filters.
  • the radio frequency receiving circuit further includes a single-turn dual circuit; the single-turn dual circuit is configured to receive a radio frequency signal, convert the radio frequency signal into a differential signal, and input the low noise amplifier;
  • the first loop-through buffer includes a first portion and a second portion, and the first portion of the first loop-through buffer and the second portion of the first loop-through buffer include The voltage buffer circuit and the feedback circuit; the first part of the first loop-through buffer and the second part of the first loop-through buffer are respectively used to output to the input end of the first filter And processing the two differential signals of the two or the two differential signals output at the output end of the first filter.
  • the loop-through output circuit can be provided with high input impedance and low output impedance, and the driving capability of the loop-through output circuit can be improved.
  • the feedback circuit composed of the current mirror and the first transistor can improve the loop gain of the voltage buffer circuit, reduce the output impedance of the loop-through output power, and the loop-through output circuit has better linearity performance. Converting the received single-ended signal into a differential signal for processing can reduce the mutual interference between the signals during the process, thereby helping to avoid signal distortion on each channel, and can output a higher-quality image and sound signal to the TV device .
  • a loop-through output circuit can be derived from the output of the single slip circuit.
  • the signals processed by each element in the loop-through output circuit are differential signals, and the signals output by each element are also differential signals.
  • the loop-through output circuit may further include a third amplifier, a fourth amplifier, and a second filter.
  • the third amplifier, the fourth amplifier, the second filter, and the second analog-to-digital converter are connected in sequence, and are used to sequentially connect the The differential signal output from the output of the double circuit is subjected to low noise amplification, amplification, and analog-to-digital conversion.
  • the above-mentioned loop-through output circuit adopts a differential structure, which can improve the anti-interference ability of the loop-through output circuit, and because the loop-through output circuit is derived from the output of the single-turn dual circuit, there is no need to arrange a single-turn in the loop-through output circuit.
  • Two circuits can realize the differential structure, which can simplify the circuit structure.
  • the low-noise amplifier is a differential amplifier
  • the differential amplifier includes a first input resistor, a first feedback capacitor, a first feedback resistor, a second input resistor, a second feedback capacitor, and a second feedback Resistor, first-stage operational amplifier, adjustable capacitor, and second-stage operational amplifier; the resistance value of the first input resistance, the resistance value of the first feedback resistance, the resistance value of the second input resistance, and the The resistance of the second feedback resistor is adjustable and is used to adjust the gain of the differential amplifier; wherein one end of the first input resistance is one input end of the differential amplifier and one end of the first input resistance Is connected to one output terminal of the single-turn dual circuit, the other end of the first input resistor is connected to one end of a first parallel circuit and a non-inverting input terminal of the first-stage operational amplifier, and the first The parallel circuit is a parallel circuit composed of the first feedback capacitor and the first feedback resistor; the negative-phase output terminal of the first-stage operational amplifier is connected to one end of the
  • the other input end, one end of the second input resistance is connected to the other output end of the single-turn dual circuit, the other end of the second input resistance is connected to one end of a second parallel circuit, and the first The negative-phase input terminal of the first-stage operational amplifier is connected, and the second parallel circuit is a parallel circuit composed of the second feedback capacitor and the second feedback resistor;
  • the other end of the adjustable capacitor is connected to the negative-phase input terminal of the second-stage operational amplifier; the negative-phase output terminal of the second-stage operational amplifier is connected to the other end of the second parallel circuit.
  • the differential amplifier in the embodiment of the present application includes a two-stage operational amplifier, the first-stage amplifier is used to amplify the signal, and the second-stage amplifier is used to provide driving capability, which is helpful to realize driving a large load.
  • the radio frequency receiving circuit 10 adopts a fully differential structure, which is helpful to improve the anti-interference performance of the circuit.
  • the first loop-through buffer can be used to isolate the loop-through output circuit from the radio frequency receiving circuit.
  • the loop-through output circuit includes N branches, and the N branches are connected in parallel; an i-th branch among the N branches is used to connect the first branch
  • the signal output by the loop-through buffer to the i-th branch is loop-through output; wherein, N is a positive integer greater than or equal to 1, and i is an integer satisfying 1 ⁇ i ⁇ N, and the first The i branches are any of the N branches.
  • the loop-through output circuit includes M branches; the first loop-through buffer includes M second loop-through buffers, and each of the M branches includes one The second loop-through buffer; the output end of the second loop-through buffer on the k-th branch is connected to the input end of the second loop-through buffer on the k + 1 branch, and the k + th
  • the second loop-through buffer on one branch is used to buffer a signal output from an output of the second loop-through buffer on the k-th branch; wherein M is a positive value greater than or equal to 2.
  • the branches are two adjacent branches among the M branches.
  • the second loop-through buffer on the k-th branch can be used to isolate the k-th branch from the RF receiving circuit.
  • the k-th branch further includes a second amplifier, and an input end of the second amplifier is connected to an output end of the second loop-through buffer on the k-th branch. For signal amplification.
  • the radio frequency receiving circuit further includes a gain controller, and the gain controller is configured to adjust a gain of the first amplifier.
  • an embodiment of the present application provides a loop-through output circuit.
  • the loop-through output circuit is configured to loop-through output a radio frequency receiving circuit.
  • the radio frequency receiving circuit includes a low noise amplifier, a first filter, and a first An analog-to-digital converter for sequentially amplifying, filtering, and analog-to-digital conversion of the received signal;
  • the loop-through output circuit includes a first loop-through buffer, and the first loop-through buffer includes a voltage buffer circuit and a feedback A circuit for voltage buffering a signal output at an input terminal of the first filter or a signal output at an output terminal of the first filter, and an output terminal of the voltage buffer circuit outputs
  • the signal is used for loop-through output, and the feedback circuit is used to feed back the signal output from the output end of the voltage buffer circuit to the input end of the voltage buffer circuit to improve the loop gain of the voltage buffer circuit.
  • a voltage buffer circuit and a feedback circuit may be designed to sequentially output a signal at an input end of the first filter or a signal output at an output end of the first filter. Perform voltage buffering and signal feedback.
  • the feedback circuit in the loop-through buffer can improve the loop gain of the voltage buffer circuit and reduce the output impedance of the loop-through output circuit.
  • the loop-through output circuit has better linearity performance. Then, it is not necessary to set a low-noise amplifier, a mixer, a filter, and a variable gain amplifier in the loop-through circuit, thereby reducing the complexity of the loop-through output circuit structure.
  • the signal of the input loop-through output circuit is amplified by the variable gain amplifier in the RF receiving circuit according to the principle that the input power of the analog-to-digital converter is a constant power value
  • the signal of the input loop-through output circuit It can ensure that the input power of the analog-to-digital converter in the loop-through output circuit is a constant power value, and there is no need to set different gain ranges and gain ranges for the low-noise amplifier and the variable gain amplifier in the loop-through output circuit. This reduces the complexity of the loop-through output circuit structure and reduces the power consumption of the loop-through output circuit.
  • the voltage buffer circuit includes a source follower, and the feedback circuit includes a current mirror and a first transistor; wherein: a drain of the first transistor is coupled to an input terminal of the current mirror An output end of the current mirror is coupled to a source of the source follower; the current mirror and the first transistor are configured to feed back a signal output from the output end of the source follower to the source An input terminal of the electrode follower and provides a current bias for the source of the source follower.
  • the structure of the source follower, the current mirror, and the first transistor can provide the loop-through output circuit with high input impedance and low output impedance, and can improve the driving ability of the loop-through output circuit.
  • the feedback circuit composed of the current mirror and the first transistor can improve the loop gain of the voltage buffer circuit and reduce the output impedance of the loop-through output circuit.
  • the loop-through output circuit has better linearity performance, which can meet the The condition that the signal output at the input end of the filter or the signal output at the output end of the first filter performs loop-through output reduces the complexity of the loop-through output circuit structure.
  • the voltage buffer circuit is configured to perform voltage buffering on a signal output at an input end of the first filter, and the loop-through output circuit further includes a second filter and a second modulus.
  • the voltage buffer circuit is used for voltage buffering a signal output at an output end of the first filter
  • the loop-through output circuit further includes a third analog-to-digital converter for Performing analog-to-digital conversion on a signal output by the first loop-through buffer.
  • the radio frequency receiving circuit may be a narrow-band radio frequency receiving circuit or a full-band radio frequency receiving circuit.
  • the gain of the first amplifier may be adjustable to ensure that the power of the analog signal received by the first analog-to-digital converter is constant.
  • the first amplifier may be a PGA.
  • the first filter may be an anti-aliasing filter AAF or a low-pass filter LPF.
  • the first filter and the second filter may be low-pass filters.
  • the radio frequency receiving circuit further includes a single-turn dual circuit; the single-turn dual circuit is configured to receive a radio frequency signal, convert the radio frequency signal into a differential signal, and output the signal to the low noise amplifier;
  • the first loop-through buffer includes a first portion and a second portion, and the first portion of the first loop-through buffer and the second portion of the first loop-through buffer include The voltage buffer circuit and the feedback circuit; the first part of the first loop-through buffer and the second part of the first loop-through buffer are respectively used to output to the input end of the first filter And processing the two differential signals of the two or the two differential signals output at the output end of the first filter.
  • the loop-through output circuit can be provided with high input impedance and low output impedance, and the driving capability of the loop-through output circuit can be improved.
  • the feedback circuit composed of the current mirror and the first transistor can improve the loop gain of the voltage buffer circuit, reduce the output impedance of the loop-through output power, and the loop-through output circuit has better linearity performance.
  • the signal received by the loop-through output circuit is a differential signal, which can reduce mutual interference between the signals during processing, thereby helping to avoid signal distortion on each channel, and can output a higher-quality image and sound signal to the television device.
  • a loop-through output circuit can be derived from the output of the single slip circuit.
  • the signals processed by each element in the loop-through output circuit are differential signals, and the signals output by each element are also differential signals.
  • the loop-through output circuit may further include a third amplifier, a fourth amplifier, and a second filter.
  • the third amplifier, the fourth amplifier, the second filter, and the second analog-to-digital converter are connected in sequence, and are used to sequentially connect the The differential signal output from the output of the double circuit is subjected to low noise amplification, amplification, and analog-to-digital conversion.
  • the above-mentioned loop-through output circuit adopts a differential structure, which can improve the anti-interference ability of the loop-through output circuit, and because the loop-through output circuit is derived from the output of the single-turn dual circuit, there is no need to arrange a single-turn in the loop-through output circuit.
  • Two circuits can realize the differential structure, which can simplify the circuit structure.
  • the low-noise amplifier is a differential amplifier
  • the differential amplifier includes a first input resistor, a first feedback capacitor, a first feedback resistor, a second input resistor, a second feedback capacitor, and a second feedback Resistor, first-stage operational amplifier, adjustable capacitor, and second-stage operational amplifier; the resistance value of the first input resistance, the resistance value of the first feedback resistance, the resistance value of the second input resistance, and the The resistance of the second feedback resistor is adjustable and is used to adjust the gain of the differential amplifier; wherein one end of the first input resistance is one input end of the differential amplifier and one end of the first input resistance Is connected to one output terminal of the single-turn dual circuit, the other end of the first input resistor is connected to one end of a first parallel circuit and a non-inverting input terminal of the first-stage operational amplifier, and the first The parallel circuit is a parallel circuit composed of the first feedback capacitor and the first feedback resistor; the negative-phase output terminal of the first-stage operational amplifier is connected to one end of the
  • the other input end, one end of the second input resistance is connected to the other output end of the single-turn dual circuit, the other end of the second input resistance is connected to one end of a second parallel circuit, and the first The negative-phase input terminal of the first-stage operational amplifier is connected, and the second parallel circuit is a parallel circuit composed of the second feedback capacitor and the second feedback resistor;
  • the other end of the adjustable capacitor is connected to the negative-phase input terminal of the second-stage operational amplifier; the negative-phase output terminal of the second-stage operational amplifier is connected to the other end of the second parallel circuit.
  • the differential amplifier in the embodiment of the present application includes a two-stage operational amplifier, the first-stage amplifier is used to amplify the signal, and the second-stage amplifier is used to provide driving capability, which is helpful to realize driving a large load.
  • the radio frequency receiving circuit 10 adopts a fully differential structure, which is helpful to improve the anti-interference performance of the circuit.
  • the first loop-through buffer can be used to isolate the loop-through output circuit from the radio frequency receiving circuit.
  • the loop-through output circuit includes N branches, and the N branches are connected in parallel; an i-th branch among the N branches is used to connect the first branch
  • the signal output by the loop-through buffer to the i-th branch is loop-through output; wherein, N is a positive integer greater than or equal to 1, and i is an integer satisfying 1 ⁇ i ⁇ N, and the first The i branches are any of the N branches.
  • the loop-through output circuit includes M branches; the first loop-through buffer includes M second loop-through buffers, and each of the M branches includes one The second loop-through buffer; the output end of the second loop-through buffer on the k-th branch is connected to the input end of the second loop-through buffer on the k + 1 branch, and the k + th
  • the second loop-through buffer on one branch is used to buffer a signal output from an output of the second loop-through buffer on the k-th branch; wherein M is a positive value greater than or equal to 2.
  • the branches are two adjacent branches among the M branches.
  • the k-th branch further includes a second amplifier
  • the k-th branch further includes a second amplifier
  • an input end of the second amplifier is in connection with the k-th branch
  • the output end of the second loop-through buffer is connected for signal amplification.
  • an embodiment of the present application provides a set-top box, where the set-top box includes the second aspect or any possible television tuner in the second aspect.
  • an embodiment of the present application provides a radio frequency receiving system, where the radio frequency receiving system includes a radio frequency receiving device and a loop-through output device; wherein the radio frequency receiving device includes the second aspect or any one of the second aspect.
  • the radio frequency receiving circuit provided by the television tuner, and the loop-through output device includes the loop-through output circuit provided by the second aspect or any one of the possible television tuners of the second aspect.
  • FIG. 1 is a schematic structural diagram of a radio frequency receiving circuit and a loop-through output circuit according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of another radio frequency receiving circuit and a loop-through output circuit according to an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of still another RF receiving circuit and a loop-through output circuit according to an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a first loop-through buffer provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of still another radio frequency receiving circuit and a loop-through output circuit according to an embodiment of the present application
  • FIG. 6 is a schematic structural diagram of still another radio frequency receiving circuit and a loop-through output circuit according to an embodiment of the present application
  • FIG. 7 is a schematic structural diagram of still another radio frequency receiving circuit and a loop-through output circuit according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another first loop-through buffer according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a low-noise amplifier according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a loop-through output circuit according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another loop-through output circuit according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of still another loop-through output circuit according to an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of still another loop-through output circuit according to an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of still another loop-through output circuit according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a radio frequency receiving circuit 10 and a loop-through output circuit 20 according to an embodiment of the present application.
  • the radio frequency receiving circuit 10 can be used for receiving radio frequency signals and converting the radio frequency signals into digital signals so that the device can demodulate and process the signals.
  • the radio frequency receiving circuit 10 can be used in a television tuner, and the television tuner can receive a video signal in an RF form.
  • the video signal in the RF format may be, for example, a satellite television signal in the form of electromagnetic waves or a broadcast television signal in the form of electromagnetic waves.
  • the radio frequency receiving circuit 10 may include an antenna 100, a low noise amplifier (LNA) 200, a mixer 300, a variable gain amplifier (VGA) 400, and a low-pass amplifier.
  • the antenna 100, the low noise amplifier 200, the mixer 300, the low-pass filter 400, the variable gain amplifier 500, and the analog-to-digital converter 600 are connected in series in this order.
  • the antenna 100 can be used to receive radio frequency signals.
  • the radio frequency signal may be a television signal or other signals, such as a monitoring video signal, and the embodiment of the present application does not limit the radio frequency signal received by the antenna.
  • the low-noise amplifier 200 may be used for low-noise amplification of a signal output by the antenna 100 to improve the anti-noise capability of the signal.
  • the mixer 300 may be used to reduce the frequency of the received high-frequency signal and move the required signal to an intermediate frequency.
  • the variable gain amplifier 400 can be used to amplify the signal output from the mixer 300 to meet the power requirement of the signal received by the analog-to-digital converter 600.
  • the low-pass filter 500 may be used to perform low-pass filtering on a signal output from the variable gain amplifier 400 to select a signal at a required frequency band.
  • the analog-to-digital converter 600 may be configured to perform analog-to-digital conversion on an analog signal received from the variable gain amplifier 500 to obtain a digital signal, so as to perform signal demodulation in the future.
  • the gains of the low noise amplifier 200 and the variable gain amplifier 400 may be adjustable, so as to make the power of the analog signal received by the analog-to-digital converter 600 constant.
  • the loop-through output circuit 20 can realize the transmission of one video signal to multiple TV devices.
  • the loop-through output circuit 20 can be derived from the input end or output end of the low-noise amplifier 200, because the closer the signal output from the RF front-end is, the lower the non-linearity of the signal is.
  • the loop-through output circuit 20 may include a low-noise amplifier 201, a mixer 202, a variable gain amplifier 203, a low-pass filter 204, and an analog-to-digital converter 205 in series.
  • the loop-through output circuit 20 may further include a loop-through buffer (LTbuffer) 206.
  • the input of the loop-through buffer 206 is connected to the input of the low-noise amplifier 200.
  • the output of the loop-through buffer 206 The terminal is connected to the input terminal of the low-noise amplifier 201.
  • the loop-through buffer 206 may be used to isolate the loop-through output circuit 20 from the radio frequency receiving circuit 10.
  • the radio frequency receiving circuit 10 and the loop-through output circuit 20 may be included in a television tuner.
  • the radio frequency receiving circuit 10 and the loop-through output circuit 20 may be implemented by the same chip, or may be implemented by different chips. This is not limited in the embodiments of the present application.
  • the loop-through output circuit 20 derived from the input of the low-noise amplifier 200, before the signal is input to the television device, it is still necessary to use a circuit structure similar to the radio frequency receiving circuit in the loop-through output circuit to amplify the signal, Mixing, filtering, and analog-to-digital conversion processing, thereby increasing the complexity of the loop-through output circuit structure.
  • the input power of the analog-to-digital converter in the loop-through output circuit is a constant power value
  • the embodiment of the present application provides a loop-through output circuit, which can reduce the complexity of the loop-through circuit structure and reduce the power of the loop-through output circuit. Consuming.
  • the main principles involved in this application may include: In the designed loop-through buffer (the first loop-through buffer 206 in the preceding text), a voltage buffer circuit and a feedback circuit may be designed to sequentially output the voltage at the input end of the first filter.
  • the signal or the signal output at the output of the first filter performs voltage buffering and signal feedback.
  • the feedback circuit in the loop-through buffer can improve the loop gain of the voltage buffer circuit and reduce the output impedance of the loop-through output circuit.
  • the loop-through output circuit has better linearity performance.
  • the loop-through output circuit can be derived from the input end of the filter of the radio frequency receiving circuit (that is, the first filter in the preceding text) or the output end of the filter (that is, the input end of the analog-to-digital converter).
  • the signal input to the loop-through output circuit does not need to be amplified, mixed, and filtered.
  • the loop-through output circuit only includes an analog-to-digital converter, that is, the received signal can be converted into a digital signal for signal demodulation. There is no need to set low-noise amplifiers, mixers, filters, and variable gain amplifiers in the loop-through circuit, which reduces the complexity of the loop-through output circuit structure.
  • the signal of the input loop-through output circuit is amplified by the variable gain amplifier in the RF receiving circuit according to the principle that the input power of the analog-to-digital converter is a constant power value
  • the signal of the input loop-through output circuit It can ensure that the input power of the analog-to-digital converter in the loop-through output circuit is a constant power value, and there is no need to set different gain ranges and gain ranges for the low-noise amplifier and the variable gain amplifier in the loop-through output circuit. This reduces the complexity of the loop-through output circuit structure and reduces the power consumption of the loop-through output circuit.
  • FIG. 2 is another RF receiving circuit 10 and the loop-through output circuit 20 provided in the embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of still another RF receiving circuit 10 and a loop-through output circuit 20 according to an embodiment of the present application.
  • the RF receiving circuit 10 may include a low-noise amplifier 101, a first filter 102, and a first analog-to-digital converter 103, a low-noise amplifier 101, a first filter 102, and a first analog-to-digital conversion.
  • the processors 103 are connected in order to amplify, filter, and analog-to-digital convert the received signals in sequence.
  • the low-noise amplifier 101 refer to the specific description of the low-noise amplifier 200 in the radio frequency receiving circuit 10 described in FIG. 1, and for the description of the first filter 102 and the first analog-to-digital converter 103, refer to the description in FIG.
  • the detailed description of the low-pass filter 400 and the analog-to-digital converter 600 in the radio frequency receiving circuit 10 will not be repeated here.
  • the loop-through output circuit 20 may further include a first loop-through buffer 206.
  • the first loop-through buffer 206 may include a voltage buffer circuit 2061 and a feedback circuit 2062.
  • the voltage buffer circuit 2061 is used for The signal output at the input of the first filter 102 or the signal output at the output of the first filter 103 performs voltage buffering.
  • the signal output from the output of the voltage buffer circuit 2061 is used for loop-through output, and the feedback circuit 2062 uses The signal output from the output terminal of the voltage buffer circuit 2061 is fed back to the input terminal of the voltage buffer circuit 2062 to improve the loop gain of the voltage buffer circuit 2061.
  • the feedback circuit 2062 in the first loop-through buffer 206 can increase the gain of the voltage buffer circuit 2061.
  • the addition of the feedback circuit 2062 can also reduce the output impedance of the loop-through output circuit 20, thereby providing the loop-through output circuit 20 with a high input impedance and a low output impedance, which can improve the driving ability of the loop-through output circuit. Has better linearity performance. Then, a condition that the signals output at the input end of the first filter 102 or the signals output at the output end of the first filter 102 are loop-through output can be satisfied.
  • the signal input to the loop-through output circuit 20 does not need to be amplified, mixed, and filtered.
  • the loop-through output circuit 20 may include only an analog-to-digital converter, that is, the received signal may be converted into a digital signal for signal demodulation. There is no need to provide a low-noise amplifier, a mixer, a filter, a variable gain amplifier, and other components in the loop-through circuit 20, which reduces the structural complexity of the loop-through output circuit 20.
  • the signal of the input loop-through output circuit 20 is amplified by the variable gain amplifier in the radio frequency receiving circuit 10 according to the principle that the input power of the analog-to-digital converter is a constant power value, the input loop-through output circuit A signal of 10 can ensure that the input power of the analog-to-digital converter in the loop-through output circuit 20 is a constant power value.
  • a loop-through output circuit 20 can be derived from an output terminal of the first filter 102.
  • the loop-through output circuit 20 includes a third analog-to-digital converter 205 for outputting from the output terminal of the first filter 102.
  • the output signal undergoes analog-to-digital conversion.
  • the signal output by the third analog-to-digital converter 205 may be used for demodulation by a demodulator (demod).
  • the input terminal of the first loop-through buffer 206 is connected to the output terminal of the first filter 102, and the output terminal of the first loop-through buffer 206 is connected to the input terminal of the second analog-to-digital converter 205.
  • the first loop-through buffer 206 may be used to isolate the loop-through output circuit 20 from the radio frequency receiving circuit 10.
  • the input loop The signal of the pass-through output circuit 20 can ensure that the input power of the second analog-to-digital converter 206 in the loop-through output circuit 20 is a constant power value, and it is not necessary to set different gain ranges and gain ranges for the amplifier in the loop-through output circuit 20, As a result, the complexity of the loop-through output circuit 20 and the power consumption of the loop-through output circuit are reduced.
  • the loop-through output circuit 20 may be derived from the input end of the first filter 102.
  • the loop-through output circuit 20 may include a second filter 204 and a second analog-to-digital converter 205.
  • the second filter 204 and the second analog-to-digital converter 205 are connected in sequence, and are used for filtering and analog-to-digital conversion of a signal output from the input end of the first filter 102.
  • the signal output by the second analog-to-digital converter 205 can be used for demodulation by a demodulator (demod).
  • demodulator demodulator
  • the loop-through output circuit 20 described in FIG. 3 there is no need to provide a low-noise amplifier and a variable gain amplifier in the loop-through circuit 20, which reduces the complexity of the loop-through output circuit structure and the power consumption of the loop-through output circuit.
  • the signal of the input loop-through output circuit 20 is amplified by the low-noise amplifier 101 in the radio frequency receiving circuit 10 according to the principle that the input power of the first analog-to-digital converter 103 is a constant power value, the input loop The signal of the pass-through output circuit 20 can ensure that the input power of the second analog-to-digital converter 205 in the loop-through output circuit 20 is a constant power value.
  • the gain of the low-noise amplifier 101 may be adjustable to ensure that the power of the analog signal received by the first analog-to-digital converter 103 is constant.
  • the low-noise amplifier 101 may be a programmable gain amplifier (PGA).
  • the first filter 102 may be an anti-aliasing filter (AAF) or a low-pass filter (LPF), which is not limited in this embodiment of the present application.
  • AAF anti-aliasing filter
  • LPF low-pass filter
  • FIG. 4 is a schematic structural diagram of a first loop-through buffer 206 according to an embodiment of the present application.
  • the first loop-through buffer may be the first loop-through buffer 206 in FIGS. 2 and 3.
  • the voltage buffer circuit 2061 includes a source follower
  • the feedback circuit 2062 includes a current mirror (composed of M3 and M5) and a first transistor M7.
  • the drain of the first transistor M7 is coupled to the input terminal of a current mirror composed of M3 and M5, and the output terminal of the current mirror composed of M3 and M5 is coupled to the source of M1 in the source follower 2061.
  • the current mirror composed of M3 and M5 and the first transistor M7 are used to feed back the signal output from the output terminal of the source follower 2061 to the input terminal of the source follower 2061, and the source follower 2061
  • the source provides current bias.
  • the voltage of the signal output at the input terminal of the first filter 102 or the signal output at the output terminal of the first filter 102 is Vi, and is input to the voltage buffer circuit 2061.
  • Voltage buffering is performed by the voltage buffer circuit 2061 and the feedback circuit 2062 to obtain an output voltage Vo.
  • the source follower 2061 includes a current source bias I B , a transistor M1, a resistor R B, and an output series resistor Ros.
  • the output series resistor Ros is used for impedance matching.
  • the structure of the source follower, the current mirror composed of M3 and M5, and the first transistor M7 can provide the loop-through output circuit 20 with high input impedance and low output impedance. , Can improve the drive ability of the loop-through output circuit.
  • the current mirror composed of M3 and M5 and the feedback circuit 2062 composed of the first transistor M7 the loop gain of the voltage buffer circuit can be improved, and the output impedance of the loop-through output circuit 20 can be reduced.
  • the loop-through output circuit 20 has better linearity Performance, it can meet the conditions of loop-through output of the signal output at the input end of the first filter 102 or the signal output at the output end of the first filter 102.
  • radio frequency receiving circuit 10 described in FIG. 2 and FIG. 3 may be a narrow-band radio frequency receiving circuit or a full-band radio frequency receiving circuit. These are described separately below.
  • FIG. 5 is a schematic structural diagram of still another radio frequency receiving circuit 10 and a loop-through output circuit 20 according to an embodiment of the present application.
  • the radio frequency receiving circuit 10 is a narrow-band radio frequency receiving circuit.
  • the radio frequency receiving circuit 10 further includes a mixer 104 for reducing the frequency of the received high-frequency signal and moving the required signal to an intermediate frequency.
  • the gain of the low-noise amplifier 101 may be adjustable, and the first filter 102 may be a low-pass filter.
  • the narrowband radio frequency receiving circuit may further include a variable gain amplifier 105, which can adjust the gain of the variable gain amplifier 105 and the gain of the low noise amplifier 101 to make the power of the analog signal received by the first analog-to-digital converter 103 constant.
  • the low-noise amplifier 101 the first filter 102, the first analog-to-digital converter 103, the mixer 104, and the variable gain amplifier 105, refer to the low-noise amplifier 200, the low-pass filter 500, The analog-to-digital converter 600, the mixer 300, and the variable gain amplifier 400 are not repeated here.
  • the loop-through output circuit 20 reference may be made to the loop-through output circuit 20 described in FIG. 3.
  • the first loop-through buffer 206 in the loop-through output circuit 20 may be the first loop-through buffer 206 in any one of FIG. 2, FIG. 3, and FIG. 4, and details are not described herein again.
  • the loop-through output circuit 20 may also be derived from the output end of the first filter 102.
  • the loop-through output circuit 20 may also be derived from the output end of the first filter 102.
  • FIG. 6 is a schematic structural diagram of still another RF receiving circuit 10 and a loop-through output circuit 20 according to an embodiment of the present application.
  • the radio frequency receiving circuit 10 is a full-band radio frequency receiving circuit.
  • the radio frequency receiving circuit 10 may further include a tracking filter 106 for filtering a user's selection from the radio frequency signals of the full-band television received from the antenna.
  • the low-noise amplifier 101, the first filter 102, the first analog-to-digital converter 103, the mixer 104, and the variable gain amplifier 105 refer to the low-noise amplifier 200, the low-pass filter 500, The analog-to-digital converter 600, the mixer 300, and the variable gain amplifier 400 are not repeated here.
  • the loop-through output circuit 20 reference may be made to the loop-through output circuit 20 described in FIGS. 2 and 3.
  • the first loop-through buffer 206 in the loop-through output circuit 20 may be the first loop-through buffer 206 in any one of FIG. 2, FIG. 3, and FIG. 4, and details are not described herein again.
  • the loop-through output circuit 20 may also be derived from the input end of the first filter 102.
  • the loop-through output circuit 20 may also be derived from the input end of the first filter 102.
  • a single-to-differential (S2D) circuit can also be used.
  • the single-to-double circuit is used to convert a single-ended signal received from an antenna into a differential signal, and input the differential signal to the low-noise amplifier 101. Converting the received single-ended signal into a differential signal for processing can reduce the mutual interference between the signals during the process, thereby helping to avoid signal distortion on each channel, and can output a higher-quality image and sound signal to the TV device .
  • FIG. 7, is a schematic structural diagram of still another RF receiving circuit 10 and a loop-through output circuit 20 according to an embodiment of the present application.
  • the single-ended signal is converted into a differential signal through the single-to-dual circuit 107.
  • the low-noise amplifier 101, the first filter 102, the first analog-to-digital converter 103, and the variable gain amplifier 105 refer to the low-noise amplifier 200, the low-pass filter 500, and the analog-to-digital converter in sequence in FIG. 1 600 and the variable gain amplifier 400 are not repeated here.
  • the low noise amplifier 101, the first filter 102, the first analog-to-digital converter 103, and the variable gain amplifier 105 all have a differential structure.
  • the loop-through output circuit 20 may be derived from the input end or the output end of the first filter 102 (not shown in FIG. 7, and reference may be made to the lead-out position of the loop-through output circuit 20 in FIGS. 5 and 6).
  • the loop-through output circuit 20 can also be derived from the output of the single-turn dual circuit 107. As shown in FIG. 7, the differential signal output from the output terminal of the single slip circuit 107 is input to the loop-through output circuit 20.
  • the signals processed by each element in the loop-through output circuit 20 are differential signals, and the signals output by each element are also differential signals.
  • the loop-through output circuit 20 may further include a third amplifier 201, a fourth amplifier 203, and a second filter 204.
  • the third amplifier 201, the fourth amplifier 203, the second filter 204, and the second analog-to-digital converter 205 are connected in sequence. It is used to sequentially perform low-noise amplification, amplification, and analog-to-digital conversion on the differential signals output from the output ends of the single-to-double circuit.
  • the above-mentioned loop-through output circuit adopts a differential structure, which can improve the anti-interference ability of the loop-through output circuit, and since the loop-through output circuit 20 is derived from the output of the single-turn dual circuit 107, there is no need to use the loop-through output circuit 20
  • the single-turn dual-circuit layout in the middle can realize the differential structure, which can simplify the circuit structure.
  • the single-turn dual circuit 107 may be an on-chip passive balun, and the single-turn dual circuit 107 may also be an active balun, which is not limited in the embodiment of the present application.
  • the radio frequency receiving circuit 10 described in FIG. 7 is only used to explain the embodiment of the present application.
  • the position of the single-turn dual circuit 107 is not limited to the position between the antenna 100 and the low-noise amplifier 101, and may be other positions.
  • the position of the input signal of the loop-through output circuit 20 is not limited to between the single-turn dual circuit 107 and the low-noise amplifier 101, and may be other positions, which are not limited in the embodiment of the present application.
  • the structure of the first loop-through buffer 206 may also be a differential structure.
  • FIG. 8 is a schematic structural diagram of another first loop-through buffer 206 according to an embodiment of the present application.
  • the first loop-through buffer 206 in the loop-through output circuit 20, includes a first portion 2063 and a second portion 2064, the first portion 2063 of the first loop-through buffer, and the first portion of the first loop-through buffer.
  • the two parts 2064 each include a voltage buffer circuit and a feedback circuit.
  • the first portion 2063 of the first loop-through buffer and the second portion 2064 of the first loop-through buffer are respectively used for two differential signals output at the input of the first filter 102 or the output of the first filter 102
  • the two differential signals output from the processing are processed.
  • the voltage of the differential signal output at the input terminal of the first filter 102 or the differential signal output at the output terminal of the first filter 102 is Vip and Vin, and is input to the voltage buffer circuit 2061.
  • the voltage Vip at one end of the differential signal is input to the first portion 2063 of the first loop-through buffer, and the voltage Vin at the other end of the differential signal is input to the second portion 2064 of the first loop-through buffer.
  • the voltage buffer circuit 2061 and the feedback circuit 2062 in the first part of the first loop-through buffer 2063 perform voltage buffering on the input signal Vip to obtain an output voltage Vop.
  • the voltage buffer circuit 2061 ′ and The feedback circuit 2062 'performs voltage buffering on the input signal Vin to obtain an output voltage Von.
  • the structure of the source follower, the current mirror composed of M3 and M5, and the first transistor M7 may be: Providing the loop-through output circuit 20 with high input impedance and low output impedance can improve the driving ability of the loop-through output circuit.
  • the structure of the source follower, the current mirror composed of M3 and M5, and the first transistor M7 can provide the loop-through output circuit 20 with high input impedance and low output impedance. , Can improve the drive ability of the loop-through output circuit.
  • the feedback circuit composed of the current mirror and the first transistor can improve the loop gain of the voltage buffer circuit and reduce the output impedance of the loop-through output circuit 20.
  • the loop-through output circuit 20 has better linearity performance, which can meet the A condition for loop-through output of a signal output at an input terminal of the first filter 102 or a signal output at an output terminal of the first filter 102.
  • the loop-through output circuit 20 adopts a differential structure, so that the differential signal has the characteristics that the amplitude of the signal is equal, and the phase is 180 degrees out of phase. The even-order nonlinearity is very good.
  • the low-noise amplifier used in the embodiments of the present application may be a low-noise differential amplifier in a CMOS process, which helps reduce costs.
  • the low-noise amplifier 101 is a differential amplifier.
  • FIG. 9 is a schematic structural diagram of a low-noise amplifier 101 according to an embodiment of the present application.
  • the differential amplifier 101 may include a first input resistor Rin1, a first feedback resistor Rf1, a first feedback capacitor Cf1, a second input resistor Rin2, a second feedback resistor Rf2, a second feedback capacitor Cf2, and a first operation.
  • Amplifier A1 adjustable capacitor CL
  • second-stage operational amplifier A2 In general, in order to ensure that the signal output by the differential amplifier 101 shown in FIG. 8 is a differential signal, the sizes of Rf1 and Rf2 are equal, and the sizes of Cf1 and Cf2 are equal.
  • one end of the first input resistance Rin1 is one input end of the differential amplifier 101, one end of the first input resistance Rin1 is connected to one output end of the single-turn dual circuit 107, and the other ends of the first input resistance Rin1 are respectively It is connected to one end of the first parallel circuit and the non-inverting input terminal of the first-stage operational amplifier A1.
  • the first parallel circuit is a parallel circuit composed of a first feedback capacitor Cf1 and a first feedback resistor Rf1.
  • the negative-phase output terminal of the first-stage operational amplifier A1 is respectively connected to one end of the adjustable capacitor and the non-inverted-phase input terminal of the second-stage operational amplifier A2.
  • the non-inverting output terminal of the second-stage operational amplifier A2 is connected to the other end of the first parallel circuit.
  • One end of the second input resistance Rin2 is the other input end of the differential amplifier 101.
  • One end of the second input resistance Rin2 is connected to the other output end of the single-turn dual circuit 107.
  • the other ends of the second input resistance Rin2 are respectively connected in parallel with the second.
  • One end of the circuit is connected to the negative-phase input end of the first-stage operational amplifier A1, and the second parallel circuit is a parallel circuit composed of a second feedback capacitor Cf2 and a second feedback resistor Rf2.
  • the non-inverting output terminal of the first-stage operational amplifier A1 is respectively connected to the other end of the adjustable capacitor CL and the negative-phase input terminal of the second-stage operational amplifier A2.
  • the negative-phase output terminal of the second-stage operational amplifier A2 is connected to the other end of the second parallel circuit.
  • the gain of the differential amplifier 101 can be adjusted by adjusting the resistances of Rin1, Rin2, Rf1, and Rf2. Therefore, in the above case, the adjustable range of the gain of the differential amplifier 101 is related to the adjustable range of the resistance values of the resistors Rin1, Rin2, Rf1, and Rf2. The larger the adjustable range of the resistors Rin1, Rin2, Rf1, and Rf2 is In this case, the adjustable range of the gain of the differential amplifier 101 is larger.
  • Gain represents the gain of the signal
  • Rf represents the magnitude of the feedback resistor
  • Rin represents the magnitude of the input resistor Rin
  • A represents the open-loop gain of the differential amplifier.
  • the lead-through output circuit 20 may include a plurality of branches, and the plurality of branches are connected in parallel. Each of the multiple branches can process signals and output digital signals for signal demodulation.
  • the loop-through output circuit 20 may include N branches connected in parallel, and the i-th branch among the N branches is used to loop the signal output from the first loop-through buffer 206 to the i-th branch. Pass output.
  • Each of the N branches includes a second analog-to-digital converter 205.
  • the second analog-to-digital converter 205 is configured to output the input end of the first filter 102 or the output of the first filter 102 to the signal on the i branch. Analog-to-digital conversion.
  • N is a positive integer greater than or equal to 1
  • i is an integer satisfying 1 ⁇ i ⁇ N
  • the i-th branch is any of the N branches.
  • FIG. 10 is a schematic structural diagram of a loop-through output circuit 20 according to an embodiment of the present application.
  • the loop-through output circuit 20 may include N branches, and N may be an integer greater than or equal to 1.
  • a loop-through output circuit 20 is derived from the output of the filter 102 in the radio frequency receiving circuit 10.
  • a first loop-through buffer 206 may be first provided in the loop-through output circuit 20.
  • the input of the first loop-through buffer 206 is connected to the output of the first filter 102.
  • the output terminal of the buffer 206 is connected to the input terminals of the N parallel branches.
  • the first loop-through buffer 206 may be used to isolate the loop-through output circuit 20 from the radio frequency receiving circuit 10.
  • each branch includes a second analog-to-digital converter 205.
  • the digital signal output by the second analog-to-digital converter 205 can be used for The demodulator demodulates a television signal.
  • the radio frequency receiving circuit 10 reference may be made to the radio frequency receiving circuit described in any one of FIG. 1 to FIG. 3.
  • the derived loop-through output circuit 20 may further include a plurality of secondary loop-connected branches.
  • FIG. 11 is a schematic structural diagram of another loop-through output circuit 20 according to an embodiment of the present application.
  • the loop-through output circuit 20 may include M cascaded loop-through branches.
  • the first loop-through buffer 206 includes M second loop-through buffers 207, and each of the M branches includes a second loop-through buffer 207.
  • the output of the second loop-through buffer 207 on the k-th branch 208 is connected to the input of the second loop-through buffer 207 on the k + 1-th branch 210, and on the k + 1-th branch 210
  • the second loop-through buffer 207 is configured to buffer a signal output from an output terminal of the second loop-through buffer 207 on the k-th branch 208.
  • M is a positive integer greater than or equal to 2
  • k is an integer satisfying 1 ⁇ k ⁇ M
  • the k-th branch 208 is any one of the M branches.
  • the k-th branch 208 and the k + 1-th branch 210 are two adjacent branches among the M branches.
  • each branch may further include a second amplifier 209.
  • FIG. 12 is a schematic structural diagram of still another loop-through output circuit 20 according to an embodiment of the present application.
  • the input of the second amplifier 209 is connected to the output of the second loop-through buffer 207 on the k-th branch 208, and the output of the second amplifier 209
  • the terminal is connected to the second analog-to-digital converter 205 of the k-th branch 208, and the second amplifier 209 is used for signal amplification.
  • the signal output by the second loop-through buffer 207 needs to be amplified by the second amplifier 209 and then output.
  • the k + 1th branch 210 is also derived from the output of the second amplifier 209 of the kth branch 208. For each branch, you can choose to close or open the switch to choose not to use or use the second amplifier 209 on the branch for amplification.
  • the number of the second amplifiers 209 in the branch of the cascaded loop-through is not limited in the embodiment of the present application. In actual applications, it can be determined whether to set for each cascade branch according to the requirements.
  • connection of the second loop-through buffer 207 in the circuit is not limited to the connection shown in FIG. 11 and FIG. 12, and may also be other manners.
  • FIG. 13 is a schematic structural diagram of still another loop-through output circuit 20 according to an embodiment of the present application. As shown in FIG. 13, for the k-th branch 208, the second loop-through buffer 207 may be located on the k-th branch 208. In the embodiment of the present application, the positions of the second loop-through buffer 207 in the loop-through output circuit 20 and a plurality of branches are not limited.
  • the loop-through output circuit 20 may include multiple branches connected in parallel, and may also include branches connected to multiple secondary loops.
  • FIG. 14 is a schematic structural diagram of still another loop-through output circuit 20 according to an embodiment of the present application. As shown in FIG. 14, the loop-through output circuit 20 may include two parts: a parallel portion 21 and a cascaded loop-through portion 22.
  • the parallel section 21 includes a plurality of parallel branches. As shown in FIG. 14, the parallel section 21 may include N branches, and N may be an integer greater than or equal to 1. Each of the N branches includes a second analog-to-digital converter 205, and a signal output from the second analog-to-digital converter 205 of each branch can be used to demodulate a television signal. For the specific description of the parallel part 21, reference may be made to the loop-through output circuit described in FIG. 11, which is not repeated here.
  • the cascading loop-through section 22 may include multiple branches of the cascading loop-through, as shown in FIG. 14, may include N ′ branches, N ′ may also be an integer greater than or equal to 1, and N ′ and N may be equal , Can also vary.
  • Each of the N ′ branches includes a second analog-to-digital converter 205, and a signal output from the second analog-to-digital converter 205 of each branch can be used to demodulate a television signal.
  • the loop-through output circuit 20 may be implemented by a separate chip, or may be implemented by integrating with the radio frequency receiving circuit 10 in one chip.
  • This application The embodiment is not limited thereto.
  • each branch of the loop-through output circuit 20 connected in parallel may be implemented by independent chips, or multiple parallel branches may be integrated in one or more chips, which is not limited in the embodiment of the present application.
  • Each of the multiple branches of the cascading loop-through can be implemented by an independent chip, or can be implemented by integrating the cascaded multiple branches in one or more chips, which is not described in the embodiment of the present application. limited.
  • the loop-through output circuit 20 described in any one of FIG. 10 to FIG. 14 may also be derived from the input end of the first filter 102, and then the output end of the first loop-through buffer 206 may be in multiple lines.
  • a second filter is connected in series before the branch to filter the signal output from the first loop-through buffer.
  • the structure of the first loop-through buffer 206 may be referred to the first loop-through buffer 206 described in FIGS. 2 to 4 and is not described here anymore. To repeat. If the loop-through output circuit 20 has a differential structure, the structure of the first loop-through buffer 206 may refer to the first loop-through buffer 206 described in FIG. 8.
  • the radio frequency receiving circuit 10 described in any one of FIGS. 10 to 14 may further include a single-turn dual circuit 107.
  • the single-turn dual circuit 107 is configured to receive a radio frequency signal, convert the radio frequency signal into a differential signal, and input the low noise amplifier 101.
  • the input signal and output signal of the low-noise amplifier 101, the first filter 102, and the first analog-to-digital converter 103 in the radio frequency receiving circuit 10 shown in any one of FIGS. 10 to 14 are differential signals.
  • the input signals and output signals of the first loop-through buffer 206 and the components in the multiple branches in the loop-through output circuit 20 shown in any one of FIGS. 10 to 14 are differential signals.
  • the loop-through output circuit 20 described in any one of FIG. 10 to FIG. 14 is also used to lead from the output end of the single-turn dual circuit 107.
  • the loop-through output circuit 20 may further include a third amplifier and a second filter, and the third amplifier, the second filter, and the second analog-to-digital converter are connected in order to sequentially
  • the differential signal output from the output end of the single-turn dual circuit is amplified, filtered, and analog-to-digital converted.
  • the third amplifier and the second filter may be connected to the output end of the first loop-through buffer 206 and connected before multiple branches, or may be connected to the output end of the first loop-through buffer 206, and Each branch includes a third amplifier and a second filter, which are not limited in the embodiment of the present application.
  • an embodiment of the present application further provides a television tuner.
  • the television tuner includes a radio frequency receiving circuit and a loop-through output circuit.
  • the RF receiving circuit may be the RF receiving circuit 10 described in any one of FIGS. 1 to 3, and the loop-through output circuit may be any of FIGS. 2, 3, 5, 6, 7, and 10 to 14.
  • the loop-through output circuit 20 described in a figure is not repeated here.
  • the RF receiving circuit may include fewer devices, and may also include more devices.
  • the radio frequency receiving circuit may further include one or more mixers.
  • the loop-through output circuit may also include fewer devices, and may include more devices.
  • the loop-through output circuit may also include a demodulator.
  • the radio frequency receiving circuit and the loop-through output circuit of the television tuner may be integrated on the same chip, or may be integrated on different chips, which is not limited in the embodiment of the present application.
  • an embodiment of the present application also provides a set-top box, which may include a TV tuner.
  • the TV tuner includes a radio frequency receiving circuit and a loop-through output circuit.
  • the RF receiving circuit may be the RF receiving circuit 10 described in any one of FIGS. 1 to 3, and the loop-through output circuit may be any of FIGS. 2, 3, 5, 6, 7, and 10 to 14.
  • the loop-through output circuit 20 described in a figure is not repeated here.
  • an embodiment of the present application further provides a radio frequency receiving system.
  • the radio frequency receiving system includes a radio frequency receiving device and a loop-through output device.
  • the radio frequency receiving device includes a low noise amplifier, a first filter, and a first analog-to-digital converter. , For low-noise amplification, filtering, and analog-to-digital conversion of the received signal in sequence.
  • the loop-through output device includes a first loop-through buffer.
  • the first loop-through buffer includes a voltage buffer circuit and a feedback circuit.
  • the voltage buffer circuit is configured to output a signal at an input end of the first filter or an output of the first filter.
  • the signals output from the terminals are buffered by voltage.
  • the signals output from the output of the voltage buffer circuit are used for loop-through output.
  • the feedback circuit is used to feed back the signals output from the output of the voltage buffer circuit to the input of the voltage buffer circuit.
  • the radio frequency receiving device may include the radio frequency receiving circuit 10 described in any one of FIG. 1 to FIG. 3.
  • the loop-through output device may include the loop-through output circuit 20 described in FIG. 2, FIG. 3, FIG. 5, FIG. 6, FIG. 7, and any one of FIGS. 10 to 14.

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Abstract

Disclosed are a loop output circuit, a TV tuner and a radio frequency receiving system. The TV tuner comprises a radio frequency receiving circuit and a loop output circuit, wherein the radio frequency receiving circuit includes a low-noise amplifier, a first filter and a first analog-digital converter for performing low-noise amplification, filtering and analog-digital conversion on the received signal in sequence; the loop output circuit includes a first loop buffer; the first loop buffer comprises a voltage buffering circuit and a feedback circuit; the voltage buffering circuit is used for performing voltage buffering on a signal output at the input end of the first filter or a signal output at the output end of the first filter; a signal output at the output end of the voltage buffering circuit is used for loop output; the feedback circuit is used for feeding the signal output at the output end of the voltage buffering circuit back to the input end of the voltage buffering circuit, so as to improve the loop gain of the voltage buffering circuit. According to the embodiment of the present application, the complexity of the loop output circuit structure and the power consumption of the loop output circuit can be reduced.

Description

环通输出电路、电视调谐器和射频接收***Loop-through output circuit, TV tuner and RF receiving system 技术领域Technical field
本申请涉及电路技术领域，尤其涉及一种环通输出电路、电视调谐器和射频接收***。The present application relates to the field of circuit technology, and in particular, to a loop-through output circuit, a television tuner, and a radio frequency receiving system.
背景技术Background technique
环通输出(loop though，LT)是指在视频信号进行输出时，把一路视频信号输送给多个设备使用。视频的环通输出可以应用在多种场景下，例如监控视频的环通输出、***视频信号的环通输出。Loop-through output (LT) refers to sending one video signal to multiple devices for use when the video signal is being output. The loop-through output of video can be applied in various scenarios, such as the loop-through output of surveillance video and the loop-through output of satellite TV video signals.
目前，在电视接收***中，视频信号在以射频(radio frequency，RF)信号的形式接收之后，电视调谐器(TV tuner)可以对射频信号进行放大、滤波和模数转换等处理过程。之后电视设备可以根据上述处理后输出的信号进行视频播放。在电视接收***中，往往是在射频信号进行放大之前或者在射频信号进行放大之后引出环通输出电路。环通输出电路可以包含多条通路，多条通路中每条通路输出的信号均可以通过电视设备进行视频播放。At present, in a television receiving system, after a video signal is received in the form of a radio frequency (RF) signal, a television tuner (TV tuner) can amplify, filter, and convert analog signals to radio frequency signals. The television device can then perform video playback according to the signal output after the above processing. In a television receiving system, a loop-through output circuit is often introduced before the RF signal is amplified or after the RF signal is amplified. The loop-through output circuit can include multiple channels, and the signal output by each channel in the multiple channels can be used for video playback through television equipment.
然而，从视频信号进行放大前后引出的多条通路中，针对每条通路来说，传输的视频信号仍然需要经过放大、滤波、模数转换处理。另外，在信号经过环通输出后，一般仍然需要一定程度放大，并且要求放大增益可调。因此环通输出后的每条通路均需要实现信号放大的增益范围和增益档位，从而使环通输出电路的硬件实现方案更加复杂，且增加了环通输出电路的功耗。However, from the multiple paths leading out before and after the video signal is amplified, for each path, the transmitted video signal still needs to be amplified, filtered, and analog-to-digital converted. In addition, after the signal passes through the loop-through output, it still generally needs a certain degree of amplification, and the amplification gain is required to be adjustable. Therefore, each path after the loop-through output needs to realize the gain range and gain range of the signal amplification, thereby making the hardware implementation of the loop-through output circuit more complicated and increasing the power consumption of the loop-through output circuit.
发明内容Summary of the Invention
本申请实施例公开了一种环通输出电路、电视调谐器和机顶盒，可以降低环通输出电路实现方案的复杂度，并减少功耗。The embodiments of the present application disclose a loop-through output circuit, a television tuner, and a set-top box, which can reduce the complexity of the implementation scheme of the loop-through output circuit and reduce power consumption.
第一方面，本申请实施例提供一种电视调谐器，所述电视调谐器包括射频接收电路和环通输出电路；其中：所述射频接收电路包括低噪声放大器、第一滤波器和第一模数转换器，用于依次对接收到的信号进行低噪声放大、滤波和模数转换；所述环通输出电路包括第一环通缓冲器，所述第一环通缓冲器包括电压缓冲电路和反馈电路，所述电压缓冲电路用于对所述第一滤波器的输入端处输出的信号或者所述第一滤波器的输出端处输出的信号进行电压缓冲，所述电压缓冲电路的输出端输出的信号用于进行环通输出，所述反馈电路用于将所述电压缓冲电路的输出端输出的信号反馈到所述电压缓冲电路的输入端，以提高所述电压缓冲电路的环路增益。In a first aspect, an embodiment of the present application provides a television tuner. The television tuner includes a radio frequency receiving circuit and a loop-through output circuit. The radio frequency receiving circuit includes a low noise amplifier, a first filter, and a first mode. A digital converter for sequentially low-noise amplification, filtering, and analog-to-digital conversion of the received signal; the loop-through output circuit includes a first loop-through buffer, and the first loop-through buffer includes a voltage buffer circuit and A feedback circuit, the voltage buffer circuit is configured to perform voltage buffering on a signal output at an input terminal of the first filter or a signal output at an output terminal of the first filter, and an output terminal of the voltage buffer circuit The output signal is used for loop-through output, and the feedback circuit is used to feed back the signal output from the output end of the voltage buffer circuit to the input end of the voltage buffer circuit to improve the loop gain of the voltage buffer circuit .
上述的电视调谐器中，在第一环通缓冲器中，可以设计电压缓冲电路和反馈电路依次对第一滤波器的输入端处输出的信号或者第一滤波器的输出端处输出的信号进行电压缓冲和信号反馈。环通缓冲器中的反馈电路可以提高电压缓冲电路的环路增益，降低环通输出电路的输出阻抗，从而可以为环通输出电路提供高输入阻抗和低输出阻抗，可以提高对环通输出电路的驱动能力，环通输出电路具有更好的线性度性能。可以满足对第一滤波器的输入端处输出的信号或者第一滤波器的输出端处输出的信号进行环通输出的条件。则可以无需在环通电路中设置低噪声放大器、混频器、滤波器和可变增益放大器等器件，降低了 环通输出电路结构的复杂度。另外，由于输入环通输出电路的信号是经过射频接收电路中可变增益放大器根据模数转换器的输入功率为恒定功率值的原则对信号进行放大得到的，因此，输入环通输出电路的信号可以保证在环通输出电路中模数转换器的输入功率为恒定功率值，无需在环通输出电路中针对低噪声放大器以及可变增益放大器设置不同的增益范围和增益档位。从而降低了环通输出电路结构的复杂度，并降低环通输出电路的功耗。In the above-mentioned television tuner, in the first loop-through buffer, a voltage buffer circuit and a feedback circuit may be designed to sequentially perform a signal output at the input end of the first filter or a signal output at the output end of the first filter. Voltage buffering and signal feedback. The feedback circuit in the loop-through buffer can increase the loop gain of the voltage buffer circuit and reduce the output impedance of the loop-through output circuit, thereby providing the loop-through output circuit with high input impedance and low output impedance, which can improve the loop-through output circuit. The drive capability of the loop-through output circuit has better linearity performance. The condition that the signal output at the input end of the first filter or the signal output at the output end of the first filter is loop-through can be satisfied. This eliminates the need to set up low-noise amplifiers, mixers, filters, and variable gain amplifiers in the loop-through circuit, reducing the complexity of the loop-through output circuit structure. In addition, because the signal of the input loop-through output circuit is amplified by the variable gain amplifier in the RF receiving circuit according to the principle that the input power of the analog-to-digital converter is a constant power value, the signal of the input loop-through output circuit It can ensure that the input power of the analog-to-digital converter in the loop-through output circuit is a constant power value, and there is no need to set different gain ranges and gain ranges for the low-noise amplifier and the variable gain amplifier in the loop-through output circuit. This reduces the complexity of the loop-through output circuit structure and reduces the power consumption of the loop-through output circuit.
在一种可能的设计中，所述电压缓冲电路包含源极跟随器，所述反馈电路包含电流镜和第一晶体管；其中：所述第一晶体管的漏极与所述电流镜的输入端耦合，所述电流镜的输出端与所述源极跟随器的源极耦合；所述电流镜和所述第一晶体管用于将所述源极跟随器的输出端输出的信号反馈到所述源极跟随器的输入端，并为所述源极跟随器的源极提供电流偏置。上述的电压缓冲电路中，源极跟随器、电流镜和第一晶体管的结构，可以为环通输出电路提供高输入阻抗和低输出阻抗，可以提高对环通输出电路的驱动能力。另外，通过电流镜和第一晶体管组成的反馈电路可以提高电压缓冲电路的环路增益，降低环通输出电路的输出阻抗，环通输出电路具有更好的线性度性能，则可以满足对第一滤波器的输入端处输出的信号或者第一滤波器的输出端处输出的信号进行环通输出的条件，降低了环通输出电路结构的复杂度。In a possible design, the voltage buffer circuit includes a source follower, and the feedback circuit includes a current mirror and a first transistor; wherein: a drain of the first transistor is coupled to an input terminal of the current mirror An output end of the current mirror is coupled to a source of the source follower; the current mirror and the first transistor are configured to feed back a signal output from the output end of the source follower to the source An input terminal of the electrode follower and provides a current bias for the source of the source follower. In the above voltage buffer circuit, the structure of the source follower, the current mirror, and the first transistor can provide the loop-through output circuit with high input impedance and low output impedance, and can improve the driving ability of the loop-through output circuit. In addition, the feedback circuit composed of the current mirror and the first transistor can improve the loop gain of the voltage buffer circuit and reduce the output impedance of the loop-through output circuit. The loop-through output circuit has better linearity performance, which can meet the The condition that the signal output at the input end of the filter or the signal output at the output end of the first filter performs loop-through output reduces the complexity of the loop-through output circuit structure.
在一种可能的设计中，所述电压缓冲电路用于对所述第一滤波器的输入端处输出的信号进行电压缓冲，所述环通输出电路还包括第二滤波器和第二模数转换器，用于对所述第一环通缓冲器输出的信号进行滤波和模数转换。In a possible design, the voltage buffer circuit is configured to perform voltage buffering on a signal output at an input end of the first filter, and the loop-through output circuit further includes a second filter and a second modulus. A converter for filtering and analog-to-digital conversion of a signal output by the first loop-through buffer.
在一种可能的设计中，所述电压缓冲电路用于对所述第一滤波器的输出端处输出的信号进行电压缓冲，所述环通输出电路还包括第三模数转换器，用于对所述第一环通缓冲器输出的信号进行模数转换。In a possible design, the voltage buffer circuit is used for voltage buffering a signal output at an output end of the first filter, and the loop-through output circuit further includes a third analog-to-digital converter for Performing analog-to-digital conversion on a signal output by the first loop-through buffer.
其中，射频接收电路可以是窄带射频接收电路，也可以是全频带射频接收电路。The radio frequency receiving circuit may be a narrow-band radio frequency receiving circuit or a full-band radio frequency receiving circuit.
其中，第一放大器的增益可以是可调的，用于保证第一模数转换器接收到的模拟信号的功率为恒定的。The gain of the first amplifier may be adjustable to ensure that the power of the analog signal received by the first analog-to-digital converter is constant.
可选的，第一放大器可以是PGA。第一滤波器可以是抗混叠滤波器AAF，也可以是低通滤波器LPF。Optionally, the first amplifier may be a PGA. The first filter may be an anti-aliasing filter AAF or a low-pass filter LPF.
可选的，第一滤波器和第二滤波器可以是低通滤波器。Optionally, the first filter and the second filter may be low-pass filters.
在一种可能的设计中，所述射频接收电路还包括单转双电路；所述单转双电路用于接收射频信号，将所述射频信号转换为差分信号输入到所述低噪声放大器；在所述环通输出电路中，所述第一环通缓冲器包括第一部分和第二部分，所述第一环通缓冲器的第一部分和所述第一环通缓冲器的第二部分均包含所述电压缓冲电路和所述反馈电路；所述第一环通缓冲器的第一部分和所述第一环通缓冲器的第二部分分别用于对所述第一滤波器的输入端处输出的两路差分信号或者所述第一滤波器的输出端处输出的两路差分信号进行处理。上述的方案中，可以为环通输出电路提供高输入阻抗和低输出阻抗，可以提高对环通输出电路的驱动能力。另外，通过电流镜和第一晶体管组成的反馈电路可以提高电压缓冲电路的环路增益，降低环通输出电的输出阻抗，环通输出电路具有更好的线性度性能。将接收的单端信号转换为差分信号进行处理，能够降低处理过程中信号之间的相互干扰，进而有助于避免各个频道上的信号失真，能够向电视设备输出图像和伴音质量更高的信号。In a possible design, the radio frequency receiving circuit further includes a single-turn dual circuit; the single-turn dual circuit is configured to receive a radio frequency signal, convert the radio frequency signal into a differential signal, and input the low noise amplifier; In the loop-through output circuit, the first loop-through buffer includes a first portion and a second portion, and the first portion of the first loop-through buffer and the second portion of the first loop-through buffer include The voltage buffer circuit and the feedback circuit; the first part of the first loop-through buffer and the second part of the first loop-through buffer are respectively used to output to the input end of the first filter And processing the two differential signals of the two or the two differential signals output at the output end of the first filter. In the above solution, the loop-through output circuit can be provided with high input impedance and low output impedance, and the driving capability of the loop-through output circuit can be improved. In addition, the feedback circuit composed of the current mirror and the first transistor can improve the loop gain of the voltage buffer circuit, reduce the output impedance of the loop-through output power, and the loop-through output circuit has better linearity performance. Converting the received single-ended signal into a differential signal for processing can reduce the mutual interference between the signals during the process, thereby helping to avoid signal distortion on each channel, and can output a higher-quality image and sound signal to the TV device .
可选的，可以从单转差电路的输出端引出环通输出电路。环通输出电路中每个元件处理的信号均为差分信号，每个元件输出的信号也均为差分信号。环通输出电路还可以包括第三放大器、第四放大器和第二滤波器，第三放大器、第四放大器、第二滤波器和第二模数转换器依次连接，用于依次将从所述单转双电路的输出端输出的差分信号进行低噪声放大、放大、模数转换。上述的环通输出电路中采用差分结构，可以提高环通输出电路的抗干扰能力，且由于是从单转双电路的输出端引出环通输出电路，因此无需在环通输出电路中布局单转双电路即可实现差分结构，可以简化电路结构。Optionally, a loop-through output circuit can be derived from the output of the single slip circuit. The signals processed by each element in the loop-through output circuit are differential signals, and the signals output by each element are also differential signals. The loop-through output circuit may further include a third amplifier, a fourth amplifier, and a second filter. The third amplifier, the fourth amplifier, the second filter, and the second analog-to-digital converter are connected in sequence, and are used to sequentially connect the The differential signal output from the output of the double circuit is subjected to low noise amplification, amplification, and analog-to-digital conversion. The above-mentioned loop-through output circuit adopts a differential structure, which can improve the anti-interference ability of the loop-through output circuit, and because the loop-through output circuit is derived from the output of the single-turn dual circuit, there is no need to arrange a single-turn in the loop-through output circuit. Two circuits can realize the differential structure, which can simplify the circuit structure.
在一种可能的设计中，所述低噪声放大器为差分放大器，所述差分放大器包括第一输入电阻、第一反馈电容、第一反馈电阻、第二输入电阻、第二反馈电容、第二反馈电阻、第一级运算放大器、可调电容和第二级运算放大器；所述第一输入电阻的阻值、所述第一反馈电阻的阻值、所述第二输入电阻的阻值和所述第二反馈电阻的阻值是可调的，用于调整所述差分放大器的增益；其中，所述第一输入电阻的一端为所述差分放大器的一个输入端，所述第一输入电阻的一端与所述单转双电路的一个输出端连接，所述第一输入电阻的另一端分别与第一并联电路的一端、以及所述第一级运算放大器的正相输入端连接，所述第一并联电路为所述第一反馈电容和所述第一反馈电阻组成的并联电路；所述第一级运算放大器的负相输出端分别与所述可调电容的一端、所述第二级运算放大器的正相输入端连接；所述第二级运算放大器的正相输出端与所述第一并联电路的另一端连接；所述第二输入电阻的一端为所述差分放大器的另一个输入端，所述第二输入电阻的一端与所述单转双电路的另一输出端连接，所述第二输入电阻的另一端分别与第二并联电路的一端、以及所述第一级运算放大器的负相输入端连接，所述第二并联电路为所述第二反馈电容和所述第二反馈电阻组成的并联电路；所述第一级运算放大器的正相输出端分别与所述可调电容的另一端、所述第二级运算放大器的负相输入端连接；所述第二级运算放大器的负相输出端与所述第二并联电路的另一端连接。In a possible design, the low-noise amplifier is a differential amplifier, and the differential amplifier includes a first input resistor, a first feedback capacitor, a first feedback resistor, a second input resistor, a second feedback capacitor, and a second feedback Resistor, first-stage operational amplifier, adjustable capacitor, and second-stage operational amplifier; the resistance value of the first input resistance, the resistance value of the first feedback resistance, the resistance value of the second input resistance, and the The resistance of the second feedback resistor is adjustable and is used to adjust the gain of the differential amplifier; wherein one end of the first input resistance is one input end of the differential amplifier and one end of the first input resistance Is connected to one output terminal of the single-turn dual circuit, the other end of the first input resistor is connected to one end of a first parallel circuit and a non-inverting input terminal of the first-stage operational amplifier, and the first The parallel circuit is a parallel circuit composed of the first feedback capacitor and the first feedback resistor; the negative-phase output terminal of the first-stage operational amplifier is connected to one end of the adjustable capacitor, The non-inverting input terminal of the second-stage operational amplifier is connected; the non-inverting output terminal of the second-stage operational amplifier is connected to the other end of the first parallel circuit; one end of the second input resistor is the one of the differential amplifier. The other input end, one end of the second input resistance is connected to the other output end of the single-turn dual circuit, the other end of the second input resistance is connected to one end of a second parallel circuit, and the first The negative-phase input terminal of the first-stage operational amplifier is connected, and the second parallel circuit is a parallel circuit composed of the second feedback capacitor and the second feedback resistor; The other end of the adjustable capacitor is connected to the negative-phase input terminal of the second-stage operational amplifier; the negative-phase output terminal of the second-stage operational amplifier is connected to the other end of the second parallel circuit.
上述的射频接收电路中，有助于实现高线性度。而且，由于本申请实施例中的差分放大器中包括两级运算放大器，第一级放大器用于对信号进行放大，第二级放大器用于提供驱动能力，有助于实现驱动大负载，本申请实施例射频接收电路10采用了全差分结构，有利于提高电路的抗干扰性。In the above-mentioned radio frequency receiving circuit, high linearity is facilitated. Moreover, since the differential amplifier in the embodiment of the present application includes a two-stage operational amplifier, the first-stage amplifier is used to amplify the signal, and the second-stage amplifier is used to provide driving capability, which is helpful to realize driving a large load. The radio frequency receiving circuit 10 adopts a fully differential structure, which is helpful to improve the anti-interference performance of the circuit.
其中，第一环通缓冲器可以用于将环通输出电路与射频接收电路进行隔离。The first loop-through buffer can be used to isolate the loop-through output circuit from the radio frequency receiving circuit.
在一种可能的设计中，所述环通输出电路包括N条支路，所述N条支路并联连接；所述N条支路中的第i条支路，用于对所述第一环通缓冲器输出到所述第i条支路上的信号进行环通输出；其中，所述N为大于或等于1的正整数，所述i为满足1≤i≤N的整数，所述第i条支路为所述N条支路中任一条支路。In a possible design, the loop-through output circuit includes N branches, and the N branches are connected in parallel; an i-th branch among the N branches is used to connect the first branch The signal output by the loop-through buffer to the i-th branch is loop-through output; wherein, N is a positive integer greater than or equal to 1, and i is an integer satisfying 1 ≦ i ≦ N, and the first The i branches are any of the N branches.
在一种可能的设计中，所述环通输出电路包括M条支路；所述第一环通缓冲器包括M个第二环通缓冲器，所述M条支路分别包含一个所述第二环通缓冲器；第k条支路上的所述第二环通缓冲器的输出端与第k+1条支路上的所述第二环通缓冲器的输入端相连，所述第k+1条支路上的所述第二环通缓冲器用于缓存所述第k条支路上的所述第二环通缓冲器的输出端输出的信号；其中，所述M为大于或等于2的正整数，所述k为满足1≤k≤M的整数，所述第k条支路为所述M条支路中任一条支路；所述第k条支路与所述第k+1条支 路为所述M条支路中相邻的两条支路。In a possible design, the loop-through output circuit includes M branches; the first loop-through buffer includes M second loop-through buffers, and each of the M branches includes one The second loop-through buffer; the output end of the second loop-through buffer on the k-th branch is connected to the input end of the second loop-through buffer on the k + 1 branch, and the k + th The second loop-through buffer on one branch is used to buffer a signal output from an output of the second loop-through buffer on the k-th branch; wherein M is a positive value greater than or equal to 2. An integer, where k is an integer satisfying 1≤k≤M, and the k-th branch is any of the M-th branches; the k-th branch and the k + 1-th branch The branches are two adjacent branches among the M branches.
其中，第k条支路上的第二环通缓冲器可以用于将第k条支路与射频接收电路进行隔离。The second loop-through buffer on the k-th branch can be used to isolate the k-th branch from the RF receiving circuit.
在一种可能的设计中，所述第k条支路还包括第二放大器，所述第二放大器的输入端与所述第k条支路上的所述第二环通缓冲器的输出端连接，用于进行信号放大。In a possible design, the k-th branch further includes a second amplifier, and an input end of the second amplifier is connected to an output end of the second loop-through buffer on the k-th branch. For signal amplification.
在一种可能的设计中，所述射频接收电路还包括增益控制器，所述增益控制器用于调节所述第一放大器的增益。In a possible design, the radio frequency receiving circuit further includes a gain controller, and the gain controller is configured to adjust a gain of the first amplifier.
第二方面，本申请实施例提供一种环通输出电路，所述环通输出电路用于对射频接收电路进行环通输出，所述射频接收电路包括低噪声放大器、第一滤波器和第一模数转换器，用于依次对接收到的信号进行放大、滤波和模数转换；所述环通输出电路包括第一环通缓冲器，所述第一环通缓冲器包括电压缓冲电路和反馈电路，所述电压缓冲电路用于对所述第一滤波器的输入端处输出的信号或者所述第一滤波器的输出端处输出的信号进行电压缓冲，所述电压缓冲电路的输出端输出的信号用于进行环通输出，所述反馈电路用于将所述电压缓冲电路的输出端输出的信号反馈到所述电压缓冲电路的输入端，以提高所述电压缓冲电路的环路增益。In a second aspect, an embodiment of the present application provides a loop-through output circuit. The loop-through output circuit is configured to loop-through output a radio frequency receiving circuit. The radio frequency receiving circuit includes a low noise amplifier, a first filter, and a first An analog-to-digital converter for sequentially amplifying, filtering, and analog-to-digital conversion of the received signal; the loop-through output circuit includes a first loop-through buffer, and the first loop-through buffer includes a voltage buffer circuit and a feedback A circuit for voltage buffering a signal output at an input terminal of the first filter or a signal output at an output terminal of the first filter, and an output terminal of the voltage buffer circuit outputs The signal is used for loop-through output, and the feedback circuit is used to feed back the signal output from the output end of the voltage buffer circuit to the input end of the voltage buffer circuit to improve the loop gain of the voltage buffer circuit.
上述的环通输出电路中，在第一环通缓冲器中，可以设计电压缓冲电路和反馈电路依次对第一滤波器的输入端处输出的信号或者第一滤波器的输出端处输出的信号进行电压缓冲和信号反馈。环通缓冲器中的反馈电路可以提高电压缓冲电路的环路增益，降低环通输出电路的输出阻抗，环通输出电路具有更好的线性度性能。则可以无需在环通电路中设置低噪声放大器、混频器、滤波器和可变增益放大器等器件，降低了环通输出电路结构的复杂度。另外，由于输入环通输出电路的信号是经过射频接收电路中可变增益放大器根据模数转换器的输入功率为恒定功率值的原则对信号进行放大得到的，因此，输入环通输出电路的信号可以保证在环通输出电路中模数转换器的输入功率为恒定功率值，无需在环通输出电路中针对低噪声放大器以及可变增益放大器设置不同的增益范围和增益档位。从而降低了环通输出电路结构的复杂度，并降低环通输出电路的功耗。In the above loop-through output circuit, in the first loop-through buffer, a voltage buffer circuit and a feedback circuit may be designed to sequentially output a signal at an input end of the first filter or a signal output at an output end of the first filter. Perform voltage buffering and signal feedback. The feedback circuit in the loop-through buffer can improve the loop gain of the voltage buffer circuit and reduce the output impedance of the loop-through output circuit. The loop-through output circuit has better linearity performance. Then, it is not necessary to set a low-noise amplifier, a mixer, a filter, and a variable gain amplifier in the loop-through circuit, thereby reducing the complexity of the loop-through output circuit structure. In addition, because the signal of the input loop-through output circuit is amplified by the variable gain amplifier in the RF receiving circuit according to the principle that the input power of the analog-to-digital converter is a constant power value, the signal of the input loop-through output circuit It can ensure that the input power of the analog-to-digital converter in the loop-through output circuit is a constant power value, and there is no need to set different gain ranges and gain ranges for the low-noise amplifier and the variable gain amplifier in the loop-through output circuit. This reduces the complexity of the loop-through output circuit structure and reduces the power consumption of the loop-through output circuit.
在一种可能的设计中，所述电压缓冲电路包含源极跟随器，所述反馈电路包含电流镜和第一晶体管；其中：所述第一晶体管的漏极与所述电流镜的输入端耦合，所述电流镜的输出端与所述源极跟随器的源极耦合；所述电流镜和所述第一晶体管用于将所述源极跟随器的输出端输出的信号反馈到所述源极跟随器的输入端，并为所述源极跟随器的源极提供电流偏置。上述的电压缓冲电路中，源极跟随器、电流镜和第一晶体管的结构，可以为环通输出电路提供高输入阻抗和低输出阻抗，可以提高对环通输出电路的驱动能力。另外，通过电流镜和第一晶体管组成的反馈电路可以提高电压缓冲电路的环路增益，降低环通输出电路的输出阻抗，环通输出电路具有更好的线性度性能，则可以满足对第一滤波器的输入端处输出的信号或者第一滤波器的输出端处输出的信号进行环通输出的条件，降低了环通输出电路结构的复杂度。In a possible design, the voltage buffer circuit includes a source follower, and the feedback circuit includes a current mirror and a first transistor; wherein: a drain of the first transistor is coupled to an input terminal of the current mirror An output end of the current mirror is coupled to a source of the source follower; the current mirror and the first transistor are configured to feed back a signal output from the output end of the source follower to the source An input terminal of the electrode follower and provides a current bias for the source of the source follower. In the above voltage buffer circuit, the structure of the source follower, the current mirror, and the first transistor can provide the loop-through output circuit with high input impedance and low output impedance, and can improve the driving ability of the loop-through output circuit. In addition, the feedback circuit composed of the current mirror and the first transistor can improve the loop gain of the voltage buffer circuit and reduce the output impedance of the loop-through output circuit. The loop-through output circuit has better linearity performance, which can meet the The condition that the signal output at the input end of the filter or the signal output at the output end of the first filter performs loop-through output reduces the complexity of the loop-through output circuit structure.
在一种可能的设计中，所述电压缓冲电路用于对所述第一滤波器的输入端处输出的信号进行电压缓冲，所述环通输出电路还包括第二滤波器和第二模数转换器，用于对所述第一环通缓冲器输出的信号进行滤波和模数转换。In a possible design, the voltage buffer circuit is configured to perform voltage buffering on a signal output at an input end of the first filter, and the loop-through output circuit further includes a second filter and a second modulus. A converter for filtering and analog-to-digital conversion of a signal output by the first loop-through buffer.
在一种可能的设计中，所述电压缓冲电路用于对所述第一滤波器的输出端处输出的信号进行电压缓冲，所述环通输出电路还包括第三模数转换器，用于对所述第一环通缓冲器输出的信号进行模数转换。In a possible design, the voltage buffer circuit is used for voltage buffering a signal output at an output end of the first filter, and the loop-through output circuit further includes a third analog-to-digital converter for Performing analog-to-digital conversion on a signal output by the first loop-through buffer.
其中，射频接收电路可以是窄带射频接收电路，也可以是全频带射频接收电路。The radio frequency receiving circuit may be a narrow-band radio frequency receiving circuit or a full-band radio frequency receiving circuit.
其中，第一放大器的增益可以是可调的，用于保证第一模数转换器接收到的模拟信号的功率为恒定的。The gain of the first amplifier may be adjustable to ensure that the power of the analog signal received by the first analog-to-digital converter is constant.
可选的，第一放大器可以是PGA。第一滤波器可以是抗混叠滤波器AAF，也可以是低通滤波器LPF。Optionally, the first amplifier may be a PGA. The first filter may be an anti-aliasing filter AAF or a low-pass filter LPF.
可选的，第一滤波器和第二滤波器可以是低通滤波器。Optionally, the first filter and the second filter may be low-pass filters.
在一种可能的设计中，所述射频接收电路还包括单转双电路；所述单转双电路用于接收射频信号，将所述射频信号转换为差分信号输出到所述低噪声放大器；在所述环通输出电路中，所述第一环通缓冲器包括第一部分和第二部分，所述第一环通缓冲器的第一部分和所述第一环通缓冲器的第二部分均包含所述电压缓冲电路和所述反馈电路；所述第一环通缓冲器的第一部分和所述第一环通缓冲器的第二部分分别用于对所述第一滤波器的输入端处输出的两路差分信号或者所述第一滤波器的输出端处输出的两路差分信号进行处理。上述的方案中，可以为环通输出电路提供高输入阻抗和低输出阻抗，可以提高对环通输出电路的驱动能力。另外，通过电流镜和第一晶体管组成的反馈电路可以提高电压缓冲电路的环路增益，降低环通输出电的输出阻抗，环通输出电路具有更好的线性度性能。环通输出电路接收的信号为差分信号，能够降低处理过程中信号之间的相互干扰，进而有助于避免各个频道上的信号失真，能够向电视设备输出图像和伴音质量更高的信号。In a possible design, the radio frequency receiving circuit further includes a single-turn dual circuit; the single-turn dual circuit is configured to receive a radio frequency signal, convert the radio frequency signal into a differential signal, and output the signal to the low noise amplifier; In the loop-through output circuit, the first loop-through buffer includes a first portion and a second portion, and the first portion of the first loop-through buffer and the second portion of the first loop-through buffer include The voltage buffer circuit and the feedback circuit; the first part of the first loop-through buffer and the second part of the first loop-through buffer are respectively used to output to the input end of the first filter And processing the two differential signals of the two or the two differential signals output at the output end of the first filter. In the above solution, the loop-through output circuit can be provided with high input impedance and low output impedance, and the driving capability of the loop-through output circuit can be improved. In addition, the feedback circuit composed of the current mirror and the first transistor can improve the loop gain of the voltage buffer circuit, reduce the output impedance of the loop-through output power, and the loop-through output circuit has better linearity performance. The signal received by the loop-through output circuit is a differential signal, which can reduce mutual interference between the signals during processing, thereby helping to avoid signal distortion on each channel, and can output a higher-quality image and sound signal to the television device.
可选的，可以从单转差电路的输出端引出环通输出电路。环通输出电路中每个元件处理的信号均为差分信号，每个元件输出的信号也均为差分信号。环通输出电路还可以包括第三放大器、第四放大器和第二滤波器，第三放大器、第四放大器、第二滤波器和第二模数转换器依次连接，用于依次将从所述单转双电路的输出端输出的差分信号进行低噪声放大、放大、模数转换。上述的环通输出电路中采用差分结构，可以提高环通输出电路的抗干扰能力，且由于是从单转双电路的输出端引出环通输出电路，因此无需在环通输出电路中布局单转双电路即可实现差分结构，可以简化电路结构。Optionally, a loop-through output circuit can be derived from the output of the single slip circuit. The signals processed by each element in the loop-through output circuit are differential signals, and the signals output by each element are also differential signals. The loop-through output circuit may further include a third amplifier, a fourth amplifier, and a second filter. The third amplifier, the fourth amplifier, the second filter, and the second analog-to-digital converter are connected in sequence, and are used to sequentially connect the The differential signal output from the output of the double circuit is subjected to low noise amplification, amplification, and analog-to-digital conversion. The above-mentioned loop-through output circuit adopts a differential structure, which can improve the anti-interference ability of the loop-through output circuit, and because the loop-through output circuit is derived from the output of the single-turn dual circuit, there is no need to arrange a single-turn in the loop-through output circuit. Two circuits can realize the differential structure, which can simplify the circuit structure.
在一种可能的设计中，所述低噪声放大器为差分放大器，所述差分放大器包括第一输入电阻、第一反馈电容、第一反馈电阻、第二输入电阻、第二反馈电容、第二反馈电阻、第一级运算放大器、可调电容和第二级运算放大器；所述第一输入电阻的阻值、所述第一反馈电阻的阻值、所述第二输入电阻的阻值和所述第二反馈电阻的阻值是可调的，用于调整所述差分放大器的增益；其中，所述第一输入电阻的一端为所述差分放大器的一个输入端，所述第一输入电阻的一端与所述单转双电路的一个输出端连接，所述第一输入电阻的另一端分别与第一并联电路的一端、以及所述第一级运算放大器的正相输入端连接，所述第一并联电路为所述第一反馈电容和所述第一反馈电阻组成的并联电路；所述第一级运算放大器的负相输出端分别与所述可调电容的一端、所述第二级运算放大器的正相输入端连接；所述第二级运算放大器的正相输出端与所述第一并联电路的另一端连接；所述第二输入电阻的一端为所述差分放大器的另一个输入端，所述第二输入电阻的一端与所述单转双 电路的另一输出端连接，所述第二输入电阻的另一端分别与第二并联电路的一端、以及所述第一级运算放大器的负相输入端连接，所述第二并联电路为所述第二反馈电容和所述第二反馈电阻组成的并联电路；所述第一级运算放大器的正相输出端分别与所述可调电容的另一端、所述第二级运算放大器的负相输入端连接；所述第二级运算放大器的负相输出端与所述第二并联电路的另一端连接。In a possible design, the low-noise amplifier is a differential amplifier, and the differential amplifier includes a first input resistor, a first feedback capacitor, a first feedback resistor, a second input resistor, a second feedback capacitor, and a second feedback Resistor, first-stage operational amplifier, adjustable capacitor, and second-stage operational amplifier; the resistance value of the first input resistance, the resistance value of the first feedback resistance, the resistance value of the second input resistance, and the The resistance of the second feedback resistor is adjustable and is used to adjust the gain of the differential amplifier; wherein one end of the first input resistance is one input end of the differential amplifier and one end of the first input resistance Is connected to one output terminal of the single-turn dual circuit, the other end of the first input resistor is connected to one end of a first parallel circuit and a non-inverting input terminal of the first-stage operational amplifier, and the first The parallel circuit is a parallel circuit composed of the first feedback capacitor and the first feedback resistor; the negative-phase output terminal of the first-stage operational amplifier is connected to one end of the adjustable capacitor, The non-inverting input terminal of the second-stage operational amplifier is connected; the non-inverting output terminal of the second-stage operational amplifier is connected to the other end of the first parallel circuit; one end of the second input resistor is the one of the differential amplifier. The other input end, one end of the second input resistance is connected to the other output end of the single-turn dual circuit, the other end of the second input resistance is connected to one end of a second parallel circuit, and the first The negative-phase input terminal of the first-stage operational amplifier is connected, and the second parallel circuit is a parallel circuit composed of the second feedback capacitor and the second feedback resistor; The other end of the adjustable capacitor is connected to the negative-phase input terminal of the second-stage operational amplifier; the negative-phase output terminal of the second-stage operational amplifier is connected to the other end of the second parallel circuit.
上述的射频接收电路中，有助于实现高线性度。而且，由于本申请实施例中的差分放大器中包括两级运算放大器，第一级放大器用于对信号进行放大，第二级放大器用于提供驱动能力，有助于实现驱动大负载，本申请实施例射频接收电路10采用了全差分结构，有利于提高电路的抗干扰性。In the above-mentioned radio frequency receiving circuit, high linearity is facilitated. Moreover, since the differential amplifier in the embodiment of the present application includes a two-stage operational amplifier, the first-stage amplifier is used to amplify the signal, and the second-stage amplifier is used to provide driving capability, which is helpful to realize driving a large load. The radio frequency receiving circuit 10 adopts a fully differential structure, which is helpful to improve the anti-interference performance of the circuit.
其中，第一环通缓冲器可以用于将环通输出电路与射频接收电路进行隔离。The first loop-through buffer can be used to isolate the loop-through output circuit from the radio frequency receiving circuit.
在一种可能的设计中，所述环通输出电路包括N条支路，所述N条支路并联连接；所述N条支路中的第i条支路，用于对所述第一环通缓冲器输出到所述第i条支路上的信号进行环通输出；其中，所述N为大于或等于1的正整数，所述i为满足1≤i≤N的整数，所述第i条支路为所述N条支路中任一条支路。In a possible design, the loop-through output circuit includes N branches, and the N branches are connected in parallel; an i-th branch among the N branches is used to connect the first branch The signal output by the loop-through buffer to the i-th branch is loop-through output; wherein, N is a positive integer greater than or equal to 1, and i is an integer satisfying 1 ≦ i ≦ N, and the first The i branches are any of the N branches.
在一种可能的设计中，所述环通输出电路包括M条支路；所述第一环通缓冲器包括M个第二环通缓冲器，所述M条支路分别包含一个所述第二环通缓冲器；第k条支路上的所述第二环通缓冲器的输出端与第k+1条支路上的所述第二环通缓冲器的输入端相连，所述第k+1条支路上的所述第二环通缓冲器用于缓存所述第k条支路上的所述第二环通缓冲器的输出端输出的信号；其中，所述M为大于或等于2的正整数，所述k为满足1≤k≤M的整数，所述第k条支路为所述M条支路中任一条支路；所述第k条支路与所述第k+1条支路为所述M条支路中相邻的两条支路。In a possible design, the loop-through output circuit includes M branches; the first loop-through buffer includes M second loop-through buffers, and each of the M branches includes one The second loop-through buffer; the output end of the second loop-through buffer on the k-th branch is connected to the input end of the second loop-through buffer on the k + 1 branch, and the k + th The second loop-through buffer on one branch is used to buffer a signal output from an output of the second loop-through buffer on the k-th branch; wherein M is a positive value greater than or equal to 2. An integer, where k is an integer satisfying 1≤k≤M, and the k-th branch is any of the M-th branches; the k-th branch and the k + 1-th branch The branches are two adjacent branches among the M branches.
在一种可能的设计中，所述第k条支路还包括第二放大器，所述第k条支路还包括第二放大器，所述第二放大器的输入端与所述第k条支路上的所述第二环通缓冲器的输出端连接，用于进行信号放大。In a possible design, the k-th branch further includes a second amplifier, the k-th branch further includes a second amplifier, and an input end of the second amplifier is in connection with the k-th branch The output end of the second loop-through buffer is connected for signal amplification.
第三方面，本申请实施例提供一种机顶盒，所述机顶盒包含第二方面或第二方面任一种可能的电视调谐器。In a third aspect, an embodiment of the present application provides a set-top box, where the set-top box includes the second aspect or any possible television tuner in the second aspect.
第四方面，本申请实施例提供一种射频接收***，所述射频接收***包括射频接收设备和环通输出设备；其中：所述射频接收设备包含第二方面或第二方面任一种可能的电视调谐器所提供的射频接收电路，所述环通输出设备包含第二方面或第二方面任一种可能的电视调谐器所提供的环通输出电路。In a fourth aspect, an embodiment of the present application provides a radio frequency receiving system, where the radio frequency receiving system includes a radio frequency receiving device and a loop-through output device; wherein the radio frequency receiving device includes the second aspect or any one of the second aspect. The radio frequency receiving circuit provided by the television tuner, and the loop-through output device includes the loop-through output circuit provided by the second aspect or any one of the possible television tuners of the second aspect.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
下面对本申请实施例涉及的附图进行介绍。The drawings related to the embodiments of the present application are described below.
图1是本申请实施例提供的一种射频接收电路和环通输出电路的结构示意图；1 is a schematic structural diagram of a radio frequency receiving circuit and a loop-through output circuit according to an embodiment of the present application;
图2是本申请实施例提供的另一种射频接收电路和环通输出电路的结构示意图；2 is a schematic structural diagram of another radio frequency receiving circuit and a loop-through output circuit according to an embodiment of the present application;
图3是本申请实施例提供的又一种射频接收电路和环通输出电路的结构示意图；3 is a schematic structural diagram of still another RF receiving circuit and a loop-through output circuit according to an embodiment of the present application;
图4是本申请实施例提供的一种第一环通缓冲器的结构示意图；4 is a schematic structural diagram of a first loop-through buffer provided by an embodiment of the present application;
图5是本申请实施例提供的再一种射频接收电路和环通输出电路的结构示意图；5 is a schematic structural diagram of still another radio frequency receiving circuit and a loop-through output circuit according to an embodiment of the present application;
图6是本申请实施例提供的再一种射频接收电路和环通输出电路的结构示意图；6 is a schematic structural diagram of still another radio frequency receiving circuit and a loop-through output circuit according to an embodiment of the present application;
图7是本申请实施例提供的再一种射频接收电路和环通输出电路的结构示意图；7 is a schematic structural diagram of still another radio frequency receiving circuit and a loop-through output circuit according to an embodiment of the present application;
图8是本申请实施例提供的另一种第一环通缓冲器的结构示意图；8 is a schematic structural diagram of another first loop-through buffer according to an embodiment of the present application;
图9是本申请实施例提供的一种低噪声放大器的结构示意图；9 is a schematic structural diagram of a low-noise amplifier according to an embodiment of the present application;
图10是本申请实施例提供的一种环通输出电路的结构示意图；10 is a schematic structural diagram of a loop-through output circuit according to an embodiment of the present application;
图11是本申请实施例提供的另一种环通输出电路的结构示意图；11 is a schematic structural diagram of another loop-through output circuit according to an embodiment of the present application;
图12是本申请实施例提供的又一种环通输出电路的结构示意图；12 is a schematic structural diagram of still another loop-through output circuit according to an embodiment of the present application;
图13是本申请实施例提供的再一种环通输出电路的结构示意图；13 is a schematic structural diagram of still another loop-through output circuit according to an embodiment of the present application;
图14是本申请实施例提供的再一种环通输出电路的结构示意图。FIG. 14 is a schematic structural diagram of still another loop-through output circuit according to an embodiment of the present application.
具体实施方式detailed description
下面结合本申请实施例中的附图对本申请实施例进行描述。本申请实施例的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释，而非旨在限定本申请。The following describes the embodiments of the present application with reference to the drawings in the embodiments of the present application. The terms used in the implementation part of the examples of the application are only used to explain specific examples of the application, and are not intended to limit the application.
请参见图1，图1是本申请实施例提供的一种射频接收电路10和环通输出电路20的结构示意图。射频接收电路10可以用于接收射频信号，并将射频信号转换为数字信号，以便设备可以进行信号的解调并处理。该射频接收电路10可以用于电视调谐器，电视调谐器可以接收RF形式的视频信号。RF形式的视频信号例如可以是电磁波形式的***信号或者电磁波形式的广播电视信号。Please refer to FIG. 1, which is a schematic structural diagram of a radio frequency receiving circuit 10 and a loop-through output circuit 20 according to an embodiment of the present application. The radio frequency receiving circuit 10 can be used for receiving radio frequency signals and converting the radio frequency signals into digital signals so that the device can demodulate and process the signals. The radio frequency receiving circuit 10 can be used in a television tuner, and the television tuner can receive a video signal in an RF form. The video signal in the RF format may be, for example, a satellite television signal in the form of electromagnetic waves or a broadcast television signal in the form of electromagnetic waves.
如图1所示，射频接收电路10可以包括天线100、低噪声放大器(low noise amplifier，LNA)200、混频器(mixer)300、可变增益放大器(variable gain amplifier，VGA)400、低通滤波器(low pass filter，LPF)500和模数转换器(analog-to-digital converter，ADC)600。天线100、低噪声放大器200、混频器300、低通滤波器400、可变增益放大器500和模数转换器600依次串联。As shown in FIG. 1, the radio frequency receiving circuit 10 may include an antenna 100, a low noise amplifier (LNA) 200, a mixer 300, a variable gain amplifier (VGA) 400, and a low-pass amplifier. A low-pass filter (LPF) 500 and an analog-to-digital converter (ADC) 600. The antenna 100, the low noise amplifier 200, the mixer 300, the low-pass filter 400, the variable gain amplifier 500, and the analog-to-digital converter 600 are connected in series in this order.
其中，天线100可以用于接收射频信号。射频信号可以是电视信号，也可以是其他信号，例如监控视频信号等，本申请实施例对天线接收的射频信号不作限定。低噪声放大器200可以用于对天线100输出的信号进行低噪声放大，来提高信号的抗噪声能力。混频器300可以用于降低接收到的高频信号的频率，将需要的信号搬移到中频处。可变增益放大器400可以用于对混频器300输出的信号进行放大，以满足模数转换器600接收到的信号的功率要求。低通滤波器500可以用于对可变增益放大器400输出的信号进行低通滤波，选出需要的频带处的信号。模数转换器600可以用于将从可变增益放大器500接收到的模拟信号进行模数转换得到数字信号，以便后续进行信号解调。其中，低噪声放大器200和可变增益放大器400的增益均可以是可调的，用于使模数转换器600接收到的模拟信号的功率恒定。The antenna 100 can be used to receive radio frequency signals. The radio frequency signal may be a television signal or other signals, such as a monitoring video signal, and the embodiment of the present application does not limit the radio frequency signal received by the antenna. The low-noise amplifier 200 may be used for low-noise amplification of a signal output by the antenna 100 to improve the anti-noise capability of the signal. The mixer 300 may be used to reduce the frequency of the received high-frequency signal and move the required signal to an intermediate frequency. The variable gain amplifier 400 can be used to amplify the signal output from the mixer 300 to meet the power requirement of the signal received by the analog-to-digital converter 600. The low-pass filter 500 may be used to perform low-pass filtering on a signal output from the variable gain amplifier 400 to select a signal at a required frequency band. The analog-to-digital converter 600 may be configured to perform analog-to-digital conversion on an analog signal received from the variable gain amplifier 500 to obtain a digital signal, so as to perform signal demodulation in the future. Wherein, the gains of the low noise amplifier 200 and the variable gain amplifier 400 may be adjustable, so as to make the power of the analog signal received by the analog-to-digital converter 600 constant.
在对电视信号进行接收和处理的过程中，环通输出电路20可以实现将一路视频信号输送给多个电视设备使用。可以从低噪声放大器200的输入端处或者输出端处引出环通输出电路20，这是由于越靠近射频前端输出的信号对信号的非线性要求越低。During the process of receiving and processing TV signals, the loop-through output circuit 20 can realize the transmission of one video signal to multiple TV devices. The loop-through output circuit 20 can be derived from the input end or output end of the low-noise amplifier 200, because the closer the signal output from the RF front-end is, the lower the non-linearity of the signal is.
如图1所示，本申请实施例以从低噪声放大器200的输入端处引出环通输出电路为例进行介绍。环通输出电路20可以包含依次串联的低噪声放大器201、混频器202、可变增 益放大器203、低通滤波器204和模数转换器205。另外，如图1所示，环通输出电路20还可以包括环通缓冲器(LTbuffer)206，环通缓冲器206的输入端与低噪声放大器200的输入端连接，环通缓冲器206的输出端与低噪声放大器201的输入端连接。环通缓冲器206可以用于将环通输出电路20与射频接收电路10进行隔离。As shown in FIG. 1, the embodiment of the present application is described by taking a loop-through output circuit as an example from the input end of the low-noise amplifier 200. The loop-through output circuit 20 may include a low-noise amplifier 201, a mixer 202, a variable gain amplifier 203, a low-pass filter 204, and an analog-to-digital converter 205 in series. In addition, as shown in FIG. 1, the loop-through output circuit 20 may further include a loop-through buffer (LTbuffer) 206. The input of the loop-through buffer 206 is connected to the input of the low-noise amplifier 200. The output of the loop-through buffer 206 The terminal is connected to the input terminal of the low-noise amplifier 201. The loop-through buffer 206 may be used to isolate the loop-through output circuit 20 from the radio frequency receiving circuit 10.
本申请实施例中，射频接收电路10和环通输出电路20可以是包含在电视调谐器中，射频接收电路10和环通输出电路20可以是同一芯片实现的，也可以是不同的芯片实现的，本申请实施例对此不作限定。In the embodiment of the present application, the radio frequency receiving circuit 10 and the loop-through output circuit 20 may be included in a television tuner. The radio frequency receiving circuit 10 and the loop-through output circuit 20 may be implemented by the same chip, or may be implemented by different chips. This is not limited in the embodiments of the present application.
然而，从低噪声放大器200的输入端处引出的环通输出电路20中，在将信号输入电视设备之前，仍然需要使用环通输出电路中与射频接收电路类似的电路结构，对信号进行放大、混频、滤波和模数转换处理，从而增加了环通输出电路结构的复杂度。另外，为保证环通输出电路中模数转换器的输入功率为恒定功率值，也需要在环通输出电路20中针对低噪声放大器201以及可变增益放大器203设置不同的增益范围和增益档位，进一步提高了环通输出电路结构的复杂度和环通输出电路的功耗。However, in the loop-through output circuit 20 derived from the input of the low-noise amplifier 200, before the signal is input to the television device, it is still necessary to use a circuit structure similar to the radio frequency receiving circuit in the loop-through output circuit to amplify the signal, Mixing, filtering, and analog-to-digital conversion processing, thereby increasing the complexity of the loop-through output circuit structure. In addition, in order to ensure that the input power of the analog-to-digital converter in the loop-through output circuit is a constant power value, it is also necessary to set different gain ranges and gain ranges for the low-noise amplifier 201 and the variable gain amplifier 203 in the loop-through output circuit 20. , Further increasing the complexity of the loop-through output circuit structure and the power consumption of the loop-through output circuit.
基于上述图1的射频接收电路10和环通输出电路20的结构示意图，本申请实施例提供了一种环通输出电路，可以降低环通电路结构的复杂度，并减少环通输出电路的功耗。Based on the schematic structural diagram of the radio frequency receiving circuit 10 and the loop-through output circuit 20 of FIG. 1, the embodiment of the present application provides a loop-through output circuit, which can reduce the complexity of the loop-through circuit structure and reduce the power of the loop-through output circuit. Consuming.
本申请涉及的主要原理可包括：在设计的环通缓冲器(前后文中的第一环通缓冲器206)中，可以设计电压缓冲电路和反馈电路依次对第一滤波器的输入端处输出的信号或者第一滤波器的输出端处输出的信号进行电压缓冲和信号反馈。环通缓冲器中的反馈电路可以提高电压缓冲电路的环路增益，降低环通输出电路的输出阻抗，环通输出电路具有更好的线性度性能。则可以从射频接收电路的滤波器(即前后文中的第一滤波器)的输入端处或者滤波器的输出端处(也即是模数转换器的输入端处)引出环通输出电路。则输入环通输出电路的信号无需进行放大、混频和滤波处理，环通输出电路仅包含模数转换器，即可以将接收到的信号转换为数字信号供信号解调。无需在环通电路中设置低噪声放大器、混频器、滤波器和可变增益放大器等器件，降低了环通输出电路结构的复杂度。另外，由于输入环通输出电路的信号是经过射频接收电路中可变增益放大器根据模数转换器的输入功率为恒定功率值的原则对信号进行放大得到的，因此，输入环通输出电路的信号可以保证在环通输出电路中模数转换器的输入功率为恒定功率值，无需在环通输出电路中针对低噪声放大器以及可变增益放大器设置不同的增益范围和增益档位。从而降低了环通输出电路结构的复杂度，并降低环通输出电路的功耗。The main principles involved in this application may include: In the designed loop-through buffer (the first loop-through buffer 206 in the preceding text), a voltage buffer circuit and a feedback circuit may be designed to sequentially output the voltage at the input end of the first filter. The signal or the signal output at the output of the first filter performs voltage buffering and signal feedback. The feedback circuit in the loop-through buffer can improve the loop gain of the voltage buffer circuit and reduce the output impedance of the loop-through output circuit. The loop-through output circuit has better linearity performance. The loop-through output circuit can be derived from the input end of the filter of the radio frequency receiving circuit (that is, the first filter in the preceding text) or the output end of the filter (that is, the input end of the analog-to-digital converter). The signal input to the loop-through output circuit does not need to be amplified, mixed, and filtered. The loop-through output circuit only includes an analog-to-digital converter, that is, the received signal can be converted into a digital signal for signal demodulation. There is no need to set low-noise amplifiers, mixers, filters, and variable gain amplifiers in the loop-through circuit, which reduces the complexity of the loop-through output circuit structure. In addition, because the signal of the input loop-through output circuit is amplified by the variable gain amplifier in the RF receiving circuit according to the principle that the input power of the analog-to-digital converter is a constant power value, the signal of the input loop-through output circuit It can ensure that the input power of the analog-to-digital converter in the loop-through output circuit is a constant power value, and there is no need to set different gain ranges and gain ranges for the low-noise amplifier and the variable gain amplifier in the loop-through output circuit. This reduces the complexity of the loop-through output circuit structure and reduces the power consumption of the loop-through output circuit.
基于上述的主要原理，下面说明本申请提供的几个实施例。Based on the above main principles, several embodiments provided in the present application are described below.
基于图1所描述的射频接收电路10和环通输出电路20，请一并参阅图2和图3，图2是本申请实施例提供的另一种射频接收电路10和环通输出电路20的结构示意图。图3是本申请实施例提供的又一种射频接收电路10和环通输出电路20的结构示意图。Based on the RF receiving circuit 10 and the loop-through output circuit 20 described in FIG. 1, please refer to FIG. 2 and FIG. 3 together. FIG. 2 is another RF receiving circuit 10 and the loop-through output circuit 20 provided in the embodiment of the present application. Schematic. FIG. 3 is a schematic structural diagram of still another RF receiving circuit 10 and a loop-through output circuit 20 according to an embodiment of the present application.
如图2和图3所示，射频接收电路10可以包含低噪声放大器101、第一滤波器102和第一模数转换器103，低噪声放大器101、第一滤波器102和第一模数转换器103依次连接，用于依次对接收到的信号进行放大、滤波和模数转换。关于低噪声放大器101的描述可以 参考图1所描述的射频接收电路10中低噪声放大器200的具体描述，关于第一滤波器102和第一模数转换器103的描述可以参考图1所描述的射频接收电路10中低通滤波器400和模数转换器600的具体描述，这里不再赘述。As shown in FIGS. 2 and 3, the RF receiving circuit 10 may include a low-noise amplifier 101, a first filter 102, and a first analog-to-digital converter 103, a low-noise amplifier 101, a first filter 102, and a first analog-to-digital conversion. The processors 103 are connected in order to amplify, filter, and analog-to-digital convert the received signals in sequence. For the description of the low-noise amplifier 101, refer to the specific description of the low-noise amplifier 200 in the radio frequency receiving circuit 10 described in FIG. 1, and for the description of the first filter 102 and the first analog-to-digital converter 103, refer to the description in FIG. The detailed description of the low-pass filter 400 and the analog-to-digital converter 600 in the radio frequency receiving circuit 10 will not be repeated here.
如图2和图3所示，环通输出电路20还可以包括第一环通缓冲器206，第一环通缓冲器206可以包括电压缓冲电路2061和反馈电路2062，电压缓冲电路2061用于对第一滤波器102的输入端处输出的信号或者第一滤波器103的输出端处输出的信号进行电压缓冲，电压缓冲电路2061的输出端输出的信号用于进行环通输出，反馈电路2062用于将电压缓冲电路2061的输出端输出的信号反馈到电压缓冲电路2062的输入端，以提高电压缓冲电路2061的环路增益。As shown in FIGS. 2 and 3, the loop-through output circuit 20 may further include a first loop-through buffer 206. The first loop-through buffer 206 may include a voltage buffer circuit 2061 and a feedback circuit 2062. The voltage buffer circuit 2061 is used for The signal output at the input of the first filter 102 or the signal output at the output of the first filter 103 performs voltage buffering. The signal output from the output of the voltage buffer circuit 2061 is used for loop-through output, and the feedback circuit 2062 uses The signal output from the output terminal of the voltage buffer circuit 2061 is fed back to the input terminal of the voltage buffer circuit 2062 to improve the loop gain of the voltage buffer circuit 2061.
第一环通缓冲器206中的反馈电路2062可以提高电压缓冲电路2061的增益。反馈电路2062的增加还可以降低环通输出电路20的输出阻抗，从而可以为环通输出电路20提供高输入阻抗和低输出阻抗，可以提高对环通输出电路的驱动能力，环通输出电路20具有更好的线性度性能。则可以满足对第一滤波器102的输入端处输出的信号或者第一滤波器102的输出端处输出的信号进行环通输出的条件。输入环通输出电路20的信号无需进行放大、混频和滤波处理，环通输出电路20可以仅包含模数转换器，即可以将接收到的信号转换为数字信号供信号解调。无需在环通电路20中设置低噪声放大器、混频器、滤波器和可变增益放大器等器件，降低了环通输出电路20结构的复杂度。另外，由于输入环通输出电路20的信号是经过射频接收电路10中可变增益放大器根据模数转换器的输入功率为恒定功率值的原则对信号进行放大得到的，因此，输入环通输出电路10的信号可以保证在环通输出电路20中模数转换器的输入功率为恒定功率值，无需在环通输出电路20中针对低噪声放大器以及可变增益放大器设置不同的增益范围和增益档位。从而降低了环通输出电路20结构的复杂度，并降低环通输出电路20的功耗。The feedback circuit 2062 in the first loop-through buffer 206 can increase the gain of the voltage buffer circuit 2061. The addition of the feedback circuit 2062 can also reduce the output impedance of the loop-through output circuit 20, thereby providing the loop-through output circuit 20 with a high input impedance and a low output impedance, which can improve the driving ability of the loop-through output circuit. Has better linearity performance. Then, a condition that the signals output at the input end of the first filter 102 or the signals output at the output end of the first filter 102 are loop-through output can be satisfied. The signal input to the loop-through output circuit 20 does not need to be amplified, mixed, and filtered. The loop-through output circuit 20 may include only an analog-to-digital converter, that is, the received signal may be converted into a digital signal for signal demodulation. There is no need to provide a low-noise amplifier, a mixer, a filter, a variable gain amplifier, and other components in the loop-through circuit 20, which reduces the structural complexity of the loop-through output circuit 20. In addition, since the signal of the input loop-through output circuit 20 is amplified by the variable gain amplifier in the radio frequency receiving circuit 10 according to the principle that the input power of the analog-to-digital converter is a constant power value, the input loop-through output circuit A signal of 10 can ensure that the input power of the analog-to-digital converter in the loop-through output circuit 20 is a constant power value. There is no need to set different gain ranges and gain ranges for the low-noise amplifier and variable gain amplifier in the loop-through output circuit 20. . As a result, the complexity of the loop-through output circuit 20 is reduced, and the power consumption of the loop-through output circuit 20 is reduced.
如图2所示，可以从第一滤波器102的输出端处引出环通输出电路20，环通输出电路20包括第三模数转换器205，用于将从第一滤波器102的输出端输出的信号进行模数转换。第三模数转换器205输出的信号可以用于解调器(demod)进行信号解调。As shown in FIG. 2, a loop-through output circuit 20 can be derived from an output terminal of the first filter 102. The loop-through output circuit 20 includes a third analog-to-digital converter 205 for outputting from the output terminal of the first filter 102. The output signal undergoes analog-to-digital conversion. The signal output by the third analog-to-digital converter 205 may be used for demodulation by a demodulator (demod).
如图2所示，第一环通缓冲器206的输入端与第一滤波器102的输出端连接，第一环通缓冲器206的输出端与第二模数转换器205的输入端连接。第一环通缓冲器206可以用于将环通输出电路20与射频接收电路10进行隔离。As shown in FIG. 2, the input terminal of the first loop-through buffer 206 is connected to the output terminal of the first filter 102, and the output terminal of the first loop-through buffer 206 is connected to the input terminal of the second analog-to-digital converter 205. The first loop-through buffer 206 may be used to isolate the loop-through output circuit 20 from the radio frequency receiving circuit 10.
图2和所描述的环通输出电路20中，无需在环通电路20中设置低噪声放大器、滤波器和可变增益放大器等器件，降低了环通输出电路结构的复杂度和环通输出电路的功耗。另外，由于输入环通输出电路20的信号是经过射频接收电路10中低噪声放大器101根据第一模数转换器103的输入功率为恒定功率值的原则对信号进行放大得到的，因此，输入环通输出电路20的信号可以保证在环通输出电路20中第二模数转换器206的输入功率为恒定功率值，无需在环通输出电路20中针对放大器设置不同的增益范围和增益档位，从而降低了环通输出电路20结构的复杂度和环通输出电路的功耗。In FIG. 2 and the described loop-through output circuit 20, there is no need to provide low-noise amplifiers, filters, and variable gain amplifiers in the loop-through circuit 20, which reduces the complexity of the loop-through output circuit structure and the loop-through output circuit. Power consumption. In addition, since the signal of the input loop-through output circuit 20 is amplified by the low-noise amplifier 101 in the radio frequency receiving circuit 10 according to the principle that the input power of the first analog-to-digital converter 103 is a constant power value, the input loop The signal of the pass-through output circuit 20 can ensure that the input power of the second analog-to-digital converter 206 in the loop-through output circuit 20 is a constant power value, and it is not necessary to set different gain ranges and gain ranges for the amplifier in the loop-through output circuit 20, As a result, the complexity of the loop-through output circuit 20 and the power consumption of the loop-through output circuit are reduced.
可选的，如图3所示，可以从第一滤波器102的输入端处引出环通输出电路20，环通输出电路20可以包括第二滤波器204和第二模数转换器205。第二滤波器204和第二模数转换器205依次连接，用于将第一滤波器102的输入端输出的信号进行滤波和模数转换。 第二模数转换器205输出的信号可以用于解调器(demod)进行信号解调。其中，关于图3中射频接收电路10和环通输出电路20的具体描述可以参考图2所描述的射频接收电路10和环通输出电路20，这里不再赘述。Optionally, as shown in FIG. 3, the loop-through output circuit 20 may be derived from the input end of the first filter 102. The loop-through output circuit 20 may include a second filter 204 and a second analog-to-digital converter 205. The second filter 204 and the second analog-to-digital converter 205 are connected in sequence, and are used for filtering and analog-to-digital conversion of a signal output from the input end of the first filter 102. The signal output by the second analog-to-digital converter 205 can be used for demodulation by a demodulator (demod). For specific descriptions of the RF receiving circuit 10 and the loop-through output circuit 20 in FIG. 3, reference may be made to the RF receiving circuit 10 and the loop-through output circuit 20 described in FIG. 2, and details are not described herein again.
图3所描述的环通输出电路20中，无需在环通电路20中设置低噪声放大器和可变增益放大器等器件，降低了环通输出电路结构的复杂度和环通输出电路的功耗。另外，由于输入环通输出电路20的信号是经过射频接收电路10中低噪声放大器101根据第一模数转换器103的输入功率为恒定功率值的原则对信号进行放大得到的，因此，输入环通输出电路20的信号可以保证在环通输出电路20中第二模数转换器205的输入功率为恒定功率值，无需在环通输出电路20中针对放大器设置不同的增益范围和增益档位，从而降低了环通输出电路20结构的复杂度和环通输出电路的功耗。In the loop-through output circuit 20 described in FIG. 3, there is no need to provide a low-noise amplifier and a variable gain amplifier in the loop-through circuit 20, which reduces the complexity of the loop-through output circuit structure and the power consumption of the loop-through output circuit. In addition, since the signal of the input loop-through output circuit 20 is amplified by the low-noise amplifier 101 in the radio frequency receiving circuit 10 according to the principle that the input power of the first analog-to-digital converter 103 is a constant power value, the input loop The signal of the pass-through output circuit 20 can ensure that the input power of the second analog-to-digital converter 205 in the loop-through output circuit 20 is a constant power value. There is no need to set different gain ranges and gain ranges for the amplifier in the loop-through output circuit 20, As a result, the complexity of the loop-through output circuit 20 and the power consumption of the loop-through output circuit are reduced.
其中，在图2和图3所描述的电路结构中，低噪声放大器101的增益可以是可调的，用于保证第一模数转换器103接收到的模拟信号的功率为恒定的。低噪声放大器101可以是可编程增益放大器(programmable gain amplifier，PGA)。第一滤波器102可以是抗混叠滤波器(anti-aliasing filter，AAF)，也可以是低通滤波器(low pass flter，LPF)，本申请实施例对此不作限定。本申请实施例中涉及到的滤波器通常情况下为低通滤波器，但本申请实施例对此不作限定。In the circuit structures described in FIG. 2 and FIG. 3, the gain of the low-noise amplifier 101 may be adjustable to ensure that the power of the analog signal received by the first analog-to-digital converter 103 is constant. The low-noise amplifier 101 may be a programmable gain amplifier (PGA). The first filter 102 may be an anti-aliasing filter (AAF) or a low-pass filter (LPF), which is not limited in this embodiment of the present application. The filters involved in the embodiments of the present application are generally low-pass filters, but the embodiments of the present application do not limit this.
可选的，图4是本申请实施例提供的一种第一环通缓冲器206的结构示意图。该第一环通缓冲器可以是图2和图3中的第一环通缓冲器206。如图4所示，第一环通缓冲器206中，电压缓冲电路2061包含源极跟随器，反馈电路2062包含电流镜(由M3和M5组成)和第一晶体管M7。Optionally, FIG. 4 is a schematic structural diagram of a first loop-through buffer 206 according to an embodiment of the present application. The first loop-through buffer may be the first loop-through buffer 206 in FIGS. 2 and 3. As shown in FIG. 4, in the first loop-through buffer 206, the voltage buffer circuit 2061 includes a source follower, and the feedback circuit 2062 includes a current mirror (composed of M3 and M5) and a first transistor M7.
其中，第一晶体管M7的漏极与M3和M5组成的电流镜的输入端耦合，M3和M5组成的电流镜的输出端与源极跟随器2061中M1的源极耦合。如图4所示，M3和M5组成的电流镜和第一晶体管M7用于将源极跟随器2061的输出端输出的信号反馈到源极跟随器2061的输入端，并为源极跟随器2061的源极提供电流偏置。如图4所示，第一滤波器102的输入端处输出的信号或者第一滤波器102的输出端处输出的信号的电压为Vi，输入到电压缓冲电路2061中。通过电压缓冲电路2061和反馈电路2062进行电压缓冲得到输出电压为Vo。源极跟随器2061包含电流源偏置I B、晶体管M1、电阻R B和输出串联电阻Ros，输出串联电阻Ros用于阻抗匹配。 The drain of the first transistor M7 is coupled to the input terminal of a current mirror composed of M3 and M5, and the output terminal of the current mirror composed of M3 and M5 is coupled to the source of M1 in the source follower 2061. As shown in FIG. 4, the current mirror composed of M3 and M5 and the first transistor M7 are used to feed back the signal output from the output terminal of the source follower 2061 to the input terminal of the source follower 2061, and the source follower 2061 The source provides current bias. As shown in FIG. 4, the voltage of the signal output at the input terminal of the first filter 102 or the signal output at the output terminal of the first filter 102 is Vi, and is input to the voltage buffer circuit 2061. Voltage buffering is performed by the voltage buffer circuit 2061 and the feedback circuit 2062 to obtain an output voltage Vo. The source follower 2061 includes a current source bias I B , a transistor M1, a resistor R B, and an output series resistor Ros. The output series resistor Ros is used for impedance matching.
图4所描述的第一环通缓冲器206中，源极跟随器、由M3和M5组成的电流镜和第一晶体管M7的结构，可以为环通输出电路20提供高输入阻抗和低输出阻抗，可以提高对环通输出电路的驱动能力。另外，通过M3和M5组成的电流镜和第一晶体管M7组成的反馈电路2062可以提高电压缓冲电路的环路增益，降低环通输出电路20的输出阻抗，环通输出电路20具有更好的线性度性能，则可以满足对第一滤波器102的输入端处输出的信号或者第一滤波器102的输出端处输出的信号进行环通输出的条件。In the first loop-through buffer 206 described in FIG. 4, the structure of the source follower, the current mirror composed of M3 and M5, and the first transistor M7 can provide the loop-through output circuit 20 with high input impedance and low output impedance. , Can improve the drive ability of the loop-through output circuit. In addition, through the current mirror composed of M3 and M5 and the feedback circuit 2062 composed of the first transistor M7, the loop gain of the voltage buffer circuit can be improved, and the output impedance of the loop-through output circuit 20 can be reduced. The loop-through output circuit 20 has better linearity Performance, it can meet the conditions of loop-through output of the signal output at the input end of the first filter 102 or the signal output at the output end of the first filter 102.
可以理解的，图2和图3所描述的射频接收电路10可以是窄带射频接收电路，也可以是全频带射频接收电路。以下分别进行描述。It can be understood that the radio frequency receiving circuit 10 described in FIG. 2 and FIG. 3 may be a narrow-band radio frequency receiving circuit or a full-band radio frequency receiving circuit. These are described separately below.
请参阅图5，图5是本申请实施例提供的再一种射频接收电路10和环通输出电路20的结构示意图。该射频接收电路10为窄带射频接收电路，该射频接收电路10还包含混频 器104，用于降低接收到的高频信号的频率，将需要的信号搬移到中频处。其中，低噪声放大器101的增益可以是可调的，第一滤波器102可以是低通滤波器。该窄带射频接收电路还可以包含可变增益放大器105，可以调节可变增益放大器105的增益与低噪声放大器101的增益来使第一模数转换器103接收到的模拟信号的功率恒定。关于低噪声放大器101、第一滤波器102、第一模数转换器103、混频器104和可变增益放大器105的具体描述可以依次参考图1中低噪声放大器200、低通滤波器500、模数转换器600、混频器300和可变增益放大器400，这里不再赘述。关于环通输出电路20的具体描述可以参考图3所描述的环通输出电路20。环通输出电路20中第一环通缓冲器206可以是图2、图3和图4中任一个中的第一环通缓冲器206，这里不再赘述。Please refer to FIG. 5, which is a schematic structural diagram of still another radio frequency receiving circuit 10 and a loop-through output circuit 20 according to an embodiment of the present application. The radio frequency receiving circuit 10 is a narrow-band radio frequency receiving circuit. The radio frequency receiving circuit 10 further includes a mixer 104 for reducing the frequency of the received high-frequency signal and moving the required signal to an intermediate frequency. The gain of the low-noise amplifier 101 may be adjustable, and the first filter 102 may be a low-pass filter. The narrowband radio frequency receiving circuit may further include a variable gain amplifier 105, which can adjust the gain of the variable gain amplifier 105 and the gain of the low noise amplifier 101 to make the power of the analog signal received by the first analog-to-digital converter 103 constant. For detailed descriptions of the low-noise amplifier 101, the first filter 102, the first analog-to-digital converter 103, the mixer 104, and the variable gain amplifier 105, refer to the low-noise amplifier 200, the low-pass filter 500, The analog-to-digital converter 600, the mixer 300, and the variable gain amplifier 400 are not repeated here. For a detailed description of the loop-through output circuit 20, reference may be made to the loop-through output circuit 20 described in FIG. 3. The first loop-through buffer 206 in the loop-through output circuit 20 may be the first loop-through buffer 206 in any one of FIG. 2, FIG. 3, and FIG. 4, and details are not described herein again.
可选的，在带射频接收电路中，环通输出电路20还可以从第一滤波器102的输出端处引出，可以参考图2所描述的实施例，这里不再赘述。Optionally, in the radio frequency receiving circuit, the loop-through output circuit 20 may also be derived from the output end of the first filter 102. For the embodiment described with reference to FIG. 2, details are not described herein.
请参阅图6，图6是本申请实施例提供的再一种射频接收电路10和环通输出电路20的结构示意图。该射频接收电路10为全频带射频接收电路，该射频接收电路10还可以包含频率跟随滤波器(tracking filter)106，用于对从天线接收到的全频带的电视的射频信号中筛选出用户选择的频带所在的频段的窄带的电视的射频信号。然后，发送给低噪声放大器101等进行后续的信号处理。关于低噪声放大器101、第一滤波器102、第一模数转换器103、混频器104和可变增益放大器105的具体描述可以依次参考图1中低噪声放大器200、低通滤波器500、模数转换器600、混频器300和可变增益放大器400，这里不再赘述。关于环通输出电路20的具体描述可以参考图2和图3所描述的环通输出电路20。环通输出电路20中第一环通缓冲器206可以是图2、图3和图4中任一个中的第一环通缓冲器206，这里不再赘述。Please refer to FIG. 6, which is a schematic structural diagram of still another RF receiving circuit 10 and a loop-through output circuit 20 according to an embodiment of the present application. The radio frequency receiving circuit 10 is a full-band radio frequency receiving circuit. The radio frequency receiving circuit 10 may further include a tracking filter 106 for filtering a user's selection from the radio frequency signals of the full-band television received from the antenna. The radio frequency signal of a narrow-band television in the frequency band in which the frequency band is located. Then, it is sent to the low-noise amplifier 101 and the like for subsequent signal processing. For detailed descriptions of the low-noise amplifier 101, the first filter 102, the first analog-to-digital converter 103, the mixer 104, and the variable gain amplifier 105, refer to the low-noise amplifier 200, the low-pass filter 500, The analog-to-digital converter 600, the mixer 300, and the variable gain amplifier 400 are not repeated here. For a detailed description of the loop-through output circuit 20, reference may be made to the loop-through output circuit 20 described in FIGS. 2 and 3. The first loop-through buffer 206 in the loop-through output circuit 20 may be the first loop-through buffer 206 in any one of FIG. 2, FIG. 3, and FIG. 4, and details are not described herein again.
可选的，在全频带射频接收电路10中，环通输出电路20还可以从第一滤波器102的输入端处引出，可以参考图3所描述的实施例，这里不再赘述。Optionally, in the full-band radio frequency receiving circuit 10, the loop-through output circuit 20 may also be derived from the input end of the first filter 102. For the embodiment described in FIG. 3, reference is not made here.
可选的，射频接收电路10中，也可以使用单转双电路(single to differential，S2D)。单转双电路用于将从天线接收的单端信号转换为差分信号，并将差分信号输入给低噪声放大器101。将接收的单端信号转换为差分信号进行处理，能够降低处理过程中信号之间的相互干扰，进而有助于避免各个频道上的信号失真，能够向电视设备输出图像和伴音质量更高的信号。具体的，请参阅图7，图7是本申请实施例提供的再一种射频接收电路10和环通输出电路20的结构示意图。在天线接收射频信号后，通过单转双电路107将单端信号转换为差分信号。关于低噪声放大器101、第一滤波器102、第一模数转换器103和可变增益放大器105的功能具体描述可以依次参考图1中低噪声放大器200、低通滤波器500、模数转换器600和可变增益放大器400，这里不再赘述。低噪声放大器101、第一滤波器102、第一模数转换器103和可变增益放大器105均为差分结构。Optionally, in the radio frequency receiving circuit 10, a single-to-differential (S2D) circuit can also be used. The single-to-double circuit is used to convert a single-ended signal received from an antenna into a differential signal, and input the differential signal to the low-noise amplifier 101. Converting the received single-ended signal into a differential signal for processing can reduce the mutual interference between the signals during the process, thereby helping to avoid signal distortion on each channel, and can output a higher-quality image and sound signal to the TV device . Specifically, please refer to FIG. 7, which is a schematic structural diagram of still another RF receiving circuit 10 and a loop-through output circuit 20 according to an embodiment of the present application. After the antenna receives the radio frequency signal, the single-ended signal is converted into a differential signal through the single-to-dual circuit 107. For detailed descriptions of the functions of the low-noise amplifier 101, the first filter 102, the first analog-to-digital converter 103, and the variable gain amplifier 105, refer to the low-noise amplifier 200, the low-pass filter 500, and the analog-to-digital converter in sequence in FIG. 1 600 and the variable gain amplifier 400 are not repeated here. The low noise amplifier 101, the first filter 102, the first analog-to-digital converter 103, and the variable gain amplifier 105 all have a differential structure.
环通输出电路20可以从第一滤波器102的输入端处或者输出端处引出(图7中未示出，可参考图5和图6中环通输出电路20的引出位置)。环通输出电路20还可以从单转双电路107的输出端处引出。如图7所示，单转差电路107的输出端输出的差分信号输入到环通输出电路20。环通输出电路20中每个元件处理的信号均为差分信号，每个元件输出的信 号也均为差分信号。环通输出电路20还可以包括第三放大器201、第四放大器203和第二滤波器204，第三放大器201、第四放大器203、第二滤波器204和第二模数转换器205依次连接，用于依次将从所述单转双电路的输出端输出的差分信号进行低噪声放大、放大、模数转换。上述的环通输出电路中采用差分结构，可以提高环通输出电路的抗干扰能力，且由于是从单转双电路107的输出端处引出环通输出电路20，因此无需在环通输出电路20中布局单转双电路即可实现差分结构，可以简化电路结构。The loop-through output circuit 20 may be derived from the input end or the output end of the first filter 102 (not shown in FIG. 7, and reference may be made to the lead-out position of the loop-through output circuit 20 in FIGS. 5 and 6). The loop-through output circuit 20 can also be derived from the output of the single-turn dual circuit 107. As shown in FIG. 7, the differential signal output from the output terminal of the single slip circuit 107 is input to the loop-through output circuit 20. The signals processed by each element in the loop-through output circuit 20 are differential signals, and the signals output by each element are also differential signals. The loop-through output circuit 20 may further include a third amplifier 201, a fourth amplifier 203, and a second filter 204. The third amplifier 201, the fourth amplifier 203, the second filter 204, and the second analog-to-digital converter 205 are connected in sequence. It is used to sequentially perform low-noise amplification, amplification, and analog-to-digital conversion on the differential signals output from the output ends of the single-to-double circuit. The above-mentioned loop-through output circuit adopts a differential structure, which can improve the anti-interference ability of the loop-through output circuit, and since the loop-through output circuit 20 is derived from the output of the single-turn dual circuit 107, there is no need to use the loop-through output circuit 20 The single-turn dual-circuit layout in the middle can realize the differential structure, which can simplify the circuit structure.
其中，单转双电路107可以是为片上无源巴伦，单转双电路107也可以是为有源巴伦，本申请实施例不作限制。The single-turn dual circuit 107 may be an on-chip passive balun, and the single-turn dual circuit 107 may also be an active balun, which is not limited in the embodiment of the present application.
图7所描述的射频接收电路10仅用于解释本申请实施例，单转双电路107的位置不限于天线100与低噪声放大器101之间，也可以是其他位置。环通输出电路20的输入信号的位置也不限于单转双电路107和低噪声放大器101之间，也可以是其他位置，本申请实施例不作限制。The radio frequency receiving circuit 10 described in FIG. 7 is only used to explain the embodiment of the present application. The position of the single-turn dual circuit 107 is not limited to the position between the antenna 100 and the low-noise amplifier 101, and may be other positions. The position of the input signal of the loop-through output circuit 20 is not limited to between the single-turn dual circuit 107 and the low-noise amplifier 101, and may be other positions, which are not limited in the embodiment of the present application.
在环通输出电路20上的信号为差分信号的场景下，第一环通缓冲器206的结构也可以是差分结构。具体的，请参阅图8，图8是本申请实施例提供的另一种第一环通缓冲器206的结构示意图。如图8所示，在环通输出电路20中，第一环通缓冲器206包括第一部分2063和第二部分2064，第一环通缓冲器的第一部分2063和第一环通缓冲器的第二部分2064均包含电压缓冲电路和反馈电路。第一环通缓冲器的第一部分2063和第一环通缓冲器的第二部分2064分别用于对第一滤波器102的输入端处输出的两路差分信号或者第一滤波器102的输出端处输出的两路差分信号进行处理。In a scenario where the signal on the loop-through output circuit 20 is a differential signal, the structure of the first loop-through buffer 206 may also be a differential structure. Specifically, please refer to FIG. 8, which is a schematic structural diagram of another first loop-through buffer 206 according to an embodiment of the present application. As shown in FIG. 8, in the loop-through output circuit 20, the first loop-through buffer 206 includes a first portion 2063 and a second portion 2064, the first portion 2063 of the first loop-through buffer, and the first portion of the first loop-through buffer. The two parts 2064 each include a voltage buffer circuit and a feedback circuit. The first portion 2063 of the first loop-through buffer and the second portion 2064 of the first loop-through buffer are respectively used for two differential signals output at the input of the first filter 102 or the output of the first filter 102 The two differential signals output from the processing are processed.
具体的，如图8所示，第一滤波器102的输入端处输出的差分信号或者第一滤波器102的输出端处输出的差分信号的电压为Vip和Vin，输入到电压缓冲电路2061中。差分信号的一端电压Vip输入到第一环通缓冲器的第一部分2063，差分信号的另一端电压Vin输入到第一环通缓冲器的第二部分2064。第一环通缓冲器的第一部分2063中电压缓冲电路2061和反馈电路2062对输入信号Vip进行电压缓冲得到输出电压为Vop，第一环通缓冲器的第二部分2064中电压缓冲电路2061′和反馈电路2062′对输入信号Vin进行电压缓冲得到输出电压为Von。Specifically, as shown in FIG. 8, the voltage of the differential signal output at the input terminal of the first filter 102 or the differential signal output at the output terminal of the first filter 102 is Vip and Vin, and is input to the voltage buffer circuit 2061. . The voltage Vip at one end of the differential signal is input to the first portion 2063 of the first loop-through buffer, and the voltage Vin at the other end of the differential signal is input to the second portion 2064 of the first loop-through buffer. The voltage buffer circuit 2061 and the feedback circuit 2062 in the first part of the first loop-through buffer 2063 perform voltage buffering on the input signal Vip to obtain an output voltage Vop. The voltage buffer circuit 2061 ′ and The feedback circuit 2062 'performs voltage buffering on the input signal Vin to obtain an output voltage Von.
图8所描述的第一环通缓冲器206中，针对第一环通缓冲器的第一部分2063来说，源极跟随器、由M3和M5组成的电流镜和第一晶体管M7的结构，可以为环通输出电路20提供高输入阻抗和低输出阻抗，可以提高对环通输出电路的驱动能力。针对第一环通缓冲器的第二部分来说，源极跟随器、由M3和M5组成的电流镜和第一晶体管M7的结构，可以为环通输出电路20提供高输入阻抗和低输出阻抗，可以提高对环通输出电路的驱动能力。另外，通过电流镜和第一晶体管组成的反馈电路可以提高电压缓冲电路的环路增益，降低环通输出电路20的输出阻抗，环通输出电路20具有更好的线性度性能，则可以满足对第一滤波器102的输入端处输出的信号或者第一滤波器102的输出端处输出的信号进行环通输出的条件。再者，环通输出电路20采用差分结构，因此受差分信号具有信号的幅度大小相等、相位相差180度的特性的影响，偶数阶的非线性特性很好。本申请实施例中采用的低噪声放大器可以为CMOS工艺的低噪差分放大器，有助于降低成本。In the first loop-through buffer 206 described in FIG. 8, for the first portion 2063 of the first loop-through buffer, the structure of the source follower, the current mirror composed of M3 and M5, and the first transistor M7 may be: Providing the loop-through output circuit 20 with high input impedance and low output impedance can improve the driving ability of the loop-through output circuit. For the second part of the first loop-through buffer, the structure of the source follower, the current mirror composed of M3 and M5, and the first transistor M7 can provide the loop-through output circuit 20 with high input impedance and low output impedance. , Can improve the drive ability of the loop-through output circuit. In addition, the feedback circuit composed of the current mirror and the first transistor can improve the loop gain of the voltage buffer circuit and reduce the output impedance of the loop-through output circuit 20. The loop-through output circuit 20 has better linearity performance, which can meet the A condition for loop-through output of a signal output at an input terminal of the first filter 102 or a signal output at an output terminal of the first filter 102. In addition, the loop-through output circuit 20 adopts a differential structure, so that the differential signal has the characteristics that the amplitude of the signal is equal, and the phase is 180 degrees out of phase. The even-order nonlinearity is very good. The low-noise amplifier used in the embodiments of the present application may be a low-noise differential amplifier in a CMOS process, which helps reduce costs.
在射频接收电路10上的信号为差分信号的场景下，低噪声放大器101为差分放大器。请参阅图9，图9是本申请实施例提供的一种低噪声放大器101的结构示意图。In a scenario where the signal on the radio frequency receiving circuit 10 is a differential signal, the low-noise amplifier 101 is a differential amplifier. Please refer to FIG. 9, which is a schematic structural diagram of a low-noise amplifier 101 according to an embodiment of the present application.
如图9所示，差分放大器101可以包括第一输入电阻Rin1、第一反馈电阻Rf1、第一反馈电容Cf1、第二输入电阻Rin2、第二反馈电阻Rf2、第二反馈电容Cf2、第一运算放大器A1、可调电容CL和第二级运算放大器A2。通常情况下，为了保证图8所示的差分放大器101输出的信号为差分信号，Rf1和Rf2的大小相等，Cf1和Cf2的大小相等。As shown in FIG. 9, the differential amplifier 101 may include a first input resistor Rin1, a first feedback resistor Rf1, a first feedback capacitor Cf1, a second input resistor Rin2, a second feedback resistor Rf2, a second feedback capacitor Cf2, and a first operation. Amplifier A1, adjustable capacitor CL, and second-stage operational amplifier A2. In general, in order to ensure that the signal output by the differential amplifier 101 shown in FIG. 8 is a differential signal, the sizes of Rf1 and Rf2 are equal, and the sizes of Cf1 and Cf2 are equal.
如图9所示，第一输入电阻Rin1的一端为差分放大器101的一个输入端，第一输入电阻Rin1的一端与单转双电路107的一个输出端连接，第一输入电阻Rin1的另一端分别与第一并联电路的一端、以及第一级运算放大器A1的正相输入端连接，第一并联电路为第一反馈电容Cf1和第一反馈电阻Rf1组成的并联电路。第一级运算放大器A1的负相输出端分别与可调电容的一端、第二级运算放大器A2的正相输入端连接。第二级运算放大器A2的正相输出端与第一并联电路的另一端连接。第二输入电阻Rin2的一端为差分放大器101的另一个输入端，第二输入电阻Rin2的一端与单转双电路107的另一输出端连接，第二输入电阻Rin2的另一端分别与第二并联电路的一端、以及第一级运算放大器A1的负相输入端连接，第二并联电路为第二反馈电容Cf2和第二反馈电阻Rf2组成的并联电路。第一级运算放大器A1的正相输出端分别与可调电容CL的另一端、第二级运算放大器A2的负相输入端连接。第二级运算放大器A2的负相输出端与第二并联电路的另一端连接。可以通过调节Rin1、Rin2、Rf1和Rf2的阻值，来调整差分放大器101的增益。因此，在上述情况下，差分放大器101的增益的可调范围与电阻Rin1、Rin2、Rf1和Rf2的阻值的可调节范围相关，在电阻Rin1、Rin2、Rf1和Rf2的可调节范围越大的情况下，差分放大器101的增益的可调范围越大。As shown in FIG. 9, one end of the first input resistance Rin1 is one input end of the differential amplifier 101, one end of the first input resistance Rin1 is connected to one output end of the single-turn dual circuit 107, and the other ends of the first input resistance Rin1 are respectively It is connected to one end of the first parallel circuit and the non-inverting input terminal of the first-stage operational amplifier A1. The first parallel circuit is a parallel circuit composed of a first feedback capacitor Cf1 and a first feedback resistor Rf1. The negative-phase output terminal of the first-stage operational amplifier A1 is respectively connected to one end of the adjustable capacitor and the non-inverted-phase input terminal of the second-stage operational amplifier A2. The non-inverting output terminal of the second-stage operational amplifier A2 is connected to the other end of the first parallel circuit. One end of the second input resistance Rin2 is the other input end of the differential amplifier 101. One end of the second input resistance Rin2 is connected to the other output end of the single-turn dual circuit 107. The other ends of the second input resistance Rin2 are respectively connected in parallel with the second. One end of the circuit is connected to the negative-phase input end of the first-stage operational amplifier A1, and the second parallel circuit is a parallel circuit composed of a second feedback capacitor Cf2 and a second feedback resistor Rf2. The non-inverting output terminal of the first-stage operational amplifier A1 is respectively connected to the other end of the adjustable capacitor CL and the negative-phase input terminal of the second-stage operational amplifier A2. The negative-phase output terminal of the second-stage operational amplifier A2 is connected to the other end of the second parallel circuit. The gain of the differential amplifier 101 can be adjusted by adjusting the resistances of Rin1, Rin2, Rf1, and Rf2. Therefore, in the above case, the adjustable range of the gain of the differential amplifier 101 is related to the adjustable range of the resistance values of the resistors Rin1, Rin2, Rf1, and Rf2. The larger the adjustable range of the resistors Rin1, Rin2, Rf1, and Rf2 is In this case, the adjustable range of the gain of the differential amplifier 101 is larger.
由于图9所示的差分放大器采用了电阻的大环反馈技术，信号的增益满足表达式(1)：Because the differential amplifier shown in Figure 9 uses a large-loop feedback technique with a resistor, the gain of the signal satisfies Expression (1):
Figure PCTCN2018091090-appb-000001
Figure PCTCN2018091090-appb-000001
其中，Gain表示信号的增益；Rf表示反馈电阻的大小；Rin表示输入电阻Rin的大小，A表示差分放大器的开环增益。通过表达式(1)可以看出，差分放大器101的信号的增益并不随温度、工艺、电源电压等的变化而变化，只与输入电阻和反馈电阻的比值有关，因而有助于实现高线性度。而且，由于本申请实施例中图9所示的差分放大器101中包括两级运算放大器，第一级放大器用于对信号进行放大，第二级放大器用于提供驱动能力，有助于实现驱动大负载，本申请实施例射频接收电路10采用了全差分结构，有利于提高电路的抗干扰性。Among them, Gain represents the gain of the signal; Rf represents the magnitude of the feedback resistor; Rin represents the magnitude of the input resistor Rin, and A represents the open-loop gain of the differential amplifier. It can be seen from the expression (1) that the gain of the signal of the differential amplifier 101 does not change with changes in temperature, process, power supply voltage, etc., and is only related to the ratio of the input resistance and the feedback resistance, thus helping to achieve high linearity . Moreover, since the differential amplifier 101 shown in FIG. 9 in the embodiment of the present application includes a two-stage operational amplifier, the first-stage amplifier is used to amplify the signal, and the second-stage amplifier is used to provide the driving capability, which is helpful to achieve a large driving power. Load, the radio frequency receiving circuit 10 in the embodiment of the present application adopts a fully differential structure, which is beneficial to improving the anti-interference performance of the circuit.
在引出的环通输出电路20中可以包含多条支路，这多条支路并联连接。多条支路中每条支路均可以对信号进行处理，输出数字信号，用于进行信号解调。具体的，环通输出电路20可以包含N条支路并联连接，N条支路中的第i条支路，用于对第一环通缓冲器206输出到第i条支路上的信号进行环通输出。N条支路中每条支路均包含第二模数转换器205。针对N条支路中的第i条支路，第二模数转换器205用于将第一滤波器102的输入端或者第一滤波器102的输出端输出到第i条支路上的信号进行模数转换。其中，N为大于或等 于1的正整数，i为满足1≤i≤N的整数，第i条支路为N条支路中任一条支路。The lead-through output circuit 20 may include a plurality of branches, and the plurality of branches are connected in parallel. Each of the multiple branches can process signals and output digital signals for signal demodulation. Specifically, the loop-through output circuit 20 may include N branches connected in parallel, and the i-th branch among the N branches is used to loop the signal output from the first loop-through buffer 206 to the i-th branch. Pass output. Each of the N branches includes a second analog-to-digital converter 205. For the i branch of the N branches, the second analog-to-digital converter 205 is configured to output the input end of the first filter 102 or the output of the first filter 102 to the signal on the i branch. Analog-to-digital conversion. Among them, N is a positive integer greater than or equal to 1, i is an integer satisfying 1 ≦ i ≦ N, and the i-th branch is any of the N branches.
具体的，请参阅图10，图10是本申请实施例提供的一种环通输出电路20的结构示意图。如图10所示，环通输出电路20可以包含N条支路，N可以是大于等于1的整数。从射频接收电路10中滤波器102的输出端处引出环通输出电路20。如图10所示，首先可以在引出的环通输出电路20设置第一环通缓冲器206，第一环通缓冲器206的输入端与第一滤波器102的输出端连接，第一环通缓冲器206的输出端与N条并联的支路的输入端连接。第一环通缓冲器206可以用于将环通输出电路20与射频接收电路10进行隔离。如图10所示，N条并联的支路中，每条支路均包含第二模数转换器205，对于每条支路来说，第二模数转换器205输出的数字信号可以用于解调器解调电视信号。关于射频接收电路10的具体描述，可以参考图1～图3任一项所描述的射频接收电路。Specifically, please refer to FIG. 10, which is a schematic structural diagram of a loop-through output circuit 20 according to an embodiment of the present application. As shown in FIG. 10, the loop-through output circuit 20 may include N branches, and N may be an integer greater than or equal to 1. A loop-through output circuit 20 is derived from the output of the filter 102 in the radio frequency receiving circuit 10. As shown in FIG. 10, a first loop-through buffer 206 may be first provided in the loop-through output circuit 20. The input of the first loop-through buffer 206 is connected to the output of the first filter 102. The output terminal of the buffer 206 is connected to the input terminals of the N parallel branches. The first loop-through buffer 206 may be used to isolate the loop-through output circuit 20 from the radio frequency receiving circuit 10. As shown in FIG. 10, among the N parallel branches, each branch includes a second analog-to-digital converter 205. For each branch, the digital signal output by the second analog-to-digital converter 205 can be used for The demodulator demodulates a television signal. For a specific description of the radio frequency receiving circuit 10, reference may be made to the radio frequency receiving circuit described in any one of FIG. 1 to FIG. 3.
引出的环通输出电路20还可以包含多次级联环通的支路。具体的，请参阅图11，图11是本申请实施例提供的另一种环通输出电路20的结构示意图。如图11所示，环通输出电路20可以包括M条级联环通的支路。第一环通缓冲器206包括M个第二环通缓冲器207，M条支路分别包含一个第二环通缓冲器207。第k条支路208上的第二环通缓冲器207的输出端与第k+1条支路210上的第二环通缓冲器207的输入端相连，第k+1条支路210上的第二环通缓冲器207用于缓存第k条支路208上的第二环通缓冲器207的输出端输出的信号。The derived loop-through output circuit 20 may further include a plurality of secondary loop-connected branches. Specifically, please refer to FIG. 11, which is a schematic structural diagram of another loop-through output circuit 20 according to an embodiment of the present application. As shown in FIG. 11, the loop-through output circuit 20 may include M cascaded loop-through branches. The first loop-through buffer 206 includes M second loop-through buffers 207, and each of the M branches includes a second loop-through buffer 207. The output of the second loop-through buffer 207 on the k-th branch 208 is connected to the input of the second loop-through buffer 207 on the k + 1-th branch 210, and on the k + 1-th branch 210 The second loop-through buffer 207 is configured to buffer a signal output from an output terminal of the second loop-through buffer 207 on the k-th branch 208.
其中，M为大于或等于2的正整数，k为满足1≤k≤M的整数，第k条支路208为M条支路中任一条支路。第k条支路208与第k+1条支路210为M条支路中相邻的两条支路。Among them, M is a positive integer greater than or equal to 2, k is an integer satisfying 1 ≦ k ≦ M, and the k-th branch 208 is any one of the M branches. The k-th branch 208 and the k + 1-th branch 210 are two adjacent branches among the M branches.
关于射频接收电路10的具体描述，可以参考图1～图3任一项所描述的射频接收电路。可选的，每条支路还可以包括第二放大器209。请参阅图12，图12是本申请实施例提供的又一种环通输出电路20的结构示意图。如图12所示，对于第k条支路208来说，第二放大器209的输入端与第k条支路208上的第二环通缓冲器207的输出端连接，第二放大器209的输出端与第k条支路208的第二模数转换器205连接，第二放大器209用于进行信号放大。For a specific description of the radio frequency receiving circuit 10, reference may be made to the radio frequency receiving circuit described in any one of FIG. 1 to FIG. 3. Optionally, each branch may further include a second amplifier 209. Please refer to FIG. 12, which is a schematic structural diagram of still another loop-through output circuit 20 according to an embodiment of the present application. As shown in FIG. 12, for the k-th branch 208, the input of the second amplifier 209 is connected to the output of the second loop-through buffer 207 on the k-th branch 208, and the output of the second amplifier 209 The terminal is connected to the second analog-to-digital converter 205 of the k-th branch 208, and the second amplifier 209 is used for signal amplification.
如图12所示，对于第k条支路208来说，当第k条支路208中的开关断开时，第二环通缓冲器207输出的信号需要经过第二放大器209放大之后，输出给第k条支路208的第二模数转换器205。并且第k+1条支路210也是从第k条支路208的第二放大器209的输出端处引出。对于每条支路来说，都可以根据需求选择闭合或者断开开关以选择不使用或者使用支路上的第二放大器209进行放大。As shown in FIG. 12, for the k-th branch 208, when the switch in the k-th branch 208 is turned off, the signal output by the second loop-through buffer 207 needs to be amplified by the second amplifier 209 and then output. A second analog-to-digital converter 205 for the k-th branch 208. And the k + 1th branch 210 is also derived from the output of the second amplifier 209 of the kth branch 208. For each branch, you can choose to close or open the switch to choose not to use or use the second amplifier 209 on the branch for amplification.
可以理解的，本申请实施例对级联环通的支路中第二放大器209的数量不作限定。实际应用中可以根据需求针对各个级联支路确定是否设置。It can be understood that the number of the second amplifiers 209 in the branch of the cascaded loop-through is not limited in the embodiment of the present application. In actual applications, it can be determined whether to set for each cascade branch according to the requirements.
可选的，第二环通缓冲器207在电路中的连接不限于图11和图12所示出的连接，还可以是其他方式。请参阅图13，图13是本申请实施例提供的再一种环通输出电路20的结构示意图。如图13所示，对于第k条支路208来说，第二环通缓冲器207可以是在引出的该第k个支路208上。本申请实施例对第二环通缓冲器207在环通输出电路20中与多条支 路的位置不作限定。Optionally, the connection of the second loop-through buffer 207 in the circuit is not limited to the connection shown in FIG. 11 and FIG. 12, and may also be other manners. Please refer to FIG. 13, which is a schematic structural diagram of still another loop-through output circuit 20 according to an embodiment of the present application. As shown in FIG. 13, for the k-th branch 208, the second loop-through buffer 207 may be located on the k-th branch 208. In the embodiment of the present application, the positions of the second loop-through buffer 207 in the loop-through output circuit 20 and a plurality of branches are not limited.
可选的，环通输出电路20可以包含多条并联的支路，也可以包含多次级联环通的支路。具体的，请参阅图14，图14是本申请实施例提供的再一种环通输出电路20的结构示意图。如图14所示，环通输出电路20可以包含两部分：并联部分21和级联环通部分22。Optionally, the loop-through output circuit 20 may include multiple branches connected in parallel, and may also include branches connected to multiple secondary loops. Specifically, please refer to FIG. 14, which is a schematic structural diagram of still another loop-through output circuit 20 according to an embodiment of the present application. As shown in FIG. 14, the loop-through output circuit 20 may include two parts: a parallel portion 21 and a cascaded loop-through portion 22.
其中，并联部分21包含多条并联的支路，如图14所示，可以包含N条支路，N可以是大于或等于1的整数。N条支路中每条支路均包含第二模数转换器205，每条支路的第二模数转换器205输出的信号可以用于解调器解调电视信号。关于并联部分21的具体描述可以参考图11所描述的环通输出电路，这里不再赘述。The parallel section 21 includes a plurality of parallel branches. As shown in FIG. 14, the parallel section 21 may include N branches, and N may be an integer greater than or equal to 1. Each of the N branches includes a second analog-to-digital converter 205, and a signal output from the second analog-to-digital converter 205 of each branch can be used to demodulate a television signal. For the specific description of the parallel part 21, reference may be made to the loop-through output circuit described in FIG. 11, which is not repeated here.
级联环通部分22可以包含多条级联环通的支路，如图14所示，可以包含N′条支路，N′也可以是大于或等于1的整数，N′和N可以相等，也可以不等。N′条支路中每条支路均包含第二模数转换器205，每条支路的第二模数转换器205输出的信号可以用于解调器解调电视信号。关于级联环通部分22的具体描述可以参考图12所描述的环通输出电路，这里不再赘述。The cascading loop-through section 22 may include multiple branches of the cascading loop-through, as shown in FIG. 14, may include N ′ branches, N ′ may also be an integer greater than or equal to 1, and N ′ and N may be equal , Can also vary. Each of the N ′ branches includes a second analog-to-digital converter 205, and a signal output from the second analog-to-digital converter 205 of each branch can be used to demodulate a television signal. For the detailed description of the cascaded loop-through section 22, reference may be made to the loop-through output circuit described in FIG. 12, which is not repeated here.
其中，图10～图14任一个图所描述环通输出电路20中，环通输出电路20可以是独立的芯片实现的，也可以是和射频接收电路10集成在一个芯片中实现的，本申请实施例对此不作限定。另外，环通输出电路20中并联的每条支路可以是独立的芯片实现的，也可以是并联的多条支路集成在一个或多个芯片中实现的，本申请实施例对此不作限定。级联环通的多条支路中每条支路可以是独立的芯片实现的，也可以是级联的多条支路集成在一个或多个芯片中实现的，本申请实施例对此不作限定。Among the loop-through output circuits 20 described in any one of FIGS. 10 to 14, the loop-through output circuit 20 may be implemented by a separate chip, or may be implemented by integrating with the radio frequency receiving circuit 10 in one chip. This application The embodiment is not limited thereto. In addition, each branch of the loop-through output circuit 20 connected in parallel may be implemented by independent chips, or multiple parallel branches may be integrated in one or more chips, which is not limited in the embodiment of the present application. . Each of the multiple branches of the cascading loop-through can be implemented by an independent chip, or can be implemented by integrating the cascaded multiple branches in one or more chips, which is not described in the embodiment of the present application. limited.
可选的，图10～图14任一个图所描述环通输出电路20还可以是从第一滤波器102的输入端处引出的，则第一环通缓冲器206的输出端可以在多条支路之前串联一个第二滤波器，用于对从第一环通缓冲器输出的信号进行滤波。Optionally, the loop-through output circuit 20 described in any one of FIG. 10 to FIG. 14 may also be derived from the input end of the first filter 102, and then the output end of the first loop-through buffer 206 may be in multiple lines. A second filter is connected in series before the branch to filter the signal output from the first loop-through buffer.
可选的，图10～图14任一个图所描述的环通输出电路中，第一环通缓冲器206的结构可以参考图2～图4所描述的第一环通缓冲器206这里不再赘述。如果环通输出电路20为差分结构，则第一环通缓冲器206的结构可以参考图8所描述的第一环通缓冲器206。图10～图14任一个图所描述射频接收电路10还可以包括单转双电路107，单转双电路107用于接收射频信号，将射频信号转换为差分信号输入到低噪声放大器101。则图10～图14任一个图所示的射频接收电路10中低噪声放大器101、第一滤波器102和第一模数转换器103的输入的信号和输出信号均为差分信号。图10～图14任一个图所示的环通输出电路20中第一环通缓冲器206以及多条支路中元件的输入信号和输出信号均为差分信号。Optionally, in the loop-through output circuit described in any one of FIGS. 10 to 14, the structure of the first loop-through buffer 206 may be referred to the first loop-through buffer 206 described in FIGS. 2 to 4 and is not described here anymore. To repeat. If the loop-through output circuit 20 has a differential structure, the structure of the first loop-through buffer 206 may refer to the first loop-through buffer 206 described in FIG. 8. The radio frequency receiving circuit 10 described in any one of FIGS. 10 to 14 may further include a single-turn dual circuit 107. The single-turn dual circuit 107 is configured to receive a radio frequency signal, convert the radio frequency signal into a differential signal, and input the low noise amplifier 101. Then, the input signal and output signal of the low-noise amplifier 101, the first filter 102, and the first analog-to-digital converter 103 in the radio frequency receiving circuit 10 shown in any one of FIGS. 10 to 14 are differential signals. The input signals and output signals of the first loop-through buffer 206 and the components in the multiple branches in the loop-through output circuit 20 shown in any one of FIGS. 10 to 14 are differential signals.
可选的，图10～图14任一个图所描述的环通输出电路20还用于从所述单转双电路107的输出端处引出。该情况下，环通输出电路20还可以包括第三放大器和第二滤波器，所述第三放大器、所述第二滤波器和所述第二模数转换器依次连接，用于依次将从所述单转双电路的输出端输出的所述差分信号进行放大、滤波和模数转换。其中，第三放大器、第二滤波器可以是在第一环通缓冲器206的输出端，且在多条支路之前连接的，也可以是在第一环通缓冲器206的输出端，且在每条支路中均包含第三放大器和第二滤波器，本申请实施例不作限定。Optionally, the loop-through output circuit 20 described in any one of FIG. 10 to FIG. 14 is also used to lead from the output end of the single-turn dual circuit 107. In this case, the loop-through output circuit 20 may further include a third amplifier and a second filter, and the third amplifier, the second filter, and the second analog-to-digital converter are connected in order to sequentially The differential signal output from the output end of the single-turn dual circuit is amplified, filtered, and analog-to-digital converted. The third amplifier and the second filter may be connected to the output end of the first loop-through buffer 206 and connected before multiple branches, or may be connected to the output end of the first loop-through buffer 206, and Each branch includes a third amplifier and a second filter, which are not limited in the embodiment of the present application.
另外，本申请实施例还提供了一种电视调谐器。其中，该电视调谐器包括射频接收电路和环通输出电路。其中：射频接收电路可以是图1～图3任一个图所描述的射频接收电路10，环通输出电路可以是图2、图3、图5、图6、图7和图10～图14任一个图所描述的环通输出电路20，这里不再赘述。In addition, an embodiment of the present application further provides a television tuner. The television tuner includes a radio frequency receiving circuit and a loop-through output circuit. Wherein, the RF receiving circuit may be the RF receiving circuit 10 described in any one of FIGS. 1 to 3, and the loop-through output circuit may be any of FIGS. 2, 3, 5, 6, 7, and 10 to 14. The loop-through output circuit 20 described in a figure is not repeated here.
还需要说明的是，本申请实施例对电视调谐器中包括的器件不做限制。射频接收电路可以包括更少的器件，也可以包括更多的器件。例如，射频接收电路为窄带射频接收电路的情况下，射频接收电路还可以包含一个或多个混频器。环通输出电路也可以包括更少的器件，也可以包括更多的器件。例如，环通输出电路还可以包含解调器。It should also be noted that the embodiments of the present application do not limit the devices included in the television tuner. The RF receiving circuit may include fewer devices, and may also include more devices. For example, when the radio frequency receiving circuit is a narrowband radio frequency receiving circuit, the radio frequency receiving circuit may further include one or more mixers. The loop-through output circuit may also include fewer devices, and may include more devices. For example, the loop-through output circuit may also include a demodulator.
其中，电视调谐器的射频接收电路和环通输出电路可以集成在同一个芯片上，也可以集成在不同的芯片上，本申请实施例对此不作限定。The radio frequency receiving circuit and the loop-through output circuit of the television tuner may be integrated on the same chip, or may be integrated on different chips, which is not limited in the embodiment of the present application.
另外，本申请实施例还提供了一种机顶盒，该机顶盒可以包含电视调谐器。电视调谐器包括射频接收电路和环通输出电路。其中：射频接收电路可以是图1～图3任一个图所描述的射频接收电路10，环通输出电路可以是图2、图3、图5、图6、图7和图10～图14任一个图所描述的环通输出电路20，这里不再赘述。In addition, an embodiment of the present application also provides a set-top box, which may include a TV tuner. The TV tuner includes a radio frequency receiving circuit and a loop-through output circuit. Wherein, the RF receiving circuit may be the RF receiving circuit 10 described in any one of FIGS. 1 to 3, and the loop-through output circuit may be any of FIGS. 2, 3, 5, 6, 7, and 10 to 14. The loop-through output circuit 20 described in a figure is not repeated here.
另外，本申请实施例还提供了一种射频接收***，该射频接收***包括射频接收设备和环通输出设备；其中：射频接收设备包括低噪声放大器、第一滤波器和第一模数转换器，用于依次对接收到的信号进行低噪声放大、滤波和模数转换。In addition, an embodiment of the present application further provides a radio frequency receiving system. The radio frequency receiving system includes a radio frequency receiving device and a loop-through output device. The radio frequency receiving device includes a low noise amplifier, a first filter, and a first analog-to-digital converter. , For low-noise amplification, filtering, and analog-to-digital conversion of the received signal in sequence.
环通输出设备包括第一环通缓冲器，第一环通缓冲器包括电压缓冲电路和反馈电路，电压缓冲电路用于对第一滤波器的输入端处输出的信号或者第一滤波器的输出端处输出的信号进行电压缓冲，电压缓冲电路的输出端输出的信号用于进行环通输出，反馈电路用于将电压缓冲电路的输出端输出的信号反馈到电压缓冲电路的输入端。The loop-through output device includes a first loop-through buffer. The first loop-through buffer includes a voltage buffer circuit and a feedback circuit. The voltage buffer circuit is configured to output a signal at an input end of the first filter or an output of the first filter. The signals output from the terminals are buffered by voltage. The signals output from the output of the voltage buffer circuit are used for loop-through output. The feedback circuit is used to feed back the signals output from the output of the voltage buffer circuit to the input of the voltage buffer circuit.
其中，射频接收设备可以包含图1～图3任一个图所描述的射频接收电路10。环通输出设备可以包含图2、图3、图5、图6、图7和图10～图14任一个图所描述的环通输出电路20。The radio frequency receiving device may include the radio frequency receiving circuit 10 described in any one of FIG. 1 to FIG. 3. The loop-through output device may include the loop-through output circuit 20 described in FIG. 2, FIG. 3, FIG. 5, FIG. 6, FIG. 7, and any one of FIGS. 10 to 14.
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, this application also intends to include these modifications and variations.

Claims (23)

  1. 一种电视调谐器，其特征在于，所述电视调谐器包括射频接收电路和环通输出电路；其中：A television tuner, characterized in that the television tuner comprises a radio frequency receiving circuit and a loop-through output circuit; wherein:
    所述射频接收电路包括低噪声放大器、第一滤波器和第一模数转换器，用于依次对接收到的信号进行低噪声放大、滤波和模数转换；The radio frequency receiving circuit includes a low-noise amplifier, a first filter, and a first analog-to-digital converter, which are used to sequentially perform low-noise amplification, filtering, and analog-to-digital conversion on a received signal;
    所述环通输出电路包括第一环通缓冲器，所述第一环通缓冲器包括电压缓冲电路和反馈电路；The loop-through output circuit includes a first loop-through buffer, and the first loop-through buffer includes a voltage buffer circuit and a feedback circuit;
    其中，所述电压缓冲电路用于对所述第一滤波器的输入端处输出的信号或者所述第一滤波器的输出端处输出的信号进行电压缓冲；所述电压缓冲电路的输出端输出的信号用于进行环通输出；所述反馈电路用于将所述电压缓冲电路的输出端输出的信号反馈到所述电压缓冲电路的输入端，以提高所述电压缓冲电路的环路增益。The voltage buffer circuit is configured to perform voltage buffering on a signal output at an input terminal of the first filter or a signal output at an output terminal of the first filter; the output terminal of the voltage buffer circuit outputs The signal is used for loop-through output; the feedback circuit is used to feed back the signal output from the output end of the voltage buffer circuit to the input end of the voltage buffer circuit to improve the loop gain of the voltage buffer circuit.
  2. 根据权利要求1所述的电视调谐器，其特征在于，所述电压缓冲电路包含源极跟随器，所述反馈电路包含电流镜和第一晶体管；其中：The television tuner according to claim 1, wherein the voltage buffer circuit includes a source follower, and the feedback circuit includes a current mirror and a first transistor; wherein:
    所述第一晶体管的漏极与所述电流镜的输入端耦合，所述电流镜的输出端与所述源极跟随器的源极耦合；所述电流镜和所述第一晶体管用于将所述源极跟随器的输出端输出的信号反馈到所述源极跟随器的输入端，并为所述源极跟随器的源极提供电流偏置。A drain of the first transistor is coupled to an input terminal of the current mirror, and an output terminal of the current mirror is coupled to a source of the source follower; the current mirror and the first transistor are used to connect A signal output from an output terminal of the source follower is fed back to an input terminal of the source follower, and a current bias is provided for a source of the source follower.
  3. 根据权利要求1或2所述的电视调谐器，其特征在于，所述电压缓冲电路用于对所述第一滤波器的输入端处输出的信号进行电压缓冲，所述环通输出电路还包括第二滤波器和第二模数转换器，用于对所述第一环通缓冲器输出的信号进行滤波和模数转换。The television tuner according to claim 1 or 2, wherein the voltage buffer circuit is configured to perform voltage buffering on a signal output at an input end of the first filter, and the loop-through output circuit further includes A second filter and a second analog-to-digital converter are configured to perform filtering and analog-to-digital conversion on a signal output by the first loop-through buffer.
  4. 根据权利要求1或2所述的电视调谐器，其特征在于，所述电压缓冲电路用于对所述第一滤波器的输出端处输出的信号进行电压缓冲，所述环通输出电路还包括第三模数转换器，用于对所述第一环通缓冲器输出的信号进行模数转换。The television tuner according to claim 1 or 2, wherein the voltage buffer circuit is configured to perform voltage buffering on a signal output at an output end of the first filter, and the loop-through output circuit further includes A third analog-to-digital converter is configured to perform analog-to-digital conversion on a signal output by the first loop-through buffer.
  5. 根据权利要求1至4任一项所述的电视调谐器，其特征在于，所述射频接收电路还包括单转双电路；所述单转双电路用于接收射频信号，将所述射频信号转换为差分信号输入到所述低噪声放大器；The television tuner according to any one of claims 1 to 4, wherein the radio frequency receiving circuit further comprises a single-to-dual circuit; the single-to-dual circuit is used to receive a radio frequency signal and convert the radio frequency signal Inputting a differential signal to the low noise amplifier;
    在所述环通输出电路中，所述第一环通缓冲器包括第一部分和第二部分，所述第一环通缓冲器的第一部分和所述第一环通缓冲器的第二部分均包含所述电压缓冲电路和所述反馈电路；所述第一环通缓冲器的第一部分和所述第一环通缓冲器的第二部分分别用于对所述第一滤波器的输入端处输出的两路差分信号或者所述第一滤波器的输出端处输出的两路差分信号进行处理。In the loop-through output circuit, the first loop-through buffer includes a first portion and a second portion, and the first portion of the first loop-through buffer and the second portion of the first loop-through buffer are both Including the voltage buffer circuit and the feedback circuit; the first part of the first loop-through buffer and the second part of the first loop-through buffer are respectively used for inputting the first filter The two differential signals output or the two differential signals output at the output end of the first filter are processed.
  6. 根据权利要求5所述的电视调谐器，其特征在于，所述低噪声放大器为差分放大器，所述差分放大器包括第一输入电阻、第一反馈电容、第一反馈电阻、第二输入电阻、第二反馈电容、第二反馈电阻、第一级运算放大器、可调电容和第二级运算放大器；所述第一 输入电阻的阻值、所述第一反馈电阻的阻值、所述第二输入电阻的阻值和所述第二反馈电阻的阻值是可调的，用于调整所述差分放大器的增益；The television tuner according to claim 5, wherein the low noise amplifier is a differential amplifier, and the differential amplifier comprises a first input resistor, a first feedback capacitor, a first feedback resistor, a second input resistor, a first Two feedback capacitors, a second feedback resistor, a first-stage operational amplifier, an adjustable capacitor, and a second-stage operational amplifier; the resistance of the first input resistor, the resistance of the first feedback resistor, and the second input The resistance value of the resistor and the resistance value of the second feedback resistor are adjustable and used to adjust the gain of the differential amplifier;
    其中，所述第一输入电阻的一端为所述差分放大器的一个输入端，所述第一输入电阻的一端与所述单转双电路的一个输出端连接，所述第一输入电阻的另一端分别与第一并联电路的一端、以及所述第一级运算放大器的正相输入端连接，所述第一并联电路为所述第一反馈电容和所述第一反馈电阻组成的并联电路；Wherein, one end of the first input resistance is one input end of the differential amplifier, one end of the first input resistance is connected to one output end of the single-turn dual circuit, and the other end of the first input resistance Respectively connected to one end of a first parallel circuit and a non-inverting input terminal of the first-stage operational amplifier, and the first parallel circuit is a parallel circuit composed of the first feedback capacitor and the first feedback resistor;
    所述第一级运算放大器的负相输出端分别与所述可调电容的一端、所述第二级运算放大器的正相输入端连接；The negative-phase output terminal of the first-stage operational amplifier is connected to one end of the adjustable capacitor and the non-inverted input terminal of the second-stage operational amplifier;
    所述第二级运算放大器的正相输出端与所述第一并联电路的另一端连接；A non-inverting output terminal of the second-stage operational amplifier is connected to the other end of the first parallel circuit;
    所述第二输入电阻的一端为所述差分放大器的另一个输入端，所述第二输入电阻的一端与所述单转双电路的另一输出端连接，所述第二输入电阻的另一端分别与第二并联电路的一端、以及所述第一级运算放大器的负相输入端连接，所述第二并联电路为所述第二反馈电容和所述第二反馈电阻组成的并联电路；One end of the second input resistance is the other input end of the differential amplifier, one end of the second input resistance is connected to the other output end of the single-turn dual circuit, and the other end of the second input resistance Respectively connected to one end of a second parallel circuit and the negative-phase input terminal of the first-stage operational amplifier, and the second parallel circuit is a parallel circuit composed of the second feedback capacitor and the second feedback resistor;
    所述第一级运算放大器的正相输出端分别与所述可调电容的另一端、所述第二级运算放大器的负相输入端连接；A non-inverting output terminal of the first-stage operational amplifier is connected to the other end of the adjustable capacitor and a negative-phase input terminal of the second-stage operational amplifier;
    所述第二级运算放大器的负相输出端与所述第二并联电路的另一端连接。The negative-phase output terminal of the second-stage operational amplifier is connected to the other end of the second parallel circuit.
  7. 根据权利要求1至6任一项所述的电视调谐器，其特征在于，所述环通输出电路包括N条支路，所述N条支路并联连接；所述N条支路中的第i条支路，用于对所述第一环通缓冲器输出到所述第i条支路上的信号进行环通输出；The television tuner according to any one of claims 1 to 6, wherein the loop-through output circuit includes N branches, and the N branches are connected in parallel; the first of the N branches i branches for loop-through output of signals output by the first loop-through buffer to the i-th branch;
    其中，所述N为大于或等于1的正整数，所述i为满足1≤i≤N的整数，所述第i条支路为所述N条支路中任一条支路。Wherein, N is a positive integer greater than or equal to 1, the i is an integer satisfying 1 ≦ i ≦ N, and the i-th branch is any one of the N branches.
  8. 根据权利要求1至6任一项所述的电视调谐器，其特征在于，所述环通输出电路包括M条支路；The television tuner according to any one of claims 1 to 6, wherein the loop-through output circuit includes M branches;
    所述第一环通缓冲器包括M个第二环通缓冲器，所述M条支路分别包含一个所述第二环通缓冲器；第k条支路上的所述第二环通缓冲器的输出端与第k+1条支路上的所述第二环通缓冲器的输入端相连，所述第k+1条支路上的所述第二环通缓冲器用于缓存所述第k条支路上的所述第二环通缓冲器的输出端输出的信号；The first loop-through buffer includes M second loop-through buffers, and each of the M branches includes one of the second loop-through buffers; the second loop-through buffer on the k-th branch The output end of is connected to the input end of the second loop-through buffer on the k + 1 branch, and the second loop-through buffer on the k + 1 branch is used to buffer the kth A signal output from an output end of the second loop-through buffer on a branch road;
    其中，所述M为大于或等于2的正整数，所述k为满足1≤k≤M的整数，所述第k条支路为所述M条支路中任一条支路；所述第k条支路与所述第k+1条支路为所述M条支路中相邻的两条支路。Wherein, M is a positive integer greater than or equal to 2, k is an integer satisfying 1 ≦ k ≦ M, and the kth branch is any one of the M branches; the first The k branches and the k + 1th branch are two adjacent branches among the M branches.
  9. 根据权利要求8所述的电视调谐器，其特征在于，所述第k条支路还包括第二放大器，所述第二放大器的输入端与所述第k条支路上的所述第二环通缓冲器的输出端连接，用于进行信号放大。The television tuner according to claim 8, wherein the k-th branch further comprises a second amplifier, an input of the second amplifier and the second loop on the k-th branch. The output of the pass buffer is connected for signal amplification.
  10. 根据权利要求1至9任一项所述的电视调谐器，其特征在于，所述射频接收电路 还包括增益控制器，所述增益控制器用于调节所述低噪声放大器的增益。The television tuner according to any one of claims 1 to 9, wherein the radio frequency receiving circuit further comprises a gain controller, and the gain controller is configured to adjust a gain of the low noise amplifier.
  11. 一种环通输出电路，其特征在于，所述环通输出电路用于对射频接收电路进行环通输出，所述射频接收电路包括低噪声放大器、第一滤波器和第一模数转换器，用于依次对接收到的信号进行放大、滤波和模数转换；A loop-through output circuit, characterized in that the loop-through output circuit is used to loop-through output a radio frequency receiving circuit, and the radio frequency receiving circuit includes a low noise amplifier, a first filter, and a first analog-to-digital converter. Used to sequentially amplify, filter, and analog-to-digital convert the received signal;
    所述环通输出电路包括第一环通缓冲器，所述第一环通缓冲器包括电压缓冲电路和反馈电路，所述电压缓冲电路用于对所述第一滤波器的输入端处输出的信号或者所述第一滤波器的输出端处输出的信号进行电压缓冲，所述电压缓冲电路的输出端输出的信号用于进行环通输出，所述反馈电路用于将所述电压缓冲电路的输出端输出的信号反馈到所述电压缓冲电路的输入端，以提高所述电压缓冲电路的环路增益。The loop-through output circuit includes a first loop-through buffer, and the first loop-through buffer includes a voltage buffer circuit and a feedback circuit. The voltage buffer circuit is configured to output a voltage at the input end of the first filter. The signal or the signal output at the output terminal of the first filter performs voltage buffering. The signal output from the output terminal of the voltage buffer circuit is used for loop-through output, and the feedback circuit is used to convert the voltage of the voltage buffer circuit. The signal output from the output terminal is fed back to the input terminal of the voltage buffer circuit to improve the loop gain of the voltage buffer circuit.
  12. 根据权利要求11所述的环通输出电路，其特征在于，所述电压缓冲电路包含源极跟随器，所述反馈电路包含电流镜和第一晶体管；其中：The loop-through output circuit according to claim 11, wherein the voltage buffer circuit includes a source follower, and the feedback circuit includes a current mirror and a first transistor; wherein:
    所述第一晶体管的漏极与所述电流镜的输入端耦合，所述电流镜的输出端与所述源极跟随器的源极耦合；所述电流镜和所述第一晶体管用于将所述源极跟随器的输出端输出的信号反馈到所述源极跟随器的输入端，并为所述源极跟随器的源极提供电流偏置。A drain of the first transistor is coupled to an input terminal of the current mirror, and an output terminal of the current mirror is coupled to a source of the source follower; the current mirror and the first transistor are used to connect A signal output from an output terminal of the source follower is fed back to an input terminal of the source follower, and a current bias is provided for a source of the source follower.
  13. 根据权利要求11或12所述的环通输出电路，其特征在于，所述电压缓冲电路用于对所述第一滤波器的输入端处输出的信号进行电压缓冲，所述环通输出电路还包括第二滤波器和第二模数转换器，用于对所述第一环通缓冲器输出的信号进行滤波和模数转换。The loop-through output circuit according to claim 11 or 12, wherein the voltage buffer circuit is configured to perform voltage buffering on a signal output at an input end of the first filter, and the loop-through output circuit further comprises: It includes a second filter and a second analog-to-digital converter for filtering and analog-to-digital conversion on the signal output by the first loop-through buffer.
  14. 根据权利要求11或12所述的环通输出电路，其特征在于，所述电压缓冲电路用于对所述第一滤波器的输出端处输出的信号进行电压缓冲，所述环通输出电路还包括第三模数转换器，用于对所述第一环通缓冲器输出的信号进行模数转换。The loop-through output circuit according to claim 11 or 12, wherein the voltage buffer circuit is configured to perform voltage buffering on a signal output at an output end of the first filter, and the loop-through output circuit further It includes a third analog-to-digital converter for performing analog-to-digital conversion on a signal output by the first loop-through buffer.
  15. 根据权利要求11至14任一项所述的环通输出电路，其特征在于，所述射频接收电路还包括单转双电路；所述单转双电路用于接收射频信号，将所述射频信号转换为差分信号输入到所述低噪声放大器；The loop-through output circuit according to any one of claims 11 to 14, wherein the radio frequency receiving circuit further comprises a single-to-dual circuit; the single-to-dual circuit is configured to receive a radio frequency signal and convert the radio frequency signal Converted into a differential signal and input to the low noise amplifier;
    在所述环通输出电路中，所述第一环通缓冲器包括第一部分和第二部分，所述第一环通缓冲器的第一部分和所述第一环通缓冲器的第二部分均包含所述电压缓冲电路和所述反馈电路；所述第一环通缓冲器的第一部分和所述第一环通缓冲器的第二部分分别用于对所述第一滤波器的输入端处输出的两路差分信号或者所述第一滤波器的输出端处输出的两路差分信号进行处理。In the loop-through output circuit, the first loop-through buffer includes a first portion and a second portion, and the first portion of the first loop-through buffer and the second portion of the first loop-through buffer are both Including the voltage buffer circuit and the feedback circuit; the first part of the first loop-through buffer and the second part of the first loop-through buffer are respectively used for inputting the first filter The two differential signals output or the two differential signals output at the output end of the first filter are processed.
  16. 根据权利要求15所述的环通输出电路，其特征在于，所述低噪声放大器为差分放大器，所述差分放大器包括第一输入电阻、第一反馈电容、第一反馈电阻、第二输入电阻、第二反馈电容、第二反馈电阻、第一级运算放大器、可调电容和第二级运算放大器；所述第一输入电阻的阻值、所述第一反馈电阻的阻值、所述第二输入电阻的阻值和所述第二反 馈电阻的阻值是可调的，用于调整所述差分放大器的增益；The loop-through output circuit according to claim 15, wherein the low noise amplifier is a differential amplifier, and the differential amplifier comprises a first input resistor, a first feedback capacitor, a first feedback resistor, a second input resistor, A second feedback capacitor, a second feedback resistor, a first-stage operational amplifier, an adjustable capacitor, and a second-stage operational amplifier; the resistance of the first input resistor, the resistance of the first feedback resistor, and the second The resistance of the input resistor and the resistance of the second feedback resistor are adjustable and used to adjust the gain of the differential amplifier;
    其中，所述第一输入电阻的一端为所述差分放大器的一个输入端，所述第一输入电阻的一端与所述单转双电路的一个输出端连接，所述第一输入电阻的另一端分别与第一并联电路的一端、以及所述第一级运算放大器的正相输入端连接，所述第一并联电路为所述第一反馈电容和所述第一反馈电阻组成的并联电路；Wherein, one end of the first input resistance is one input end of the differential amplifier, one end of the first input resistance is connected to one output end of the single-turn dual circuit, and the other end of the first input resistance Respectively connected to one end of a first parallel circuit and a non-inverting input terminal of the first-stage operational amplifier, and the first parallel circuit is a parallel circuit composed of the first feedback capacitor and the first feedback resistor;
    所述第一级运算放大器的负相输出端分别与所述可调电容的一端、所述第二级运算放大器的正相输入端连接；The negative-phase output terminal of the first-stage operational amplifier is connected to one end of the adjustable capacitor and the non-inverted input terminal of the second-stage operational amplifier;
    所述第二级运算放大器的正相输出端与所述第一并联电路的另一端连接；A non-inverting output terminal of the second-stage operational amplifier is connected to the other end of the first parallel circuit;
    所述第二输入电阻的一端为所述差分放大器的另一个输入端，所述第二输入电阻的一端与所述单转双电路的另一输出端连接，所述第二输入电阻的另一端分别与第二并联电路的一端、以及所述第一级运算放大器的负相输入端连接，所述第二并联电路为所述第二反馈电容和所述第二反馈电阻组成的并联电路；One end of the second input resistance is the other input end of the differential amplifier, one end of the second input resistance is connected to the other output end of the single-turn dual circuit, and the other end of the second input resistance Respectively connected to one end of a second parallel circuit and the negative-phase input terminal of the first-stage operational amplifier, and the second parallel circuit is a parallel circuit composed of the second feedback capacitor and the second feedback resistor;
    所述第一级运算放大器的正相输出端分别与所述可调电容的另一端、所述第二级运算放大器的负相输入端连接；A non-inverting output terminal of the first-stage operational amplifier is connected to the other end of the adjustable capacitor and a negative-phase input terminal of the second-stage operational amplifier;
    所述第二级运算放大器的负相输出端与所述第二并联电路的另一端连接。The negative-phase output terminal of the second-stage operational amplifier is connected to the other end of the second parallel circuit.
  17. 根据权利要求11至16任一项所述的环通输出电路，其特征在于，所述环通输出电路包括N条支路，所述N条支路并联连接；所述N条支路中的第i条支路，用于对所述第一环通缓冲器输出到所述第i条支路上的信号进行环通输出；The loop-through output circuit according to any one of claims 11 to 16, wherein the loop-through output circuit includes N branches, and the N branches are connected in parallel; An i-th branch for loop-through outputting a signal output from the first loop-through buffer to the i-th branch;
    其中，所述N为大于或等于1的正整数，所述i为满足1≤i≤N的整数，所述第i条支路为所述N条支路中任一条支路。Wherein, N is a positive integer greater than or equal to 1, the i is an integer satisfying 1 ≦ i ≦ N, and the i-th branch is any one of the N branches.
  18. 根据权利要求11至16任一项所述的环通输出电路，其特征在于，所述环通输出电路包括M条支路；The loop-through output circuit according to any one of claims 11 to 16, wherein the loop-through output circuit includes M branches;
    所述第一环通缓冲器包括M个第二环通缓冲器，所述M条支路分别包含一个所述第二环通缓冲器；第k条支路上的所述第二环通缓冲器的输出端与第k+1条支路上的所述第二环通缓冲器的输入端相连，所述第k+1条支路上的所述第二环通缓冲器用于缓存所述第k条支路上的所述第二环通缓冲器的输出端输出的信号；The first loop-through buffer includes M second loop-through buffers, and each of the M branches includes one of the second loop-through buffers; the second loop-through buffer on the k-th branch The output end of is connected to the input end of the second loop-through buffer on the k + 1 branch, and the second loop-through buffer on the k + 1 branch is used to buffer the kth A signal output from an output end of the second loop-through buffer on a branch road;
    其中，所述M为大于或等于2的正整数，所述k为满足1≤k≤M的整数，所述第k条支路为所述M条支路中任一条支路；所述第k条支路与所述第k+1条支路为所述M条支路中相邻的两条支路。Wherein, M is a positive integer greater than or equal to 2, k is an integer satisfying 1 ≦ k ≦ M, and the kth branch is any one of the M branches; the first The k branches and the k + 1th branch are two adjacent branches among the M branches.
  19. 根据权利要求18所述的环通输出电路，其特征在于，所述第k条支路还包括第二放大器，所述第二放大器的输入端与所述第k条支路上的所述第二环通缓冲器的输出端连接，用于进行信号放大。The loop-through output circuit according to claim 18, wherein the k-th branch further includes a second amplifier, and an input terminal of the second amplifier is connected to the second amplifier on the k-th branch. The output of the loop-through buffer is connected for signal amplification.
  20. 一种射频接收***，其特征在于，所述射频接收***包括射频接收设备和环通输出设备；其中：A radio frequency receiving system, characterized in that the radio frequency receiving system comprises a radio frequency receiving device and a loop-through output device; wherein:
    所述射频接收设备包括低噪声放大器、第一滤波器和第一模数转换器，用于依次对接收到的信号进行低噪声放大、滤波和模数转换；The radio frequency receiving device includes a low-noise amplifier, a first filter, and a first analog-to-digital converter, which are used to sequentially perform low-noise amplification, filtering, and analog-to-digital conversion on a received signal;
    所述环通输出设备包括第一环通缓冲器，所述第一环通缓冲器包括电压缓冲电路和反馈电路，所述电压缓冲电路用于对所述第一滤波器的输入端处输出的信号或者所述第一滤波器的输出端处输出的信号进行电压缓冲，所述电压缓冲电路的输出端输出的信号用于进行环通输出，所述反馈电路用于将所述电压缓冲电路的输出端输出的信号反馈到所述电压缓冲电路的输入端，以提高所述电压缓冲电路的环路增益。The loop-through output device includes a first loop-through buffer, and the first loop-through buffer includes a voltage buffer circuit and a feedback circuit. The voltage buffer circuit is configured to output a voltage at an input end of the first filter. The signal or the signal output at the output terminal of the first filter performs voltage buffering. The signal output from the output terminal of the voltage buffer circuit is used for loop-through output, and the feedback circuit is used to convert the voltage of the voltage buffer circuit. The signal output from the output terminal is fed back to the input terminal of the voltage buffer circuit to improve the loop gain of the voltage buffer circuit.
  21. 根据权利要求20所述的射频接收***，其特征在于，所述电压缓冲电路包含源极跟随器，所述反馈电路包含电流镜和第一晶体管；其中：The radio frequency receiving system according to claim 20, wherein the voltage buffer circuit includes a source follower, and the feedback circuit includes a current mirror and a first transistor; wherein:
    所述第一晶体管的漏极与所述电流镜的输入端耦合，所述电流镜的输出端与所述源极跟随器的源极耦合；所述电流镜和所述第一晶体管用于将所述源极跟随器的输出端输出的信号反馈到所述源极跟随器的输入端，并为所述源极跟随器的源极提供电流偏置。A drain of the first transistor is coupled to an input terminal of the current mirror, and an output terminal of the current mirror is coupled to a source of the source follower; the current mirror and the first transistor are used to connect A signal output from an output terminal of the source follower is fed back to an input terminal of the source follower, and a current bias is provided for a source of the source follower.
  22. 根据权利要求20或21所述的射频接收***，其特征在于，所述电压缓冲电路用于对所述第一滤波器的输入端处输出的信号进行电压缓冲，所述环通输出电路还包括第二滤波器和第二模数转换器，用于对所述第一环通缓冲器输出的信号进行滤波和模数转换。The radio frequency receiving system according to claim 20 or 21, wherein the voltage buffer circuit is used for voltage buffering a signal output at an input end of the first filter, and the loop-through output circuit further includes A second filter and a second analog-to-digital converter are configured to perform filtering and analog-to-digital conversion on a signal output by the first loop-through buffer.
  23. 根据权利要求20或21所述的射频接收***，其特征在于，所述电压缓冲电路用于对所述第一滤波器的输出端处输出的信号进行电压缓冲，所述环通输出电路还包括第三模数转换器，用于对所述第一环通缓冲器输出的信号进行模数转换。The radio frequency receiving system according to claim 20 or 21, wherein the voltage buffer circuit is used for voltage buffering a signal output at an output end of the first filter, and the loop-through output circuit further includes A third analog-to-digital converter is configured to perform analog-to-digital conversion on a signal output by the first loop-through buffer.
PCT/CN2018/091090 2018-06-13 2018-06-13 Loop output circuit, tv tuner and radio frequency receiving system WO2019237283A1 (en)

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