WO2019233562A1

WO2019233562A1 - A signal processing arrangement for a transmitter, and a method for such an arrangement

Info

Publication number: WO2019233562A1
Application number: PCT/EP2018/064741
Authority: WO
Inventors: Liang RONG; Bingxin Li; Chen Wang; Fuquan Zhang; Jinming WANG; Xun GU
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2018-06-05
Filing date: 2018-06-05
Publication date: 2019-12-12
Also published as: CN112119618A; CN112119618B

Abstract

The invention relates to a signal processing arrangement (100; 101; 103) for a transmitter (200; 201). The signal processing arrangement (100) comprises: a first up-conversion and mixing module (110) configured to up-convert and mix a demodulated in-phase signal (I_DM) and a demodulated quadrature signal (Q_DM) and output a first up-converted and mixed positive phase signal (IQ_PA) and a second up-converted and mixed positive phase signal (IQ_PB); a second up-conversion and mixing module (112) configured to up-convert and mix the demodulated in-phase signal (I_DM) and the demodulated quadrature signal (Q_DM) and output a first up-converted and mixed negative phase signal (IQ_NA) and a second up- converted and mixed negative phase signal (IQ_NB); a first harmonic filter (114) configured to receive the first up-converted and mixed positive phase signal (IQ_PA) and the second up- converted and mixed positive phase signal (IQ_PB) and output a first group of digital signals (IQ_PDA1, IQ_PDA2,..., IQ_PDAn) and a second group of digital signals (IQ_PDB1, IQ_PDB2,..., IQ_PDBn); and a second harmonic filter (116) configured to receive the first up-converted and mixed negative phase signal (IQ_NA) and the second up-converted and mixed negative phase signal (IQ_NB) and output a third group of digital signals (IQ_NDA1, IQ_NDA2,..., IQ_NDAn) and a fourth group of digital signals (IQ_NDB1, IQ_NDB2,..., IQ_NDBn). The invention also relates to a transmitter (200; 201) and a method (300) for a signal processing arrangement (100; 101; 103). By embodiments of the present invention, an improved DTX/DPA architecture for a transmitter is provided. In conventional DTX/DPA architectures, the up-conversion and mixing modules are placed after the harmonic filters and are thus receiving signals from the harmonic filters. By placing the up-conversion and mixing modules before the harmonic filters, the up- conversion and mixing modules use a lower frequency compared to conventional DTX/DPA architectures, and thus the power consumption can be reduced.

Description

A SIGNAL PROCESSING ARRANGEMENT FOR A TRANSMITTER, AND A METHOD FOR SUCH AN ARRANGEMENT

Technical Field

Aspects of the present invention relate to a signal processing arrangement for a transmitter. More specifically, aspects of the present invention relate to a signal processing arrangement configured to perform a part of a digital filtering. Aspects of the present invention also relate to a transmitter including a signal processing arrangement and to a method for a signal processing arrangement.

Background

In recent years, digital transmitters (DTX) and digital power amplifiers (DPA) have undergone an extensive development with support from Complementary Metal Oxide Semiconductor (CMOS) technology. Due to CMOS process scaling, digital components can nowadays switch at a high frequency which even surpasses radio frequencies while still keeping the operating power low.

Summary

An objective of embodiments of the invention is to provide a solution which mitigates or solves the drawbacks and problems of conventional solutions.

Another objective of embodiments of the present invention is to provide an improved DTX/DPA architecture for a transmitter.

According to a first aspect of the invention, the above-mentioned and other objectives are attained by providing a signal processing arrangement for a transmitter, wherein the signal processing arrangement comprises:

an in-phase demodulator configured to receive a modulated in-phase signal, demodulate the modulated in-phase signal and output a demodulated in-phase signal; a quadrature demodulator configured to receive a modulated quadrature signal, demodulate the modulated quadrature signal and output a demodulated quadrature signal; a first up-conversion and mixing module configured to receive the demodulated in- phase signal and the demodulated quadrature signal, up-convert and mix the demodulated in-phase signal and the demodulated quadrature signal and output a first up-converted and mixed positive phase signal and a second up-converted and mixed positive phase signal; a second up-conversion and mixing module configured to receive the demodulated in-phase signal and the demodulated quadrature signal, up-convert and mix the demodulated in-phase signal and the demodulated quadrature signal and output a first up- converted and mixed negative phase signal and a second up-converted and mixed negative phase signal;

a first harmonic filter configured to receive the first up-converted and mixed positive phase signal and the second up-converted and mixed positive phase signal, perform a part of a digital filtering of the first up-converted and mixed positive phase signal and the second up-converted and mixed positive phase signal and output a first group of digital signals and a second group of digital signals; and

a second harmonic filter configured to receive the first up-converted and mixed negative phase signal and the second up-converted and mixed negative phase signal, perform a part of a digital filtering of the first up-converted and mixed negative phase signal and the second up-converted and mixed negative phase signal and output a third group of digital signals and a fourth group of digital signals.

By the signal processing arrangement according to the first aspect, an improved DTX/DPA architecture for a transmitter is provided. In conventional DTX/DPA architectures, the up- conversion and mixing module/-s is/are placed after the harmonic filters and is/are thus receiving signals from the harmonic filters. By placing the up-conversion and mixing modules before the harmonic filters, the up-conversion and mixing modules can use a lower frequency compared to conventional DTX/DPA architectures, and thus the power consumption can be reduced. Further, the number of digital building blocks in the up- conversion and mixing module and in a following serializer can be reduced, which reduces the power consumption and also saves more design area on the chip in relation to conventional DTX/DPA architectures. The complexity of the structure of the following serializer can also be reduced, e.g. there is no need for channel combinations and cross overs in the serializer, and thus results in a reduction of the amount of manual work in favour of digital programming parts in the DTX/DPA architecture. Thus, with the signal processing arrangement according to the first aspect, the performance of the DTX/DPA transmitter is improved. By the signal processing arrangement according to the first aspect, the demodulation in the demodulators and the up-converting and mixing process in the up- conversion and mixing modules can be simplified. Further, since the first and second up- conversion and mixing modules are moved to before the harmonic filters, the number of input signal groups to the up-conversion and mixing modules can be further reduced by the order of the digital filtering of the harmonic filters in relation to conventional technology, and the power consumption is further reduced by‘N’ times, where‘N’ is the digital filter order. Each harmonic filter is configured to perform an at least a part of a digital filtering and hence not necessarily configured to perform the complete digital filtering of the signals. Further filtering steps are, or may be, performed by modules/blocks following the harmonic filters, e.g. as described in the detailed description hereinbelow.

In a possible implementation form of the signal processing arrangement according to the first aspect, the in-phase demodulator and the quadrature demodulator are configured to operate at a modulation frequency, wherein the first up-conversion and mixing module and the second up-conversion and mixing module are configured to use the modulation frequency, and wherein the first harmonic filter and the second harmonic filter are configured to operate at a carrier frequency which exceeds the modulation frequency. The wording“the first up-conversion and mixing module and the second up-conversion and mixing module are configured to use a frequency” can mean that they are configured to receive a signal at the frequency of the previous module. By means of this implementation form, the power consumption of the first and second up-conversion and mixing modules can be reduced by approx. 50% in comparison with conventional technology.

In a further possible implementation form of the signal processing arrangement according to the first aspect, the first harmonic filter and the second harmonic filter are configured to operate at a carrier frequency which is at least twice as high as the modulation frequency. By means of this implementation form, the power consumption of the first and second up- conversion and mixing modules can be further reduced in relation to conventional technology.

In another possible implementation form of the signal processing arrangement according to the first aspect, the signal processing arrangement comprises a serializer configured to receive the first and second groups of digital signals from the first harmonic filter and the third and fourth groups of digital signals from the second harmonic filter, serialize digital signals of the first, second, third and fourth groups of digital signals into serialized digital signals, and output the serialized digital signals. By means of this implementation form and the overall inventive concept, the serializer can be directly connected to the harmonic filters. Further, by means of this implementation form, fully switching high-efficiency power amplifiers can be directly connected to the serializer.

In yet another possible implementation form of the signal processing arrangement according to the first aspect, the serializer is configured to operate at a local oscillator frequency which exceeds the carrier frequency. By means of this implementation form, the data rate speed can be matched to previous signal processing blocks, or modules, and an efficient signal processing is provided. In still another possible implementation form of the signal processing arrangement according to the first aspect, the serializer is configured to operate at a local oscillator frequency which is at least twice as high as the carrier frequency.

In a possible implementation form of the signal processing arrangement according to the first aspect, the serializer is configured to operate at a local oscillator frequency which is equal to the carrier frequency. By means of this implementation form, the same clock signal to the harmonic filter and the serializer can be used.

In a further possible implementation form of the signal processing arrangement according to the first aspect, the signal processing arrangement comprises a plurality of power amplifiers, wherein each power amplifier of the plurality of power amplifiers is configured to receive a serialized digital signal among the serialized digital signals, power amplify the serialized digital signal and output a power-amplified digital signal. By means of this implementation form, each signal path may have a different power amplification level, and the plurality of power amplifiers may realize a part of the digital filtering.

In another possible implementation form of the signal processing arrangement according to the first aspect, the signal processing arrangement comprises:

an in-phase modulator configured to receive an in-phase signal, modulate the in- phase signal and output the modulated in-phase signal; and

a quadrature modulator configured to receive a quadrature signal, modulate the quadrature signal and output the modulated quadrature signal.

In yet another possible implementation form of the signal processing arrangement according to the first aspect, each of the in-phase modulator and the quadrature modulator is configured to perform Pulse Code Modulation.

In still another possible implementation form of the signal processing arrangement according to the first aspect, each of the in-phase modulator and the quadrature modulator is configured to perform Pulse Width Modulation.

The use of Pulse Code Modulation or Pulse Width Modulation in the in-phase modulator and the quadrature modulator simplifies the circuit design and increases the possible processing speed in comparison with modulators configured to perform sigma-delta modulation. Furthermore, the use of Pulse Code Modulation or Pulse Width Modulation in the in-phase modulator and the quadrature modulator improves the noise shaping performance in comparison with modulators configured to perform sigma-delta modulation.

In a possible implementation form of the signal processing arrangement according to the first aspect, each of the in-phase modulator and the quadrature modulator is configured to operate at the modulation frequency.

In a further possible implementation form of the signal processing arrangement according to the first aspect, each of the in-phase demodulator and the quadrature demodulator is configured to perform Pulse Code Demodulation.

In another possible implementation form of the signal processing arrangement according to the first aspect, each of the in-phase demodulator and the quadrature demodulator is configured to perform Pulse Width Demodulation.

The use of Pulse Code Modulation or Pulse Width Modulation in the in-phase demodulator and the quadrature demodulator simplifies the circuit design and increases the possible processing speed. Furthermore, the use of Pulse Code Modulation or Pulse Width Modulation in the in-phase demodulator and the quadrature demodulator improves the noise shaping performance.

In yet another possible implementation form of the signal processing arrangement according to the first aspect, each of the in-phase demodulator and the quadrature demodulator is configured to perform a linear mapping of Pulse Code Modulation or Pulse Width Modulation codes into different Pulse Width demodulation pulse width representations based on a Look-Up Table mapping. By means of this implementation form, an efficient signal processing is provided.

In still another possible implementation form of the signal processing arrangement according to the first aspect, each of the first harmonic filter and the second harmonic filter comprises at least one harmonic filter block having two inputs configured to receive signals from the respective up-conversion and mixing module, wherein each harmonic filter block comprises a plurality of first-phase data shifters and a plurality of second-phase data shifters, wherein a multiplexer is arranged between a first-phase data shifter of the plurality of first-phase data shifters and a previous first-phase data shifter of the plurality of first- phase data shifters, wherein a multiplexer is arranged between a second-phase data shifter of the plurality of second-phase data shifters and a previous second-phase data shifter of the plurality of second-phase data shifters except before a first first-phase data shifter of the plurality of first-phase data shifters and a first second-phase data shifter of the plurality of second-phase data shifters, and wherein the multiplexer is configured to output signals to only one of a first-phase data shifter of the plurality of first-phase data shifters and a second- phase data shifter of the plurality of second-phase data shifters. By means of this implementation form, an efficient digital filtering, or efficient part of the digital filtering, is provided.

In a possible implementation form of the signal processing arrangement according to the first aspect, a multiplexer is arranged between a first input of the two inputs of the harmonic filter block and each of the first-phase data shifters, and a multiplexer is arranged between a second input of the two inputs of the harmonic filter block and each of the second-phase data shifters except before the first first-phase data shifter and the first second-phase data shifter.

In a further possible implementation form of the signal processing arrangement according to the first aspect, each first-phase data shifter of the first harmonic filter is configured to output a digital signal of the first group of digital signals, and each second-phase data shifter of the first harmonic filter is configured to output a digital signal of the second group of digital signals, and wherein each first-phase data shifter of the second harmonic filter is configured to output a digital signal of the third group of digital signals, and each second-phase data shifter of the second harmonic filter is configured to output a digital signal of the fourth group of digital signals.

According to a second aspect of the invention, the above-mentioned and other objectives are attained by providing a transmitter comprising a signal processing arrangement according to the first aspect.

According to a third aspect of the invention, the above-mentioned and other objectives are attained by providing a method for a signal processing arrangement, the method comprising:

receiving a modulated in-phase signal and demodulating the modulated in-phase signal;

receiving a modulated quadrature signal and demodulating the modulated quadrature signal; up-converting and mixing the demodulated in-phase signal and the demodulated quadrature signal and outputting a first up-converted and mixed positive phase signal and a second up-converted and mixed positive phase signal;

up-converting and mixing the demodulated in-phase signal and the demodulated quadrature signal and outputting a first up-converted and mixed negative phase signal and a second up-converted and mixed negative phase signal;

performing a part of a digital filtering of the first up-converted and mixed signal positive phase and the second up-converted and mixed positive phase signal and outputting a first group of digital signals and a second group of digital signals; and

performing a part of a digital filtering of the first up-converted and mixed negative phase signal and the second up-converted and mixed negative phase signal and outputting a third group of digital signals and a fourth group of digital signals.

The method according to the third aspect can be extended into implementation forms corresponding to the implementation forms of the signal processing arrangement according to the first aspect. Hence, an implementation form of the method comprises the feature(s) of the corresponding implementation form of the signal processing arrangement.

The advantages of the methods according to the third aspect are the same as those for the corresponding implementation forms of the signal processing arrangement according to the first aspect.

The invention also relates to a computer program, characterized in program code, which when run by at least one processor causes said at least one processor to execute any method according to embodiments of the invention. Further, the invention also relates to a computer program product comprising a computer readable medium and said mentioned computer program, wherein said computer program is included in the computer readable medium, and comprises of one or more from the group: ROM (Read-Only Memory), PROM (Programmable ROM), EPROM (Erasable PROM), Flash memory, EEPROM (Electrically EPROM) and hard disk drive.

The above-mentioned features and implementation forms, respectively, may be combined in various possible ways providing further advantageous implementations.

Further applications and advantages of the embodiments of the present invention will be apparent from the following detailed description. Brief Description of the Drawings

The appended drawings are intended to clarify and explain different embodiments of the present invention, in which:

Fig. 1 schematically illustrates a signal processing arrangement for a transmitter

according to an embodiment of the present invention;

Fig. 2 schematically illustrates a signal processing arrangement for a transmitter

according to an embodiment of the present invention;

Fig. 3 schematically illustrates a transmitter comprising a signal processing

arrangement according to embodiments of the present invention;

Fig. 4 is a schematic diagram illustrating an embodiment of a harmonic filter block of the first harmonic filter or second harmonic filter;

Fig. 5 is a schematic diagram illustrating a signal processing arrangement and a

transmitter according to embodiments of the present invention;

Fig. 6 schematically illustrates a transmitter device in a wireless communication system including embodiments of the present invention; and

Fig. 7 is a flow chart schematically illustrating aspects of a method according to the present invention.

Detailed Description

The above-mentioned trend regarding CMOS technology provides the motivation for the inventors to realize a DTX/DPA in a pure digital style. In a DTX/DPA architecture according to conventional technology the demand of using digital signal processing as much as possible removes the use of a digital-to-analog converter (DAC). The DAC is replaced by a digital up-sampling module to align the data flow bit rate with a digital carrier signal later in the DTX/DPA. For the same reason, the analog channel bandwidth filter is also removed. To compensate for the digitized signal quantization noise problem, a noise shaping algorithm/module may be used to enhance the signal-to-noise performance, and during this stage different DPA modulation algorithms and different types of DPAs emerged. For example, some may use analog-to-digital (ADC) sampling algorithm and others may use sigma-delta modulation (SDM) algorithm or pulse width modulation (PWM) algorithm, so these algorithms categorize the DTX/DPA into RF-DAC / RF-SDM / RF-PWM type DTX/DPA.

A DTX/DPA is a transmitter architecture which implements mostly digital switching blocks/modules for signal processing/modulation and switching power amplifiers (PA) as output stage to amplify output RF power. A DTX/DPA is different from a traditional analog/RF transmitter because the internal signal flow has mostly on/off switching digital characteristics instead of a continuous analog/RF signal.

After the noise shaping processing, the digital signal with multiple level representation often needs to be further processed and mapped into a fully switching on/off (O’s or Ts) signal. Here, the digital demodulation module may be used. In this stage, the digital signal will finally be synchronized into bit rates for the digital carrier signal and is turned into a fully ones/zeros bit sequence. The demodulation method can match the previous modulation algorithm but it is also possible to use a combination of modulation techniques. As an example, SDM modulation may use ADC or PWM style demodulation methods.

With digitized high-speed baseband data according to conventional technology, digital up- conversion and mixing may also be realized in digital style. For example, when‘1010...10’ represents 0-degree phase carrier signal, its complementary signal Ό101 ...0T represents 180-degree negative phase signal. And with more bits combination, l-channel and Q- channel carrier frequency signals can be represented in digital bits. This greatly facilitates the RF digital up-conversion process since a simple‘AND’ logic operation is sufficient. Since the digital RF l/Q carrier signal has a fixed pattern for every baseband modulation cycle, a batch process can help to reduce the processing clock frequency, and parallel data bits are generated during this process.

In DTX/DPA architectures according to conventional technology, a digital signal may be modulated into an in-phase signal and a quadrature signal. According to conventional technology, sigma-delta modulation (SDM) may be used for noise shaping processing, and pulse-width modulation (PWM) translation may be used as digital demodulation for the in- phase signal and the quadrature signal, respectively. Conventionally, connected to the digital demodulation modules are repeaters configured to data-rate match the signal from PWM to the RF carrier signal. Connected to the repeaters is an interleaver module which realizes digital up-conversion and mixing. The mixed digital signal is then fed to a power amplifier (PA). Conventionally, the power amplifier is connected to a load which is configured to radiate RF signal into the surrounding air.

Conventionally, modulation harmonics are quite common for DTX/DPAs which use a different modulation processing frequency different from the carrier frequency. Thus, once the modulation frequency is too small, modulation harmonics will be quite close to the band- of-interest and then the system bandpass filter may be quite hard to attenuate. Each structure of Figs. 1 -3 and 5 can be described as a DTX/DPA architecture, such as a DTX/DPA architecture in a pure digital style, which provides a solution which mitigates or solves the drawbacks and problems of conventional solutions.

Fig. 1 schematically illustrates a signal processing arrangement 100 for a transmitter according to an embodiment of the invention. The signal processing arrangement 100 includes an in-phase demodulator 106 configured to receive a modulated in-phase signal IM, demodulate the modulated in-phase signal IM and output a demodulated in-phase signal IDM. Further, the signal processing arrangement 100 includes a quadrature demodulator 108 configured to receive a modulated quadrature signal Q_M, demodulate the modulated quadrature signal Q_M and output a demodulated quadrature signal QDM-

The signal processing arrangement 100 of Fig. 1 also includes a first up-conversion and mixing module 1 1 0 configured to receive the demodulated in-phase signal I_DM and the demodulated quadrature signal QDM, up-convert and mix the demodulated in-phase signal IDM and the demodulated quadrature signal QDM and output a first up-converted and mixed positive phase signal IQPA and a second up-converted and mixed positive phase signal IQPB. Furthermore, the signal processing arrangement 100 includes a second up-conversion and mixing module 1 1 2 configured to receive the demodulated in-phase signal IDM and the demodulated quadrature signal QDM, up-convert and mix the demodulated in-phase signal IDM and the demodulated quadrature signal QDM and output a first up-converted and mixed negative phase signal IQNA and a second up-converted and mixed negative phase signal IQNB.

Further, the signal processing arrangement 100 includes a first harmonic filter 1 14 configured to receive the first up-converted and mixed positive phase signal IQPA and the second up-converted and mixed positive phase signal IQPB, perform a part of a digital filtering of the first up-converted and mixed positive phase signal IQ_PA and the second up- converted and mixed positive phase signal IQ_PB and output a first group of digital signals IQPDAI , IQPDA2, , IQpDAn and a second group of digital signals IQPDEM , IQPDB2, . . . , IQPDB_R. The signal processing arrangement 100 also includes a second harmonic filter 1 16 configured to receive the first up-converted and mixed negative phase signal IQNA and the second up- converted and mixed negative phase signal IQNB, perform a part of a digital filtering of the first up-converted and mixed negative phase signal IQNA and the second up-converted and mixed negative phase signal IQNB and output a third group of digital signals IQNDAI , IQNDA2, . . , IQNDA_H and a fourth group of digital signals IQNDBI , IQNDB2, . . . , IQNDB_R. Each harmonic filter 1 14, 1 16 is configured to perform at least pa/Tof a digital filtering. Hence, the harmonic filter 1 14, 1 16 do not need to be configured to perform the complete digital filtering of the signals. Instead, further filtering steps are performed by modules/blocks, such as power amplifiers 130a, 130b,..., 130n and a power combination filter 136, following the harmonic filters 1 14, 1 16, as described below in connection with Fig. 3. By the inventive signal processing arrangement, the demodulation in the demodulators 106, 108 and the up- converting and mixing process in the up-conversion and mixing modules 1 10, 1 12 can be simplified.

With reference to Fig. 1 , the in-phase demodulator 106 and the quadrature demodulator 108 are configured to operate at a modulation frequency f_m, and the first up-conversion and mixing module 1 10 and the second up-conversion and mixing module 1 12 are configured to use the modulation frequency f_m. The first harmonic filter 1 14 and the second harmonic filter 1 16 are configured to operate at a carrier frequency f_c which exceeds the modulation frequency f_m. By placing the up-conversion and mixing modules 1 10, 1 12 before the harmonic filters 1 14, 1 16, the up-conversion and mixing modules 1 10, 1 12 can use a lower frequency compared to conventional DTX/DPA architectures, and thus the power consumption can be reduced. The first harmonic filter 1 14 and the second harmonic filter 1 16 may even be configured to operate at a carrier frequency f_c which is at least twice as high as the modulation frequency f_m.

According to further aspects of the signal processing arrangement 100, the first up- conversion and mixing module 1 10 is configured to up-convert and mix the demodulated in- phase signal IDM and the demodulated quadrature signal QDM based on at least one group of local oscillation, LO, patterns, e.g. two groups of LO patterns L01 and L02. Further, the second up-conversion and mixing module 1 12 is configured to up-convert and mix the demodulated in-phase signal IDM and the demodulated quadrature signal QDM based on the group/-s of LO patterns L01 , L02 used by the first up-conversion and mixing module 1 10. When the up-conversion and mixing is based on a group of LO patterns, one or more patterns/values of that group of LO patterns may be applied. A first group of LO patterns according to an eight bits version may be as follows:

IJo1_positive: 1000.1000

IJo1_negative: 0010.0010

QJo1_positive: 0100.0100.

Q_lo1_negative: 0001 .0001 A second group of LO patterns according to an eight bits version may be as follows:

IJo2_positive: 0001 .0001

IJo2_negative: 0100.0100

QJo2_positive: 1000.1000

Q_lo2_negative: 0010.0010

It is assumed, for example, that the modulated in-phase signal IM value is +3, and the modulated quadrature signal QM value is -2. In the in-phase demodulator 106, +3 (IM) is demodulated into 0.01 1 1 .1 1 10 (I_DM), where the first Ό’ represents the“positive value”, and the last four digits‘1 1 10’ are the mirror of the 8-to-5 bits Ό1 1 1’ in left-right-swap style. In a corresponding manner, in the quadrature demodulator 108, -2 (Q_M) is demodulated into 1 .001 1 .1 100 (QDM) , where the first‘1’ represent the“negative value”. The first up-conversion and mixing module 1 10 translates the input data from the in-phase demodulator 106 and the quadrature demodulator 108, but its purpose is only to up-convert and mix the input with positive phase LO and output positive phase values. When the first up-conversion and mixing module 1 10 receives the demodulated value 0.01 1 1 .1 1 10 (IDM) from the in-phase demodulator 106 and the demodulated value 1 .001 1 .1 100 (QDM) from the quadrature demodulator 108, the first up-conversion and mixing module 1 10 recognizes that the original modulated in-phase signal IM is a positive value and that there should be an up-conversion with the positive IJo pattern. Thus, the first up-conversion and mixing module 1 10‘bit AND’- operates on the value 0.01 1 1 .1 1 10 (I DM) with 1000.1000 ( IJo 1 _positive) and obtains the temporary value/data 0000.1000. Further, the first up-conversion and mixing module 1 10 also needs to‘bit AND’-operate on the Q path value, but since the Q value is negative, the first up-conversion and mixing module 1 10 up-converts 001 1 .1 100 (QDM) with 0001 .0001 (Q_lo1_negative) and obtains the temporary data 0001 .0000. The final operation in the first up-conversion and mixing module 1 10 is to mix the two temporary data 0000.1000 and 0001 .0000 by a ‘bit OR’ operation, and the first output 0001 .1000 from the first up- conversion and mixing module 1 10 is provided, i.e. the first up-converted and mixed positive phase signal IQ_PA. The second up-conversion and mixing module 1 12 also receives the data 0.01 1 1 .1 1 10 (I DM) and 1 .001 1 .1 100 (QDM) but are used for generating negative phase up-converted and mixed data. Thus, when the second up-conversion and mixing module 1 12 recognizes that the original modulated in-phase signal IM is a positive value and the original modulated quadrature signal QM is a negative value, the second up-conversion and mixing module 1 12 up-converts 01 1 1 .1 1 10 ( IDM) with 0010.0010 (IJo1_negative) and up- converts 001 1 .1 100 (QDM) with 0100.0100 (Q_lo1_positive). Then, the two temporary data in the second up-conversion and mixing module 1 12 are 0010.0010 and 0000.0100, and after‘bit OR’ mixing, the output 0010.01 10 is provided, i.e. the first up-converted and mixed negative phase signal IQNA. For the first up-conversion and mixing module 1 1 0 to obtain the second up-converted and mixed positive phase signal IQPB and for the second up- conversion and mixing module 1 12 to obtain the second up-converted and mixed negative phase signal IQNB, the second group of LO patterns is applied in a corresponding manner.

According to aspects of the signal processing arrangement 100, the first up-conversion and mixing module 1 10 is used to translate input data/signals from the in-phase demodulator 106 and the quadrature demodulator 108. The purpose of the first up-conversion and mixing module 1 10 is to up-convert and mix input signals with LO patterns and output the first up- converted and mixed positive phase signal IQ_PA and the second up-converted and mixed positive phase signal IQ_PB. The second up-conversion and mixing module 1 12 is also used to translate input data/signals from the in-phase demodulator 106 and the quadrature demodulator 108. The purpose of the second up-conversion and mixing module 1 12 is to up-convert and mix input signals with the LO patterns and output the first up-converted and mixed negative phase signal IQNA and the second up-converted and mixed negative phase signal IQNB.

Each of the in-phase demodulator 106 and the quadrature demodulator 108 may be configured to perform Pulse Code Demodulation. Alternatively, each of the in-phase demodulator 106 and the quadrature demodulator 108 may be configured to perform Pulse Width Demodulation. Each of the in-phase demodulator 106 and the quadrature demodulator 108 may be configured to perform a linear mapping of Pulse Code Modulation or Pulse Width Modulation codes into different Pulse Width demodulation pulse width representations based on a Look-Up Table, LUT, mapping, whereby an efficient signal processing is provided.

Fig. 2 schematically illustrates a signal processing arrangement 101 for a transmitter according to a further embodiment. The signal processing arrangement 101 includes, in addition to the modules/blocks disclosed in Fig. 1 and described above, an in-phase modulator 102 configured to receive an in-phase signal I, modulate the in-phase signal I and output the modulated in-phase signal l_M, and a quadrature modulator 104 configured to receive a quadrature signal Q, modulate the quadrature signal Q and output the modulated quadrature signal QM. Each of the in-phase modulator 102 and the quadrature modulator 104 may be configured to perform Pulse Code Modulation, PCM. Alternatively, each of the in-phase modulator 102 and the quadrature modulator 104 may be configured to perform Pulse Width Modulation, PWM. Each of the in-phase modulator 102 and the quadrature modulator 104 is configured to operate at the modulation frequency f_m at which the in-phase demodulator 106 and the quadrature demodulator 108 are configured to operate.

Fig. 3 schematically illustrates an embodiment of a transmitter 200 comprising the signal processing arrangement 101 as disclosed above in relation to Fig. 2. In addition, the signal processing arrangement 101 includes a serializer 1 18 configured to receive the first and second groups of digital signals IQPDAI , IQPDA2, . . . , IQPDAH; IQPDBI , IQPDB2, . . . , IQPDBH from the first harmonic filter 1 14 and the third and fourth groups of digital signals IQNDAI , IQNDA2, . . . , IQNDA_H ; IQNDBI , IQNDB2_J , IQNDB_H from the second harmonic filter 1 16, serialize the digital signals of the first, second, third and fourth groups of digital signals IQPDAI , IQPDA2, · . · , IQPDA_H; IQPDBI , IQPDB2, · · · , IQpDBn! IQNDAI , IQNDA2, · · · , IQNDAn! IQNDBI , IQNDB2, · · · , IQNDBn into serialized digital signals, and output the serialized digital signals. The serializer 1 18 may be configured to operate at a local oscillator frequency f_to which exceeds the carrier frequency f_c. For example, the serializer 1 18 is configured to operate at a local oscillator frequency fi₀ which is at least twice as high as the carrier frequency f_c. Alternatively, the serializer 1 18 may be configured to operate at a local oscillator frequency fi₀ which is equal to the carrier frequency f_c. One aspect of the disclosed embodiments is that the processing delay can be more accurately controlled when the data is sent from the respective harmonic filter 1 14, 1 16 to the serializer 1 18, and the serializer 1 18, which may be a high-speed serializer, can accept data at a more accurate timing instead of conventional information-dependent delayed data.

Furthermore, the signal processing arrangement 101 of Fig. 3 includes a plurality of power amplifiers 130a, 130b,..., 130n. Each power amplifier 130a, 130b,..., 130n of the plurality of power amplifiers 130a, 130b,..., 130n is configured to receive a serialized digital signal among the serialized digital signals from the serializer 1 18, power amplify the serialized digital signal and output a power-amplified digital signal. The power amplifiers 130a, 130b,..., 130n connected to the serializer 1 18 are configured to perform a part of the digital filtering by adding signal weight (increasing/decreasing power level). A switching capacitance power combination network may realize the final step of digital filtering and combine multiple power amplifiers output power into simple single-ended or differential output power. The transmitter 200 may include a power combination filter 136 which realizes steps of the filtering and combines the power-amplified serialized digital signals into a combined output signal which is output to a load in the form of an antenna 138. The power combination filter 136 may be realized in a large number of ways and its function is to combine the power amplified serialized digital signals from the power amplifiers 130a, 130b,..., 130n. With reference to Fig. 3, the final signal processing steps are made in the power combination filter 136. The first harmonic filter 1 14 may be configured to realize a part of the signal processing steps necessary for filtering out modulation harmonics in the demodulated in-phase signal IDM and in the demodulated quadrature signal QDM. Correspondingly, the second harmonic filter 1 16 may be configured to realize a part of the signal processing steps necessary for filtering out modulation harmonics in the demodulated in-phase signal IDM and in the demodulated quadrature phase signal QDM. The remainder of the steps needed for filtering out modulation harmonics in the demodulated in-phase signal IDM and in the demodulated quadrature signal QDM are performed in the power combination filter 136 after the serializer 1 18. The antenna 138 is connected to the power combination filter 136.

The transmitter 200 includes a digital up-sampling device 132 comprising an input 134. The digital up-sampling device 132 does not necessarily form part of the signal processing arrangement 101 . The digital up-sampling device 132 is configured to receive a digital input signal SIN via the input 134 and up-sample and transform the digital input signal SIN into an in-phase signal I and a quadrature signal Q.

The digital up-sampling device 132 is driven by a first clock signal CLK1 . With reference to Fig. 2, also the in-phase modulator 102 and the quadrature modulator 104 are driven by the first clock signal CLK1 . The frequency of the first clock signal CLK1 is called the modulation frequency f_m. With reference to Figs. 1 and 2, the in-phase demodulator 106 and the quadrature demodulator 108 are also driven by the first clock signal CLK1 . The first harmonic filter 1 14 and the second harmonic filter 1 16 are driven by a second clock signal CLK2 of a first phase PH1 and a second phase PH2. The frequency of the second clock signal CLK2 is called the carrier frequency f_c. With reference to Fig. 3, the serializer 1 18 is driven by a third clock signal CLK3 having the local oscillator frequency fi₀, which may be at least twice as high as the carrier frequency f_c.

With reference to Fig. 4, each of the first harmonic filter 1 14 and the second harmonic filter 1 16 is illustrated in more detail. Each of the first harmonic filter 1 14 and the second harmonic filter 1 16 includes at least one harmonic filter block 140 which has two inputs 142, 144 configured to receive signals IQPA, IQPB; IQNA, IQNB from the first up-conversion and mixing module 1 10 or the second up-conversion and mixing module 1 12. The harmonic filter block 140 includes a plurality of first-phase data shifters 148, 148’, 148” and a plurality of second- phase data shifters 150, 150’, 150”. A multiplexer (MUX) 152, 152’ is arranged between a first-phase data shifter 148’, 148” of the plurality of first-phase data shifters 148, 148’, 148” and a previous first-phase data shifter 148, 148’ of the plurality of first-phase data shifters 148, 148’, 148”, and a MUX 154, 154’ is arranged between a second-phase data shifter 150’, 150” of the plurality of second-phase data shifters 150, 150’, 150” and a previous second-phase data shifter 150, 150’ of the plurality of second-phase data shifters 150, 150’, 150” except before a first first-phase data shifter 148 of the plurality of first-phase data shifters 148, 148’, 148” and a first second-phase data shifter 150 of the plurality of second- phase data shifters 150, 150’, 150”. Thus, there is no MUX arranged before first first-phase data shifter 148, and there is no MUX arranged before the first second-phase data shifter 150. The MUX 152, 152’, 154, 154’ is configured to output signals to only one of a first- phase data shifter 148’, 148” of the plurality of first-phase data shifters and a second-phase data shifter 150’, 150” of the plurality of second-phase data shifters. Further, a MUX 152, 152’ is arranged between a first input 142 of the two inputs 142, 144 of the harmonic filter block 140 and each of the first-phase data shifters 148’, 148”, and a MUX 154, 154’ is arranged between a second input 144 of the two inputs 142, 144 of the harmonic filter block 140 and each of the second-phase data shifters 150’, 150” except before the first first-phase data shifter 148 and the first second-phase data shifter 150. Thus, there is no MUX arranged between the first first-phase data shifter 148 and the first input 142, and there is no MUX arranged between the first second-phase data shifter 150 and the second input 144. In alternative wording, the first first-phase data shifter 148 is connected to the first input 142 without any intermediate MUX, and the first second-phase data shifter 150 is connected to the second input 144 without any intermediate MUX. Each MUX 152, 152’, 154, 154’ may be configured to output the signal from the respective input 142, 144 of the harmonic filter block 140 or the signal from a previous data shifter 148, 148’, 150, 150’.

Each first-phase data shifter 148, 148’, 148” of the first harmonic filter 1 14 is configured to output a digital signal of the first group of digital signals IQPDAI , IQPDA2, . . . , IQPDA_R. Each second-phase data shifter 150, 150’, 150” of the first harmonic filter 1 14 is configured to output a digital signal of the second group of digital signals IQPDEM , IQPDB2. . . IQPDB_R. Each first-phase data shifter 148, 148’, 148” of the second harmonic filter 1 16 is configured to output a digital signal of the third group of digital signals IQNDAI , IQNDA2, . . . , IQNDA_R. Each second-phase data shifter 150, 150’, 150” of the second harmonic filter 1 16 is configured to output a digital signal of the fourth group of digital signals IQNDBI , IQNDB2, · · · , IQNDB_R. In Fig. 4, a first vertical line 156 with arrows represents the above-mentioned first phase PH1 , and a second vertical line 158 with arrows represents the above-mentioned second phase PH2. The number of serialized digital signals output from the serializer 1 18 corresponds to the number of digital signals output from the first harmonic filter 1 14 and the second harmonic filter 1 16, which in turn corresponds to the number of output signals from the first-phase data shifters 148, 148’, 148” and the second-phase data shifters 150, 150’, 150” of the first harmonic filter 1 14 and the second harmonic filter 1 16. It is to be understood that each filter block 140 may include any suitable number of data shifters 148, 148’, 148”, 150, 150’, 150” and any suitable number of multiplexers 152, 152’, 154, 154’.

With reference to Fig. 2, a first path can be defined by the in-phase modulator 102, the in- phase demodulator 106, the first up-conversion and mixing module 1 10 and the first harmonic filter 1 14, and a second path can be defined by the quadrature modulator 104, the quadrature demodulator 108, the second up-conversion and mixing module 1 12 and the second harmonic filter 1 16. It is to be understood that each path of the first and second paths of Fig. 2 may be configured in a cascaded manner, i.e. as a cascaded architecture.

For example, in Fig. 5, which schematically illustrates a signal processing arrangement 103 and a transmitter 201 according to embodiments, three cascaded in-phase modulator blocks 102’ and three cascaded in-phase demodulator blocks 106’ are provided. Further, three cascaded quadrature modulator blocks 104’ and three cascaded quadrature demodulator blocks 108’ are provided. In Fig. 5, three up-conversion and mixing modules 1 10’ and three harmonic filter blocks 140’ are also provided. As in the previous embodiments, a serializer 1 18 is connected to the harmonic filter blocks 140’ and the power amplifiers 130a, 130b,..., 130n. The power amplifiers 130a, 130b,..., 130n are connected to a power combination filter 136, which in turn is connected to an antenna 138. A digital up-sampling device 132 is connected to the modulator blocks 102’, 104’. A digital baseband 160 may be connected to the digital up-sampling device 132. Each demodulator block 106’, 108’ is connected to at least one modulator block 102’, 104’ and an up-conversion and mixing module 1 10’. Each harmonic filter block 140’ is connected to an up-conversion and mixing module 1 10’ and the serializer 1 18. It is to be understood that each path of the above- mentioned first and second paths may include any suitable number of cascaded modulator blocks 102’, 104’, demodulator blocks 106’, 108’, up-conversion and mixing modules 1 10’ and harmonic filter blocks 140’. By means of the cascaded architecture, a lower flat noise floor is provided.

Fig. 6 schematically shows a transmitter device 300, e.g. a mobile phone, in a wireless communication system 400. The transmitter device 300 comprises a transmitter 200; 201 according to Fig. 3 or Fig. 5. The wireless communication system 400 also comprises a base station 500 which may also comprise a transmitter 200; 201 , e.g. according to any one of the embodiments described above. The dotted arrow A1 represents transmissions from the transmitter device 300 to the base station 500, which are usually called up-link transmissions. The full arrow A2 represents transmissions from the base station 500 to the transmitter device 300, which are usually called down-link transmissions.

The transmitter device 300 including the transmitter 200; 201 herein disclosed may be denoted as a user device, a User Equipment (UE), a mobile station, an internet of things (loT) device, a sensor device, a wireless terminal and/or a mobile terminal, and is enabled to communicate wirelessly in a wireless communication system, sometimes also referred to as a cellular radio system, especially an LTE or New Radio (NR/5G) communication system. The UEs may further be referred to as mobile telephones, cellular telephones, computer tablets or laptops with wireless capability. The UEs in the present context may be, e.g., portable, pocket-storable, hand-held, computer-comprised, or vehicle-mounted mobile devices, enabled to communicate voice and/or data, via the radio access network, with another entity, such as another receiver or a server. The UE can be a Station (STA), which is any device that contains an IEEE 802.1 1 -conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM). The UE may also be configured for communication in 3GPP related LTE and LTE-Advanced, in WiMAX and its evolution, and in fifth generation wireless technologies, such as New Radio.

The transmitter device 300 may also be a radio client device, an access client device, an access point, or a base station, e.g., a Radio Base Station (RBS), which in some networks may be referred to as transmitter,“gNB”,“gNodeB”,“eNB”,“eNodeB”,“NodeB” or“B node”, depending on the technology and terminology used. The radio network nodes may be of different classes such as, e.g., macro eNodeB, home eNodeB or pico base station, based on transmission power and thereby also cell size. The radio network node can be a Station (STA), which is any device that contains an IEEE 802.1 1 -conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM). The radio client device may also be a base station corresponding to the fifth generation (5G) wireless systems.

With reference to Fig. 7, a method 300 for a signal processing arrangement 100 is also provided. The method 300 comprises:

receiving 302 a modulated in-phase signal l_M and demodulating 304 the modulated in-phase signal IM;

receiving 306 a modulated quadrature signal Q_M and demodulating 308 the modulated quadrature signal Q_M; up-converting and mixing 31 0 the demodulated in-phase signal IDM and the demodulated quadrature signal QDM and outputting a first up-converted and mixed positive phase signal IQPA and a second up-converted and mixed positive phase signal IQPB;

up-converting and mixing 312 the demodulated in-phase signal I_DM and the demodulated quadrature signal Q_DM and outputting a first up-converted and mixed negative phase signal IQ_NA and a second up-converted and mixed negative phase signal IQ_NB; performing 314 a part of a digital filtering of the first up-converted and mixed signal positive phase IQPA and the second up-converted and mixed positive phase signal IQPB and outputting a first group of digital signals IQPDAI , IQPDA2, . . . , IQPDA_H and a second group of digital signals IQ_PDBI , IQPDB2, . · · , IQPDBH ; and

performing 316 a part of a digital filtering of the first up-converted and mixed negative phase signal IQNA and the second up-converted and mixed negative phase signal IQNB and outputting a third group of digital signals IQNDAI , IQNDA2, . . . , IQNDA_H and a fourth group of digital signals IQNDBI , IQNDB2, · · · , IONOBP-

Furthermore, any method according to embodiments of the invention may be implemented in a computer program, having code means, which when run by processing means causes the processing means to execute the steps of the method. The computer program is included in a computer readable medium of a computer program product. The computer readable medium may comprise essentially any memory, such as a ROM (Read-Only Memory), a PROM (Programmable Read-Only Memory), an EPROM (Erasable PROM), a Flash memory, an EEPROM (Electrically Erasable PROM), or a hard disk drive.

The features of the different embodiments of the signal processing arrangement, method, transmitter and transmitter device disclosed above may be combined in various possible ways providing further advantageous embodiments.

Finally, it should be understood that the invention is not limited to the embodiments described above, but also are related to and incorporates all embodiments within the scope of the appended independent claims.

Claims

1 . A signal processing arrangement (100) for a transmitter (200), wherein the signal processing arrangement (100) comprises:

an in-phase demodulator (106) configured to receive a modulated in-phase signal (IM), demodulate the modulated in-phase signal (IM) and output a demodulated in-phase signal (IDM) ;

a quadrature demodulator (108) configured to receive a modulated quadrature signal (QM), demodulate the modulated quadrature signal (QM) and output a demodulated quadrature signal (QDM);

a first up-conversion and mixing module (1 10) configured to receive the demodulated in-phase signal (IDM) and the demodulated quadrature signal (QDM), up-convert and mix the demodulated in-phase signal ( IDM) and the demodulated quadrature signal (QDM) and output a first up-converted and mixed positive phase signal ( IQPA) and a second up-converted and mixed positive phase signal (IQPB) ;

a second up-conversion and mixing module (1 12) configured to receive the demodulated in-phase signal ( IDM) and the demodulated quadrature signal (QDM) , up- convert and mix the demodulated in-phase signal (I DM) and the demodulated quadrature signal (QDM) and output a first up-converted and mixed negative phase signal (IQNA) and a second up-converted and mixed negative phase signal (IQNB) ;

a first harmonic filter (1 14) configured to receive the first up-converted and mixed positive phase signal (IQP_A) and the second up-converted and mixed positive phase signal (IQPB), perform a part of a digital filtering of the first up-converted and mixed positive phase signal (IQPA) and the second up-converted and mixed positive phase signal (IQPB) and output a first group of digital signals (IQPDAI , IQPDA2,... , IQPDA_H) and a second group of digital signals (IQPDBI , IQPDB2, ..., IQPDBH) ; and

a second harmonic filter (1 16) configured to receive the first up-converted and mixed negative phase signal (IQNA) and the second up-converted and mixed negative phase signal (IQNB), perform a part of a digital filtering of the first up-converted and mixed negative phase signal (IQNA) and the second up-converted and mixed negative phase signal (IQNB) and output a third group of digital signals (IQNDAI , IQNDA2, . . . , IQNDA_H) and a fourth group of digital signals (IQNDB I , IQNDB2, . . . , IQNDBR).

2. A signal processing arrangement (100) according to claim 1 , wherein the in-phase demodulator (106) and the quadrature demodulator (108) are configured to operate at a modulation frequency (f_m), wherein the first up-conversion and mixing module (1 10) and the second up-conversion and mixing module (1 12) are configured to use the modulation frequency (f_m), and wherein the first harmonic filter (1 14) and the second harmonic filter (1 16) are configured to operate at a carrier frequency (f_c) which exceeds the modulation frequency (f_m).

3. A signal processing arrangement (100) according to claim 2, wherein the first harmonic filter (1 14) and the second harmonic filter (1 16) are configured to operate at a carrier frequency (f_c) which is at least twice as high as the modulation frequency (f_m).

4. A signal processing arrangement (100) according to claim 2 or 3, wherein the signal processing arrangement (100) comprises a serializer (1 18) configured to receive the first and second groups of digital signals (IQPDAI , IQPDA2, . · · , IQPDAH; IQPDBI , IQPDB2, . . . , IQPDBH) from the first harmonic filter (1 14) and the third and fourth groups of digital signals (IQNDAI , IQNDA2, . . . , IQNDAH ; IQNDBI , IQNDB2, . . . , IQNDBH) from the second harmonic filter (1 16), serialize digital signals of the first, second, third and fourth groups of digital signals ( IQPDAI , IQPDA2, .. . , IQpDAn! IQPDBI , IQPDB2, .. . , IQpDBn! IQNDAI , IQNDA2, .. . , IQNDAn! IQNDBI , IQNDB2, .. . , IQNDBn) into serialized digital signals, and output the serialized digital signals.

5. A signal processing arrangement (100) according to claim 4, wherein the serializer (1 18) is configured to operate at a local oscillator frequency (fi₀) which exceeds the carrier frequency (f_c).

6. A signal processing arrangement (100) according to claim 5, wherein the serializer (1 18) is configured to operate at a local oscillator frequency (f_|0) which is at least twice as high as the carrier frequency (f_c).

7. A signal processing arrangement (100) according to claim 4, wherein the serializer (1 18) is configured to operate at a local oscillator frequency (fi₀) which is equal to the carrier frequency (f_c).

8. A signal processing arrangement (100) according to any of the claims 4 to 7, wherein the signal processing arrangement (100) comprises a plurality of power amplifiers (130a, 130b,..., 130n), wherein each power amplifier (130a, 130b,..., 130n) of the plurality of power amplifiers (130a, 130b,..., 130n) is configured to receive a serialized digital signal among the serialized digital signals, power amplify the serialized digital signal and output a power- amplified digital signal.

9. A signal processing arrangement (101 ) according to any of the claims 1 to 8, wherein the signal processing arrangement (101 ) comprises:

an in-phase modulator (102) configured to receive an in-phase signal (I), modulate the in-phase signal (I) and output the modulated in-phase signal ( IM) ; and

a quadrature modulator (104) configured to receive a quadrature signal (Q), modulate the quadrature signal (Q) and output the modulated quadrature signal (QM).

10. A signal processing arrangement (101 ) according to claim 9, wherein each of the in- phase modulator (102) and the quadrature modulator (104) is configured to operate at the modulation frequency (f_m).

1 1 . A signal processing arrangement (101 ) according to any of the claims 1 to 10, wherein each of the in-phase demodulator (106) and the quadrature demodulator (108) is configured to perform a linear mapping of Pulse Code Modulation or Pulse Width Modulation codes into different Pulse Width demodulation pulse width representations based on a Look-Up Table mapping.

12. A signal processing arrangement (100) according to any of the claims 1 to 1 1 , wherein each of the first harmonic filter (1 14) and the second harmonic filter (1 16) comprises at least one harmonic filter block (140) having two inputs (142, 144) configured to receive signals (IQPA, IQPB; IQNA, IQNB) from the respective up-conversion and mixing module (1 10; 1 12), wherein each harmonic filter block (140) comprises a plurality of first-phase data shifters (148, 148’, 148”) and a plurality of second-phase data shifters (150, 150’, 150”), wherein a multiplexer (152, 152’) is arranged between a first-phase data shifter (148’, 148”) of the plurality of first-phase data shifters and a previous first-phase data shifter (148, 148’) of the plurality of first-phase data shifters, wherein a multiplexer (154, 154’) is arranged between a second-phase data shifter (150’, 150”) of the plurality of second-phase data shifters and a previous second-phase data shifter (150, 150’) of the plurality of second-phase data shifters except before a first first-phase data shifter (148) of the plurality of first-phase data shifters and a first second-phase data shifter (150) of the plurality of second-phase data shifters, and wherein the multiplexer (152, 152’, 154, 154’) is configured to output signals to only one of a first-phase data shifter (148’, 148”) of the plurality of first-phase data shifters and a second-phase data shifter (150’, 150”) of the plurality of second-phase data shifters.

13. A signal processing arrangement (100) according claim 12, wherein a multiplexer (152, 152’) is arranged between a first input (142) of the two inputs (142, 144) of the harmonic filter block (140) and each of the first-phase data shifters (148’, 148”), and a multiplexer (154, 154’) is arranged between a second input (144) of the two inputs (142, 144) of the harmonic filter block (140) and each of the second-phase data shifters (150’, 150”) except before the first first-phase data shifter (148) and the first second-phase data shifter (150).

14. A signal processing arrangement (100) according claim 12 or 13, wherein each first- phase data shifter (148, 148’, 148”) of the first harmonic filter (1 14) is configured to output a digital signal of the first group of digital signals (IQPDAI , IQPDA2, . . . , IQPDA_H), and each second-phase data shifter (150, 150’, 150”) of the first harmonic filter (1 14) is configured to output a digital signal of the second group of digital signals (IQPDBI , IQPDB2. . . IQPDB_H), and wherein each first-phase data shifter (148, 148’, 148”) of the second harmonic filter (1 16) is configured to output a digital signal of the third group of digital signals (IQNDAI , IQNDA2, . . . , IQNDA_H), and each second-phase data shifter (150, 150’, 150”) of the second harmonic filter (1 16) is configured to output a digital signal of the fourth group of digital signals (IQNDBI , IQNDB2, , IQNDBn).

15. A transmitter (200) comprising a signal processing arrangement (100) according to any of the preceding claims.

16. A method (300) for a signal processing arrangement (100), the method (300) comprising:

receiving (302) a modulated in-phase signal (I_M) and demodulating (304) the modulated in-phase signal (I_M);

receiving (306) a modulated quadrature signal (Q_M) and demodulating (308) the modulated quadrature signal (Q_M) ;

up-converting and mixing (310) the demodulated in-phase signal (I_DM) and the demodulated quadrature signal (Q_DM) and outputting a first up-converted and mixed positive phase signal (IQ_PA) and a second up-converted and mixed positive phase signal (IQ_PB); up-converting and mixing (312) the demodulated in-phase signal (I_DM) and the demodulated quadrature signal (Q_DM) and outputting a first up-converted and mixed negative phase signal (IQ_NA) and a second up-converted and mixed negative phase signal (IQNB);

performing (314) a part of a digital filtering of the first up-converted and mixed signal positive phase (IQ_PA) and the second up-converted and mixed positive phase signal (IQ_PB) and outputting a first group of digital signals (IQPDAI , IQPDA2, ..., IQPDA_H) and a second group of digital signals (IQPDBI , IQPDB2, ... , IQPDB_H); and performing (316) a part of a digital filtering of the first up-converted and mixed negative phase signal (IQ_NA) and the second up-converted and mixed negative phase signal (IQ_NB) and outputting a third group of digital signals (IQNDAI , IQNDA2, ..., IQNDA_H) and a fourth group of digital signals (IQNDBI , IQNDB2, ... , IONOB_P).