WO2019228271A1 - Pixel circuit and driving method therefor, and display device - Google Patents

Pixel circuit and driving method therefor, and display device Download PDF

Info

Publication number
WO2019228271A1
WO2019228271A1 PCT/CN2019/088364 CN2019088364W WO2019228271A1 WO 2019228271 A1 WO2019228271 A1 WO 2019228271A1 CN 2019088364 W CN2019088364 W CN 2019088364W WO 2019228271 A1 WO2019228271 A1 WO 2019228271A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
coupled
transistor
circuit
terminal
Prior art date
Application number
PCT/CN2019/088364
Other languages
French (fr)
Chinese (zh)
Inventor
李俊杰
李园园
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2019228271A1 publication Critical patent/WO2019228271A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Definitions

  • the present disclosure relates to the field of display technology, and more particularly, to a pixel circuit, a driving method thereof, and a display device.
  • AMOLED active matrix organic light emitting diode panel
  • LCD liquid crystal display
  • TFTs thin film transistors
  • the present disclosure provides a pixel circuit including a reset sub-circuit coupled to a first node and a second node for resetting the first node and the second node; A light-emitting sub-circuit, coupled to the fourth node; a driving sub-circuit, coupled to the first node, the third node, and the fourth node, and including a driving transistor for supplying a driving current to the light-emitting sub-circuit A storage sub-circuit, coupled to the first node and the second node, for storing voltage information related to a power supply voltage and a threshold voltage of the driving transistor; a data input sub-circuit, coupled to the first node A three node for supplying the driving transistor with a data voltage on pixel display; and a control sub-circuit coupled to the second node and the third node for controlling the storage sub-circuit and the driving A connection of a sub-circuit, wherein when the driving sub-circuit drives the light-emitting sub-circuit to emit light
  • the reset sub-circuit includes a first transistor and a second transistor; a first terminal of the first transistor is coupled to a first power source for providing the power voltage, and the first The second terminal of the transistor is coupled to the first node, and the control terminal of the first transistor is coupled to the first signal terminal; and the first terminal of the second transistor is coupled to the initial voltage signal terminal, so A second terminal of the second transistor is coupled to the second node, and a control terminal of the second transistor is coupled to a second signal terminal.
  • the storage sub-circuit includes a first capacitor coupled between the first node and the second node.
  • the data input sub-circuit includes a third transistor, a first terminal of the third transistor is coupled to a data voltage signal terminal, and a second terminal of the third transistor is coupled to the data transistor.
  • the third node, the control terminal of the third transistor is coupled to the second signal terminal.
  • the control sub-circuit includes a fourth transistor, a first terminal of the fourth transistor is coupled to the second node, and a second terminal of the fourth transistor is coupled to the second node.
  • the third node, the control terminal of the fourth transistor is coupled to the third signal terminal.
  • a first terminal of the driving transistor is coupled to the first node
  • a second terminal of the driving transistor is coupled to the fourth node
  • a control terminal of the driving transistor is coupled Connected to the third node.
  • the light-emitting sub-circuit includes a diode, a first terminal of the diode is coupled to the fourth node, and a second terminal of the diode is coupled to a second power source.
  • the reset sub-circuit is further coupled to the fourth node.
  • the reset sub-circuit includes a sixth transistor, a first terminal of the sixth transistor is coupled to an initial voltage signal terminal, and a second terminal of the sixth transistor is coupled to the first transistor. Four nodes, the control terminal of the sixth transistor is coupled to the second signal terminal.
  • the present disclosure also provides a driving method of a pixel circuit
  • the pixel circuit includes: a reset sub-circuit coupled to a first node and a second node; a storage sub-circuit coupled to the first node And the second node; a data input sub-circuit coupled to the third node; a control sub-circuit coupled to the second node and the third node; a driving sub-circuit coupled to the first node The third node and the fourth node, and including a driving transistor; and a light-emitting sub-circuit coupled to the fourth node;
  • the driving method includes: in a reset period of a cycle time for displaying a frame of image Using the reset sub-circuit to reset the first node and the second node, and using the data input sub-circuit to provide the driving transistor with a data voltage on pixel display; at the cycle time, In the compensation period after the reset period, the data input sub-circuit is used to provide the driving transistor with a data voltage related to pixel display,
  • Storing voltage information related to a power supply voltage and a threshold voltage of the driving transistor and in a light emitting period after the compensation period of the cycle time, using the control subcircuit to store the storage subcircuit and the
  • the driving sub-circuit is electrically connected and transmits the voltage information stored in the storage sub-circuit to the third node, and the driving sub-circuit is used to provide a driving current to the light-emitting sub-circuit, the driving current and the power supply
  • the voltage is independent of the threshold voltage.
  • the reset sub-circuit is further coupled to the fourth node.
  • the driving method further comprises: using the reset sub-circuit to reset the fourth node during the reset period.
  • the reset sub-circuit includes: a first transistor and a second transistor; a first terminal of the first transistor is coupled to a first power source, and a second terminal of the first transistor is coupled To the first node, a control terminal of the first transistor is coupled to a first signal terminal; and a first terminal of the second transistor is coupled to an initial voltage signal terminal and a second terminal of the second transistor Coupled to the second node, and a control terminal of the second transistor is coupled to a second signal terminal.
  • the storage sub-circuit includes: a first capacitor coupled between the first node and the second node.
  • the data input sub-circuit includes a third transistor, a first terminal of the third transistor is coupled to a data voltage signal terminal, and a second terminal of the third transistor is coupled to the The third node, the control terminal of the third transistor is coupled to the second signal terminal.
  • the control sub-circuit includes a fourth transistor, a first terminal of the fourth transistor is coupled to the second node, and a second terminal of the fourth transistor is coupled to the second node.
  • the third node, the control terminal of the fourth transistor is coupled to the third signal terminal.
  • a first terminal of the driving transistor is coupled to the first node
  • a second terminal of the driving transistor is coupled to the fourth node
  • a control terminal of the driving transistor is coupled Connected to the third node.
  • the light-emitting sub-circuit includes a diode, a first terminal of the diode is coupled to the fourth node, and a second terminal of the diode is coupled to a second power source.
  • the reset sub-circuit includes a sixth transistor, a first terminal of the sixth transistor is coupled to an initial voltage signal terminal, and a second terminal of the sixth transistor is coupled to the first transistor.
  • the fourth node, the control terminal of the sixth transistor is coupled to the second signal terminal.
  • the present disclosure also provides a display device including the pixel circuit described herein.
  • FIG. 1 is a schematic structural diagram illustrating a pixel circuit according to some embodiments of the present disclosure
  • FIG. 2 is a schematic structural diagram illustrating a pixel circuit according to some embodiments of the present disclosure
  • FIG. 3 is a signal timing diagram illustrating a pixel circuit according to some embodiments of the present disclosure.
  • FIG. 4 is a flowchart illustrating a driving method of a pixel circuit according to some embodiments of the present disclosure.
  • FIG. 1 is a schematic structural diagram illustrating a pixel circuit according to some embodiments of the present disclosure.
  • the pixel circuit includes a reset sub-circuit 101, a storage sub-circuit 102, a data input sub-circuit 103, a control sub-circuit 104, a driving sub-circuit 105, and a light-emitting sub-circuit 106.
  • the reset sub-circuit 101 and the storage sub-circuit 102 are respectively coupled to the first node N1 and the second node N2, the data input sub-circuit 103 is coupled to the third node N3, and the control sub-circuit 104 is coupled to the second node N2 and third The node N3, the driving sub-circuit 105 is coupled to the first node N1, the third node N3, and the fourth node N4, and the light-emitting sub-circuit 106 is coupled to the fourth node N4.
  • the reset sub-circuit 101 is configured to reset the first node N1 and the second node N2 during a reset period of a cycle time for displaying a frame of image to charge the storage sub-circuit 102.
  • the storage sub-circuit 102 stores voltage information related to the power supply voltage of the first power source ELVDD and the threshold voltage of the driving transistor of the driving sub-circuit 105 in a compensation period after the reset period for displaying a frame time of a frame, and Discharging during this compensation period causes the voltage at the first node N1 to be used as a compensation voltage.
  • the data input sub-circuit 103 is used to input a data voltage regarding pixel display to the third node N3 during the reset period and the compensation period, thereby supplying the data voltage to the driving transistor.
  • the control sub-circuit 104 controls the storage sub-circuit 102 and the driving sub-circuit 105 during the light-emitting period after the compensation period for displaying the cycle time of one frame of image, to turn on the driving sub-circuit 105 through the storage sub-circuit 102 during the light-emitting period.
  • the driving sub-circuit 105 is configured to provide a driving current to the light-emitting sub-circuit 106 during the light-emitting period to drive the light-emitting sub-circuit 106 to emit light.
  • the reset sub-circuit 101 is coupled to the first node N1 and the second node N2, and the storage sub-circuit 102 is coupled to the first node N1 and the second node N2. Therefore, the reset sub-circuit 101 and the storage sub-circuit 102 ⁇ 102 coupling.
  • the data input sub-circuit 103 is coupled to the third node N3
  • the control sub-circuit 104 is coupled to the second node N2 and the third node N3
  • the driving sub-circuit 105 is coupled to the first node N1, the third node N3, and the third node N3.
  • the four-node N4 and the light-emitting sub-circuit 106 are coupled to the fourth node N4.
  • the driving sub-circuit 105 is coupled to the reset sub-circuit 101, the storage sub-circuit 102, the data input sub-circuit 103, the control sub-circuit 104 and the light-emitting sub-circuit 106, respectively.
  • the control sub-circuit 104 is coupled to the data input sub-circuit 103, the storage sub-circuit 102 and the reset sub-circuit 101, respectively.
  • the reset sub-circuit is used to reset the first node and the second node during the reset period to charge the storage sub-circuit; the storage sub-circuit is discharged during the compensation period so that the voltage at the first node is used as the compensation voltage ;
  • the data input sub-circuit is used to input the data voltage to the third node during the reset period and the compensation period;
  • the control sub-circuit is used to couple the storage sub-circuit and the driving sub-circuit during the light-emitting period to enable the driving using the storage sub-circuit during the light-emitting period Sub-circuit; the driving sub-circuit is used to drive the light-emitting sub-circuit to emit light during the light-emitting period.
  • FIG. 2 is a structural diagram illustrating a pixel circuit according to some embodiments of the present disclosure.
  • the pixel circuit includes a reset sub-circuit 101, a storage sub-circuit 102, a data input sub-circuit 103, a control sub-circuit 104, a driving sub-circuit 105, and a light-emitting sub-circuit 106.
  • the reset sub-circuit 101 is coupled to the first node N1 and the second node N2, the storage sub-circuit 102 is coupled to the first node N1 and the second node N2, and the data input sub-circuit 103 is coupled to the third node N3 to control the sub-circuit 104 is coupled to the second node N2 and the third node N3, the driving sub-circuit 105 is coupled to the first node N1, the third node N3, and the fourth node N4, and the light-emitting sub-circuit 106 is coupled to the fourth node N4.
  • the reset sub-circuit 101 is configured to reset the first node N1 and the second node N2 during a reset period to charge the storage sub-circuit 102.
  • the storage sub-circuit 102 is discharged during the compensation period so that the voltage at the first node is used as the compensation voltage.
  • the data input sub-circuit 103 is configured to input a data voltage to the third node N3 during the reset period and the compensation period.
  • the control sub-circuit 104 is used for coupling the storage sub-circuit 102 and the driving sub-circuit 105 during the light-emitting period, so as to turn on the driving sub-circuit 105 using the storage sub-circuit during the light-emitting period.
  • the driving sub-circuit 105 is configured to drive the light-emitting sub-circuit 106 to emit light during a light-emitting period.
  • the reset sub-circuit 101 includes a first transistor T1 and a second transistor T2; a first terminal of the first transistor T1 is coupled to the first power source ELVDD, and a second terminal of the first transistor T1 is coupled to the first Node N1, the control terminal of the first transistor T1 is coupled to the first signal terminal S1; the first terminal of the second transistor T2 is coupled to the initial voltage signal terminal int, and the second terminal of the second transistor T2 is coupled to the second node N2, the control terminal of the second transistor T2 is coupled to the second signal terminal S2.
  • the storage sub-circuit 102 includes a capacitor C, a first terminal of the capacitor C is coupled to the first node N1, so that the first terminal of the capacitor C is coupled to the second terminal of the first transistor T1, and the capacitor C The second terminal is coupled to the second node N2, so that the second terminal of the capacitor C is coupled to the second terminal of the second transistor T2.
  • the data input sub-circuit 103 includes a third transistor T3, a first terminal of the third transistor T3 is coupled to the data voltage signal terminal Data, and a second terminal of the third transistor T3 is coupled to the third node N3.
  • the control terminal of the third transistor T3 is coupled to the second signal terminal S2.
  • the control sub-circuit 104 includes a fourth transistor T4, and a first terminal of the fourth transistor T4 is coupled to the second node N2, so that the first terminal of the fourth transistor T4 and the second terminal of the capacitor C and The second terminal of the second transistor T2 is coupled, and the second terminal of the fourth transistor T4 is coupled to the third node N3, so that the second terminal of the fourth transistor T4 is coupled to the second terminal of the third transistor T3.
  • the control terminal of the four transistor T4 is coupled to the third signal terminal S3.
  • the driving sub-circuit 105 includes a fifth transistor T5, and the first terminal of the fifth transistor T5 is coupled to the first node N1, so that the first terminal of the fifth transistor T5 and the first terminal of the capacitor C and The first terminal of the first transistor T1 is coupled, the second terminal of the fifth transistor T5 is coupled to the fourth node N4, and the control terminal of the fifth transistor T5 is coupled to the third node N3, so that the fifth transistor T5 The control terminal is coupled to the second terminal of the third transistor T3 and the second terminal of the fourth transistor T4.
  • the light-emitting sub-circuit 106 includes a diode D, a first terminal of the diode D is coupled to the fourth node N4, so that the first terminal of the diode D is coupled to the second terminal of the fifth transistor T5, and the diode D The second terminal is coupled to the second power source ELVSS.
  • the reset sub-circuit 101 is further coupled to the fourth node N4, and the reset sub-circuit 101 is further configured to reset the fourth node N4 during a reset period.
  • the reset sub-circuit 101 further includes a sixth transistor T6, a first terminal of the sixth transistor T6 is coupled to the initial voltage signal terminal int, and a second terminal of the sixth transistor T6 is coupled to the fourth node N4, so that the first The second terminal of the six transistor T6 is coupled to the first terminal of the diode D and the second terminal of the fifth transistor T5, and the control terminal of the sixth transistor T6 is coupled to the second signal terminal S2.
  • the diode D is an OLED.
  • the pixel circuit described herein is applied to an Active-Matrix Organic Light Emitting Diode (AMOLED).
  • AMOLED Active-Matrix Organic Light Emitting Diode
  • the first transistor T1 to the sixth transistor T6 are all thin film transistors (Thin Film Transistor, TFT for short).
  • FIG. 3 is a signal timing diagram illustrating a pixel circuit according to some embodiments of the present disclosure. The working principle of the pixel circuit according to some embodiments of the present disclosure is described in detail below with reference to FIGS. 2 and 3.
  • the first transistor T1 is turned on under the control of the voltage signal output from the first signal terminal S1, and the second transistor T2 is controlled by the voltage signal output from the second signal terminal S2
  • the bottom is turned on, wherein the voltage signal output from the first signal terminal S1 is a low level, and the voltage signal output from the second signal terminal S2 is a low level.
  • the first power source voltage ELVDD V output from the input power source ELVDD via the first node N1 of the first transistor T1 is turned on, the initial voltage signal output terminal of the initial voltage V int int via the second transistor T2 is turned on input node N2.
  • the sixth transistor T6 is turned on under the control of the voltage signal output from the second signal terminal S2, and the initial voltage V int output from the initial voltage signal terminal int is input to the fourth node through the turned-on sixth transistor T6. N4.
  • the first terminal of the diode D is an anode, and the second terminal of the diode D is a cathode.
  • the third transistor T3 is turned on under the control of the voltage signal output from the second signal terminal S2, and the fourth transistor T4 is turned off under the control of the voltage signal output from the third signal terminal S3.
  • the voltage signal output from the signal terminal S3 is high.
  • the first transistor T1 is turned off under the control of the voltage signal output from the first signal terminal S1
  • the second transistor T2 is turned on under the control of the voltage signal output from the second signal terminal S2
  • the third transistor T3 is turned on
  • the two signal terminals S2 are turned on under the control of a voltage signal.
  • the voltage signal output from the first signal terminal S1 is high level
  • the voltage signal output from the second signal terminal S2 is low level.
  • the first power source ELVDD cannot continuously input the power voltage V ELVDD to the first node N1, and therefore, the first terminal of the capacitor C will be discharged.
  • the gate-source voltage V gs of the fifth transistor T5 is equal to its threshold voltage V th . T5 is turned off, and the first terminal of capacitor C stops discharging.
  • V data -V th is the compensation voltage
  • the voltage of the first terminal of the capacitor C is equal to the voltage V N1 of the first node N1 .
  • the second transistor T2, the third transistor T3, and the sixth transistor T6 are turned off under the control of the voltage signal output from the second signal terminal S2, and the control of the voltage signal output from the first transistor T1 at the first signal terminal S1 is controlled.
  • the fourth transistor T4 is turned on under the control of the voltage signal output from the third signal terminal S3.
  • the voltage signals output from the first signal terminal S1 and the third signal terminal S3 are both low, and the second signal The voltage signal output from the terminal S2 is high.
  • the voltage of the second terminal of the capacitor C is coupled as V int + V ELVDD- (V data -V th ) due to the bootstrap effect of the capacitor C (ie, the instantaneous voltage difference holding function), where the capacitor C
  • the second terminal of the capacitor C is coupled to the control terminal of the fifth transistor T5
  • W and L are the width and length of the conductive channel of the fifth transistor M5
  • Cox is the capacitance of the gate oxide layer per unit area
  • u is the carrier mobility of the fifth transistor M5.
  • the pixel circuit described in this article uses six thin film transistors, namely the first transistor T1 to the sixth transistor T6, to achieve pixel compensation, thereby reducing the difficulty of wiring and increasing the wiring for high PPI (pixel density) pixels. space.
  • the reset sub-circuit is used to reset the first node and the second node during the reset period to charge the storage sub-circuit; the storage sub-circuit is discharged during the compensation period to make the first The voltage of the node becomes the compensation voltage; the data input sub-circuit writes the data voltage to the third node during the reset period and the compensation period; the control sub-circuit couples the storage sub-circuit and the driving sub-circuit during the light-emitting period so that the storage sub-circuit The driving sub-circuit is turned on during the light-emitting period; the driving sub-circuit drives the light-emitting sub-circuit to emit light during the light-emitting period.
  • the pixel circuit described herein implements pixel compensation by using 6 thin film transistors, thereby reducing wiring difficulties and increasing wiring space for high PPI pixels.
  • FIG. 4 is a flowchart illustrating a driving method of a pixel circuit according to some embodiments of the present disclosure.
  • the pixel circuit includes a reset sub-circuit, a storage sub-circuit, a data input sub-circuit, a control sub-circuit, a driving sub-circuit, and a light-emitting sub-circuit.
  • the reset subcircuit is coupled to the first node and the second node
  • the storage subcircuit is coupled to the first node and the second node
  • the data input subcircuit is coupled to the third node
  • the control subcircuit is coupled to the second node.
  • the driving sub-circuit is coupled to the first node, the third node, and the fourth node
  • the light-emitting sub-circuit is coupled to the fourth node.
  • a driving method of a pixel circuit includes:
  • step 301 during the reset period, the first node and the second node are reset using a reset sub-circuit to charge the storage sub-circuit, and the data input sub-circuit is used to provide the driving transistor with a data voltage on the pixel display.
  • a data input sub-circuit is used to provide the driving transistor with a data voltage regarding the pixel display
  • a storage sub-circuit is used to store voltage information related to the power supply voltage and the threshold voltage of the driving transistor.
  • step 303 in the light-emitting period, the control sub-circuit is used to electrically connect the storage sub-circuit and the driving sub-circuit and transfer the voltage information stored in the storage sub-circuit to the third node, so as to turn on the driver through the storage sub-circuit during the light-emitting period
  • the driving sub-circuit is used to provide a driving current to the light-emitting sub-circuit to drive the light-emitting sub-circuit to emit light, the driving current is independent of the power supply voltage and the threshold voltage of the driving transistor.
  • the pixel circuit includes the pixel circuit described herein, and a detailed description of the pixel circuit will not be repeated here.
  • the first node and the second node are reset using a reset subcircuit to charge the storage subcircuit, and the data input subcircuit is used to The data voltage is input to the third node; during the compensation period, the data input sub-circuit is used to continue to input the data voltage to the third node, and the storage sub-circuit is discharged so that the voltage of the first node becomes the compensation voltage; during the light-emitting period, the control sub-circuit
  • the storage sub-circuit and the driving sub-circuit are coupled so that the storage sub-circuit turns on the driving sub-circuit, and the driving sub-circuit is used to drive the light-emitting sub-circuit to emit light.
  • Embodiment 4 of the present disclosure provides a display device.
  • the display device includes a pixel sub-circuit provided in the above-mentioned Embodiment 2.
  • a pixel sub-circuit provided in the above-mentioned Embodiment 2.
  • the pixel sub-circuit refer to the above-mentioned Embodiment 2, which is not described herein again.
  • the reset sub-circuit is used to reset the first node and the second node during the reset period to charge the storage sub-circuit; the storage sub-circuit is used to discharge during the compensation period, So that the voltage of the first node becomes the compensation voltage; the data input sub-circuit is used to input the data voltage to the third node during the reset period and the compensation period, so that the driving sub-circuit is turned off during the reset period and the compensation period; the control sub-circuit is used for The storage sub-circuit is controlled to be coupled to the driving sub-circuit during the light-emitting period, so that the storage sub-circuit controls the driving sub-circuit to be turned on; the driving sub-circuit is used to drive the light-emitting sub-circuit to emit light during the light-emitting period. As a result, pixel compensation is achieved and the display effect is improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

The present disclosure provides a pixel circuit, a driving method therefor, and a display device. Said pixel circuit comprises: a reset subcircuit coupled to a first node and a second node and used for resetting the first node and the second node; a light-emitting subcircuit coupled to a fourth node; a driving subcircuit coupled to the first node, a third node, and the fourth node, comprising a driving transistor, and used for providing a driving current to the light-emitting subcircuit; a memory subcircuit coupled to the first node and the second node and used for storing voltage information related to a power supply voltage and a threshold voltage of the driving transistor; a data input subcircuit coupled to the third node and used for providing a data voltage related to pixel display to the driving transistor; and a control subcircuit coupled to the second node and the third node and used for controlling a connection between the memory subcircuit and the driving subcircuit.

Description

像素电路及其驱动方法、显示装置Pixel circuit, driving method thereof, and display device 技术领域Technical field
本公开涉及显示技术领域，更具体地，涉及像素电路及其驱动方法、显示装置。The present disclosure relates to the field of display technology, and more particularly, to a pixel circuit, a driving method thereof, and a display device.
背景技术Background technique
目前，柔性显示装置的市场需求越来越大，AMOLED(有源矩阵有机发光二极体面板)显示技术正在逐步取代传统的LCD显示技术。为了追求更好的显示画面质量，通常要求显示器件具有更高的像素密度(PPI)和像素补偿效果，以提高显示效果。At present, the market demand for flexible display devices is increasing, and AMOLED (active matrix organic light emitting diode panel) display technology is gradually replacing traditional LCD display technology. In order to pursue better display picture quality, display devices are generally required to have higher pixel density (PPI) and pixel compensation effects to improve display effects.
但现有的像素电路，采用的薄膜晶体管(TFT)数量较多，使得布线难度增加，不利于增大显示器件的像素密度，影响了显示器件的显示效果。However, the existing pixel circuits use a large number of thin film transistors (TFTs), which makes wiring difficult, which is not conducive to increasing the pixel density of the display device, which affects the display effect of the display device.
发明内容Summary of the Invention
一方面，本公开提供了一种像素电路，所述像素电路包括：复位子电路，耦接至第一节点和第二节点，用于对所述第一节点和所述第二节点进行复位；发光子电路，耦接至第四节点；驱动子电路，耦接至所述第一节点、第三节点和所述第四节点，并且包括驱动晶体管，用于向所述发光子电路提供驱动电流；存储子电路，耦接至所述第一节点和所述第二节点，用于存储与电源电压和所述驱动晶体管的阈值电压有关的电压信息；数据输入子电路，耦接至所述第三节点，用于向所述驱动晶体管提供关于像素显示的数据电压；和控制子电路，耦接至所述第二节点和所述第三节点，用于控制所述存储子电路与所述驱动子电路的连接，其中，在所述驱动子电路驱动所述发光子电路发光时，所述控制子电路将所述存储子电路所存储的电压信息传递至所述第三节点，以使得所述驱动电流与所述电源电压和所述阈值电压无关。In one aspect, the present disclosure provides a pixel circuit including a reset sub-circuit coupled to a first node and a second node for resetting the first node and the second node; A light-emitting sub-circuit, coupled to the fourth node; a driving sub-circuit, coupled to the first node, the third node, and the fourth node, and including a driving transistor for supplying a driving current to the light-emitting sub-circuit A storage sub-circuit, coupled to the first node and the second node, for storing voltage information related to a power supply voltage and a threshold voltage of the driving transistor; a data input sub-circuit, coupled to the first node A three node for supplying the driving transistor with a data voltage on pixel display; and a control sub-circuit coupled to the second node and the third node for controlling the storage sub-circuit and the driving A connection of a sub-circuit, wherein when the driving sub-circuit drives the light-emitting sub-circuit to emit light, the control sub-circuit transmits the voltage information stored by the storage sub-circuit to the third node So that the drive current independent of the supply voltage and the threshold voltage.
根据本公开的一个实施例，所述复位子电路包括第一晶体管和第二晶体管；所述第一晶体管的第一端子耦接至用于提供所述电源电压的第一电源，所述第一晶体管的第二端子耦接至所述第一节点，所述第一晶体管的控制端子耦接至第一信号端；并且，所述第二晶体管的第一端子耦接至初始电压信号端，所述第二晶体管的第二端子耦接至所述第二节点，所述第二晶体管的控制端子耦接至第二信号端。According to an embodiment of the present disclosure, the reset sub-circuit includes a first transistor and a second transistor; a first terminal of the first transistor is coupled to a first power source for providing the power voltage, and the first The second terminal of the transistor is coupled to the first node, and the control terminal of the first transistor is coupled to the first signal terminal; and the first terminal of the second transistor is coupled to the initial voltage signal terminal, so A second terminal of the second transistor is coupled to the second node, and a control terminal of the second transistor is coupled to a second signal terminal.
根据本公开的一个实施例，所述存储子电路包括第一电容器，耦接在所述第一节点和所述第二节点之间。According to an embodiment of the present disclosure, the storage sub-circuit includes a first capacitor coupled between the first node and the second node.
根据本公开的一个实施例，所述数据输入子电路包括第三晶体管，所述第三晶体管的第一端子耦接至数据电压信号端，所述第三晶体管的第二端子耦接至所述第三节点，所述第三晶体管的控制端子耦接至第二信号端。According to an embodiment of the present disclosure, the data input sub-circuit includes a third transistor, a first terminal of the third transistor is coupled to a data voltage signal terminal, and a second terminal of the third transistor is coupled to the data transistor. The third node, the control terminal of the third transistor is coupled to the second signal terminal.
根据本公开的一个实施例，所述控制子电路包括第四晶体管，所述第四晶体管的第一端子耦接至所述第二节点，所述第四晶体管的第二端子耦接至所述第三节点，所述第四晶体管的控制端子耦接至第三信号端。According to an embodiment of the present disclosure, the control sub-circuit includes a fourth transistor, a first terminal of the fourth transistor is coupled to the second node, and a second terminal of the fourth transistor is coupled to the second node. The third node, the control terminal of the fourth transistor is coupled to the third signal terminal.
根据本公开的一个实施例，所述驱动晶体管的第一端子耦接至所述第一节点，所述驱动晶体管的第二端子耦接至所述第四节点，所述驱动晶体管的控制端子耦接至所述第三节点。According to an embodiment of the present disclosure, a first terminal of the driving transistor is coupled to the first node, a second terminal of the driving transistor is coupled to the fourth node, and a control terminal of the driving transistor is coupled Connected to the third node.
根据本公开的一个实施例，所述发光子电路包括二极管，所述二极管的第一端子耦接至所述第四节点，所述二极管的第二端子耦接至第二电源。According to an embodiment of the present disclosure, the light-emitting sub-circuit includes a diode, a first terminal of the diode is coupled to the fourth node, and a second terminal of the diode is coupled to a second power source.
根据本公开的一个实施例，所述复位子电路还耦接至所述第四节点。According to an embodiment of the present disclosure, the reset sub-circuit is further coupled to the fourth node.
根据本公开的一个实施例，所述复位子电路包括第六晶体管，所述第六晶体管的第一端子耦接至初始电压信号端，所述第六晶体管的第二端子耦接至所述第四节点，所述第六晶体管的控制端子耦接至第二信号端。According to an embodiment of the present disclosure, the reset sub-circuit includes a sixth transistor, a first terminal of the sixth transistor is coupled to an initial voltage signal terminal, and a second terminal of the sixth transistor is coupled to the first transistor. Four nodes, the control terminal of the sixth transistor is coupled to the second signal terminal.
另一方面，本公开还提供了一种像素电路的驱动方法，所述像素电路包括：复位子电路，耦接至第一节点和第二节点；存储子电路，耦接至所述第一节点和所述第二节点；数据输入子电路，耦接至第三节点；控制子电路，耦接至所述第二节点和所述第三节点；驱动子电路，耦接至所述第一节点、所述第三节点和第四节点，并且包括驱动晶体管；和发光子电 路，耦接至所述第四节点；所述驱动方法包括：在用于显示一帧图像的周期时间的复位时段中，使用所述复位子电路对所述第一节点和所述第二节点进行复位，并且并且使用所述数据输入子电路向所述驱动晶体管提供关于像素显示的数据电压；在所述周期时间的在所述复位时段之后的补偿时段中，使用所述数据输入子电路向所述驱动晶体管提供关于像素显示的数据电压，并且使所述存储子电路来存储与电源电压和所述驱动晶体管的阈值电压有关的电压信息；和在所述周期时间的在所述补偿时段之后的发光时段中，使用所述控制子电路将所述存储子电路和所述驱动子电路电连接并将所述存储子电路所存储的电压信息传递至所述第三节点，并且使用所述驱动子电路向所述发光子电路提供驱动电流，所述驱动电流与所述电源电压和所述阈值电压无关。In another aspect, the present disclosure also provides a driving method of a pixel circuit, the pixel circuit includes: a reset sub-circuit coupled to a first node and a second node; a storage sub-circuit coupled to the first node And the second node; a data input sub-circuit coupled to the third node; a control sub-circuit coupled to the second node and the third node; a driving sub-circuit coupled to the first node The third node and the fourth node, and including a driving transistor; and a light-emitting sub-circuit coupled to the fourth node; the driving method includes: in a reset period of a cycle time for displaying a frame of image Using the reset sub-circuit to reset the first node and the second node, and using the data input sub-circuit to provide the driving transistor with a data voltage on pixel display; at the cycle time, In the compensation period after the reset period, the data input sub-circuit is used to provide the driving transistor with a data voltage related to pixel display, and the storage sub-circuit is stored. Storing voltage information related to a power supply voltage and a threshold voltage of the driving transistor; and in a light emitting period after the compensation period of the cycle time, using the control subcircuit to store the storage subcircuit and the The driving sub-circuit is electrically connected and transmits the voltage information stored in the storage sub-circuit to the third node, and the driving sub-circuit is used to provide a driving current to the light-emitting sub-circuit, the driving current and the power supply The voltage is independent of the threshold voltage.
根据本公开的一个实施例，所述复位子电路还耦接至所述第四节点。According to an embodiment of the present disclosure, the reset sub-circuit is further coupled to the fourth node.
根据本公开的一个实施例，所述驱动方法还包括：在所述复位时段中，使用所述复位子电路对所述第四节点进行复位。According to an embodiment of the present disclosure, the driving method further comprises: using the reset sub-circuit to reset the fourth node during the reset period.
根据本公开的一个实施例，所述复位子电路包括：第一晶体管和第二晶体管；所述第一晶体管的第一端子耦接至第一电源，所述第一晶体管的第二端子耦接至所述第一节点，所述第一晶体管的控制端子耦接至第一信号端；并且所述第二晶体管的第一端子耦接至初始电压信号端，所述第二晶体管的第二端子耦接至所述第二节点，所述第二晶体管的控制端子耦接至第二信号端。According to an embodiment of the present disclosure, the reset sub-circuit includes: a first transistor and a second transistor; a first terminal of the first transistor is coupled to a first power source, and a second terminal of the first transistor is coupled To the first node, a control terminal of the first transistor is coupled to a first signal terminal; and a first terminal of the second transistor is coupled to an initial voltage signal terminal and a second terminal of the second transistor Coupled to the second node, and a control terminal of the second transistor is coupled to a second signal terminal.
根据本公开的一个实施例，所述存储子电路包括：第一电容器，耦接在所述第一节点和所述第二节点之间。According to an embodiment of the present disclosure, the storage sub-circuit includes: a first capacitor coupled between the first node and the second node.
根据本公开的一个实施例，所述数据输入子电路包括：第三晶体管，所述第三晶体管的第一端子耦接至数据电压信号端，所述第三晶体管的第二端子耦接至所述第三节点，所述第三晶体管的控制端子耦接至第二信号端。According to an embodiment of the present disclosure, the data input sub-circuit includes a third transistor, a first terminal of the third transistor is coupled to a data voltage signal terminal, and a second terminal of the third transistor is coupled to the The third node, the control terminal of the third transistor is coupled to the second signal terminal.
根据本公开的一个实施例，所述控制子电路包括：第四晶体管，所述第四晶体管的第一端子耦接至所述第二节点，所述第四晶体管的第二端子耦接至所述第三节点，所述第四晶体管的控制端子耦接至第三信号端。According to an embodiment of the present disclosure, the control sub-circuit includes a fourth transistor, a first terminal of the fourth transistor is coupled to the second node, and a second terminal of the fourth transistor is coupled to the second node. The third node, the control terminal of the fourth transistor is coupled to the third signal terminal.
根据本公开的一个实施例，所述驱动晶体管的第一端子耦接至所述 第一节点，所述驱动晶体管的第二端子耦接至所述第四节点，所述驱动晶体管的控制端子耦接至所述第三节点。According to an embodiment of the present disclosure, a first terminal of the driving transistor is coupled to the first node, a second terminal of the driving transistor is coupled to the fourth node, and a control terminal of the driving transistor is coupled Connected to the third node.
根据本公开的一个实施例，所述发光子电路包括：二极管，所述二极管的第一端子耦接至所述第四节点，所述二极管的第二端子耦接至第二电源。According to an embodiment of the present disclosure, the light-emitting sub-circuit includes a diode, a first terminal of the diode is coupled to the fourth node, and a second terminal of the diode is coupled to a second power source.
根据本公开的一个实施例，所述复位子电路包括：第六晶体管，所述第六晶体管的第一端子耦接至初始电压信号端，所述第六晶体管的第二端子耦接至所述第四节点，所述第六晶体管的控制端子耦接至第二信号端。According to an embodiment of the present disclosure, the reset sub-circuit includes a sixth transistor, a first terminal of the sixth transistor is coupled to an initial voltage signal terminal, and a second terminal of the sixth transistor is coupled to the first transistor. The fourth node, the control terminal of the sixth transistor is coupled to the second signal terminal.
另一方面，本公开还提供了一种显示装置，所述显示装置包括本文所述的像素电路。In another aspect, the present disclosure also provides a display device including the pixel circuit described herein.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1是示出根据本公开的一些实施例的像素电路的结构示意图；FIG. 1 is a schematic structural diagram illustrating a pixel circuit according to some embodiments of the present disclosure;
图2是示出根据本公开的一些实施例的像素电路的结构示意图；FIG. 2 is a schematic structural diagram illustrating a pixel circuit according to some embodiments of the present disclosure;
图3是示出根据本公开的一些实施例的像素电路的信号时序图；以及FIG. 3 is a signal timing diagram illustrating a pixel circuit according to some embodiments of the present disclosure; and
图4是示出根据本公开的一些实施例的像素电路的驱动方法的流程图。FIG. 4 is a flowchart illustrating a driving method of a pixel circuit according to some embodiments of the present disclosure.
具体实施方式Detailed ways
现在将参照以下实施例更具体地描述本公开。应注意，本文仅出于说明和描述的目的呈现了一些实施例的以下描述。其并非旨在穷举或限于所公开的精确形式，并且为了避免冗余而省略相同部分。The present disclosure will now be described more specifically with reference to the following examples. It should be noted that the following description of some embodiments is presented herein for purposes of illustration and description only. It is not intended to be exhaustive or limited to the precise form disclosed, and the same portions are omitted to avoid redundancy.
图1是示出根据本公开的一些实施例的像素电路的结构示意图。参照图1，在一些实施例中，像素电路包括复位子电路101、存储子电路102、数据输入子电路103、控制子电路104、驱动子电路105和发光子电路106。复位子电路101和存储子电路102分别耦接至第一节点N1和第二节点N2，数据输入子电路103耦接至第三节点N3，控制子电路104耦接至第二节点N2和第三节点N3，驱动子电路105耦接至第一节点N1、第三节点N3和第四节点N4，发光子电路106耦接至第四节点N4。FIG. 1 is a schematic structural diagram illustrating a pixel circuit according to some embodiments of the present disclosure. Referring to FIG. 1, in some embodiments, the pixel circuit includes a reset sub-circuit 101, a storage sub-circuit 102, a data input sub-circuit 103, a control sub-circuit 104, a driving sub-circuit 105, and a light-emitting sub-circuit 106. The reset sub-circuit 101 and the storage sub-circuit 102 are respectively coupled to the first node N1 and the second node N2, the data input sub-circuit 103 is coupled to the third node N3, and the control sub-circuit 104 is coupled to the second node N2 and third The node N3, the driving sub-circuit 105 is coupled to the first node N1, the third node N3, and the fourth node N4, and the light-emitting sub-circuit 106 is coupled to the fourth node N4.
复位子电路101用于在用于显示一帧图像的周期时间的复位时段对第一节点N1和第二节点N2进行复位，以对存储子电路102进行充电。The reset sub-circuit 101 is configured to reset the first node N1 and the second node N2 during a reset period of a cycle time for displaying a frame of image to charge the storage sub-circuit 102.
存储子电路102在用于显示一帧图像的周期时间的在复位时段之后的补偿时段存储与第一电源ELVDD的电源电压和所述驱动子电路105的驱动晶体管的阈值电压有关的电压信息，并且在该补偿时段放电使得第一节点N1处电压用作补偿电压。The storage sub-circuit 102 stores voltage information related to the power supply voltage of the first power source ELVDD and the threshold voltage of the driving transistor of the driving sub-circuit 105 in a compensation period after the reset period for displaying a frame time of a frame, and Discharging during this compensation period causes the voltage at the first node N1 to be used as a compensation voltage.
数据输入子电路103用于在复位时段和补偿时段将关于像素显示的数据电压输入第三节点N3，从而将该数据电压提供给驱动晶体管。The data input sub-circuit 103 is used to input a data voltage regarding pixel display to the third node N3 during the reset period and the compensation period, thereby supplying the data voltage to the driving transistor.
控制子电路104在用于显示一帧图像的周期时间的在补偿时段之后的发光时段控制存储子电路102和驱动子电路105连接，以在该发光时段通过存储子电路102开启驱动子电路105。The control sub-circuit 104 controls the storage sub-circuit 102 and the driving sub-circuit 105 during the light-emitting period after the compensation period for displaying the cycle time of one frame of image, to turn on the driving sub-circuit 105 through the storage sub-circuit 102 during the light-emitting period.
驱动子电路105用于在发光时段向发光子电路106提供驱动电流以驱动该发光子电路106发光。The driving sub-circuit 105 is configured to provide a driving current to the light-emitting sub-circuit 106 during the light-emitting period to drive the light-emitting sub-circuit 106 to emit light.
如图1所示，复位子电路101耦接至第一节点N1和第二节点N2，存储子电路102耦接至第一节点N1和第二节点N2，因此，复位子电路101与存储子电路102耦接。此外，数据输入子电路103耦接至第三节点N3，控制子电路104耦接至第二节点N2和第三节点N3，驱动子电路105耦接至第一节点N1、第三节点N3和第四节点N4，发光子电路106耦接至第四节点N4，因此，驱动子电路105分别与复位子电路101、存储子电路102、数据输入子电路103、控制子电路104和发光子电路106耦接，并且控制子电路104分别与数据输入子电路103、存储子电路102和复位子电路101耦接。As shown in FIG. 1, the reset sub-circuit 101 is coupled to the first node N1 and the second node N2, and the storage sub-circuit 102 is coupled to the first node N1 and the second node N2. Therefore, the reset sub-circuit 101 and the storage sub-circuit 102 连接。 102 coupling. In addition, the data input sub-circuit 103 is coupled to the third node N3, the control sub-circuit 104 is coupled to the second node N2 and the third node N3, and the driving sub-circuit 105 is coupled to the first node N1, the third node N3, and the third node N3. The four-node N4 and the light-emitting sub-circuit 106 are coupled to the fourth node N4. Therefore, the driving sub-circuit 105 is coupled to the reset sub-circuit 101, the storage sub-circuit 102, the data input sub-circuit 103, the control sub-circuit 104 and the light-emitting sub-circuit 106, respectively. The control sub-circuit 104 is coupled to the data input sub-circuit 103, the storage sub-circuit 102 and the reset sub-circuit 101, respectively.
根据本公开，复位子电路用于在复位时段对第一节点和第二节点进行复位，以对存储子电路进行充电；存储子电路在补偿时段放电，以使第一节点处电压用作补偿电压；数据输入子电路用于在复位时段和补偿时段将数据电压输入第三节点；控制子电路用于在发光时段使存储子电路和驱动子电路耦接，以在发光时段使用存储子电路开启驱动子电路；驱动子电路用于在发光时段驱动发光子电路进行发光。从而实现了像素补偿，提高了显示效果。According to the present disclosure, the reset sub-circuit is used to reset the first node and the second node during the reset period to charge the storage sub-circuit; the storage sub-circuit is discharged during the compensation period so that the voltage at the first node is used as the compensation voltage ; The data input sub-circuit is used to input the data voltage to the third node during the reset period and the compensation period; the control sub-circuit is used to couple the storage sub-circuit and the driving sub-circuit during the light-emitting period to enable the driving using the storage sub-circuit during the light-emitting period Sub-circuit; the driving sub-circuit is used to drive the light-emitting sub-circuit to emit light during the light-emitting period. As a result, pixel compensation is achieved and the display effect is improved.
图2是示出根据本公开的一些实施例的像素电路的结构示意图。参 照图2，在一些实施例中，像素电路包括复位子电路101、存储子电路102、数据输入子电路103、控制子电路104、驱动子电路105和发光子电路106。复位子电路101耦接至第一节点N1和第二节点N2，存储子电路102耦接至第一节点N1和第二节点N2，数据输入子电路103耦接至第三节点N3，控制子电路104耦接至第二节点N2和第三节点N3，驱动子电路105耦接至第一节点N1、第三节点N3和第四节点N4，并且发光子电路106耦接至第四节点N4。FIG. 2 is a structural diagram illustrating a pixel circuit according to some embodiments of the present disclosure. Referring to FIG. 2, in some embodiments, the pixel circuit includes a reset sub-circuit 101, a storage sub-circuit 102, a data input sub-circuit 103, a control sub-circuit 104, a driving sub-circuit 105, and a light-emitting sub-circuit 106. The reset sub-circuit 101 is coupled to the first node N1 and the second node N2, the storage sub-circuit 102 is coupled to the first node N1 and the second node N2, and the data input sub-circuit 103 is coupled to the third node N3 to control the sub-circuit 104 is coupled to the second node N2 and the third node N3, the driving sub-circuit 105 is coupled to the first node N1, the third node N3, and the fourth node N4, and the light-emitting sub-circuit 106 is coupled to the fourth node N4.
复位子电路101用于在复位时段对第一节点N1和第二节点N2进行复位，以对存储子电路102进行充电。存储子电路102在补偿时段放电，以使第一节点处电压用作补偿电压。The reset sub-circuit 101 is configured to reset the first node N1 and the second node N2 during a reset period to charge the storage sub-circuit 102. The storage sub-circuit 102 is discharged during the compensation period so that the voltage at the first node is used as the compensation voltage.
数据输入子电路103用于在复位时段和补偿时段将数据电压输入第三节点N3。The data input sub-circuit 103 is configured to input a data voltage to the third node N3 during the reset period and the compensation period.
控制子电路104用于在发光时段使存储子电路102和驱动子电路105耦接，以在发光时段使用存储子电路开启驱动子电路105。The control sub-circuit 104 is used for coupling the storage sub-circuit 102 and the driving sub-circuit 105 during the light-emitting period, so as to turn on the driving sub-circuit 105 using the storage sub-circuit during the light-emitting period.
驱动子电路105用于在发光时段驱动发光子电路106进行发光。The driving sub-circuit 105 is configured to drive the light-emitting sub-circuit 106 to emit light during a light-emitting period.
本一些实施例中，复位子电路101包括第一晶体管T1和第二晶体管T2；第一晶体管T1的第一端子耦接至第一电源ELVDD，第一晶体管T1的第二端子耦接至第一节点N1，第一晶体管T1的控制端子耦接至第一信号端S1；第二晶体管T2的第一端子耦接至初始电压信号端int，第二晶体管T2的第二端子耦接至第二节点N2，第二晶体管T2的控制端子耦接至第二信号端S2。In some embodiments, the reset sub-circuit 101 includes a first transistor T1 and a second transistor T2; a first terminal of the first transistor T1 is coupled to the first power source ELVDD, and a second terminal of the first transistor T1 is coupled to the first Node N1, the control terminal of the first transistor T1 is coupled to the first signal terminal S1; the first terminal of the second transistor T2 is coupled to the initial voltage signal terminal int, and the second terminal of the second transistor T2 is coupled to the second node N2, the control terminal of the second transistor T2 is coupled to the second signal terminal S2.
本一些实施例中，存储子电路102包括电容器C，电容器C的第一端子耦接至第一节点N1，以使电容C的第一端子与第一晶体管T1的第二端子耦接，电容器C的第二端子耦接至第二节点N2，以使电容器C的第二端子与第二晶体管T2的第二端子耦接。In some embodiments, the storage sub-circuit 102 includes a capacitor C, a first terminal of the capacitor C is coupled to the first node N1, so that the first terminal of the capacitor C is coupled to the second terminal of the first transistor T1, and the capacitor C The second terminal is coupled to the second node N2, so that the second terminal of the capacitor C is coupled to the second terminal of the second transistor T2.
本一些实施例中，数据输入子电路103包括第三晶体管T3，第三晶体管T3的第一端子耦接至数据电压信号端Data，第三晶体管T3的第二端子耦接至第三节点N3，第三晶体管T3的控制端子耦接至第二信号端S2。In some embodiments, the data input sub-circuit 103 includes a third transistor T3, a first terminal of the third transistor T3 is coupled to the data voltage signal terminal Data, and a second terminal of the third transistor T3 is coupled to the third node N3. The control terminal of the third transistor T3 is coupled to the second signal terminal S2.
本一些实施例中，控制子电路104包括第四晶体管T4，第四晶体管T4的第一端子耦接至第二节点N2，以使第四晶体管T4的第一端子与电容 器C的第二端子和第二晶体管T2的第二端子耦接，第四晶体管T4的第二端子耦接至第三节点N3，以使第四晶体管T4的第二端子与第三晶体管T3的第二端子耦接，第四晶体管T4的控制端子耦接至第三信号端S3。In some embodiments, the control sub-circuit 104 includes a fourth transistor T4, and a first terminal of the fourth transistor T4 is coupled to the second node N2, so that the first terminal of the fourth transistor T4 and the second terminal of the capacitor C and The second terminal of the second transistor T2 is coupled, and the second terminal of the fourth transistor T4 is coupled to the third node N3, so that the second terminal of the fourth transistor T4 is coupled to the second terminal of the third transistor T3. The control terminal of the four transistor T4 is coupled to the third signal terminal S3.
本一些实施例中，驱动子电路105包括第五晶体管T5，第五晶体管T5的第一端子耦接至第一节点N1，以使第五晶体管T5的第一端子与电容器C的第一端子和第一晶体管T1的第一端子耦接，第五晶体管T5的第二端子与耦接至第四节点N4，第五晶体管T5的控制端子耦接至第三节点N3，以使第五晶体管T5的控制端子与第三晶体管T3的第二端子和第四晶体管T4的第二端子耦接。In some embodiments, the driving sub-circuit 105 includes a fifth transistor T5, and the first terminal of the fifth transistor T5 is coupled to the first node N1, so that the first terminal of the fifth transistor T5 and the first terminal of the capacitor C and The first terminal of the first transistor T1 is coupled, the second terminal of the fifth transistor T5 is coupled to the fourth node N4, and the control terminal of the fifth transistor T5 is coupled to the third node N3, so that the fifth transistor T5 The control terminal is coupled to the second terminal of the third transistor T3 and the second terminal of the fourth transistor T4.
本一些实施例中，发光子电路106包括二极管D，二极管D的第一端子耦接至第四节点N4，以使二极管D的第一端子与第五晶体管T5的第二端子耦接，二极管D的第二端子耦接至第二电源ELVSS。In some embodiments, the light-emitting sub-circuit 106 includes a diode D, a first terminal of the diode D is coupled to the fourth node N4, so that the first terminal of the diode D is coupled to the second terminal of the fifth transistor T5, and the diode D The second terminal is coupled to the second power source ELVSS.
本一些实施例中，复位子电路101还耦接至第四节点N4，复位子电路101还用于在复位时段对第四节点N4进行复位。具体地，复位子电路101还包括第六晶体管T6，第六晶体管T6的第一端子耦接至初始电压信号端int，第六晶体管T6的第二端子耦接至第四节点N4，以使第六晶体管T6的第二端子与二极管D的第一端子和第五晶体管T5的第二端子耦接，第六晶体管T6的控制端子耦接至第二信号端S2。In some embodiments, the reset sub-circuit 101 is further coupled to the fourth node N4, and the reset sub-circuit 101 is further configured to reset the fourth node N4 during a reset period. Specifically, the reset sub-circuit 101 further includes a sixth transistor T6, a first terminal of the sixth transistor T6 is coupled to the initial voltage signal terminal int, and a second terminal of the sixth transistor T6 is coupled to the fourth node N4, so that the first The second terminal of the six transistor T6 is coupled to the first terminal of the diode D and the second terminal of the fifth transistor T5, and the control terminal of the sixth transistor T6 is coupled to the second signal terminal S2.
本一些实施例中，二极管D为OLED。In some embodiments, the diode D is an OLED.
本一些实施例中，本文所述的像素电路应用于有源矩阵有机发光二极体面板(Active-matrix Organic Light Emitting Diode，简称：AMOLED)。In some embodiments, the pixel circuit described herein is applied to an Active-Matrix Organic Light Emitting Diode (AMOLED).
本一些实施例中，第一晶体管T1至第六晶体管T6均为薄膜晶体管(Thin Film Transistor，简称：TFT)。In some embodiments, the first transistor T1 to the sixth transistor T6 are all thin film transistors (Thin Film Transistor, TFT for short).
图3是示出根据本公开的一些实施例的像素电路的信号时序图。下面结合图2和图3对根据本公开的一些实施例的像素电路的工作原理进行详细描述。FIG. 3 is a signal timing diagram illustrating a pixel circuit according to some embodiments of the present disclosure. The working principle of the pixel circuit according to some embodiments of the present disclosure is described in detail below with reference to FIGS. 2 and 3.
如图2和图3所示，在复位时段t1，第一晶体管T1在第一信号端S1输出的电压信号的控制下导通，第二晶体管T2在第二信号端S2输出的电压信号的控制下导通，其中，第一信号端S1输出的电压信号为低电平，第二信号端S2输出的电压信号为低电平。此时，第一电源ELVDD输出的 电源电压V ELVDD通过导通的第一晶体管T1输入第一节点N1，初始电压信号端int输出的初始电压V int通过导通的第二晶体管T2输入第二节点N2。换言之，在复位时段，第一节点P1的电压V N1＝V ELVDD，第二节点N2的电压V N2＝V int，从而实现对第一节点N1和第二节点N2的复位，进而为下一时段的工作做好复位和准备工作。此时，电容器C的第一端子的电压为V N1＝V ELVDD，电容器C的第二端子的电压为V N2＝V int，从而实现在复位时段t1对电容器C的第一端子和第二端子进行充电。 As shown in FIGS. 2 and 3, during the reset period t1, the first transistor T1 is turned on under the control of the voltage signal output from the first signal terminal S1, and the second transistor T2 is controlled by the voltage signal output from the second signal terminal S2 The bottom is turned on, wherein the voltage signal output from the first signal terminal S1 is a low level, and the voltage signal output from the second signal terminal S2 is a low level. At this time, the first power source voltage ELVDD V output from the input power source ELVDD via the first node N1 of the first transistor T1 is turned on, the initial voltage signal output terminal of the initial voltage V int int via the second transistor T2 is turned on input node N2. In other words, during the reset period, the voltage of the first node P1 V N1 = V ELVDD and the voltage of the second node N2 V N2 = V int , so that the reset of the first node N1 and the second node N2 is realized, and then the next period Reset and prepare for the job. At this time, the voltage of the first terminal of the capacitor C is V N1 = V ELVDD , and the voltage of the second terminal of the capacitor C is V N2 = V int , so that the first and second terminals of the capacitor C are realized during the reset period t1. Charge it.
此外，在复位时段t1，第六晶体管T6在第二信号端S2输出的电压信号的控制下导通，初始电压信号端int输出的初始电压V int通过导通的第六晶体管T6输入第四节点N4。此时，第四节点N4的电压V N4＝V int，从而实现对第四节点N4的复位。由于二极管D的第一端子耦接至第四节点N4，因此，对第四节点N4的复位实际上即是对二极管D的第一端子进行复位。在该实施例中，二极管D的第一端子为阳极，二极管D的第二端子为阴极。 In addition, during the reset period t1, the sixth transistor T6 is turned on under the control of the voltage signal output from the second signal terminal S2, and the initial voltage V int output from the initial voltage signal terminal int is input to the fourth node through the turned-on sixth transistor T6. N4. At this time, the voltage of the fourth node N4 is V N4 = V int , so that the fourth node N4 is reset. Since the first terminal of the diode D is coupled to the fourth node N4, resetting the fourth node N4 is actually resetting the first terminal of the diode D. In this embodiment, the first terminal of the diode D is an anode, and the second terminal of the diode D is a cathode.
此外，在复位时段t1，第三晶体管T3在第二信号端S2输出的电压信号的控制下导通，第四晶体管T4在第三信号端S3输出的电压信号的控制下截止，其中，第三信号端S3输出的电压信号为高电平。此时，数据电压信号端Data输出的数据电压V data通过导通的第三晶体管T3输入第三节点N3。因此，在复位时段t1，第三节点N3的电压V N3＝V data，其中，数据电压V data为高电平。 In addition, during the reset period t1, the third transistor T3 is turned on under the control of the voltage signal output from the second signal terminal S2, and the fourth transistor T4 is turned off under the control of the voltage signal output from the third signal terminal S3. The voltage signal output from the signal terminal S3 is high. At this time, the data voltage V data output from the data voltage signal terminal Data is input to the third node N3 through the third transistor T3 that is turned on. Therefore, during the reset period t1, the voltage V N3 of the third node N3 = V data , where the data voltage V data is at a high level.
在补偿时段t2，第一晶体管T1在第一信号端S1输出的电压信号的控制下截止，第二晶体管T2在第二信号端S2输出的电压信号的控制下导通，第三晶体管T3在第二信号端S2输出的电压信号的控制下导通，其中，第一信号端S1输出的电压信号为高电平，第二信号端S2输出的电压信号为低电平。此时，数据电压信号端Data输出的数据电压V data通过导通的第三晶体管T3输入第三节点N3。因此，在补偿时段t2，第三节点N3的电压V N3＝V data，其中，数据电压V data为高电平。此时，在补偿时段t2，由于第一晶体管T1截止，使得第一电源ELVDD无法将电源电压V ELVDD持续输入第一节点N1，因此，电容器C的第一端子将放电。当第一节点N1的电压V N1由于电容器C的第一端子放电而从V ELVDD变化至V data-V th时，第五晶体管T5的栅源电压V gs等于其阈值电压V th，第五晶体管T5截止，电容器C 的第一端子停止放电。因此，存在以下电压关系：V th＝V gs＝V N3-V N1＝V data-V N1，其中，V gs为第五晶体管T5的控制端子与第一端子之间的电压，因此，V N1＝V data-V th，即，此时第一节点N1的电压为V data-V th。其中，V data-V th为补偿电压，电容器C的第一端子的电压等于第一节点N1的电压V N1。 In the compensation period t2, the first transistor T1 is turned off under the control of the voltage signal output from the first signal terminal S1, the second transistor T2 is turned on under the control of the voltage signal output from the second signal terminal S2, and the third transistor T3 is turned on The two signal terminals S2 are turned on under the control of a voltage signal. The voltage signal output from the first signal terminal S1 is high level, and the voltage signal output from the second signal terminal S2 is low level. At this time, the data voltage V data output from the data voltage signal terminal Data is input to the third node N3 through the third transistor T3 that is turned on. Therefore, during the compensation period t2, the voltage V N3 of the third node N3 = V data , where the data voltage V data is at a high level. At this time, during the compensation period t2, because the first transistor T1 is turned off, the first power source ELVDD cannot continuously input the power voltage V ELVDD to the first node N1, and therefore, the first terminal of the capacitor C will be discharged. When the voltage V N1 of the first node N1 changes from V ELVDD to V data -V th due to the discharge of the first terminal of the capacitor C, the gate-source voltage V gs of the fifth transistor T5 is equal to its threshold voltage V th . T5 is turned off, and the first terminal of capacitor C stops discharging. Therefore, the following voltage relationship exists: V th = V gs = V N3 -V N1 = V data -V N1 , where V gs is the voltage between the control terminal and the first terminal of the fifth transistor T5, so V N1 = V data -V th , that is, the voltage of the first node N1 at this time is V data -V th . Among them, V data -V th is the compensation voltage, and the voltage of the first terminal of the capacitor C is equal to the voltage V N1 of the first node N1 .
在发光时段t3，第二晶体管T2、第三晶体管T3和第六晶体管T6在第二信号端S2输出的电压信号的控制下截止，第一晶体管T1在第一信号端S1输出的电压信号的控制下导通，第四晶体管T4在第三信号端S3输出的电压信号的控制下导通，其中，第一信号端S1和第三信号端S3输出的电压信号均为低电平，第二信号端S2输出的电压信号为高电平。此时，第一电源ELVDD输出的电源电压V ELVDD通过导通的第一晶体管T1输入第一节点N1，第一节点N1的电压V N1＝V ELVDD。另一方面，由于电容器C的自举效应(即瞬时电压差保持功能)，使得电容器C的第二端子的电压被耦合为V int+V ELVDD-(V data-V th)，其中，电容器C的第二端子的电压为第二节点N2的电压，即V N2＝V int+V ELVDD-(V data-V th)。同时，由于第二节点N2和第三节点N3通过导通的第四晶体管T4耦接，使得电容器C的第二端子与第五晶体管T5的控制端子耦接，第三节点N3的电压V N3等于第二节点N2的电压V N2，即第三节点N3的电压V N3等于电容器C的第二端子的电压，也即V N3＝V N2＝V int+V ELVDD-(V data-V th)。此时，第五晶体管T5的控制端子与第一端子之间的电压V gs＝V N3-V N1＝V int+V ELVDD-(V data-V th)-V ELVDD＝V int-V data+V th，其中，V th为负值，V int-V data为负值，因此，第五晶体管T5在第三节点N3处的电压V N3，即电容器C的第二端子处的电压，的控制下导通。此时，流经二极管D的电流为： During the light-emitting period t3, the second transistor T2, the third transistor T3, and the sixth transistor T6 are turned off under the control of the voltage signal output from the second signal terminal S2, and the control of the voltage signal output from the first transistor T1 at the first signal terminal S1 is controlled. The fourth transistor T4 is turned on under the control of the voltage signal output from the third signal terminal S3. The voltage signals output from the first signal terminal S1 and the third signal terminal S3 are both low, and the second signal The voltage signal output from the terminal S2 is high. At this time, the first power source voltage ELVDD V output from the input power source ELVDD via the first node N1 of the first transistor T1 is turned on, the first node N1 voltage V N1 = V ELVDD. On the other hand, the voltage of the second terminal of the capacitor C is coupled as V int + V ELVDD- (V data -V th ) due to the bootstrap effect of the capacitor C (ie, the instantaneous voltage difference holding function), where the capacitor C The voltage of the second terminal is the voltage of the second node N2, that is, V N2 = V int + V ELVDD- (V data -V th ). At the same time, since the second node N2 and the third node N3 are coupled through the turned-on fourth transistor T4, the second terminal of the capacitor C is coupled to the control terminal of the fifth transistor T5, and the voltage V N3 of the third node N3 is equal to The voltage V N2 of the second node N2, that is, the voltage V N3 of the third node N3 is equal to the voltage of the second terminal of the capacitor C, that is, V N3 = V N2 = V int + V ELVDD- (V data -V th ). At this time, the voltage between the control terminal and the first terminal of the fifth transistor T5 is V gs = V N3 -V N1 = V int + V ELVDD- (V data -V th ) -V ELVDD = V int -V data + V th , where V th is negative and V int -V data is negative. Therefore, the control of the voltage V N3 of the fifth transistor T5 at the third node N3 , that is, the voltage of the second terminal of the capacitor C, is controlled. Under conduction. At this time, the current flowing through the diode D is:
I＝WC oxu/2L*(V gs-V th) 2＝WC oxu/2L*(V N3-V N1-V th)＝WC oxu/2L*(V int-V Data) 2。其中，W和L是第五晶体管M5的导电沟道的宽度和长度，C ox是单位面积的栅氧化层电容，u是第五晶体管M5的载流子迁移率。 I = WC ox u / 2L * (V gs -V th ) 2 = WC ox u / 2L * (V N3 -V N1 -V th ) = WC ox u / 2L * (V int -V Data ) 2 . Among them, W and L are the width and length of the conductive channel of the fifth transistor M5, Cox is the capacitance of the gate oxide layer per unit area, and u is the carrier mobility of the fifth transistor M5.
在该实施例中，从流经二极管D的电流的公式I＝WC oxu/2L*(V int-V Data) 2中可以看出，流经二极管D的电流I与初始电压V int和数据电压V Data相关，与电源电压V ELVDD和第五晶体管T5(即，驱动晶体管)的阈值电压V th无关，因此，消除了在发光时段T3电源电压V ELVDD和阈值电压V th对流经二极管D的电流I的影响，实现了补偿电源电压V ELVDD和阈值电压V th的效果，即实 现了像素补偿，从而提升了显示效果。 In this embodiment, from the formula I = WC ox u / 2L * (V int -V Data ) 2 of the current flowing through the diode D, it can be seen that the current I flowing through the diode D and the initial voltage V int and data The voltage V Data is related to the power supply voltage V ELVDD and the threshold voltage V th of the fifth transistor T5 (ie, the driving transistor). Therefore, the power source voltage V ELVDD and the threshold voltage V th to the current flowing through the diode D during the light-emitting period T3 are eliminated. The effect of the current I achieves the effect of compensating the power supply voltage V ELVDD and the threshold voltage V th , that is, implementing pixel compensation, thereby improving the display effect.
另一方面，本文所述的像素电路通过采用6个薄膜晶体管，即第一晶体管T1至第六晶体管T6，来实现像素补偿，因此减少了布线难度，为高PPI(像素密度)像素增加了布线空间。On the other hand, the pixel circuit described in this article uses six thin film transistors, namely the first transistor T1 to the sixth transistor T6, to achieve pixel compensation, thereby reducing the difficulty of wiring and increasing the wiring for high PPI (pixel density) pixels. space.
本文所述的像素电路的技术方案中，复位子电路用于在复位时段对第一节点和第二节点进行复位，以对存储子电路进行充电；存储子电路在补偿时段放电，以使第一节点的电压变为补偿电压；数据输入子电路在复位时段和补偿时段将数据电压写入第三节点；控制子电路在发光时段使存储子电路和驱动子电路耦接，以使存储子电路在发光时段开启驱动子电路；驱动子电路在发光时段驱动发光子电路进行发光。从而实现了像素补偿，提高了显示效果。此外，本文所述的像素电路通过采用6个薄膜晶体管，实现了像素补偿，由此减少了布线难度，为高PPI像素增加了布线空间。In the technical solution of the pixel circuit described herein, the reset sub-circuit is used to reset the first node and the second node during the reset period to charge the storage sub-circuit; the storage sub-circuit is discharged during the compensation period to make the first The voltage of the node becomes the compensation voltage; the data input sub-circuit writes the data voltage to the third node during the reset period and the compensation period; the control sub-circuit couples the storage sub-circuit and the driving sub-circuit during the light-emitting period so that the storage sub-circuit The driving sub-circuit is turned on during the light-emitting period; the driving sub-circuit drives the light-emitting sub-circuit to emit light during the light-emitting period. As a result, pixel compensation is achieved and the display effect is improved. In addition, the pixel circuit described herein implements pixel compensation by using 6 thin film transistors, thereby reducing wiring difficulties and increasing wiring space for high PPI pixels.
图4是示出根据本公开的一些实施例的像素电路的驱动方法的流程图。该像素电路包括复位子电路、存储子电路、数据输入子电路、控制子电路、驱动子电路和发光子电路。其中，复位子电路耦接至第一节点和第二节点，存储子电路耦接至第一节点和第二节点，数据输入子电路耦接至第三节点，控制子电路耦接至第二节点和第三节点，驱动子电路耦接至第一节点、第三节点和第四节点，并且发光子电路耦接至第四节点。FIG. 4 is a flowchart illustrating a driving method of a pixel circuit according to some embodiments of the present disclosure. The pixel circuit includes a reset sub-circuit, a storage sub-circuit, a data input sub-circuit, a control sub-circuit, a driving sub-circuit, and a light-emitting sub-circuit. The reset subcircuit is coupled to the first node and the second node, the storage subcircuit is coupled to the first node and the second node, the data input subcircuit is coupled to the third node, and the control subcircuit is coupled to the second node. With the third node, the driving sub-circuit is coupled to the first node, the third node, and the fourth node, and the light-emitting sub-circuit is coupled to the fourth node.
参照图4，像素电路的驱动方法包括：Referring to FIG. 4, a driving method of a pixel circuit includes:
在步骤301，在复位时段，使用复位子电路对第一节点和第二节点进行复位，以对存储子电路进行充电，并且使用数据输入子电路向驱动晶体管提供关于像素显示的数据电压。In step 301, during the reset period, the first node and the second node are reset using a reset sub-circuit to charge the storage sub-circuit, and the data input sub-circuit is used to provide the driving transistor with a data voltage on the pixel display.
在步骤302，在补偿时段，使用数据输入子电路向驱动晶体管提供关于像素显示的数据电压，并且使用存储子电路来存储与电源电压和驱动晶体管的阈值电压有关的电压信息。In step 302, during the compensation period, a data input sub-circuit is used to provide the driving transistor with a data voltage regarding the pixel display, and a storage sub-circuit is used to store voltage information related to the power supply voltage and the threshold voltage of the driving transistor.
在步骤303，在发光时段，使用控制子电路将存储子电路和驱动子电路电连接并将存储子电路所存储的电压信息传递至第三节点，以在该发光时段通过存储子电路开启驱动子电路，并且使用驱动子电路向发光子电路提供驱动电流以驱动发光子电路发光，该驱动电流与电源电压和驱动晶体管的阈值电压无关。In step 303, in the light-emitting period, the control sub-circuit is used to electrically connect the storage sub-circuit and the driving sub-circuit and transfer the voltage information stored in the storage sub-circuit to the third node, so as to turn on the driver through the storage sub-circuit during the light-emitting period And the driving sub-circuit is used to provide a driving current to the light-emitting sub-circuit to drive the light-emitting sub-circuit to emit light, the driving current is independent of the power supply voltage and the threshold voltage of the driving transistor.
本一些实施例中，像素电路包括本文所述的像素电路，关于该像素电路的具体描述在此不再赘述。In some embodiments, the pixel circuit includes the pixel circuit described herein, and a detailed description of the pixel circuit will not be repeated here.
本实施例所提供的像素电路的驱动方法的技术方案中，在复位时段，使用复位子电路对第一节点和第二节点进行复位，以对存储子电路进行充电，并且使用数据输入子电路将数据电压输入第三节点；在补偿时段，继续使用数据输入子电路将数据电压输入第三节点，并且存储子电路放电，以使第一节点的电压变为补偿电压；在发光时段，控制子电路使存储子电路和驱动子电路耦接，以使存储子电路开启驱动子电路，并且使用驱动子电路驱动发光子电路进行发光。从而实现了像素补偿，提高了显示效果。In the technical solution of the driving method of the pixel circuit provided in this embodiment, during the reset period, the first node and the second node are reset using a reset subcircuit to charge the storage subcircuit, and the data input subcircuit is used to The data voltage is input to the third node; during the compensation period, the data input sub-circuit is used to continue to input the data voltage to the third node, and the storage sub-circuit is discharged so that the voltage of the first node becomes the compensation voltage; during the light-emitting period, the control sub-circuit The storage sub-circuit and the driving sub-circuit are coupled so that the storage sub-circuit turns on the driving sub-circuit, and the driving sub-circuit is used to drive the light-emitting sub-circuit to emit light. As a result, pixel compensation is achieved and the display effect is improved.
本公开实施例四提供了一种显示装置，该显示装置包括上述实施例二提供的像素子电路，关于该像素子电路的具体描述可参见上述实施例二，此处不再赘述。Embodiment 4 of the present disclosure provides a display device. The display device includes a pixel sub-circuit provided in the above-mentioned Embodiment 2. For a detailed description of the pixel sub-circuit, refer to the above-mentioned Embodiment 2, which is not described herein again.
在本文所述的显示装置的技术方案中，复位子电路用于在复位时段对第一节点和第二节点进行复位，以对存储子电路进行充电；存储子电路用于在补偿时段进行放电，以使第一节点的电压变为补偿电压；数据输入子电路用于在复位时段和补偿时段将数据电压输入第三节点，以使驱动子电路在复位时段和补偿时段截止；控制子电路用于在发光时段控制存储子电路和驱动子电路耦接，以使存储子电路控制驱动子电路开启；驱动子电路用于在发光时段驱动发光子电路进行发光。从而实现了像素补偿，提高了显示效果。In the technical solution of the display device described herein, the reset sub-circuit is used to reset the first node and the second node during the reset period to charge the storage sub-circuit; the storage sub-circuit is used to discharge during the compensation period, So that the voltage of the first node becomes the compensation voltage; the data input sub-circuit is used to input the data voltage to the third node during the reset period and the compensation period, so that the driving sub-circuit is turned off during the reset period and the compensation period; the control sub-circuit is used for The storage sub-circuit is controlled to be coupled to the driving sub-circuit during the light-emitting period, so that the storage sub-circuit controls the driving sub-circuit to be turned on; the driving sub-circuit is used to drive the light-emitting sub-circuit to emit light during the light-emitting period. As a result, pixel compensation is achieved and the display effect is improved.
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。It can be understood that the above embodiments are merely exemplary embodiments adopted for explaining the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, various variations and improvements can be made without departing from the spirit and essence of the present invention, and these variations and improvements are also considered to be within the protection scope of the present invention.

Claims (20)

  1. 一种像素电路，包括：A pixel circuit includes:
    复位子电路，耦接至第一节点和第二节点，用于对所述第一节点和所述第二节点进行复位；A reset sub-circuit, coupled to the first node and the second node, for resetting the first node and the second node;
    发光子电路，耦接至第四节点；A light-emitting sub-circuit, coupled to the fourth node;
    驱动子电路，耦接至所述第一节点、第三节点和所述第四节点，并且包括驱动晶体管，用于向所述发光子电路提供驱动电流；A driving sub-circuit, coupled to the first node, the third node, and the fourth node, and including a driving transistor for supplying a driving current to the light-emitting sub-circuit;
    存储子电路，耦接至所述第一节点和所述第二节点，用于存储与电源电压和所述驱动晶体管的阈值电压有关的电压信息；A storage sub-circuit, coupled to the first node and the second node, for storing voltage information related to a power supply voltage and a threshold voltage of the driving transistor;
    数据输入子电路，耦接至所述第三节点，用于向所述驱动晶体管提供关于像素显示的数据电压；和A data input sub-circuit, coupled to the third node, for providing the driving transistor with a data voltage on a pixel display; and
    控制子电路，耦接至所述第二节点和所述第三节点，用于控制所述存储子电路与所述驱动子电路的连接，A control sub-circuit, coupled to the second node and the third node, for controlling a connection between the storage sub-circuit and the driving sub-circuit,
    其中，在所述驱动子电路驱动所述发光子电路发光时，所述控制子电路将所述存储子电路所存储的电压信息传递至所述第三节点，以使得所述驱动电流与所述电源电压和所述阈值电压无关。Wherein, when the driving sub-circuit drives the light-emitting sub-circuit to emit light, the control sub-circuit transmits the voltage information stored in the storage sub-circuit to the third node, so that the driving current and the The power supply voltage is independent of the threshold voltage.
  2. 根据权利要求1所述的像素电路，其中，所述复位子电路包括：第一晶体管和第二晶体管；The pixel circuit according to claim 1, wherein the reset sub-circuit comprises: a first transistor and a second transistor;
    所述第一晶体管的第一端子耦接至用于提供所述电源电压的第一电源，所述第一晶体管的第二端子耦接至所述第一节点，所述第一晶体管的控制端子耦接至第一信号端；并且A first terminal of the first transistor is coupled to a first power source for providing the power supply voltage, a second terminal of the first transistor is coupled to the first node, and a control terminal of the first transistor Coupled to the first signal terminal; and
    所述第二晶体管的第一端子耦接至初始电压信号端，所述第二晶体管的第二端子耦接至所述第二节点，所述第二晶体管的控制端子耦接至第二信号端。A first terminal of the second transistor is coupled to the initial voltage signal terminal, a second terminal of the second transistor is coupled to the second node, and a control terminal of the second transistor is coupled to the second signal terminal. .
  3. 根据权利要求2所述的像素电路，其中，所述存储子电路包括：第一电容器，耦接在所述第一节点和所述第二节点之间。The pixel circuit according to claim 2, wherein the storage sub-circuit comprises: a first capacitor coupled between the first node and the second node.
  4. 根据权利要求3所述的像素电路，其中，所述数据输入子电路包括：第三晶体管，所述第三晶体管的第一端子耦接至数据电压信号端，所述第三晶体管的第二端子耦接至所述第三节点，所述第三晶体管的控制端子耦接至第二信号端。The pixel circuit according to claim 3, wherein the data input sub-circuit comprises: a third transistor, a first terminal of the third transistor is coupled to a data voltage signal terminal, and a second terminal of the third transistor Coupled to the third node, and the control terminal of the third transistor is coupled to the second signal terminal.
  5. 根据权利要求4所述的像素电路，其中，所述控制子电路包括：第四晶体管，所述第四晶体管的第一端子耦接至所述第二节点，所述第四晶体管的第二端子耦接至所述第三节点，所述第四晶体管的控制端子耦接至第三信号端。The pixel circuit according to claim 4, wherein the control sub-circuit comprises: a fourth transistor, a first terminal of the fourth transistor is coupled to the second node, and a second terminal of the fourth transistor Coupled to the third node, and a control terminal of the fourth transistor is coupled to a third signal terminal.
  6. 根据权利要求5所述的像素电路，其中，所述驱动晶体管的第一端子耦接至所述第一节点，所述驱动晶体管的第二端子耦接至所述第四节点，所述驱动晶体管的控制端子耦接至所述第三节点。The pixel circuit according to claim 5, wherein a first terminal of the driving transistor is coupled to the first node, a second terminal of the driving transistor is coupled to the fourth node, and the driving transistor The control terminal is coupled to the third node.
  7. 根据权利要求6所述的像素电路，其中，所述发光子电路包括二极管，所述二极管的第一端子耦接至所述第四节点，所述二极管的第二端子耦接至第二电源。The pixel circuit according to claim 6, wherein the light-emitting sub-circuit comprises a diode, a first terminal of the diode is coupled to the fourth node, and a second terminal of the diode is coupled to a second power source.
  8. 根据权利要求1或7所述的像素电路，其中，所述复位子电路还耦接至所述第四节点。The pixel circuit according to claim 1 or 7, wherein the reset sub-circuit is further coupled to the fourth node.
  9. 根据权利要求8所述的像素电路，其中，所述复位子电路包括：第六晶体管，所述第六晶体管的第一端子耦接至初始电压信号端，所述第六晶体管的第二端子耦接至所述第四节点，所述第六晶体管的控制端子耦接至第二信号端。The pixel circuit according to claim 8, wherein the reset sub-circuit comprises: a sixth transistor, a first terminal of the sixth transistor is coupled to an initial voltage signal terminal, and a second terminal of the sixth transistor is coupled Connected to the fourth node, and the control terminal of the sixth transistor is coupled to the second signal terminal.
  10. 一种像素电路的驱动方法，其中，所述像素电路包括：复位子电路，耦接至第一节点和第二节点；存储子电路，耦接至所述第一节点和所述第二节点；数据输入子电路，耦接至第三节点；控制子电路，耦接至所述第二节点和所述第三节点；驱动子电路，耦接至所述第一节点、所述 第三节点和第四节点，并且包括驱动晶体管；和发光子电路，耦接至所述第四节点；A method for driving a pixel circuit, wherein the pixel circuit includes a reset sub-circuit coupled to a first node and a second node, and a storage sub-circuit coupled to the first node and the second node; A data input sub-circuit is coupled to the third node; a control sub-circuit is coupled to the second node and the third node; a driving sub-circuit is coupled to the first node, the third node and A fourth node, and including a driving transistor; and a light emitting sub-circuit, coupled to the fourth node;
    所述驱动方法包括：The driving method includes:
    在用于显示一帧图像的周期时间的复位时段中，使用所述复位子电路对所述第一节点和所述第二节点进行复位，并且使用所述数据输入子电路向所述驱动晶体管提供关于像素显示的数据电压；In the reset period for displaying the cycle time of one frame of image, the reset node is used to reset the first node and the second node, and the data input sub circuit is used to provide the drive transistor Data voltage on pixel display;
    在所述周期时间的在所述复位时段之后的补偿时段中，使用所述数据输入子电路向所述驱动晶体管提供关于像素显示的数据电压，并且使用所述存储子电路来存储与电源电压和所述驱动晶体管的阈值电压有关的电压信息；和In the compensation period of the cycle time after the reset period, the data input sub-circuit is used to provide the driving transistor with a data voltage on pixel display, and the storage sub-circuit is used to store the Voltage information related to a threshold voltage of the driving transistor; and
    在所述周期时间的在所述补偿时段之后的发光时段中，使用所述控制子电路将所述存储子电路和所述驱动子电路电连接并将所述存储子电路所存储的电压信息传递至所述第三节点，并且使用所述驱动子电路向所述发光子电路提供驱动电流，所述驱动电流与所述电源电压和所述阈值电压无关。In the light-emitting period after the compensation period of the cycle time, the control sub-circuit is used to electrically connect the storage sub-circuit and the driving sub-circuit and transfer voltage information stored in the storage sub-circuit To the third node, and using the driving sub-circuit to provide a driving current to the light-emitting sub-circuit, the driving current is independent of the power supply voltage and the threshold voltage.
  11. 根据权利要求10所述的驱动方法，其中，所述复位子电路还耦接至所述第四节点。The driving method according to claim 10, wherein the reset sub-circuit is further coupled to the fourth node.
  12. 根据权利要求11所述的驱动方法，还包括：The driving method according to claim 11, further comprising:
    在所述复位时段中，使用所述复位子电路对所述第四节点进行复位。In the reset period, the fourth node is reset using the reset sub-circuit.
  13. 根据权利要求10所述的驱动方法，其中，所述复位子电路包括：第一晶体管和第二晶体管；The driving method according to claim 10, wherein the reset sub-circuit comprises: a first transistor and a second transistor;
    所述第一晶体管的第一端子耦接至第一电源，所述第一晶体管的第二端子耦接至所述第一节点，所述第一晶体管的控制端子耦接至第一信号端；并且A first terminal of the first transistor is coupled to a first power source, a second terminal of the first transistor is coupled to the first node, and a control terminal of the first transistor is coupled to a first signal terminal; and
    所述第二晶体管的第一端子耦接至初始电压信号端，所述第二晶体管的第二端子耦接至所述第二节点，所述第二晶体管的控制端子耦接至第二信号端。A first terminal of the second transistor is coupled to the initial voltage signal terminal, a second terminal of the second transistor is coupled to the second node, and a control terminal of the second transistor is coupled to the second signal terminal. .
  14. 根据权利要求13所述的驱动方法，其中，所述存储子电路包括：第一电容器，耦接在所述第一节点和所述第二节点之间。The driving method according to claim 13, wherein the storage sub-circuit comprises: a first capacitor coupled between the first node and the second node.
  15. 根据权利要求14所述的驱动方法，其中，所述数据输入子电路包括：第三晶体管，所述第三晶体管的第一端子耦接至数据电压信号端，所述第三晶体管的第二端子耦接至所述第三节点，所述第三晶体管的控制端子耦接至第二信号端。The driving method according to claim 14, wherein the data input sub-circuit comprises: a third transistor, a first terminal of the third transistor is coupled to a data voltage signal terminal, and a second terminal of the third transistor Coupled to the third node, and the control terminal of the third transistor is coupled to the second signal terminal.
  16. 根据权利要求15所述的驱动方法，其中，所述控制子电路包括：第四晶体管，所述第四晶体管的第一端子耦接至所述第二节点，所述第四晶体管的第二端子耦接至所述第三节点，所述第四晶体管的控制端子耦接至第三信号端。The driving method according to claim 15, wherein the control sub-circuit comprises: a fourth transistor, a first terminal of the fourth transistor is coupled to the second node, and a second terminal of the fourth transistor Coupled to the third node, and a control terminal of the fourth transistor is coupled to a third signal terminal.
  17. 根据权利要求16所述的驱动方法，其中，所述驱动晶体管的第一端子耦接至所述第一节点，所述驱动晶体管的第二端子耦接至所述第四节点，所述驱动晶体管的控制端子耦接至所述第三节点。The driving method according to claim 16, wherein a first terminal of the driving transistor is coupled to the first node, a second terminal of the driving transistor is coupled to the fourth node, and the driving transistor The control terminal is coupled to the third node.
  18. 根据权利要求17所述的驱动方法，其中，所述发光子电路包括：二极管，所述二极管的第一端子耦接至所述第四节点，所述二极管的第二端子耦接至第二电源。The driving method according to claim 17, wherein the light-emitting sub-circuit comprises: a diode, a first terminal of the diode is coupled to the fourth node, and a second terminal of the diode is coupled to a second power source .
  19. 根据权利要求11所述的驱动方法，其中，所述复位子电路包括：第六晶体管，所述第六晶体管的第一端子耦接至初始电压信号端，所述第六晶体管的第二端子耦接至所述第四节点，所述第六晶体管的控制端子耦接至第二信号端。The driving method according to claim 11, wherein the reset sub-circuit comprises: a sixth transistor, a first terminal of the sixth transistor is coupled to an initial voltage signal terminal, and a second terminal of the sixth transistor is coupled Connected to the fourth node, and the control terminal of the sixth transistor is coupled to the second signal terminal.
  20. 一种显示装置，包括权利要求1至9中任一项所述的像素电路。A display device comprising the pixel circuit according to any one of claims 1 to 9.
PCT/CN2019/088364 2018-05-31 2019-05-24 Pixel circuit and driving method therefor, and display device WO2019228271A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810549595.4A CN108766361A (en) 2018-05-31 2018-05-31 Pixel circuit and its driving method, display device
CN201810549595.4 2018-05-31

Publications (1)

Publication Number Publication Date
WO2019228271A1 true WO2019228271A1 (en) 2019-12-05

Family

ID=64001324

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/088364 WO2019228271A1 (en) 2018-05-31 2019-05-24 Pixel circuit and driving method therefor, and display device

Country Status (2)

Country Link
CN (1) CN108766361A (en)
WO (1) WO2019228271A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108766361A (en) * 2018-05-31 2018-11-06 京东方科技集团股份有限公司 Pixel circuit and its driving method, display device
CN111415620B (en) * 2020-03-31 2021-08-13 合肥京东方显示技术有限公司 Pixel circuit, driving method thereof and display device

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104157236A (en) * 2014-07-16 2014-11-19 京东方科技集团股份有限公司 Shift register and grid drive circuit
CN104485074A (en) * 2014-12-30 2015-04-01 合肥鑫晟光电科技有限公司 Pixel driving circuit and method and display device
CN104700776A (en) * 2015-03-25 2015-06-10 京东方科技集团股份有限公司 Pixel circuit and driving method thereof, display device
CN105632408A (en) * 2016-03-23 2016-06-01 信利（惠州）智能显示有限公司 OLED pixel driving circuit and display device
CN105913792A (en) * 2016-06-30 2016-08-31 京东方科技集团股份有限公司 Pixel circuit, semiconductor camera detection circuit and display device
CN106409224A (en) * 2016-10-28 2017-02-15 京东方科技集团股份有限公司 Pixel driving circuit, driving circuit, display substrate and display device
CN106448567A (en) * 2016-12-08 2017-02-22 合肥鑫晟光电科技有限公司 Pixel drive circuit, drive method, pixel unit and display device
CN106486063A (en) * 2016-10-26 2017-03-08 京东方科技集团股份有限公司 Pixel-driving circuit and its driving method, display floater and display device
CN106782286A (en) * 2017-03-06 2017-05-31 京东方科技集团股份有限公司 Display device, display panel and pixel-driving circuit
CN107195274A (en) * 2017-05-02 2017-09-22 深圳市华星光电技术有限公司 Pixel compensation circuit, scan drive circuit and display device
CN107437399A (en) * 2017-07-25 2017-12-05 武汉华星光电半导体显示技术有限公司 A kind of pixel compensation circuit
CN207217080U (en) * 2017-08-31 2018-04-10 京东方科技集团股份有限公司 Image element circuit, display base plate and display device
CN107945737A (en) * 2017-11-27 2018-04-20 合肥京东方光电科技有限公司 Pixel compensation circuit, its driving method, display panel and display device
CN108172172A (en) * 2017-12-22 2018-06-15 武汉华星光电半导体显示技术有限公司 Pixel-driving circuit and the display device with the pixel-driving circuit
CN108231005A (en) * 2018-03-29 2018-06-29 武汉华星光电半导体显示技术有限公司 AMOLED pixel-driving circuits, driving method, display panel and terminal
CN108281113A (en) * 2018-02-06 2018-07-13 京东方科技集团股份有限公司 Pixel circuit and its driving method, display device
CN108766361A (en) * 2018-05-31 2018-11-06 京东方科技集团股份有限公司 Pixel circuit and its driving method, display device
CN108806595A (en) * 2018-06-26 2018-11-13 京东方科技集团股份有限公司 Pixel-driving circuit and method, display panel

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104050917B (en) * 2014-06-09 2018-02-23 上海天马有机发光显示技术有限公司 A kind of image element circuit, organic EL display panel and display device
CN104882099B (en) * 2015-06-10 2017-08-25 京东方科技集团股份有限公司 A kind of pixel-driving circuit, array base palte and display device
CN107103877B (en) * 2017-05-15 2019-06-14 京东方科技集团股份有限公司 Pixel circuit and its driving method, display device
CN107945743A (en) * 2018-01-04 2018-04-20 京东方科技集团股份有限公司 A kind of image element circuit, its driving method and display device

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104157236A (en) * 2014-07-16 2014-11-19 京东方科技集团股份有限公司 Shift register and grid drive circuit
CN104485074A (en) * 2014-12-30 2015-04-01 合肥鑫晟光电科技有限公司 Pixel driving circuit and method and display device
CN104700776A (en) * 2015-03-25 2015-06-10 京东方科技集团股份有限公司 Pixel circuit and driving method thereof, display device
CN105632408A (en) * 2016-03-23 2016-06-01 信利（惠州）智能显示有限公司 OLED pixel driving circuit and display device
CN105913792A (en) * 2016-06-30 2016-08-31 京东方科技集团股份有限公司 Pixel circuit, semiconductor camera detection circuit and display device
CN106486063A (en) * 2016-10-26 2017-03-08 京东方科技集团股份有限公司 Pixel-driving circuit and its driving method, display floater and display device
CN106409224A (en) * 2016-10-28 2017-02-15 京东方科技集团股份有限公司 Pixel driving circuit, driving circuit, display substrate and display device
CN106448567A (en) * 2016-12-08 2017-02-22 合肥鑫晟光电科技有限公司 Pixel drive circuit, drive method, pixel unit and display device
CN106782286A (en) * 2017-03-06 2017-05-31 京东方科技集团股份有限公司 Display device, display panel and pixel-driving circuit
CN107195274A (en) * 2017-05-02 2017-09-22 深圳市华星光电技术有限公司 Pixel compensation circuit, scan drive circuit and display device
CN107437399A (en) * 2017-07-25 2017-12-05 武汉华星光电半导体显示技术有限公司 A kind of pixel compensation circuit
CN207217080U (en) * 2017-08-31 2018-04-10 京东方科技集团股份有限公司 Image element circuit, display base plate and display device
CN107945737A (en) * 2017-11-27 2018-04-20 合肥京东方光电科技有限公司 Pixel compensation circuit, its driving method, display panel and display device
CN108172172A (en) * 2017-12-22 2018-06-15 武汉华星光电半导体显示技术有限公司 Pixel-driving circuit and the display device with the pixel-driving circuit
CN108281113A (en) * 2018-02-06 2018-07-13 京东方科技集团股份有限公司 Pixel circuit and its driving method, display device
CN108231005A (en) * 2018-03-29 2018-06-29 武汉华星光电半导体显示技术有限公司 AMOLED pixel-driving circuits, driving method, display panel and terminal
CN108766361A (en) * 2018-05-31 2018-11-06 京东方科技集团股份有限公司 Pixel circuit and its driving method, display device
CN108806595A (en) * 2018-06-26 2018-11-13 京东方科技集团股份有限公司 Pixel-driving circuit and method, display panel

Also Published As

Publication number Publication date
CN108766361A (en) 2018-11-06

Similar Documents

Publication Publication Date Title
WO2020062802A1 (en) Display panel, and drive method for pixel circuit
KR102030632B1 (en) Organic Light Emitting Display and Driving Method Thereof
WO2019237735A1 (en) Pixel circuit and driving method therefor, and display panel and display apparatus
KR100911980B1 (en) Pixel and organic light emitting display device using the same
CN112489599B (en) AMOLED pixel driving circuit, driving method and display panel
WO2016145693A1 (en) Amoled pixel drive circuit and pixel drive method
WO2016155053A1 (en) Amoled pixel driving circuit and pixel driving method
WO2016119304A1 (en) Amoled pixel drive circuit and pixel drive method
US20220375395A1 (en) Resetting control signal generation circuitry, method and module, and display device
WO2017024754A1 (en) Pixel circuit and drive method thereof, array substrate and display device
CN113744683B (en) Pixel circuit, driving method and display device
WO2015143835A1 (en) Pixel compensation circuit, array substrate and display device
KR20150059919A (en) Pixel circuit for increasing validity of current sensing
WO2021184893A1 (en) Pixel circuit and drive method therefor, display substrate and display apparatus
WO2016119305A1 (en) Amoled pixel drive circuit and pixel drive method
WO2015014025A1 (en) Pixel drive circuit and drive method thereof, and display device
CN103021339B (en) Image element circuit, display device and driving method thereof
JP7203611B2 (en) PIXEL COMPENSATION CIRCUIT UNIT, PIXEL CIRCUIT AND DISPLAY DEVICE
WO2019237756A1 (en) Pixel circuit and driving method therefor, display panel and display device
TW201541447A (en) AMOLED (active matrix/organic light emitting diode) driving circuit
WO2020062813A1 (en) Pixel circuit and driving method therefor, and display device
WO2021046999A1 (en) Oled pixel compensation circuit and pixel compensation method
WO2021179406A1 (en) Pixel driving circuit and driving method therefor, and display panel
WO2021000816A1 (en) Pixel circuit and driving method therefor, and display device
WO2020062811A1 (en) Pixel circuit and driving method therefor, display panel, and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19810136

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 21.04.2021)

122 Ep: pct application non-entry in european phase

Ref document number: 19810136

Country of ref document: EP

Kind code of ref document: A1