WO2019227816A1 - 一种显示装置 - Google Patents

一种显示装置 Download PDF

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Publication number
WO2019227816A1
WO2019227816A1 PCT/CN2018/109706 CN2018109706W WO2019227816A1 WO 2019227816 A1 WO2019227816 A1 WO 2019227816A1 CN 2018109706 W CN2018109706 W CN 2018109706W WO 2019227816 A1 WO2019227816 A1 WO 2019227816A1
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WO
WIPO (PCT)
Prior art keywords
gate
lower substrate
upper substrate
driver
data lines
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PCT/CN2018/109706
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English (en)
French (fr)
Inventor
何文超
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2019227816A1 publication Critical patent/WO2019227816A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers

Definitions

  • the present application relates to the technical field of liquid crystal display, and in particular to a display device.
  • Display panel technology With the increasing development of display panel technology, higher and higher resolutions (such as 4K, 2K; 8K, 4K; 16K, 8K) have become the technical goals pursued by people.
  • Traditional display panels are composed of two glasses, generally The upper plate is a CF (color film) substrate, and the lower plate is a TFT (array) substrate.
  • TFT array structure (or other pixel driving structure) is distributed on the two substrates. At least one of the upper substrate and the lower substrate contains a CF substrate.
  • the present application provides a display device, which can increase the charging time of a high-resolution display panel, improve the display effect of the display panel, and increase the transmittance of the display panel.
  • the present application provides a display device.
  • the display device includes:
  • a display panel including an upper substrate and a lower substrate opposite to each other, and a liquid crystal layer located between the upper substrate and the lower substrate, and at least one of the upper substrate and the lower substrate includes Color film color resist layer;
  • the upper substrate includes n first gate lines and m first data lines, and the lower substrate includes n second gate lines and m second data lines, which together define a matrix of n rows and m columns. Multiple pixels of, where m and n are natural numbers;
  • At least one first gate driver one end corresponding to the n first gate lines is disposed on the upper substrate for driving the n first gate lines;
  • At least one first source driver one end corresponding to the m first data lines is disposed on the upper substrate, and is used to drive the m first data lines;
  • At least one second gate driver one end corresponding to the n second gate lines is disposed on the lower substrate to drive the n second gate lines;
  • At least one second source driver one end corresponding to the m second data lines is disposed on the lower substrate for driving the m second data lines;
  • the first gate driver, the first source driver, the second gate driver, and the second source driver are disposed at peripheral edges of the display panel, and the first gate driver And the second gate driver simultaneously sends out a gate signal to drive the first gate line and the corresponding second gate line at the same time.
  • the first gate driver and the second gate driver are respectively prepared directly in a non-display area of the upper substrate and a non-display area of the lower substrate; or, the first A gate driver and the second gate driver are respectively bound to the upper substrate and the lower substrate through a conductive adhesive.
  • the upper substrate further includes a first thin film transistor
  • the lower substrate further includes a second thin film transistor
  • the first thin film transistor corresponding to each row of pixels is connected to one of the n first gate lines, and the first thin film transistor corresponding to each column of pixels is connected to one or two of the m first data lines.
  • the second thin film transistor corresponding to each row of pixels is connected to one of n second gate lines, and the second thin film transistor corresponding to each column of pixels is connected to one or two of m second data lines. article.
  • the first source driver and the second source driver simultaneously send data signals to drive the first data line and the corresponding second data line at the same time.
  • the first thin film transistor corresponding to each column of pixels is connected to two of the m first data lines
  • the second thin film transistor corresponding to each column of pixels is connected to m the first Two of the two data lines.
  • the first thin film transistors corresponding to each column of pixels are staggered connected to two adjacent first data lines; the second thin film transistors corresponding to each column of pixels are staggered connected to a phase. Two adjacent second data lines.
  • the upper substrate and the lower substrate are not completely overlapped, and the first gate driver and the first source driver are correspondingly disposed at one end of a non-overlapping region of the upper substrate, respectively.
  • the second gate driver and the second source driver are respectively disposed at one end of a non-overlapping region of the lower substrate.
  • the non-overlapping area of the upper substrate and the lower substrate corresponds to a non-display area at a peripheral edge of the display panel.
  • the first gate driver and the first source driver are disposed on a side of the upper substrate facing the lower substrate; the second gate driver and the second The source driver is disposed on a side of the lower substrate facing the upper substrate.
  • the present application further provides a display device, where the display device includes:
  • a display panel including an upper substrate and a lower substrate opposite to each other, and a liquid crystal layer located between the upper substrate and the lower substrate, and at least one of the upper substrate and the lower substrate includes Color film color resist layer;
  • the upper substrate includes n first gate lines and m first data lines, and the lower substrate includes n second gate lines and m second data lines, which together define a matrix of n rows and m columns. Multiple pixels of, where m and n are natural numbers;
  • At least one first gate driver one end corresponding to the n first gate lines is disposed on the upper substrate for driving the n first gate lines;
  • At least one first source driver one end corresponding to the m first data lines is disposed on the upper substrate, and is used to drive the m first data lines;
  • At least one second gate driver one end corresponding to the n second gate lines is disposed on the lower substrate to drive the n second gate lines;
  • At least one second source driver one end corresponding to the m second data lines is disposed on the lower substrate for driving the m second data lines;
  • the number of the first gate driver is the same as the number of the second gate driver, and the number of the first source driver is the same as the number of the second source driver;
  • the first gate driver, the first source driver, the second gate driver, and the second source driver are disposed at peripheral edges of the display panel, and the first gate driver And the second gate driver simultaneously sends out a gate signal to drive the first gate line and the corresponding second gate line at the same time.
  • the first gate driver and the second gate driver are respectively prepared directly in a non-display area of the upper substrate and a non-display area of the lower substrate; or, the first A gate driver and the second gate driver are respectively bound to the upper substrate and the lower substrate through a conductive adhesive.
  • the upper substrate further includes a first thin film transistor
  • the lower substrate further includes a second thin film transistor
  • the first thin film transistor corresponding to each row of pixels is connected to one of the n first gate lines, and the first thin film transistor corresponding to each column of pixels is connected to one or two of the m first data lines.
  • the second thin film transistor corresponding to each row of pixels is connected to one of n second gate lines, and the second thin film transistor corresponding to each column of pixels is connected to one or two of m second data lines. article.
  • the first source driver and the second source driver simultaneously send data signals to drive the first data line and the corresponding second data line at the same time.
  • the first thin film transistor corresponding to each column of pixels is connected to two of the m first data lines
  • the second thin film transistor corresponding to each column of pixels is connected to m the first Two of the two data lines.
  • the first thin film transistors corresponding to each column of pixels are staggered connected to two adjacent first data lines; the second thin film transistors corresponding to each column of pixels are staggered connected to a phase. Two adjacent second data lines.
  • the upper substrate and the lower substrate are not completely overlapped, and the first gate driver and the first source driver are correspondingly disposed at one end of a non-overlapping region of the upper substrate, respectively.
  • the second gate driver and the second source driver are respectively disposed at one end of a non-overlapping region of the lower substrate.
  • the non-overlapping area of the upper substrate and the lower substrate corresponds to a non-display area at a peripheral edge of the display panel.
  • the first gate driver and the first source driver are disposed on a side of the upper substrate facing the lower substrate; the second gate driver and the second The source driver is disposed on a side of the lower substrate facing the upper substrate.
  • the beneficial effect of the present application is that, compared with the existing display device, the display device of the present application is provided with a gate driver and a source driver on both the upper and lower substrates to drive the gate and data lines of the upper and lower substrates at the same time.
  • the display device of the present application is provided with a gate driver and a source driver on both the upper and lower substrates to drive the gate and data lines of the upper and lower substrates at the same time.
  • two gate lines can work at the same time, which doubles the display panel charging time; for example, the solution disclosed in this patent is adopted, and the display panel with a resolution of 4K and 2K is charged.
  • the time is t
  • the charging time of the display panel with the resolution of 8K, 4K is t / 2
  • the charging time of the display panel with the resolution of 16K, 8K is t / 4; compared with the traditional display panel at the same resolution,
  • This solution can reduce the load of the resistance and capacitance of the display panel, solve the problem of insufficient charging of the high-resolution display panel, improve the display effect of the panel, and help increase the penetration rate of the panel.
  • FIG. 1a is a schematic plan view of a display device provided by the present application.
  • 1b is a schematic cross-sectional view of a display device provided by the present application.
  • FIG. 2 is a schematic structural diagram of an upper substrate of a display device provided by the present application.
  • FIG. 3 is a schematic structural diagram of a lower substrate of a display device provided by the present application.
  • the present application addresses the technical problem that the resistance and capacitance load of the high-resolution display panel of the prior art increases, and the charging time decreases sharply, thereby affecting the display effect and the transmittance of the display panel.
  • This embodiment can solve this defect.
  • FIG. 1a a schematic plan view of a display device provided by the present application is shown.
  • the display device includes a display panel including an upper substrate 101 and a lower substrate 102 disposed opposite to each other, and a liquid crystal layer (not labeled) located between the upper substrate 101 and the lower substrate 102.
  • the display The TFT array structure (or other pixel driving structure) of the panel is respectively distributed on the upper substrate 101 and the lower substrate 102.
  • the structure of the display panel may be: (the upper substrate 101: (CF + TFT) substrate, the lower substrate 102: TFT substrate), or: (the upper substrate 101: TFT substrate, the lower substrate 102: (CF + TFT) substrate), or: (the upper substrate 101: (CF + TFT) substrate, the lower substrate 102: (CF + TFT) substrate). That is, both the upper substrate 101 and the lower substrate 102 of the present application have the function of a TFT, that is, an array substrate.
  • the display area of the upper substrate 101 includes n first gate lines and m first data lines.
  • the display area of the lower substrate 102 includes n second gate lines and m second data lines, which together define a plurality of pixels of a matrix of n rows and m columns, where m and n are natural numbers.
  • the n first gate lines and the n second gate lines, and the m first data lines and the m second data lines are all insulated.
  • the display device further includes: at least one first gate driver 103 disposed on a right edge of the upper substrate 101 to drive n of the first gate lines; at least one first source driver 104, Disposed on the upper edge of the upper substrate 101 to drive the m first data lines; at least one second gate driver 105 is disposed on the left edge of the lower substrate 102 to drive n The second gate line; at least one second source driver 106 is disposed on a lower edge of the lower substrate 102 and is used to drive m second data lines.
  • the first gate driver 103 and the second gate driver 105 are respectively located at two ends of the display panel, and the first source driver 104 and the second source driver 106 are respectively located in the display panel.
  • first gate driver 103 and the second gate driver 105 simultaneously emit gate signals to drive the first gate line and the corresponding first gate line at the same time.
  • Two gate lines so that the charging time of the display panel is doubled.
  • the first source driver 104 and the second source driver 106 simultaneously send data signals to drive the first data line and the corresponding second data line at the same time.
  • the upper substrate 101 and the lower substrate 102 are not completely overlapped, and a non-overlapping area of the upper substrate 101 and the lower substrate 102 corresponds to a non-display area around a periphery of the display panel, and the first gate driver 103 and the first source driver 104 are respectively disposed on one end of the non-overlapping region of the upper substrate 101; the second gate driver 105 and the second source driver 106 are respectively disposed on the lower substrate 102 at one end of the non-overlapping region.
  • the first gate driver 103 and the first source driver 104 are disposed on a side of the upper substrate 101 facing the lower substrate 102; the second gate driver 105 and the second source driver 106 is disposed on a side of the lower substrate 102 facing the upper substrate 101.
  • FIG. 1b a schematic cross-sectional view of a display device provided by the present application.
  • the upper substrate 101 and the lower substrate 102 are not completely overlapped.
  • the first gate driver 103 is bonded to one end of the upper substrate 101
  • the second gate driver 105 is bonded to one end of the lower substrate 102.
  • the first source driver 104 and the second source driver 106 are similarly arranged, and will not be repeated here.
  • the first gate driver 103 and the second gate driver 105 may be directly prepared in a non-display area of the upper substrate 101 and a non-display area of the lower substrate 102, such as a GOA circuit; or, The first gate driver 103 and the second gate driver 105 are respectively bound to the upper substrate 101 and the lower substrate 102 through a conductive adhesive, such as COF (chip on film).
  • a conductive adhesive such as COF (chip on film).
  • the number of the first gate drivers 103 and the number of the second gate drivers 105 are the same, and the number of the first source drivers 104 is the same as the number of the second source drivers 106.
  • FIG. 2 it is a schematic structural diagram of an upper substrate of a display device provided by the present application.
  • the upper substrate 20 includes a color film color resist layer (not labeled) and a first thin film transistor 205;
  • the first thin film transistor 205 corresponding to each row of pixels 206 is connected to one of the n first gate lines 204, and the first thin film transistor 205 corresponding to each column of pixels 206 is connected to m the first data lines Two of 203; the first thin film transistors 205 corresponding to each column of pixels 206 are alternately connected to two adjacent first data lines 203.
  • the n first gate lines 204 and n the second gate lines, and the m first data lines 203 and the m second data lines are all insulated.
  • the first gate driver 201 is configured to send a gate signal to n of the first gate lines 204 to drive the n first gate lines 204; the first source driver 202 is configured to provide m first The data lines 203 send data signals to drive the m first data lines 203.
  • FIG. 3 it is a schematic structural diagram of a lower substrate of a display device provided by the present application.
  • the lower substrate 30 includes a second thin film transistor 305, and a second gate driver 301 and a second source driver 302 are disposed at edges of the lower substrate 30.
  • the second thin film transistor 305 corresponding to each row of pixels is connected to n
  • the second gate driver 301 is configured to send a gate signal to n of the second gate lines 304 to drive the n second gate lines 304; the second source driver 302 is configured to provide the m gates
  • the second data line 303 sends a data signal to drive m of the second data lines 303.
  • the present application does not limit the connection manner between the first data line and the first thin film transistor, and the second data line 303 and the second thin film transistor 305, which will not be repeated here.
  • the display device of the present application is provided with a gate driver and a source driver on both the upper and lower substrates to drive the gate and data lines of the upper and lower substrates at the same time, so that the frequency does not change.
  • this solution can make the display panel resistance The capacitive load is reduced, which solves the problem of insufficient charging of the high-resolution display panel, which can improve the display effect of the panel and help increase the panel penetration rate.

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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Abstract

本申请提供一种显示装置，包括：显示面板，所述显示面板包括对向设置的上基板与下基板；所述上基板与所述下基板上分别设置有相同数量的栅极线与数据线，且共同定义出多个像素；所述上基板的栅极驱动器与源极驱动器分别位于所述显示面板两端；所述下基板的栅极驱动器与源极驱动器分别位于所述显示面板的另外两端。

Description

一种显示装置 技术领域
本申请涉及液晶显示技术领域，尤其涉及一种显示装置。
 背景技术
随着显示面板技术的日益发展，越来越高的解析度（例如4K,2K;8K,4K;16K,8K）成为人们追求的技术目标，传统显示面板由上下两块玻璃组合而成，一般上板为CF（彩膜）基板，下板为TFT（阵列）基板。还有另一种显示面板结构，由上下两块玻璃组合而成，TFT 阵列结构（或其他像素驱动结构）分布于上下两个基板上，上基板与下基板中至少一者含有CF基板。
然而随着解析度的增高，面板的电容电阻负载（RC Loading）急剧增大，充电时间急剧降低（在频率不变的情况下，2K,1K充电时间为t的话，4K,2K的充电时间为t/2，8K,4K的充电时间为t/4, 16K,8K的充电时间为t/8），导致显示面板出现充电不足的问题，这些因素的叠加，严重的影响了显示面板的显示效果，以及显示面板的穿透率。
因此，有必要提供一种显示装置，以解决现有技术所存在的问题。
 技术问题
本申请提供一种显示装置，能够提高高分辨率显示面板的充电时间，能够改善显示面板的显示效果以及提升显示面板的穿透率。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种显示装置，所述显示装置包括：
显示面板，所述显示面板包括对向设置的上基板与下基板，以及位于所述上基板与所述下基板之间的液晶层，所述上基板与所述下基板中至少一者包含有彩膜色阻层；
所述上基板包括n条第一栅极线与m条第一数据线，所述下基板包括n条第二栅极线与m条第二数据线，共同定义出n行*m列之矩阵的多个像素，其中m和n为自然数；以及
至少一第一栅极驱动器，对应n条所述第一栅极线的一端设置于所述上基板上，用以驱动n条所述第一栅极线；
至少一第一源极驱动器，对应m条所述第一数据线的一端设置于所述上基板上，用以驱动m条所述第一数据线；
至少一第二栅极驱动器，对应n条所述第二栅极线的一端设置于所述下基板上，用以驱动n条所述第二栅极线；
至少一第二源极驱动器，对应m条所述第二数据线的一端设置于所述下基板上，用以驱动m条所述第二数据线；
其中，所述第一栅极驱动器、所述第一源极驱动器、所述第二栅极驱动器以及所述第二源极驱动器设置于所述显示面板的四周边缘，所述第一栅极驱动器以及所述第二栅极驱动器同时发出栅极信号用以在同一时刻驱动所述第一栅极线与对应的所述第二栅极线。
在本申请的显示装置中，所述第一栅极驱动器与所述第二栅极驱动器分别直接制备于所述上基板的非显示区域及所述下基板的非显示区域；或者，所述第一栅极驱动器与所述第二栅极驱动器分别通过导电胶绑定在所述上基板上以及所述下基板上。
在本申请的显示装置中，所述上基板还包括第一薄膜晶体管，所述下基板还包括第二薄膜晶体管；
每一行像素对应的所述第一薄膜晶体管连接n条所述第一栅极线中的一条，每一列像素对应的所述第一薄膜晶体管连接m条所述第一数据线中的一条或两条；以及
每一行像素对应的所述第二薄膜晶体管连接n条所述第二栅极线中的一条，每一列像素对应的所述第二薄膜晶体管连接m条所述第二数据线中的一条或两条。
在本申请的显示装置中，所述第一源极驱动器以及所述第二源极驱动器同时发出数据信号用以在同一时刻驱动所述第一数据线及对应的所述第二数据线。
在本申请的显示装置中，对应每一列像素的所述第一薄膜晶体管连接m条所述第一数据线中的两条，对应每一列像素的所述第二薄膜晶体管连接m条所述第二数据线中的两条。
在本申请的显示装置中，每一列像素对应的所述第一薄膜晶体管交错的连接于相邻两所述第一数据线上；每一列像素对应的所述第二薄膜晶体管交错的连接于相邻两所述第二数据线上。
在本申请的显示装置中，所述上基板与所述下基板不完全重叠设置，所述第一栅极驱动器以及所述第一源极驱动器分别对应设置于所述上基板的非重叠区域一端；所述第二栅极驱动器以及所述第二源极驱动器分别对应设置于所述下基板的非重叠区域一端。
在本申请的显示装置中，所述上基板与所述下基板的所述非重叠区域对应所述显示面板四周边缘的非显示区域。
在本申请的显示装置中，所述第一栅极驱动器以及所述第一源极驱动器设置于所述上基板面向所述下基板的一侧；所述第二栅极驱动器以及所述第二源极驱动器设置于所述下基板面向所述上基板的一侧。
为解决上述问题，本申请还提供一种显示装置，所述显示装置包括：
显示面板，所述显示面板包括对向设置的上基板与下基板，以及位于所述上基板与所述下基板之间的液晶层，所述上基板与所述下基板中至少一者包含有彩膜色阻层；
所述上基板包括n条第一栅极线与m条第一数据线，所述下基板包括n条第二栅极线与m条第二数据线，共同定义出n行*m列之矩阵的多个像素，其中m和n为自然数；以及
至少一第一栅极驱动器，对应n条所述第一栅极线的一端设置于所述上基板上，用以驱动n条所述第一栅极线；
至少一第一源极驱动器，对应m条所述第一数据线的一端设置于所述上基板上，用以驱动m条所述第一数据线；
至少一第二栅极驱动器，对应n条所述第二栅极线的一端设置于所述下基板上，用以驱动n条所述第二栅极线；
至少一第二源极驱动器，对应m条所述第二数据线的一端设置于所述下基板上，用以驱动m条所述第二数据线；
所述第一栅极驱动器与所述第二栅极驱动器的数量相同，所述第一源极驱动器的数量与所述第二源极驱动器的数量相同；
其中，所述第一栅极驱动器、所述第一源极驱动器、所述第二栅极驱动器以及所述第二源极驱动器设置于所述显示面板的四周边缘，所述第一栅极驱动器以及所述第二栅极驱动器同时发出栅极信号用以在同一时刻驱动所述第一栅极线与对应的所述第二栅极线。
在本申请的显示装置中，所述第一栅极驱动器与所述第二栅极驱动器分别直接制备于所述上基板的非显示区域及所述下基板的非显示区域；或者，所述第一栅极驱动器与所述第二栅极驱动器分别通过导电胶绑定在所述上基板上以及所述下基板上。
在本申请的显示装置中，所述上基板还包括第一薄膜晶体管，所述下基板还包括第二薄膜晶体管；
每一行像素对应的所述第一薄膜晶体管连接n条所述第一栅极线中的一条，每一列像素对应的所述第一薄膜晶体管连接m条所述第一数据线中的一条或两条；以及
每一行像素对应的所述第二薄膜晶体管连接n条所述第二栅极线中的一条，每一列像素对应的所述第二薄膜晶体管连接m条所述第二数据线中的一条或两条。
在本申请的显示装置中，所述第一源极驱动器以及所述第二源极驱动器同时发出数据信号用以在同一时刻驱动所述第一数据线及对应的所述第二数据线。
在本申请的显示装置中，对应每一列像素的所述第一薄膜晶体管连接m条所述第一数据线中的两条，对应每一列像素的所述第二薄膜晶体管连接m条所述第二数据线中的两条。
在本申请的显示装置中，每一列像素对应的所述第一薄膜晶体管交错的连接于相邻两所述第一数据线上；每一列像素对应的所述第二薄膜晶体管交错的连接于相邻两所述第二数据线上。
在本申请的显示装置中，所述上基板与所述下基板不完全重叠设置，所述第一栅极驱动器以及所述第一源极驱动器分别对应设置于所述上基板的非重叠区域一端；所述第二栅极驱动器以及所述第二源极驱动器分别对应设置于所述下基板的非重叠区域一端。
在本申请的显示装置中，所述上基板与所述下基板的所述非重叠区域对应所述显示面板四周边缘的非显示区域。
在本申请的显示装置中，所述第一栅极驱动器以及所述第一源极驱动器设置于所述上基板面向所述下基板的一侧；所述第二栅极驱动器以及所述第二源极驱动器设置于所述下基板面向所述上基板的一侧。
 有益效果
本申请的有益效果为：相较于现有的显示装置，本申请的显示装置通过在上下基板上都设置栅极驱动器及源极驱动器，用以同时驱动上下基板的栅极线与数据线，使得在频率不变的情况下，在同一时刻可以有两条栅极线在工作，使显示面板充电时间加倍；比如，采用了本专利揭露的方案，解析度为4K,2K的显示面板的充电时间为t，解析度为8K,4K的显示面板的充电时间为t/2, 解析度为16K,8K的显示面板的充电时间为t/4；相比相同解析度下的传统的显示面板，本方案可以使显示面板电阻电容负载降低，解决高分辨率显示面板充电不足的问题，可以改善面板的显示效果，并有利于提升面板穿透率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a为本申请提供的显示装置的俯视结构示意图；
图1b为本申请提供的显示装置的剖面示意图；
图2为本申请提供的显示装置的上基板结构示意图；
图3为本申请提供的显示装置的下基板结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请针对现有技术的高解析度显示面板的电阻电容负载增大，充电时间急剧降低，从而影响显示面板的显示效果以及穿透率的技术问题，本实施例能够解决该缺陷。
如图1a所示，为本申请提供的显示装置的俯视结构示意图。显示装置包括：显示面板，所述显示面板包括对向设置的上基板101与下基板102，以及位于所述上基板101与所述下基板102之间的液晶层（未标示），所述显示面板的TFT 阵列结构（或其他像素驱动结构）分别分布于所述上基板101与所述下基板102上，所述显示面板的结构可以为：（所述上基板101：（CF+ TFT）基板，所述下基板102：TFT基板），或者：（所述上基板101：TFT基板，所述下基板102：（CF+ TFT）基板），或者：（所述上基板101：（CF+ TFT）基板，所述下基板102：（CF+ TFT）基板）。即本申请的所述上基板101与所述下基板102均兼具TFT即阵列基板功能，所述上基板101的显示区域包括n条第一栅极线与m条第一数据线，所述下基板102的显示区域包括n条第二栅极线与m条第二数据线，共同定义出n行*m列之矩阵的多个像素，其中m和n为自然数。n条所述第一栅极线与n条所述第二栅极线，以及m条所述第一数据线与m条所述第二数据线均绝缘设置。
所述显示装置还包括：至少一个第一栅极驱动器103，设置于所述上基板101的右侧边缘，用以驱动n条所述第一栅极线；至少一个第一源极驱动器104，设置于所述上基板101的上侧边缘，用以驱动m条所述第一数据线；至少一个第二栅极驱动器105，设置于所述下基板102的左侧边缘，用以驱动n条所述第二栅极线；至少一个第二源极驱动器106，设置于所述下基板102的下侧边缘，用以驱动m条所述第二数据线。其中，所述第一栅极驱动器103与所述第二栅极驱动器105分别位于所述显示面板的两端，所述第一源极驱动器104与所述第二源极驱动器106分别位于所述显示面板的另外两端，其中，所述第一栅极驱动器103以及所述第二栅极驱动器105同时发出栅极信号用以在同一时刻驱动所述第一栅极线与对应的所述第二栅极线，从而使所述显示面板的充电时间加倍。可以理解的是，所述第一源极驱动器104以及所述第二源极驱动器106同时发出数据信号用以在同一时刻驱动所述第一数据线与对应的所述第二数据线。
所述上基板101与所述下基板102不完全重叠设置，所述上基板101与所述下基板102的非重叠区域对应所述显示面板四周边缘的非显示区域，所述第一栅极驱动器103以及所述第一源极驱动器104分别对应设置于所述上基板101的非重叠区域一端；所述第二栅极驱动器105以及所述第二源极驱动器106分别对应设置于所述下基板102的非重叠区域一端。所述第一栅极驱动器103以及所述第一源极驱动器104设置于所述上基板101面向所述下基板102的一侧；所述第二栅极驱动器105以及所述第二源极驱动器106设置于所述下基板102面向所述上基板101的一侧。
如图1b所示，为本申请提供的显示装置的剖面示意图。所述上基板101与所述下基板102不完全重叠设置。在两基板的非重叠区域，所述第一栅极驱动器103邦定于所述上基板101的一端，所述第二栅极驱动器105邦定于所述下基板102的一端。所述第一源极驱动器104与所述第二源极驱动器106也是相似设置，此处不再赘述。其中，所述第一栅极驱动器103与所述第二栅极驱动器105可分别直接制备于所述上基板101的非显示区域及所述下基板102的非显示区域，如GOA电路；或者，所述第一栅极驱动器103与所述第二栅极驱动器105分别通过导电胶绑定在所述上基板101上以及所述下基板102上，如COF(chip on film)。优选的，所述第一栅极驱动器103与所述第二栅极驱动器105的数量相同，所述第一源极驱动器104的数量与所述第二源极驱动器106的数量相同。
如图2所示，为本申请提供的显示装置的上基板结构示意图。上基板20包括：彩膜色阻层（未标示）以及第一薄膜晶体管205；
每一行像素206对应的所述第一薄膜晶体管205连接n条所述第一栅极线204中的一条，每一列像素206对应的所述第一薄膜晶体管205连接m条所述第一数据线203中的两条；每一列像素206对应的所述第一薄膜晶体管205交错的连接于相邻两所述第一数据线203上。n条所述第一栅极线204与n条所述第二栅极线，以及m条所述第一数据线203与m条所述第二数据线均绝缘设置。第一栅极驱动器201用于向n条所述第一栅极线204发出栅极信号驱动n条所述第一栅极线204；第一源极驱动器202用于向m条所述第一数据线203发出数据信号驱动m条所述第一数据线203。
如图3所示，为本申请提供的显示装置的下基板结构示意图。下基板30包括第二薄膜晶体管305，所述下基板30的边缘处设置有第二栅极驱动器301以及第二源极驱动器302；每一行像素对应的所述第二薄膜晶体管305连接n条所述第二栅极线304中的一条，每一列像素对应的所述第二薄膜晶体管305连接m条所述第二数据线303中的两条；每一列像素对应的所述第二薄膜晶体管305交错的连接于相邻两所述第二数据线303上。所述第二栅极驱动器301用于向n条所述第二栅极线304发出栅极信号驱动n条所述第二栅极线304；第二源极驱动器302用于向m条所述第二数据线303发出数据信号驱动m条所述第二数据线303。其中，本申请对所述第一数据线与所述第一薄膜晶体管，以及所述第二数据线303与所述第二薄膜晶体管305的连接方式不做限制，此处不再赘述。
相较于现有的显示装置，本申请的显示装置通过在上下基板上都设置栅极驱动器及源极驱动器，用以同时驱动上下基板的栅极线与数据线，使得在频率不变的情况下，在同一时刻可以有两条栅极线在工作，使显示面板充电时间加倍；比如，采用了本专利揭露的方案，解析度为4K,2K的显示面板的充电时间为t，解析度为8K,4K的显示面板的充电时间为t/2, 解析度为16K,8K的显示面板的充电时间为t/4；相比相同解析度下的传统的显示面板，本方案可以使显示面板电阻电容负载降低，解决高分辨率显示面板充电不足的问题，可以改善面板的显示效果，并有利于提升面板穿透率。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种显示装置，其包括：
    显示面板，所述显示面板包括对向设置的上基板与下基板，以及位于所述上基板与所述下基板之间的液晶层，所述上基板与所述下基板中至少一者包含有彩膜色阻层；
    所述上基板包括n条第一栅极线与m条第一数据线，所述下基板包括n条第二栅极线与m条第二数据线，共同定义出n行*m列之矩阵的多个像素，其中m和n为自然数；以及
    至少一第一栅极驱动器，对应n条所述第一栅极线的一端设置于所述上基板上，用以驱动n条所述第一栅极线；
    至少一第一源极驱动器，对应m条所述第一数据线的一端设置于所述上基板上，用以驱动m条所述第一数据线；
    至少一第二栅极驱动器，对应n条所述第二栅极线的一端设置于所述下基板上，用以驱动n条所述第二栅极线；
    至少一第二源极驱动器，对应m条所述第二数据线的一端设置于所述下基板上，用以驱动m条所述第二数据线；
    其中，所述第一栅极驱动器、所述第一源极驱动器、所述第二栅极驱动器以及所述第二源极驱动器设置于所述显示面板的四周边缘，所述第一栅极驱动器以及所述第二栅极驱动器同时发出栅极信号用以在同一时刻驱动所述第一栅极线与对应的所述第二栅极线。
  2. 根据权利要求1所述的显示装置，其中，所述第一栅极驱动器与所述第二栅极驱动器分别直接制备于所述上基板的非显示区域及所述下基板的非显示区域；或者，所述第一栅极驱动器与所述第二栅极驱动器分别通过导电胶绑定在所述上基板上以及所述下基板上。
  3. 根据权利要求1所述的显示装置，其中，所述上基板还包括第一薄膜晶体管，所述下基板还包括第二薄膜晶体管；
    每一行像素对应的所述第一薄膜晶体管连接n条所述第一栅极线中的一条，每一列像素对应的所述第一薄膜晶体管连接m条所述第一数据线中的一条或两条；以及
    每一行像素对应的所述第二薄膜晶体管连接n条所述第二栅极线中的一条，每一列像素对应的所述第二薄膜晶体管连接m条所述第二数据线中的一条或两条。
  4. 根据权利要求3所述的显示装置，其中，所述第一源极驱动器以及所述第二源极驱动器同时发出数据信号用以在同一时刻驱动所述第一数据线及对应的所述第二数据线。
  5. 根据权利要求3所述的显示装置，其中，对应每一列像素的所述第一薄膜晶体管连接m条所述第一数据线中的两条， 对应每一列像素的所述第二薄膜晶体管连接m条所述第二数据线中的两条。
  6. 根据权利要求5所述的显示装置，其中，每一列像素对应的所述第一薄膜晶体管交错的连接于相邻两所述第一数据线上；每一列像素对应的所述第二薄膜晶体管交错的连接于相邻两所述第二数据线上。
  7. 根据权利要求1所述的显示装置，其中，所述上基板与所述下基板不完全重叠设置，所述第一栅极驱动器以及所述第一源极驱动器分别对应设置于所述上基板的非重叠区域一端；所述第二栅极驱动器以及所述第二源极驱动器分别对应设置于所述下基板的非重叠区域一端。
  8. 根据权利要求7所述的显示装置，其中，所述上基板与所述下基板的所述非重叠区域对应所述显示面板四周边缘的非显示区域。
  9. 根据权利要求1所述的显示装置，其中，所述第一栅极驱动器以及所述第一源极驱动器设置于所述上基板面向所述下基板的一侧；所述第二栅极驱动器以及所述第二源极驱动器设置于所述下基板面向所述上基板的一侧。
  10. 一种显示装置，其中，所述显示装置包括：
    显示面板，所述显示面板包括对向设置的上基板与下基板，以及位于所述上基板与所述下基板之间的液晶层，所述上基板与所述下基板中至少一者包含有彩膜色阻层；
    所述上基板包括n条第一栅极线与m条第一数据线，所述下基板包括n条第二栅极线与m条第二数据线，共同定义出n行*m列之矩阵的多个像素，其中m和n为自然数；以及
    至少一第一栅极驱动器，对应n条所述第一栅极线的一端设置于所述上基板上，用以驱动n条所述第一栅极线；
    至少一第一源极驱动器，对应m条所述第一数据线的一端设置于所述上基板上，用以驱动m条所述第一数据线；
    至少一第二栅极驱动器，对应n条所述第二栅极线的一端设置于所述下基板上，用以驱动n条所述第二栅极线；
    至少一第二源极驱动器，对应m条所述第二数据线的一端设置于所述下基板上，用以驱动m条所述第二数据线；
    所述第一栅极驱动器与所述第二栅极驱动器的数量相同，所述第一源极驱动器的数量与所述第二源极驱动器的数量相同；
    其中，所述第一栅极驱动器、所述第一源极驱动器、所述第二栅极驱动器以及所述第二源极驱动器设置于所述显示面板的四周边缘，所述第一栅极驱动器以及所述第二栅极驱动器同时发出栅极信号用以在同一时刻驱动所述第一栅极线与对应的所述第二栅极线。
  11. 根据权利要求10所述的显示装置，其中，所述第一栅极驱动器与所述第二栅极驱动器分别直接制备于所述上基板的非显示区域及所述下基板的非显示区域；或者，所述第一栅极驱动器与所述第二栅极驱动器分别通过导电胶绑定在所述上基板上以及所述下基板上。
  12. 根据权利要求10所述的显示装置，其中，所述上基板还包括第一薄膜晶体管，所述下基板还包括第二薄膜晶体管；
    每一行像素对应的所述第一薄膜晶体管连接n条所述第一栅极线中的一条，每一列像素对应的所述第一薄膜晶体管连接m条所述第一数据线中的一条或两条；以及
    每一行像素对应的所述第二薄膜晶体管连接n条所述第二栅极线中的一条，每一列像素对应的所述第二薄膜晶体管连接m条所述第二数据线中的一条或两条。
  13. 根据权利要求12所述的显示装置，其中，所述第一源极驱动器以及所述第二源极驱动器同时发出数据信号用以在同一时刻驱动所述第一数据线及对应的所述第二数据线。
  14. 根据权利要求12所述的显示装置，其中，对应每一列像素的所述第一薄膜晶体管连接m条所述第一数据线中的两条， 对应每一列像素的所述第二薄膜晶体管连接m条所述第二数据线中的两条。
  15. 根据权利要求14所述的显示装置，其中，每一列像素对应的所述第一薄膜晶体管交错的连接于相邻两所述第一数据线上；每一列像素对应的所述第二薄膜晶体管交错的连接于相邻两所述第二数据线上。
  16. 根据权利要求10所述的显示装置，其中，所述上基板与所述下基板不完全重叠设置，所述第一栅极驱动器以及所述第一源极驱动器分别对应设置于所述上基板的非重叠区域一端；所述第二栅极驱动器以及所述第二源极驱动器分别对应设置于所述下基板的非重叠区域一端。
  17. 根据权利要求16所述的显示装置，其中，所述上基板与所述下基板的所述非重叠区域对应所述显示面板四周边缘的非显示区域。
  18. 根据权利要求10所述的显示装置，其中，所述第一栅极驱动器以及所述第一源极驱动器设置于所述上基板面向所述下基板的一侧；所述第二栅极驱动器以及所述第二源极驱动器设置于所述下基板面向所述上基板的一侧。
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