WO2019223567A1 - 显示基板、显示装置以及显示基板的制作方法 - Google Patents

显示基板、显示装置以及显示基板的制作方法 Download PDF

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WO2019223567A1
WO2019223567A1 PCT/CN2019/086683 CN2019086683W WO2019223567A1 WO 2019223567 A1 WO2019223567 A1 WO 2019223567A1 CN 2019086683 W CN2019086683 W CN 2019086683W WO 2019223567 A1 WO2019223567 A1 WO 2019223567A1
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layer
substrate
insulating layer
film transistor
thin film
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PCT/CN2019/086683
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English (en)
French (fr)
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康昭
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京东方科技集团股份有限公司
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Priority to US16/647,940 priority Critical patent/US11575067B2/en
Publication of WO2019223567A1 publication Critical patent/WO2019223567A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0054—Processes for devices with an active region comprising only group IV elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/34—Materials of the light emitting region containing only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
    • H01L33/502—Wavelength conversion materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0041—Processes relating to semiconductor body packages relating to wavelength conversion elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/507—Wavelength conversion elements the elements being in intimate contact with parts other than the semiconductor body or integrated with parts other than the semiconductor body

Definitions

  • the present disclosure relates to a display substrate, a display device, and a method for manufacturing a display substrate.
  • Micro-LED Micro Light-Emitting Diode
  • Micro-LED Micro Light-Emitting Diode
  • CMOS complementary metal-oxide-semiconductor
  • Micro-LED Micro Light-Emitting Diode
  • each pixel of an LED display can be addressed and individually driven to light. It can be regarded as a miniature version of an outdoor LED display. Level down to the micron level.
  • Micro-LED inherits the characteristics of high efficiency, high brightness, high reliability and fast response time of inorganic LED. It has the characteristics of self-luminous and no backlight, more energy-saving, simple structure and small size. , Thin and other advantages. In addition, because Micro LEDs are extremely small, they display ultra-high resolution.
  • Micro-LED colors are easier to accurately debug, have longer luminous life and higher brightness, and have better material stability, long life, no image Branding and other advantages. Therefore, it is another thin, light and power-saving display technology after OLED.
  • At least one embodiment of the present disclosure provides a method for manufacturing a display substrate, including: sequentially forming a light emitting diode on a first substrate and a first metal layer covering the light emitting diode; and sequentially forming an active material layer on the second substrate. And a second metal layer; combining the first metal layer on the first substrate and the second metal layer on the second substrate face to face; peeling off the second substrate; the first metal layer Patterning with the second metal layer to form a connection metal pattern electrically connected to a top electrode of the light emitting diode; and forming a thin film transistor on the first substrate, wherein an active layer of the thin film transistor is Formed by patterning the active material layer, a drain of the thin film transistor is electrically connected to the connection metal pattern.
  • forming the light emitting diode on the first substrate includes epitaxially growing a light emitting layer on the first substrate.
  • the light emitting layer includes an inorganic semiconductor material.
  • an area of the connection metal pattern is smaller than an area of a top electrode of the light emitting diode.
  • forming the thin film transistor on the first substrate includes: patterning the active material layer to form the active layer; forming a gate insulating layer on the active layer; and Forming a gate on the gate insulating layer; forming an interlayer insulating layer on the gate; forming a first transition layer connected to the active layer in the gate insulating layer and the interlayer insulating layer A hole, a second via, and a third via connected to the connection metal pattern; a source and a drain are formed on the interlayer insulating layer, and the source is connected to the source through the first via and In the active layer connection, the drain is connected to the active layer through the second via and is connected to the connection pattern through the third via.
  • forming a thin film transistor on the first substrate includes: patterning an active material layer to form the active layer; forming a drain connected to the active layer and the connection metal pattern; A gate insulating layer is formed on the drain; a gate is formed on the gate insulating layer; an interlayer insulating layer is formed on the gate; the gate insulating layer and the interlayer insulating layer are formed on the gate; Forming a first via hole connected to the active layer; and forming a source electrode on the interlayer insulating layer, the source electrode being connected to the active layer through the first via hole.
  • the manufacturing method further includes forming a buffer layer on the second substrate between the active material layer and the second metal layer, wherein the buffer layer and the active layer The material layer is simultaneously patterned to form a buffer layer pattern, and the active layer is insulated from the connection metal pattern through the buffer layer pattern.
  • the manufacturing method further includes: forming a first planarization layer on the thin film transistor; and forming a light conversion layer on the first planarization layer.
  • the light conversion layer includes a white fluorescent layer and a filter layer sequentially disposed on the first flat layer, and the filter layer includes a plurality of color photoresists with different colors.
  • the light conversion layer includes a quantum dot structure layer
  • the quantum dot material structure layer includes a plurality of colored light regions provided with quantum dot materials of different colors.
  • the manufacturing method further includes forming a second planarization layer on the light conversion layer.
  • At least one embodiment of the present disclosure provides a display substrate including a substrate and a plurality of pixel units disposed on the substrate, wherein at least one of the plurality of pixel units includes sequentially disposed along a direction away from the substrate.
  • the electrode is conductively connected to the connection metal pattern.
  • the thin film transistor is a low temperature polysilicon thin film transistor.
  • the low-temperature polysilicon thin film transistor includes: a low-temperature polysilicon active layer, a gate insulating layer, a gate, an interlayer insulating layer, a source, and a drain, which are sequentially disposed along a direction away from the connection metal pattern, wherein The source is connected to the low-temperature polysilicon active layer through the gate insulating layer and a first via in the interlayer insulating layer; the drain is connected through the gate insulating layer and the layer A second via in the interlayer insulation layer is connected to the low-temperature polysilicon active layer, and the drain is connected to the connection metal pattern through the gate insulating layer and a third via in the interlayer insulation layer. Electrical connection.
  • the low-temperature polysilicon thin film transistor includes: a low-temperature polysilicon active layer, a gate insulating layer, a drain, a gate, an interlayer insulating layer, and a source, which are sequentially disposed along a direction away from the connection metal pattern, where The source is connected to the low-temperature polysilicon active layer through the gate insulating layer and a first via in the interlayer insulating layer; the drain is disposed away from the low-temperature polysilicon active layer One side of the connection metal pattern is electrically connected to the connection metal pattern.
  • the display substrate further includes: a first planarization layer and a light conversion layer sequentially disposed along a direction away from the thin film transistor.
  • the light conversion layer includes a white fluorescent layer and a filter layer sequentially disposed on the first flat layer, and the filter layer includes a plurality of color photoresists with different colors.
  • the light conversion layer includes a quantum dot structure layer
  • the quantum dot material structure layer includes a plurality of colored light regions provided with quantum dot materials of different colors.
  • the light emitting diode is a blue light emitting diode.
  • At least one embodiment of the present disclosure provides a display device including the display substrate according to any one of the above.
  • FIG. 1 is a schematic structural diagram of a light emitting diode according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • 15 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the present disclosure.
  • the micro-LED device requires an epitaxial layer during fabrication, the epitaxial layer is relatively high and can only be fabricated on a silicon wafer or sapphire. It is difficult to directly fabricate an LED on a thin film transistor control circuit. Most of the current Micro-LED devices are separately manufactured LED and thin film transistor control circuits and then aligned and bonded. Since the registration and bonding will lose a certain degree of accuracy, it is not conducive to the production of high-resolution panels.
  • the embodiments of the present disclosure provide a display substrate, a display device, and a manufacturing method of the display substrate.
  • a display substrate provided by an embodiment of the present disclosure includes: a substrate 1 and a plurality of pixel units arranged on the substrate 1 in an array.
  • the pixel unit includes a light emitting diode 2, a connection metal 3, and a thin film transistor 5 which are sequentially disposed in a direction away from the substrate 1.
  • the connection metal 3 is conductively connected to the top electrode 4 of the light-emitting diode 2.
  • the active layer 6 of the thin film transistor 5 is insulated from the connection metal 3, and the drain electrode 7 of the thin film transistor 5 is electrically connected to the connection metal 3.
  • the light emitting diode 2 is a micro light emitting diode.
  • the substrate of the thin-film transistor 5 of the display substrate is manufactured, the substrate of the thin-film transistor 5 that has not been patterned with the active layer and the light-emitting diode 2 substrate are directly pasted. Then, the thin film transistor 5 is fabricated on the light emitting diode 2. Since the connection metal 3 is conductively connected to the top electrode 4 of the light emitting diode 2 and the drain electrode 7 of the thin film transistor 5 is conductively connected to the connection metal 3, the drain electrode 7 of the thin film transistor 5 is conductively connected to the top electrode 4 of the light emitting diode 2.
  • the manufactured light-emitting diode 2 does not need to be aligned and bonded to the thin-film transistor 5. In this way, the loss of alignment accuracy can be avoided, so that the size of the light-emitting diode 2 can be made smaller to produce a super-high-resolution display device.
  • the specific type of the thin film transistor 5 is not limited, and may be, for example, a low temperature polysilicon thin film transistor.
  • the low-temperature polysilicon thin film transistor includes a first buffer layer 8, a low-temperature polysilicon active layer 9, a second buffer layer 10, a gate insulating layer 11, and a gate 12 (see FIG. 6), an interlayer insulating layer 13, a source electrode 14 and a drain electrode 7.
  • the source electrode 14 is connected to the low-temperature polysilicon active layer 9 through the gate insulating layer 11 and the first via 15 (see FIG. 6) on the interlayer insulating layer 13; the drain electrode 7 is insulated through the gate insulating layer 11 and interlayer insulation
  • the second via 16 on the layer 13 is connected to the low-temperature polysilicon active layer 9, and the drain 7 is electrically connected to the connection metal 3 through the gate insulating layer 11 and the third via 17 on the interlayer insulating layer 13.
  • the low temperature polysilicon thin film transistor includes a first buffer layer 8, a low temperature polysilicon active layer 9, a gate insulating layer 11, and Drain 7, gate 12, interlayer insulating layer 13, and source 14.
  • the source electrode 14 is connected to the low-temperature polysilicon active layer 9 through the gate insulating layer 11 and the first via hole 15 on the interlayer insulating layer 13; Side and is conductively connected to the connection metal 3.
  • This arrangement can prevent via holes for connecting the drain electrode 7 and the low-temperature polysilicon active layer 9 on the gate insulating layer 11 and the interlayer insulating layer 13 and via holes for connecting the drain electrode 7 to the connection metal 3, thereby It can reduce the difficulty of substrate manufacturing process and improve product yield.
  • the display substrate further includes a first planarization layer 18, a white fluorescent layer 19, a filter layer 20, and a second planarization layer which are sequentially disposed along a direction away from the thin film transistor 5.
  • the planarization layer 23 and the filter layer 20 include a color photoresistor 21 corresponding to each pixel unit and a black matrix 22 defining an adjacent color photoresistor 21.
  • the light emitting diode 2 is a miniature blue light emitting diode
  • the display substrate further includes a first planarization layer 18 and a quantum dot material, which are sequentially disposed along a direction away from the thin film transistor 5.
  • the quantum dot material structure layer includes a first color light region 30, a second color light region 31, and a third color light region 32 corresponding to each pixel unit, and defines adjacent first color light regions 30 and second color light regions 31.
  • the black matrix 22 of the third color light region 32 The first colored light area 30 is provided with a green light quantum dot material structure layer, and the second colored light area 31 is provided with a red light quantum dot material structure layer.
  • the white fluorescent layer, the filter layer, and the quantum dot material layer described above are examples of the light conversion layer.
  • the light conversion layer can convert the monochromatic light emitted by the monochromatic diode into light of other colors or into light of different colors.
  • an embodiment of the present disclosure further provides a display device including a display substrate as in any one of the foregoing.
  • the size of the light emitting diode of the display device of the present technical solution can be made smaller, and the product yield and the resolution of the display device can be made higher.
  • an embodiment of the present disclosure further provides a method for manufacturing a display substrate, which includes the following steps 001-006.
  • Step 001 As shown in FIG. 1, a light emitting diode 2 and a first metal layer 25 covering the light emitting diode 2 are sequentially formed on the first substrate 24.
  • Step 002 As shown in FIG. 2, an active material layer and a second metal layer 27 of a thin film transistor are sequentially formed on the second substrate 26.
  • the example of the active material layer here may be the low-temperature polysilicon active layer 9 described above.
  • the first buffer layer 8 and the second buffer layer 10 may be formed on both sides of the active material layer.
  • the first buffer layer 8 and the second buffer layer 10 are insulating materials, and the first buffer layer 8 can prevent the active material layer from being connected to the second metal layer 27.
  • Step 003 As shown in FIG. 3, the first metal layer 25 on the first substrate 24 and the second metal layer 27 on the second substrate 26 face each other and are bonded together. For example, in this step, the first metal layer 25 and the second metal layer 27 are bonded to face each other.
  • Step 004 As shown in FIGS. 4 and 8, the second substrate 26 is peeled.
  • the second substrate 26 is peeled in this step.
  • the method of peeling the second substrate 26 is not particularly limited.
  • a sacrificial layer may be formed between the second substrate 26 and the active material layer.
  • the sacrificial layer may be decomposed or melted by means such as laser irradiation or heating, so that the second substrate can be peeled off. .
  • Step 005 Etching the first metal layer 25 and the second metal layer 27 bonded together to form a pattern of the connection metal 3 which is conductively connected to the top electrode 4 of the light emitting diode 2, and its structure is shown in FIG. 5 and FIG. Show.
  • Step 006 A thin film transistor 5 is formed on the first substrate 24 that has completed the above steps.
  • the drain electrode 7 of the thin film transistor 5 is electrically connected to the connection metal 3, as shown in FIGS. 6, 7, 10, and 11.
  • the active layer of the thin film transistor 5 may be formed by patterning an active material layer.
  • forming a light emitting diode on the first substrate includes epitaxially growing a light emitting layer on the first substrate.
  • the light emitting layer material includes an inorganic semiconductor material.
  • a step of growing an n-type contact layer, a p-type contact layer, and a buffer layer may be further included.
  • a process of forming an n-side electrode and a p-side electrode may be included.
  • one of the n-side electrode and the p-side electrode may be a top electrode of the above-mentioned light emitting diode.
  • the area of the connection metal 3 can be smaller than the area of the top electrode 4 of the light emitting diode. In this way, after the connection metal 3 is formed on the top electrode 4, it can avoid completely blocking the top electrode and affecting the light emitting diode's light .
  • the area of the connection metal 3 is smaller than 1/4 of the area of the top electrode 4.
  • the area of the connection metal 3 can be set as small as possible under the condition that the electrical transmission performance is satisfied.
  • the light emitting diode 2 and the first metal layer 25 covering the light emitting diode 2 are firstly fabricated on the first substrate 24, and then the thin film is fabricated on the second substrate 26.
  • the active material layer and the second metal layer 27 of the transistor 5 are then bonded to each other. Since the two metal layers are made on the entire substrate on the entire surface, it is less difficult to align the two metal layers when they are bonded, so the alignment accuracy requirements are lower.
  • the display substrate is manufactured by the method of the present technical solution, it is not necessary to align the manufactured light-emitting diode 2 and the thin-film transistor 5 in the process of manufacturing the display device, so that the light-emitting diode 2 and the thin-film transistor 5 can be avoided.
  • the alignment requires a smaller size of the light-emitting diode 2, thereby improving the product yield of the display substrate and the resolution of the display device.
  • the thin film transistor 5 is a low temperature polysilicon thin film transistor, and forming and forming the thin film transistor 5 on the first substrate 24 includes, for example, etching and forming an active material layer.
  • Metal 3 insulated active layer 6 see FIG.
  • a gate insulating layer 11 is formed on the active layer 6; a gate 12 pattern is formed on the gate insulating layer 11; a layer is formed on the gate 12 pattern Inter-insulating layer 13; forming a first via 15 for conducting connection between source 14 and active layer 6 on gate insulating layer 11 and inter-layer insulating layer 13; gate insulating layer 11 and inter-layer insulating layer 13 A second via 16 for conductively connecting the drain 7 to the active layer 6 is formed thereon, and a third via 17 for conductively connecting the drain 7 to the connection metal 3 is formed; a source is formed on the interlayer insulating layer 13 Pole 14 pattern and drain 7 pattern.
  • the thin film transistor is a low-temperature polysilicon thin film transistor
  • forming the thin film transistor on the first substrate 24 includes, for example, etching an active material layer to Active layer 6 connected to metal 3 insulation gap; pattern of drain electrode 7 connected to active layer 6 and connection metal 3; gate insulating layer 11 formed on drain electrode 7; gate formed on gate insulating layer 11 12 pattern; forming an interlayer insulating layer 13 on the gate 12 pattern; forming a first via 15 for conducting connection between the source electrode 14 and the active layer 6 on the gate insulating layer 11 and the interlayer insulating layer 13; A source electrode 14 pattern is formed on the interlayer insulating layer 13.
  • the method further includes: forming a first planarization layer 18 on the interlayer insulating layer 13; forming on the first planarization layer 18 White fluorescent layer 19; a filter layer 20 is formed on the white fluorescent layer 19, and the filter layer 20 includes a color photoresistor 21 corresponding to each pixel unit and a black matrix 22 defining an adjacent color photoresistor 21; A second planarization layer 23 is formed thereon.
  • the light emitting diode 2 is a blue light emitting diode
  • the method further includes: forming a first planarization layer 18 on the interlayer insulating layer 13; A quantum dot material structure layer 29 is formed on the first planarization layer 18.
  • the quantum dot material structure layer 29 includes a first color light area 30, a second color light area 31, and a third color light area 32 corresponding to each pixel unit.
  • the display device may be a VR device, an AR device, a mobile phone, a notebook computer, an e-book, or a tablet computer.

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Abstract

本公开提供一种显示基板、显示装置以及显示基板的制作方法。一种显示基板，包括：基板以及设置于所述基板上的呈阵列排布的多个像素单元，其中：所述像素单元包括沿远离所述基板方向依次设置的发光二极管、连接金属图案以及薄膜晶体管；所述连接金属图案与所述发光二极管的顶电极导电连接；所述薄膜晶体管的有源层与所述连接金属图案绝缘间隔，所述薄膜晶体管的漏极与所述连接金属图案导电连接。本公开的显示基板可以提高显示基板的产品良率，以及显示装置的分辨率。

Description

显示基板、显示装置以及显示基板的制作方法
本申请要求于2018年5月24日递交的中国专利申请第201810510492.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及一种显示基板、显示装置以及显示基板的制作方法。
背景技术
Micro-LED(Micro Light-Emitting Diode，微型发光二极管)技术，即发光二极管微缩化和矩阵化技术。指的是在一个芯片上集成的高密度微小尺寸的LED阵列，如LED显示屏每一个像素可定址、单独驱动点亮，可看成是户外LED显示屏的微缩版，将像素点距离从毫米级降低至微米级。
Micro-LED优点表现的很明显，它继承了无机LED的高效率、高亮度、高可靠度及反应时间快等特点，并且具自发光无需背光源的特性，更具节能、结构简易、体积小、薄型等优势。除此之外，由于Micro LED超微小，因此其表现出超高的解析度。
而相比OLED(Organic Light Emitting Diode，有机发光二极管)，Micro-LED色彩更容易准确的调试，有更长的发光寿命和更高的亮度以及具有较佳的材料稳定性、寿命长、无影像烙印等优点。故为继OLED之后另一具轻薄及省电优势的显示技术。
发明内容
本公开的至少一个实施例提供一种显示基板的制作方法，包括：在第一基板之上依次形成发光二极管和覆盖发光二极管的第一金属层；在第二基板之上依次形成有源材料层和第二金属层；将所述第一基板上的第一金属层与所述第二基板上的第二金属层相面对结合；将所述第二基板剥离；对所述第一金属层和所述第二金属层进行图案化，以形成与所述发光二极管的顶电极 电连接的连接金属图案；以及在所述第一基板上形成薄膜晶体管，其中所述薄膜晶体管的有源层是通过图案化所述有源材料层而形成，所述薄膜晶体管的漏极与所述连接金属图案电连接。
在一些示例中，在所述第一基板上形成所述发光二极管包括在所述第一基板上外延生长发光层。
在一些示例中，所述发光层包括无机半导体材料。
在一些示例中，所述连接金属图案的面积小于所述发光二极管的顶电极的面积。
在一些示例中，在所述第一基板上形成所述薄膜晶体管包括：将所述有源材料层图案化以形成所述有源层；在所述有源层上形成栅极绝缘层；在所述栅极绝缘层上形成栅极；在所述栅极上形成层间绝缘层；在所述栅极绝缘层以及所述层间绝缘层中形成与所述有源层连接的第一过孔和第二过孔以及与所述连接金属图案连接的第三过孔；在所述层间绝缘层上形成源极和所述漏极，所述源极通过所述第一过孔与所述有源层连接，所述漏极通过所述第二过孔与所述有源层连接且通过所述第三过孔与所述连接图案连接。
在一些示例中，在所述第一基板上形成薄膜晶体管包括：将有源材料层图案化以形成所述有源层；形成与所述有源层以及所述连接金属图案连接的漏极；在所述漏极上形成栅极绝缘层；在所述栅极绝缘层上形成栅极；在所述栅极上形成层间绝缘层；在所述栅极绝缘层以及所述层间绝缘层中形成与所述有源层连接的第一过孔；以及在所述层间绝缘层上形成源极，所述源极通过所述第一过孔与所述有源层连接。
在一些示例中，制作方法还包括，在形成所述有源材料层和所述第二金属层之间，在所述第二基板上形成缓冲层，其中，所述缓冲层与所述有源材料层被同时图案化，以形成缓冲层图案，所述有源层通过所述缓冲层图案与所述连接金属图案绝缘。
在一些示例中，制作方法还包括：在所述薄膜晶体管上形成第一平坦化层；在所述第一平坦化层上形成光转换层。
在一些示例中，所述光转化层包括依次设置在所述第一平坦层上的白荧光层和滤光层，所述滤光层包括颜色不同的多个彩色光阻。
在一些示例中，所述光转换层包括量子点结构层，所述量子点材料结构 层包括设置有不同颜色量子点材料的多个彩色光区。
在一些示例中，制作方法还包括在所述光转换层上形成第二平坦化层。
本公开的至少一个实施例提供一种显示基板，包括：基板以及设置于所述基板上的多个像素单元，其中：所述多个像素单元中的至少一个包括沿远离所述基板方向依次设置的发光二极管、连接金属图案以及薄膜晶体管；所述连接金属图案与所述发光二极管的顶电极导电连接；所述薄膜晶体管的有源层与所述连接金属图案绝缘间隔，所述薄膜晶体管的漏极与所述连接金属图案导电连接。
在一些示例中，所述薄膜晶体管为低温多晶硅薄膜晶体管。
在一些示例中，所述低温多晶硅薄膜晶体管包括：沿远离所述连接金属图案方向依次设置的低温多晶硅有源层、栅极绝缘层、栅极、层间绝缘层、源极和漏极，其中，所述源极通过所述栅极绝缘层以及所述层间绝缘层中的第一过孔与所述低温多晶硅有源层连接；所述漏极通过所述栅极绝缘层以及所述层间绝缘层中的第二过孔与所述低温多晶硅有源层连接，且所述漏极通过所述栅极绝缘层以及所述层间绝缘层中的第三过孔与所述连接金属图案电连接。
在一些示例中，所述低温多晶硅薄膜晶体管包括：沿远离所述连接金属图案方向依次设置的低温多晶硅有源层、栅极绝缘层、漏极、栅极、层间绝缘层和源极，其中，所述源极通过所述栅极绝缘层以及所述层间绝缘层中的第一过孔与所述低温多晶硅有源层连接；所述漏极设置于所述低温多晶硅有源层远离所述连接金属图案的一侧，且与所述连接金属图案电连接。
在一些示例中，显示基板还包括：沿远离所述薄膜晶体管方向依次设置的第一平坦化层和光转换层。
在一些示例中，所述光转化层包括依次设置在所述第一平坦层上的白荧光层和滤光层，所述滤光层包括颜色不同的多个彩色光阻。
在一些示例中，所述光转换层包括量子点结构层，所述量子点材料结构层包括设置有不同颜色量子点材料的多个彩色光区。
在一些示例中，所述发光二极管为蓝光发光二极管。
本公开的至少一个实施例提供一种显示装置，包括上述任一项所述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开实施例的发光二极管的结构示意图；
图2为本公开一实施例的显示基板的结构示意图；
图3为本公开另一实施例的显示基板的结构示意图；
图4为本公开又一实施例的显示基板的结构示意图；
图5为本公开一实施例的显示基板的结构示意图；
图6为本公开另一实施例的显示基板的结构示意图；
图7为本公开又一实施例的显示基板的结构示意图；
图8为本公开一实施例的显示基板的结构示意图；
图9为本公开另一实施例的显示基板的结构示意图；
图10为本公开又一实施例的显示基板的结构示意图；
图11为本公开一实施例的显示基板的结构示意图；
图12为本公开另一实施例的显示基板的结构示意图；
图13为本公开又一实施例的显示基板的结构示意图；
图14为本公开一实施例的显示基板的结构示意图；
图15为本公开实施例的显示基板的制作方法流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
由于Micro-LED器件在制作时需要外延层，外延层要求比较高，只能在硅片或者蓝宝石上制作，难以实现在薄膜晶体管控制电路上直接制作LED。目前的Micro-LED器件大部分是分别制作LED和薄膜晶体管控制电路然后再对位贴合。由于对位贴合会损失一定的精度，因此不利于高分辨率的面板 制作。
为提高显示基板的产品良率，以及显示装置的分辨率，本公开实施例提供了一种显示基板、显示装置以及显示基板的制作方法。
如图7和图12所示，本公开实施例提供的显示基板包括：基板1以及设置于基板1上的呈阵列排布的多个像素单元。像素单元包括沿远离基板1方向依次设置的发光二极管2、连接金属3以及薄膜晶体管5。连接金属3与发光二极管2的顶电极4导电连接。薄膜晶体管5的有源层6与连接金属3绝缘间隔，薄膜晶体管5的漏极7与连接金属3导电连接。发光二极管2为微型发光二极管。
本技术方案的显示基板，由于其发光二极管2制作于基板1上，在制作显示基板的薄膜晶体管5时，将制作完薄膜晶体管5的有源层未图案化的基板与发光二极管2基板直接贴合，再将薄膜晶体管5制作于发光二极管2上。由于连接金属3与发光二极管2的顶电极4导电连接，薄膜晶体管5的漏极7与连接金属3导电连接，因此薄膜晶体管5的漏极7与发光二极管2的顶电极4导电连接。本技术方案的显示基板在制作时，不需要将制作好的发光二极管2对位贴合于薄膜晶体管5。这样就可以避免对位精度的损失，从而可以将发光二极管2的尺寸做的更小，以制作出超高分辨率的显示装置。
如图7和图8所示，在本公开可选的实施例中，薄膜晶体管5的具体类型不限，例如可以为低温多晶硅薄膜晶体管。
可选的，低温多晶硅薄膜晶体管包括沿远离连接金属3方向依次设置的第一缓冲层8、低温多晶硅有源层9、第二缓冲层10、栅极绝缘层11、栅极12(请参见图6)、层间绝缘层13、源极14和漏极7。
源极14通过栅极绝缘层11以及层间绝缘层13上的第一过孔15(请参见图6)与低温多晶硅有源层9连接；漏极7通过栅极绝缘层11以及层间绝缘层13上的第二过孔16与低温多晶硅有源层9连接，且漏极7通过栅极绝缘层11以及层间绝缘层13上的第三过孔17与连接金属3导电连接。
如图13和图14所示，在本公开的实施例中，低温多晶硅薄膜晶体管包括沿远离连接金属3方向依次设置的第一缓冲层8、低温多晶硅有源层9、栅极绝缘层11、漏极7、栅极12、层间绝缘层13和源极14。
源极14通过栅极绝缘层11以及层间绝缘层13上的第一过孔15与低温 多晶硅有源层9连接；漏极7设置于低温多晶硅有源层9远离第一缓冲层8的一侧，且与连接金属3导电连接。
这样设置可以避免在栅极绝缘层11以及层间绝缘层13上开设用于使漏极7与低温多晶硅有源层9连接的过孔，以及漏极7与连接金属3连接的过孔，从而可以降低基板的制作工艺难度，提高产品良率。
如图7所示，在本公开另一可选的实施例中，显示基板还包括沿远离薄膜晶体管5方向依次设置的第一平坦化层18、白荧光层19、滤光层20以及第二平坦化层23，滤光层20包括对应每个像素单元的彩色光阻21以及界定相邻彩色光阻21的黑矩阵22。
如图8所示，在本公开又一可选的实施例中，发光二极管2为微型蓝光发光二极管，显示基板还包括沿远离薄膜晶体管5方向依次设置的第一平坦化层18、量子点材料结构层29以及第二平坦化层23。量子点材料结构层包括对应每个像素单元的第一彩色光区30、第二彩色光区31以及第三彩色光区32，以及界定相邻第一彩色光区30、第二彩色光区31以及第三彩色光区32的黑矩阵22。第一彩色光区30设置有绿光量子点材料结构层，第二彩色光区31设置有红光量子点材料结构层。
例如，上述的白荧光层和滤光层以及量子点材料层均为光转换层的示例。例如，由于外延生长的发光二极管可以为单色二极管，光转换层可以将单色二极管发出的单色光转换为其他颜色的光或转换为不同颜色的光。
基于相同的发明构思，本公开实施例还提供了一种显示装置，包括如前任一项的显示基板。
本技术方案的显示装置的发光二极管的尺寸可以做的更小，产品良率以及显示装置的分辨率可以做的更高。
如图1至图15所示，基于相同的发明构思，本公开实施例还提供了一种显示基板的制作方法，包括以下步骤001-006。
步骤001：如图1所示，在第一基板24之上依次形成发光二极管2和覆盖发光二极管2的第一金属层25。
步骤002：如图2所示，在第二基板26之上依次形成薄膜晶体管的有源材料层和第二金属层27。例如，这里的有源材料层的示例可以为上述的低温多晶硅有源层9。此外，在有源材料层的两侧，也可以形成第一缓冲层8和 第二缓冲层10。例如，第一缓冲层8和第二缓冲层10为绝缘材料，第一缓冲层8可以防止有源材料层与第二金属层27连接。
步骤003：如图3所示，将第一基板24上的第一金属层25与第二基板26上的第二金属层27相面对贴合联结。例如，在该步骤中，第一金属层25和第二金属层27彼此面对结合。
步骤004：如图4和图8所示，将第二基板26剥离。例如，在该步骤中将第二基板26剥离。将第二基板26剥离的方法没有特别限定。例如，可以在第二基板26和有源材料层之间形成牺牲层，在玻璃第二基板时，可以通过激光照射或加热等方式使牺牲层分解或熔化，从而能够使得第二基板能够被剥离。
步骤005：对贴合联结的第一金属层25和第二金属层27进行刻蚀，形成与发光二极管2的顶电极4导电连接的连接金属3的图案，其结构如图5和图9所示。
步骤006：在完成上述步骤的第一基板24上制作形成薄膜晶体管5，薄膜晶体管5的漏极7与连接金属3导电连接，如图6、图7、图10和图11所示。另外，薄膜晶体管5的有源层可以是通过图案化有源材料层而形成的。
在一些示例中，在第一基板上形成发光二极管包括在第一基板上外延生长发光层。例如，发光层材料包括无机半导体材料。在形成发光二极管的过程中，还可以包括生长n型接触层、p型接触层、缓冲层的步骤。另外，还可以包括形成n侧电极和p侧电极的过程。例如，n侧电极和p侧电极之一可以为上述发光二极管的顶电极。
如图5-8所示，连接金属3的面积可以小于发光二极管的顶电极4的面积，这样，在连接金属3形成在顶电极4上之后，可以避免完全遮挡顶电极而影响发光二极管的出光。例如，连接金属3的面积小于顶电极4的面积的1/4。例如，在满足电学传输性能的条件下，可以将连接金属3面积设置得尽量小。
采用本技术方案的显示基板的制作方法制作显示基板时，由于先在第一基板24上制作发光二极管2以及覆盖于发光二极管2上的第一金属层25，再在第二基板26上制作薄膜晶体管5的有源材料层和第二金属层27，然后再将两个金属层相面对贴合。由于两个金属层均是整面制作于对应的基板上， 因此在将两个金属层进行贴合时其对位难度较小，因此其对位精度要求较低。采用本技术方案的方法制作显示基板时，不需要在制作显示装置的过程中将制作好的发光二极管2与薄膜晶体管5进行对位贴合，这样便可以避免进行发光二极管2与薄膜晶体管5的对位，从而对于发光二极管2的尺寸要求较低，进而提高显示基板的产品良率，以及显示装置的分辨率。
如图5和图6所示，在本公开一实施例中，薄膜晶体管5为低温多晶硅薄膜晶体管，在第一基板24上制作形成薄膜晶体管5例如包括：将有源材料层刻蚀形成与连接金属3绝缘间隔的有源层6(请参见图7)；在有源层6上形成栅极绝缘层11；在栅极绝缘层11上形成栅极12图案；在栅极12图案上形成层间绝缘层13；在栅极绝缘层11以及层间绝缘层13上形成用于源极14与有源层6导电连接的第一过孔15；在栅极绝缘层11以及层间绝缘层13上形成用于漏极7与有源层6导电连接的第二过孔16，并形成用于漏极7与连接金属3导电连接的第三过孔17；在层间绝缘层13上形成源极14图案和漏极7图案。
如图10至图12所示，在本公开一可选的实施例中，薄膜晶体管为低温多晶硅薄膜晶体管，在第一基板24上制作形成薄膜晶体管例如包括：将有源材料层刻蚀形成与连接金属3绝缘间隔的有源层6；形成与有源层6以及连接金属3连接的漏极7图案；在漏极7上形成栅极绝缘层11；在栅极绝缘层11上形成栅极12图案；在栅极12图案上形成层间绝缘层13；在栅极绝缘层11以及层间绝缘层13上形成用于源极14与有源层6导电连接的第一过孔15；在层间绝缘层13上形成源极14图案。
采用上述方法可以避免在栅极绝缘层11以及层间绝缘层13上开设用于使漏极7与低温多晶硅有源层9连接的过孔，以及漏极7与连接金属3连接的过孔，从而可以降低基板的制作工艺难度，提高产品良率。
如图7和图13所示，在本公开一可选的实施例中，所述方法还包括：在层间绝缘层13上形成第一平坦化层18；在第一平坦化层18上形成白荧光层19；在白荧光层19上形成滤光层20，滤光层20包括对应每个像素单元的彩色光阻21以及界定相邻彩色光阻21的黑矩阵22；在滤光层20上形成第二平坦化层23。
如图8和图14所示，在本公开另一可选的实施例中，发光二极管2为蓝 光发光二极管，所述方法还包括：在层间绝缘层13上形成第一平坦化层18；在第一平坦化层18上形成量子点材料结构层29，量子点材料结构层29包括对应每个像素单元的第一彩色光区30、第二彩色光区31以及第三彩色光区32，以及界定相邻第一彩色光区30、第二彩色光区31以及第三彩色光区32的黑矩阵22，第一彩色光区30设置有绿光量子点材料结构层，第二彩色光区31设置有红光量子点材料结构层；在量子点材料结构层29上形成第二平坦化层23。
显示装置的具体类型不限，例如可以为VR设备、AR设备、手机、笔记本电脑、电子书以及平板电脑等等。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种显示基板的制作方法，包括：
    在第一基板之上依次形成发光二极管和覆盖发光二极管的第一金属层；
    在第二基板之上依次形成有源材料层和第二金属层；
    将所述第一基板上的第一金属层与所述第二基板上的第二金属层相面对结合；
    将所述第二基板剥离；
    对所述第一金属层和所述第二金属层进行图案化，以形成与所述发光二极管的顶电极电连接的连接金属图案；以及
    在所述第一基板上形成薄膜晶体管，
    其中所述薄膜晶体管的有源层是通过图案化所述有源材料层而形成，所述薄膜晶体管的漏极与所述连接金属图案电连接。
  2. 如权利要求1所述的制作方法，其中，在所述第一基板上形成所述发光二极管包括在所述第一基板上外延生长发光层。
  3. 如权利要求2所述的制作方法，其中，所述发光层包括无机半导体材料。
  4. 如权利要求1-3任一项所述的制作方法，其中，所述连接金属图案的面积小于所述发光二极管的顶电极的面积。
  5. 如权利要求1-4任一项所述的制作方法，其中，在所述第一基板上形成所述薄膜晶体管包括：
    将所述有源材料层图案化以形成所述有源层；
    在所述有源层上形成栅极绝缘层；
    在所述栅极绝缘层上形成栅极；
    在所述栅极上形成层间绝缘层；
    在所述栅极绝缘层以及所述层间绝缘层中形成与所述有源层连接的第一过孔和第二过孔以及与所述连接金属图案连接的第三过孔；
    在所述层间绝缘层上形成源极和所述漏极，所述源极通过所述第一过孔与所述有源层连接，所述漏极通过所述第二过孔与所述有源层连接且通过所述第三过孔与所述连接图案连接。
  6. 如权利要求1-4任一项所述的制作方法，其中，在所述第一基板上形成薄膜晶体管包括：
    将有源材料层图案化以形成所述有源层；
    形成与所述有源层以及所述连接金属图案连接的漏极；
    在所述漏极上形成栅极绝缘层；
    在所述栅极绝缘层上形成栅极；
    在所述栅极上形成层间绝缘层；
    在所述栅极绝缘层以及所述层间绝缘层中形成与所述有源层连接的第一过孔；以及
    在所述层间绝缘层上形成源极，所述源极通过所述第一过孔与所述有源层连接。
  7. 如权利要求1-6任一项所述的制作方法，还包括，在形成所述有源材料层和所述第二金属层之间，在所述第二基板上形成缓冲层，
    其中，所述缓冲层与所述有源材料层被同时图案化，以形成缓冲层图案，所述有源层通过所述缓冲层图案与所述连接金属图案绝缘。
  8. 如权利要求1-7任一项所述的制作方法，还包括：
    在所述薄膜晶体管上形成第一平坦化层；
    在所述第一平坦化层上形成光转换层。
  9. 如权利要求8所述的制作方法，其中，所述光转化层包括依次设置在所述第一平坦层上的白荧光层和滤光层，所述滤光层包括颜色不同的多个彩色光阻。
  10. 如权利要求8所述的制作方法，其中，所述光转换层包括量子点结构层，所述量子点材料结构层包括设置有不同颜色量子点材料的多个彩色光区。
  11. 如权利要求8-10任何一项所述的制作方法，还包括在所述光转换层上形成第二平坦化层。
  12. 一种显示基板，包括：基板以及设置于所述基板上的多个像素单元，其中：
    所述多个像素单元中的至少一个包括沿远离所述基板方向依次设置的发光二极管、连接金属图案以及薄膜晶体管；
    所述连接金属图案与所述发光二极管的顶电极导电连接；
    所述薄膜晶体管的有源层与所述连接金属图案绝缘间隔，所述薄膜晶体管的漏极与所述连接金属图案导电连接。
  13. 如权利要求12所述的显示基板，其中，所述薄膜晶体管为低温多晶硅薄膜晶体管。
  14. 如权利要求13所述的显示基板，其中，所述低温多晶硅薄膜晶体管包括：
    沿远离所述连接金属图案方向依次设置的低温多晶硅有源层、栅极绝缘层、栅极、层间绝缘层、源极和漏极，其中：
    其中，所述源极通过所述栅极绝缘层以及所述层间绝缘层中的第一过孔与所述低温多晶硅有源层连接；所述漏极通过所述栅极绝缘层以及所述层间绝缘层中的第二过孔与所述低温多晶硅有源层连接，且所述漏极通过所述栅极绝缘层以及所述层间绝缘层中的第三过孔与所述连接金属图案电连接。
  15. 如权利要求13所述的显示基板，其中，所述低温多晶硅薄膜晶体管包括：
    沿远离所述连接金属图案方向依次设置的低温多晶硅有源层、栅极绝缘层、漏极、栅极、层间绝缘层和源极，
    其中，所述源极通过所述栅极绝缘层以及所述层间绝缘层中的第一过孔与所述低温多晶硅有源层连接；所述漏极设置于所述低温多晶硅有源层远离所述连接金属图案的一侧，且与所述连接金属图案电连接。
  16. 如权利要求12-15任一项所述的显示基板，还包括：沿远离所述薄膜晶体管方向依次设置的第一平坦化层和光转换层。
  17. 如权利要求16所述的显示基板，其中，所述光转化层包括依次设置在所述第一平坦层上的白荧光层和滤光层，所述滤光层包括颜色不同的多个彩色光阻。
  18. 如权利要求16所述的显示基板，其中，所述光转换层包括量子点结构层，所述量子点材料结构层包括设置有不同颜色量子点材料的多个彩色光区。
  19. 如权利要求19所述的显示基板，其中，所述发光二极管为蓝光发光二极管。
  20. 一种显示装置，包括如权利要求12-19任一项所述的显示基板。
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