WO2019203019A1 - Non-volatile storage circuit - Google Patents

Non-volatile storage circuit Download PDF

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Publication number
WO2019203019A1
WO2019203019A1 PCT/JP2019/015073 JP2019015073W WO2019203019A1 WO 2019203019 A1 WO2019203019 A1 WO 2019203019A1 JP 2019015073 W JP2019015073 W JP 2019015073W WO 2019203019 A1 WO2019203019 A1 WO 2019203019A1
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WO
WIPO (PCT)
Prior art keywords
transistor
store
circuit
storage
driver
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Application number
PCT/JP2019/015073
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French (fr)
Japanese (ja)
Inventor
啓三 平賀
Original Assignee
ソニーセミコンダクタソリューションズ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by ソニーセミコンダクタソリューションズ株式会社 filed Critical ソニーセミコンダクタソリューションズ株式会社
Priority to CN201980015138.XA priority Critical patent/CN112020744A/en
Priority to JP2020514076A priority patent/JP7282749B2/en
Priority to DE112019002007.2T priority patent/DE112019002007T5/en
Publication of WO2019203019A1 publication Critical patent/WO2019203019A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell

Definitions

  • the present technology relates to a nonvolatile memory circuit, and more particularly, to a nonvolatile memory circuit that can achieve downsizing and keep power consumption low while maintaining stable writing.
  • PG Power Gating
  • PG Power Gating
  • NVFF Non-VolatileolaFlip-Floplononvolatile flip-flop
  • MTJ Magnetic Tunnel Junction
  • NVM Non Volatile Memory
  • NVFF nonlinear logic circuit
  • two MTJs are provided, and a transistor arranged on the store current path, that is, on the store path is connected to each of the MTJs. Either one of these always becomes a source connection in which the MTJ is connected to the ground side with respect to the transistor.
  • the gate width of the transistor needs to be increased in order to prevent disturbance (latch breakdown) to the latch during storage.
  • the present technology has been made in view of such a situation, and makes it possible to obtain a small nonvolatile memory circuit with low power consumption while maintaining stable writing.
  • a nonvolatile storage circuit includes a volatile storage unit that stores information, the information in the volatile storage unit is written by a store operation, and a store path at the time of the store operation by a restore operation. Includes a non-volatile storage unit from which the information is read out to the volatile storage unit through different restore paths, and all the transistors arranged on the store path are connected to the drain.
  • the nonvolatile storage circuit stores a volatile storage unit that stores information, and the information in the volatile storage unit is written by a store operation.
  • a non-volatile storage unit from which the information is read to the volatile storage unit via a restore path different from the path is provided, and all transistors arranged on the store path are connected to the drain.
  • FIG. 3 is a diagram illustrating a configuration example of an NVDFF circuit of a footer type SSR-NVFF circuit system.
  • NVDFF circuit> ⁇ Configuration example of NVDFF circuit>
  • the source-connected transistors are not arranged on the store path, and all the transistors on the store path are connected to the drain so that the nonvolatile memory is small and has low power consumption while maintaining stable writing.
  • a memory circuit can be obtained.
  • Figure 1 shows the header type SSR-NVFF (Split Store / Restore-Non-Volatile Flip-Flop) circuit type NVDFF ((Non-Volatile D Flip-Flop) non-volatile as a nonvolatile memory circuit to which this technology is applied. It is a figure which shows the structural example of a flip-flop) circuit.
  • SSR-NVFF Split Store / Restore-Non-Volatile Flip-Flop
  • NVDFF Non-Volatile D Flip-Flop
  • the NVDFF circuit 11 shown in FIG. 1 includes a volatile storage unit 21, a store driver 22, a transistor 23, a store driver 24, a transistor 25, a transistor 26, a transistor 27, a nonvolatile storage unit 28, a control driver 29, and an OR circuit 30. And a transistor 31.
  • the transistor 23, the transistor 25, the transistor 26, the transistor 27, and the transistor 31 are nMOS transistors.
  • a pMOS transistor (not shown) is used as a PS (power switch) for PG.
  • PS power switch
  • PG power switch
  • the volatile storage unit 21 includes a flip-flop circuit that temporarily holds storage data that is information supplied from the outside, and more specifically, a storage node state such as a voltage level corresponding to the storage data.
  • the volatile memory unit 21 includes an inverter 41, a transmission gate 42, a master latch 43, a transmission gate 44, a slave latch 45, and an inverter 46.
  • the master latch 43 includes an inverter 51, an inverter 52, and a transmission gate 53.
  • the slave latch 45 includes an inverter 61, an inverter 62, a transmission gate 63, and a transistor 64.
  • the slave latch 45 has a storage node N11 and a storage node N12.
  • the transmission gate 42 and the transmission gate 63 are turned on when the clock signal CLK falls and turned off when the clock signal CLK rises.
  • the transmission gate 53 and the transmission gate 44 are turned off when the clock signal CLK falls and turned on when the clock signal CLK rises.
  • the input side of the inverter 41 is an input terminal of the volatile storage unit 21, and the output side of the inverter 41 is connected to the input side of the inverter 51 via the transmission gate 42.
  • the storage node N11 of the slave latch 45 is connected to the output side of the inverter 51 via the transmission gate 44, and the output terminal of the inverter 51 is also connected to the input side of the inverter 52.
  • the output side of the inverter 52 is connected to the input side of the inverter 51 via the transmission gate 53. That is, the output side of the transmission gate 53 is connected between the inverter 51 and the transmission gate 42 via the transmission gate 53.
  • the slave latch 45 has a storage node N11 and a storage node N12 that temporarily hold a voltage level corresponding to the input storage data, and an inverter 61 is interposed between the storage node N11 and the storage node N12. Is provided.
  • the storage node N12 is connected to input terminals of the inverter 46, the inverter 62, and the store driver 24.
  • the output side of the inverter 46 is an output terminal of the volatile storage unit 21.
  • the output side of the inverter 62 is connected to the storage node N11 via the transmission gate 63.
  • a transistor 64 that is an nMOS transistor is connected to both ends of the transmission gate 63. In other words, one end of the transistor 64 is connected to the input side of the transmission gate 63, and the other end of the transistor 64 is connected to the output side of the transmission gate 63.
  • a control signal R having a predetermined voltage level is supplied to the gate of the transistor 64.
  • the input terminal of the store driver 22 is also connected to the storage node N11.
  • the store driver 22 includes an inverter that is an inverting element. That is, the store driver 22 includes a transistor 71 that is a pMOS transistor and a transistor 72 that is an nMOS transistor.
  • one end of the transistor 71 is connected to the power supply, and the transistor 72 is connected to the other end of the transistor 71.
  • a control signal SR2 is supplied to the gate of the transistor 23.
  • the output side end of the inverter composed of the transistor 71 and the transistor 72 is connected to the non-volatile storage unit 28 via the node N13.
  • the store driver 24 is an inverter that is an inverting element. That is, the store driver 24 includes a transistor 81 that is a pMOS transistor and a transistor 82 that is an nMOS transistor.
  • one end of the transistor 81 is connected to the power source, and the transistor 82 is connected to the other end of the transistor 81.
  • a control signal SR2 is supplied to the gate of the transistor 25.
  • the output side end of the inverter composed of the transistor 81 and the transistor 82 is connected to the nonvolatile storage unit 28 via the node N14.
  • the non-volatile storage unit 28 is a non-volatile storage unit, and at the time of storing (writing), voltage level states at the storage node N11 and the storage node N12, that is, storage data is written into the non-volatile storage unit 28.
  • the storage data held in the nonvolatile storage unit 28 that is, the state of the held voltage level is read to the storage node N11 and the storage node N12 through a path different from the path at the time of storage. It is.
  • the nonvolatile storage unit 28 includes a storage element 91 and a storage element 92.
  • the storage element 91 and the storage element 92 are composed of nonvolatile storage elements such as MTJ which is a magnetoresistive element and ReRAM (Resistive Random Access Memory) which is a resistance change type memory.
  • MTJ magnetoresistive element
  • ReRAM Resistive Random Access Memory
  • MTJ consists of a fixed layer (p layer) and a free layer (f layer) and a barrier layer formed between the fixed layer and the free layer. It is a nonvolatile memory element that can be changed to a state.
  • an H level that is a higher voltage level is associated with a high resistance state, in other words, “1” as stored data
  • an L level that is a lower voltage level is associated with a low resistance state.
  • the low resistance state of the MTJ is referred to as a Parallel state (hereinafter also referred to as a P state), and the high resistance state is referred to as an Anti-Parallel state (hereinafter also referred to as an AP state).
  • a P state Parallel state
  • AP state Anti-Parallel state
  • the free layer of the storage element 91 is connected to the control line L11, and the side opposite to the free layer, that is, the fixed layer of the storage element 91 is connected to the node N14.
  • the node N14 is connected to the output-side end of the store driver 24 and is also connected to the storage node N11 via the transistor 26.
  • the free layer of the storage element 92 is connected to the control line L11, and the fixed layer of the storage element 92 is connected to the node N13.
  • the node N13 is connected to the output-side end of the store driver 22 and is also connected to the storage node N12 via the transistor 27.
  • the control signal SR1 is supplied to the gates of the transistor 26 and the transistor 27.
  • a control driver 29 for controlling a voltage level in the control line L11 is connected to the control line L11 connected to the storage element 91 and the storage element 92.
  • the control driver 29 is an inverter that is an inverting element. That is, the control driver 29 includes a transistor 101 that is a pMOS transistor and a transistor 102 that is an nMOS transistor.
  • one end of the transistor 101 is connected to the power source, and the transistor 102 and the control line L11 are connected to the other end of the transistor 101.
  • the end of the transistor 102 opposite to the end to which the transistor 101 and the control line L11 are connected is connected to the ground via the transistor 31.
  • the control signal CTRL is supplied to the input side end of the control driver 29, that is, the gate of the transistor 101 and the gate of the transistor 102.
  • the output side end of the OR circuit 30 is connected to the gate of the transistor 31, and the control signal SR1 and the control signal SR2 are supplied to the input side end of the OR circuit 30.
  • the transistor 31 in each NVDFF circuit 11 is turned on in the store mode and the restore mode. To be in a state.
  • one OR circuit common to all the plurality of cells that is, all of the plurality of NVDFF circuits 11, may be provided.
  • the NVDFF circuit 11 there are four operation modes, an active mode, a store mode, a sleep mode, and a restore mode.
  • an active mode When the NVDFF circuit 11 is operated, the operation mode transitions from the active mode to the store mode, the sleep mode, and the restore mode in order.
  • PS (not shown) is turned on. Further, the control signal SR1 is set to H level, and the transistors 26 and 27 are turned on. That is, the transistor 26 and the transistor 27 are turned on (conductive state). At this time, the control signal SR2 is set to the L level.
  • the output of the inverter 41 becomes the H level.
  • This H level is input to the inverter 51 at the timing when the clock signal CLK falls, that is, when the transmission gate 42 is turned on.
  • the transmission gate 53 and the transmission gate 44 are turned on, so that the output of the inverter 51 becomes L level by the loop of the inverter 51 and the inverter 52.
  • This L level is supplied as storage data to the storage node N11 via the transmission gate 44.
  • the transmission gate 53 and the transmission gate 44 are turned off, and the transmission gate 42 and the transmission gate 63 are turned on.
  • the loop composed of inverter 61 and inverter 62 holds (stores) the L level indicating the stored data at storage node N11, and holds the H level obtained by inverting the stored data at storage node N12.
  • control signal SR1 is set to L level and the transistors 26 and 27 are turned off, and the control signal SR2 is set to H level and the transistors 23 and 25 are turned on.
  • the transistor 71 is turned on in the store driver 22 connected to the storage node N11, and the output terminal of the store driver 22, that is, the node N13 is H Become a level.
  • the transistor 82 is turned on, and the output terminal of the store driver 24, that is, the node N14 becomes L level.
  • the transistor 101 is turned on in the control driver 29, and the output terminal of the control driver 29, that is, the control line L11 is set to the H level.
  • control driver 29 since the control line L11 is at the H level and the node N14 is at the L level, the control driver 29, the control line L11, the storage element 91, the node N14, the transistor 82, and the power supply connected to the control driver 29 Store current flows through transistor 25 to ground.
  • the state “H level” held in the storage node N12 is inverted by the store driver 24 and held (stored) in the storage element 91.
  • the state “H level” held in the storage node N12 is inverted and written (stored) in the storage element 91.
  • control driver 29 turns off the transistor 101 and turns on the transistor 102.
  • the output terminal of the control driver 29, that is, the control line L11 is connected to the ground and becomes L level.
  • the transistor 71, the node N13, the storage element 92, the control line L11, the transistor 102, and the transistor are connected from the power source connected to the store driver 22.
  • Store current flows through 31 to ground.
  • a current flows from the fixed layer connected to the node N13 side to the free layer connected to the control line L11 side, so that the memory element 92 is in a high resistance state, that is, AP It becomes a state.
  • the state “L level” held in the storage node N11 is inverted by the store driver 22 and held in the storage element 92.
  • the state “L level” held in the storage node N11 is inverted and written to the storage element 92.
  • the control signal CTRL is then set to the L level, and the store operation ends.
  • a store current path (hereinafter also referred to as a store path) during the above-described store operation is shown.
  • the broken line L21 indicates a store path when information (state) is stored in the storage element 91 at the timing when the control signal CTRL is set to the L level.
  • the transistor 101, the storage element 91, the transistor 82, and the transistor 25 are arranged on the store path indicated by the broken line L21.
  • the broken line L22 indicates a store path at the time of storing information (state) to the storage element 92 at the timing when the control signal CTRL is set to the H level.
  • the transistor 71, the storage element 92, the transistor 102, and the transistor 31 are arranged on the store path indicated by the broken line L22.
  • the transistor 23, the transistor 25, the transistor 31, and the OR circuit 30 in the NVDFF circuit 11 are not provided.
  • transistors are provided on the store path at a position corresponding to between the store driver 22 and the storage element 92 and at a position corresponding to between the store driver 24 and the storage element 91. .
  • either one of these two transistors will always be a source connection in which the MTJ is connected to the ground side with respect to the transistor.
  • the store current flows through the MTJ through the source-connected transistor, the store current is reduced due to the back bias effect. Therefore, if a sufficiently large store current is to be ensured, the gate width of the transistor must be increased, resulting in an increase in circuit scale.
  • the transistor 23, the transistor 25, and the transistor 31 are provided between the store driver 22, the store driver 24, and the control driver 29 and the ground, respectively.
  • NVDFF circuit 11 it is not necessary to provide a transistor between the store driver 22 and the storage element 92 or between the store driver 24 and the storage element 91.
  • NVDFF circuit 11 no source-connected transistors are arranged in the store path, and all the transistors in the store path are connected to the drain connected to the storage element on the opposite side to the ground side. It has become.
  • the transistor 25 arranged in the store path indicated by the broken line L21 has a drain connection in which the storage element 91 is connected to the drain side (power supply side).
  • the transistor 31 arranged in the store path indicated by the broken line L22 also has a drain connection in which the storage element 92 is connected to the drain side. Further, when a store current flows through the transistor 23 during storage, the store current flows from the storage element 92 through the transistor 23 to the ground. In this case, the transistor 23 is connected to the drain.
  • the store current is not reduced due to the back bias effect, so that a sufficient store current can be ensured even if a transistor having a narrow gate width is used, and the circuit scale of the entire NVDFF circuit 11 is ensured. Can be kept small.
  • the NVDFF circuit 11 has a structure in which the voltage level of the storage node of the slave latch 45 is received by the store driver at the time of store, and the output is written to the storage element through a path that does not affect the voltage level of the storage node. Therefore, latch breakdown does not occur. That is, stable writing can be performed.
  • the NVDFF circuit 11 can provide a small NVDFF circuit 11 with low power consumption while maintaining stable writing.
  • the state transits to the sleep mode at an appropriate timing.
  • the PS (not shown) is turned off, and the power supplied to the NVDFF circuit 11 is shut off. As a result, the voltage level on the output side of the inverter 46 becomes L level.
  • control signal SR1 is set to H level to turn on the transistors 26 and 27, and the control signal SR2 is set to L level to turn off the transistors 23 and 25 (non-conductive state).
  • control signal CTRL is set to H level, the transistor 102 of the control driver 29 is turned on, and the control line L11 is connected to the ground. That is, the control line L11 becomes L level.
  • the storage element 91 is in the low resistance state, that is, the P state
  • the storage element 92 is in the high resistance state, that is, the AP state, as in the above example.
  • a restore current flows through four paths (hereinafter also referred to as a restore path) of broken lines L41 to L44.
  • the restore path indicated by the broken line L41 is a path through which a restore current flows from the power source to the ground through the transistor 81, the node N14, the storage element 91, the control line L11, the transistor 102, and the transistor 31.
  • the restore path indicated by the broken line L42 is a path through which a restore current flows from the inverter 62 to the ground through the transmission gate 63, the transistor 26, the node N14, the storage element 91, the control line L11, the transistor 102, and the transistor 31.
  • the restore path indicated by the broken line L43 is a path through which a restore current flows from the power source to the ground through the transistor 71, the node N13, the storage element 92, the control line L11, the transistor 102, and the transistor 31.
  • the restore path indicated by the broken line L44 is a path through which a restore current flows from the inverter 61 to the ground through the transistor 27, the node N13, the storage element 92, the control line L11, the transistor 102, and the transistor 31.
  • the transistor 27 has a significantly lower conductance than the transistor 26 due to an increase in the source voltage. Therefore, the current flowing through the transistor 27 is smaller than the current flowing through the transistor 26 more than the difference in resistance between the memory element 91 and the memory element 92.
  • the voltage at the storage node N12 rises higher than the voltage at the storage node N11, positive feedback is applied in the loop composed of the inverter 61 and the inverter 62 in the slave latch 45, and the storage node N12 becomes the power supply voltage (H level).
  • the storage node N11 is at the ground level (L level). That is, the storage node N11 and the storage node N12 are restored to the same voltage level state at the time of storage.
  • the NVDFF circuit described in Document 1 elements corresponding to the transistor 23 and the transistor 25 in the NVDFF circuit 11 are not provided.
  • the NVDFF circuit 11 is provided with the transistor 23 and the transistor 25, so that the restoration time can be shortened without wasteful power consumption during restoration.
  • the transistor 23 is not provided in the NVDFF circuit 11.
  • the input terminal of the store driver 22 becomes an intermediate voltage between the power supply voltage and the ground level. Both transistors 72 are turned on.
  • the NVDFF circuit 11 is provided with the transistor 23, and the transistor 23 is in the off state during the restore operation. For this reason, in the store driver 22, useless current does not flow from the power source to the ground, but current flows from the power source along the path indicated by the broken line L 43, and the current becomes a restore current.
  • the restore current flows only in the path indicated by the polygonal line L 42 and the polygonal line L 44 in the related art so that the restore current also flows in the path indicated by the polygonal line L 41 and the polygonal line L 43 in addition to them.
  • the restore current becomes larger as a whole, the time until the voltage levels of the storage node N11 and the storage node N12 return to the store state can be further shortened.
  • the short circuit at the time of restoration is used for charging the storage node, useless power consumption can be reduced and the restoration time can be shortened.
  • the operations of the active mode, the store mode, the sleep mode, and the restore mode described above are performed according to the input storage data.
  • the NVDFF circuit is configured as shown in FIG. 4, for example.
  • FIG. 4 portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted as appropriate.
  • the NVDFF circuit 201 shown in FIG. 4 is an NVDFF circuit of a footer type SSR-NVFF circuit system.
  • an nMOS transistor (not shown) is used for PG. Specifically, for example, when the PS is turned on, each part of the NVDFF circuit 201 is connected to the ground via the nMOS transistor, and when the PS is turned off, each part of the NVDFF circuit 201 is electrically disconnected from the ground and PG Is realized.
  • the NVDFF circuit 201 includes a volatile storage unit 21, a store driver 22, a transistor 23, a store driver 24, a transistor 25, a transistor 211, a transistor 212, a nonvolatile storage unit 213, a control driver 29, an XNOR circuit 214, and a transistor 31. have.
  • the circuit configuration of the NVDFF circuit 201 includes a transistor 211, a transistor 212, a nonvolatile memory unit 213, and an XNOR circuit 214 instead of the transistor 26, the transistor 27, the nonvolatile memory unit 28, and the OR circuit 30 in the NVDFF circuit 11. It becomes the composition.
  • the nonvolatile storage unit 213 includes a storage element 221 and a storage element 222 made of MTJ, ReRAM, or the like.
  • a storage element 221 and a storage element 222 made of MTJ, ReRAM, or the like.
  • the description will be continued assuming that the memory element 221 and the memory element 222 are MTJ.
  • a transistor 211 is provided between the storage node N11 and the node N14, and a transistor 212 is provided between the storage node N12 and the node N13.
  • the transistors 211 and 212 are pMOS transistors, and a control signal SR1 is supplied to the gates of the transistors 211 and 212.
  • the fixed layer (p layer) of the storage element 221 is connected to the control line L11, and the free layer (f layer) of the storage element 221 is connected to the node N14. Further, the fixed layer of the storage element 222 is connected to the control line L11, and the free layer of the storage element 222 is connected to the node N13.
  • NVDFF circuit 201 As in the NVDFF circuit 11, all transistors in the store path are connected to the drain.
  • the transistor 25 and the transistor 23 arranged in the store path have a drain connection in which the storage element 221 and the storage element 222 are connected to the drain side.
  • the transistor 31 arranged in the store path has a drain connection in which the storage element 221 and the storage element 222 are connected to the drain side.
  • control signal SR1 and the control signal SR2 are supplied to the input terminal of the XNOR circuit 214, and the output terminal of the XNOR circuit 214 is connected to the transistor 31.
  • the NVDFF circuit 201 performs the same operation as that of the NVDFF circuit 11 described above in the active mode.
  • control signal SR1 is set to H level to turn off the transistors 211 and 212
  • control signal SR2 is set to H level to turn on the transistors 23 and 25.
  • control signal CTRL is set to H level, and then the control signal CTRL is set to L level, and the state of the storage node is stored in the nonvolatile storage unit 213.
  • the state of the storage node N11 is L level and the state of the storage node N12 is H level.
  • the transistor 71 of the store driver 22 is turned on and the node N13 becomes H level, and the transistor 82 of the store driver 24 is turned on and the node N14 becomes L level.
  • the storage current flows from the control line L11 side to the node N14 side in the storage element 221, and the storage element 221 is in the high resistance state (AP state). It becomes.
  • the state of the voltage level of the storage node N12 is held (stored) in the storage element 221 as it is by the store driver 24.
  • the NVDFF circuit 201 similarly to the case of the NVDFF circuit 11, no source-connected transistors are arranged in the store path, and all the transistors in the store path are drain-connected. That is, the transistor 23, the transistor 25, and the transistor 31 are drain connected.
  • the PS (not shown) is turned off and the PG is realized. After that, when returning from the sleep state, the operation in the restore mode is performed.
  • control signal SR1 is set to the L level and the transistors 211 and 212 are turned on, and the control signal SR2 is set to the L level and the transistors 23 and 25 are turned off.
  • control signal CTRL is set to L level
  • the transistor 101 of the control driver 29 is turned on, and the control line L11 is connected to the power source. That is, the control line L11 becomes H level.
  • the memory element 221 is in the high resistance state (AP state) and the memory element 222 is in the low resistance state (P state) as in the above example.
  • the voltage of the node N14 is set to the node due to the difference in electrical resistance between the memory element 221 and the memory element 222 when the restore current flows. Lower than the voltage of N13.
  • the transistor 211 a decrease in conductance due to a decrease in source voltage appears more significantly than in the transistor 212. Accordingly, the current flowing through the transistor 211 is smaller than the current flowing through the transistor 212 more than the difference between the resistances of the memory element 221 and the memory element 222.
  • the voltage at the storage node N11 is lower than the voltage at the storage node N12, positive feedback is applied in the loop composed of the inverter 61 and the inverter 62 in the slave latch 45, and the storage node N12 becomes the power supply voltage (H level).
  • the storage node N11 is at the ground level (L level). That is, the storage node N11 and the storage node N12 are restored to the same voltage level state at the time of storage.
  • the transistor 23 and the transistor 25 are in an off state, so that a restore current does not flow from the transistor 23 or the transistor 25 to the ground, and wasteful power consumption occurs. It is suppressed.
  • the operation in each of the active mode, the store mode, the sleep mode, and the restore mode is performed according to the input storage data.
  • NVDFF circuit 201 as described above, as in the case of the NVDFF circuit 11, it is possible to achieve downsizing and keep power consumption low while maintaining stable writing.
  • the present technology can be configured as follows.
  • a volatile storage unit for storing information A non-volatile storage unit in which the information in the volatile storage unit is written by a store operation, and the information is read to the volatile storage unit by a restore path different from the store path at the time of the store operation by a restore operation; With A non-volatile memory circuit in which all the transistors arranged on the store path are connected to the drain.
  • the store driver is an inverting element.
  • the volatile storage unit has a first storage node and a second storage node,
  • the nonvolatile storage unit includes a first storage element and a second storage element, The first storage node and the first storage element are connected via a third transistor;
  • the first storage node and the second storage element are connected via the store driver;
  • the nonvolatile memory circuit according to (9), wherein the second storage node and the first storage element are connected via the other store driver.
  • (11) The nonvolatile memory circuit according to (9) or (10), wherein the first memory element and the second memory element are MTJs.
  • NVDFF circuit 21 volatile storage unit, 22 store driver, 23 transistor, 24 store driver, 25 transistor, 28 non-volatile storage unit, 29 control driver, 30 OR circuit, 31 transistor, 91 storage element, 92 storage element

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Abstract

The present art relates to a non-volatile storage circuit that allows for miniaturization and reduced power consumption while maintaining stable writing. This non-volatile storage circuit is provided with a volatile storage unit which stores information, and a non-volatile storage unit to which the information in the volatile storage unit is written by a store operation, and from which information is read into the volatile storage unit by a restore operation via a restore path that is different from the store path for the store operation, wherein all transistors disposed along the store path have the drains thereof connected together. The present art can be applied to NVDFF circuits.

Description

不揮発性記憶回路Nonvolatile memory circuit
　本技術は不揮発性記憶回路に関し、特に、安定な書き込みを維持しつつ、小型化を実現し、消費電力を低く抑えることができるようにした不揮発性記憶回路に関する。 The present technology relates to a nonvolatile memory circuit, and more particularly, to a nonvolatile memory circuit that can achieve downsizing and keep power consumption low while maintaining stable writing.
　従来、リーク電流を削減するための低消費電力技術として、PG（Power Gating）が知られている。 Conventionally, PG (Power Gating) is known as a low power consumption technology for reducing leakage current.
　また、PGを利用したNVFF（Non-Volatile Flip-Flop 不揮発性フリップフロップ）として、PG対象のフリップフロップ回路にNVM（Non Volatile Memory）であるMTJ（Magnetic Tunnel Junction）を接続し、電源復帰時にその場で論理復帰できるものが提案されている（例えば特許文献１参照）。このようなMTJを用いたNVFFでは、安定な書き込みを維持しつつ、ある程度消費電力を低く抑えることができる。 In addition, as NVFF (Non-VolatileolaFlip-Floplononvolatile flip-flop) using PG, MTJ (Magnetic Tunnel Junction) which is NVM (Non Volatile Memory) is connected to the flip-flop circuit of PG, and when the power returns There has been proposed one that can be logically restored in the field (see, for example, Patent Document 1). NVFF using such MTJ can keep power consumption low to some extent while maintaining stable writing.
国際公開第２０１６／１８５９０３号International Publication No. 2016/185903
　しかしながら、上述したNVFFではMTJへの書き込み時、すなわちストア時に十分に大きなストア電流を流すためには、ラッチを形成するトランジスタや、MTJを選択するためのトランジスタを大きくする必要があり、結果としてNVFF全体の回路規模が大きくなってしまう。 However, in the above-described NVFF, in order to flow a sufficiently large store current at the time of writing to the MTJ, that is, at the time of storing, it is necessary to enlarge the transistor for forming the latch and the transistor for selecting the MTJ. The entire circuit scale becomes large.
　例えば上述したNVFFでは２つのMTJが設けられており、それらの各MTJに対して、それぞれストア電流の経路上、すなわちストア経路上に配置されたトランジスタが接続されているが、これらの２つのトランジスタの何れか一方は、必ずトランジスタに対してグランド側にMTJが接続されたソース接続となってしまう。 For example, in the above-mentioned NVFF, two MTJs are provided, and a transistor arranged on the store current path, that is, on the store path is connected to each of the MTJs. Either one of these always becomes a source connection in which the MTJ is connected to the ground side with respect to the transistor.
　そうすると、十分な大きさのストア電流を確保するためにトランジスタのゲート幅を大きくする必要がある。また、ストア時のラッチへのディスターブ（ラッチ破壊）を防止するためにもトランジスタのゲート幅を大きくする必要がある。 Then, in order to secure a sufficiently large store current, it is necessary to increase the gate width of the transistor. In addition, the gate width of the transistor needs to be increased in order to prevent disturbance (latch breakdown) to the latch during storage.
　本技術は、このような状況に鑑みてなされたものであり、安定な書き込みを維持しつつ、小型で消費電力の低い不揮発性記憶回路を得ることができるようにするものである。 The present technology has been made in view of such a situation, and makes it possible to obtain a small nonvolatile memory circuit with low power consumption while maintaining stable writing.
　本技術の一側面の不揮発性記憶回路は、情報を記憶する揮発性記憶部と、ストア動作により前記揮発性記憶部の前記情報が書き込まれるとともに、リストア動作により、前記ストア動作時のストア経路とは異なるリストア経路で前記情報が前記揮発性記憶部へと読み出される不揮発性記憶部とを備え、前記ストア経路上に配置された全てのトランジスタがドレイン接続となっている。 A nonvolatile storage circuit according to an aspect of the present technology includes a volatile storage unit that stores information, the information in the volatile storage unit is written by a store operation, and a store path at the time of the store operation by a restore operation. Includes a non-volatile storage unit from which the information is read out to the volatile storage unit through different restore paths, and all the transistors arranged on the store path are connected to the drain.
　本技術の一側面においては、不揮発性記憶回路に、情報を記憶する揮発性記憶部と、ストア動作により前記揮発性記憶部の前記情報が書き込まれるとともに、リストア動作により、前記ストア動作時のストア経路とは異なるリストア経路で前記情報が前記揮発性記憶部へと読み出される不揮発性記憶部とが設けられ、前記ストア経路上に配置された全てのトランジスタがドレイン接続とされている。 In one aspect of the present technology, the nonvolatile storage circuit stores a volatile storage unit that stores information, and the information in the volatile storage unit is written by a store operation. A non-volatile storage unit from which the information is read to the volatile storage unit via a restore path different from the path is provided, and all transistors arranged on the store path are connected to the drain.
ヘッダ型のSSR-NVFF回路方式のNVDFF回路の構成例を示す図である。It is a figure which shows the structural example of the NVDFF circuit of a header type SSR-NVFF circuit system. ストア経路について説明する図である。It is a figure explaining a store route. リストア経路について説明する図である。It is a figure explaining a restore route. フッタ型のSSR-NVFF回路方式のNVDFF回路の構成例を示す図である。FIG. 3 is a diagram illustrating a configuration example of an NVDFF circuit of a footer type SSR-NVFF circuit system.
　以下、図面を参照して、本技術を適用した実施の形態について説明する。 Hereinafter, embodiments to which the present technology is applied will be described with reference to the drawings.
〈第１の実施の形態〉
〈NVDFF回路の構成例〉
　本技術は、ストア経路上にソース接続のトランジスタが配置されず、ストア経路上のトランジスタが全てドレイン接続となるようにすることで、安定な書き込みを維持しつつ、小型で消費電力の低い不揮発性記憶回路を得ることができるようにするものである。 <First Embodiment>
<Configuration example of NVDFF circuit>
In this technology, the source-connected transistors are not arranged on the store path, and all the transistors on the store path are connected to the drain so that the nonvolatile memory is small and has low power consumption while maintaining stable writing. A memory circuit can be obtained.
　図１は、本技術を適用した不揮発性記憶回路としてのヘッダ型のSSR-NVFF（Split Store/Restore-Non-Volatile Flip-Flop）回路方式のNVDFF（（Non-Volatile D Flip-Flop）不揮発性フリップフロップ）回路の構成例を示す図である。 Figure 1 shows the header type SSR-NVFF (Split Store / Restore-Non-Volatile Flip-Flop) circuit type NVDFF ((Non-Volatile D Flip-Flop) non-volatile as a nonvolatile memory circuit to which this technology is applied. It is a figure which shows the structural example of a flip-flop) circuit.
　図１に示すNVDFF回路１１は、揮発性記憶部２１、ストア用ドライバ２２、トランジスタ２３、ストア用ドライバ２４、トランジスタ２５、トランジスタ２６、トランジスタ２７、不揮発性記憶部２８、制御ドライバ２９、OR回路３０、およびトランジスタ３１を有している。ここでは、トランジスタ２３、トランジスタ２５、トランジスタ２６、トランジスタ２７、およびトランジスタ３１はnMOSトランジスタとなっている。 The NVDFF circuit 11 shown in FIG. 1 includes a volatile storage unit 21, a store driver 22, a transistor 23, a store driver 24, a transistor 25, a transistor 26, a transistor 27, a nonvolatile storage unit 28, a control driver 29, and an OR circuit 30. And a transistor 31. Here, the transistor 23, the transistor 25, the transistor 26, the transistor 27, and the transistor 31 are nMOS transistors.
　例えばNVDFF回路１１では、PGにはPS（パワースイッチ）として図示せぬpMOSトランジスタが用いられる。具体的には、例えばPSがオンされると、pMOSトランジスタを介してNVDFF回路１１の各部に電源線から電力が供給され、PSがオフされるとNVDFF回路１１の各部は電源線から電気的に切り離されてPGが実現される。 For example, in the NVDFF circuit 11, a pMOS transistor (not shown) is used as a PS (power switch) for PG. Specifically, for example, when PS is turned on, power is supplied from the power supply line to each part of the NVDFF circuit 11 via the pMOS transistor, and when PS is turned off, each part of the NVDFF circuit 11 is electrically connected from the power supply line. It is separated and PG is realized.
　揮発性記憶部２１は外部から供給された情報である記憶データ、より詳細には記憶データに対応する電圧レベル等の記憶ノードの状態を一時的に保持するフリップフロップ回路からなる。 The volatile storage unit 21 includes a flip-flop circuit that temporarily holds storage data that is information supplied from the outside, and more specifically, a storage node state such as a voltage level corresponding to the storage data.
　揮発性記憶部２１はインバータ４１、伝送ゲート４２、マスターラッチ４３、伝送ゲート４４、スレーブラッチ４５、およびインバータ４６を有している。 The volatile memory unit 21 includes an inverter 41, a transmission gate 42, a master latch 43, a transmission gate 44, a slave latch 45, and an inverter 46.
　また、マスターラッチ４３はインバータ５１、インバータ５２、および伝送ゲート５３を有している。 The master latch 43 includes an inverter 51, an inverter 52, and a transmission gate 53.
　さらに、スレーブラッチ４５はインバータ６１、インバータ６２、伝送ゲート６３、およびトランジスタ６４を有している。また、スレーブラッチ４５は記憶ノードN11および記憶ノードN12を有している。 Furthermore, the slave latch 45 includes an inverter 61, an inverter 62, a transmission gate 63, and a transistor 64. The slave latch 45 has a storage node N11 and a storage node N12.
　揮発性記憶部２１においては、伝送ゲート４２および伝送ゲート６３はクロック信号CLKが立ち下がったタイミングでオンし、クロック信号CLKが立ち上がったタイミングでオフする。 In the volatile storage unit 21, the transmission gate 42 and the transmission gate 63 are turned on when the clock signal CLK falls and turned off when the clock signal CLK rises.
　これに対して、伝送ゲート５３および伝送ゲート４４はクロック信号CLKが立ち下がったタイミングでオフし、クロック信号CLKが立ち上がったタイミングでオンする。 On the other hand, the transmission gate 53 and the transmission gate 44 are turned off when the clock signal CLK falls and turned on when the clock signal CLK rises.
　インバータ４１の入力側が揮発性記憶部２１の入力端子となっており、そのインバータ４１の出力側は伝送ゲート４２を介してインバータ５１の入力側に接続されている。 The input side of the inverter 41 is an input terminal of the volatile storage unit 21, and the output side of the inverter 41 is connected to the input side of the inverter 51 via the transmission gate 42.
　また、インバータ５１の出力側には、伝送ゲート４４を介してスレーブラッチ４５の記憶ノードN11が接続されているとともに、インバータ５１の出力端はインバータ５２の入力側にも接続されている。 Further, the storage node N11 of the slave latch 45 is connected to the output side of the inverter 51 via the transmission gate 44, and the output terminal of the inverter 51 is also connected to the input side of the inverter 52.
　さらに、インバータ５２の出力側は、伝送ゲート５３を介してインバータ５１の入力側に接続されている。すなわち、伝送ゲート５３の出力側は、伝送ゲート５３を介してインバータ５１と伝送ゲート４２との間に接続されている。 Furthermore, the output side of the inverter 52 is connected to the input side of the inverter 51 via the transmission gate 53. That is, the output side of the transmission gate 53 is connected between the inverter 51 and the transmission gate 42 via the transmission gate 53.
　スレーブラッチ４５は、入力された記憶データに対応する電圧レベルを一時的に保持する記憶ノードN11および記憶ノードN12を有しており、これらの記憶ノードN11と記憶ノードN12の間にはインバータ６１が設けられている。 The slave latch 45 has a storage node N11 and a storage node N12 that temporarily hold a voltage level corresponding to the input storage data, and an inverter 61 is interposed between the storage node N11 and the storage node N12. Is provided.
　また、記憶ノードN12には、インバータ４６、インバータ６２、およびストア用ドライバ２４のそれぞれの入力端子が接続されている。 The storage node N12 is connected to input terminals of the inverter 46, the inverter 62, and the store driver 24.
　インバータ４６の出力側は、揮発性記憶部２１の出力端子となっている。 The output side of the inverter 46 is an output terminal of the volatile storage unit 21.
　インバータ６２の出力側は、伝送ゲート６３を介して記憶ノードN11に接続されている。また、伝送ゲート６３の両端には、nMOSトランジスタであるトランジスタ６４が接続されている。換言すれば、トランジスタ６４の一方の端は伝送ゲート６３の入力側に接続され、トランジスタ６４の他方の端は伝送ゲート６３の出力側に接続されている。トランジスタ６４のゲートには、所定電圧レベルの制御信号Rが供給される。 The output side of the inverter 62 is connected to the storage node N11 via the transmission gate 63. A transistor 64 that is an nMOS transistor is connected to both ends of the transmission gate 63. In other words, one end of the transistor 64 is connected to the input side of the transmission gate 63, and the other end of the transistor 64 is connected to the output side of the transmission gate 63. A control signal R having a predetermined voltage level is supplied to the gate of the transistor 64.
　記憶ノードN11には、ストア用ドライバ２２の入力端子も接続されている。 The input terminal of the store driver 22 is also connected to the storage node N11.
　ストア用ドライバ２２は、反転素子であるインバータからなる。すなわち、ストア用ドライバ２２はpMOSトランジスタであるトランジスタ７１と、nMOSトランジスタであるトランジスタ７２とを有している。 The store driver 22 includes an inverter that is an inverting element. That is, the store driver 22 includes a transistor 71 that is a pMOS transistor and a transistor 72 that is an nMOS transistor.
　ストア用ドライバ２２では、トランジスタ７１の一方の端が電源に接続されており、トランジスタ７１の他方の端にはトランジスタ７２が接続されている。 In the store driver 22, one end of the transistor 71 is connected to the power supply, and the transistor 72 is connected to the other end of the transistor 71.
　また、トランジスタ７２における、トランジスタ７１が接続されている端とは反対側の端は、トランジスタ２３を介してグランドに接続されている。トランジスタ２３のゲートには制御信号SR2が供給される。 Further, the end of the transistor 72 opposite to the end to which the transistor 71 is connected is connected to the ground via the transistor 23. A control signal SR2 is supplied to the gate of the transistor 23.
　さらにトランジスタ７１およびトランジスタ７２からなるインバータの出力側の端は、ノードN13を介して不揮発性記憶部２８に接続されている。 Further, the output side end of the inverter composed of the transistor 71 and the transistor 72 is connected to the non-volatile storage unit 28 via the node N13.
　ストア用ドライバ２４は、反転素子であるインバータからなる。すなわち、ストア用ドライバ２４はpMOSトランジスタであるトランジスタ８１と、nMOSトランジスタであるトランジスタ８２とを有している。 The store driver 24 is an inverter that is an inverting element. That is, the store driver 24 includes a transistor 81 that is a pMOS transistor and a transistor 82 that is an nMOS transistor.
　ストア用ドライバ２４では、トランジスタ８１の一方の端が電源に接続されており、トランジスタ８１の他方の端にはトランジスタ８２が接続されている。 In the store driver 24, one end of the transistor 81 is connected to the power source, and the transistor 82 is connected to the other end of the transistor 81.
　また、トランジスタ８２における、トランジスタ８１が接続されている端とは反対側の端は、トランジスタ２５を介してグランドに接続されている。トランジスタ２５のゲートには制御信号SR2が供給される。 Also, the end of the transistor 82 opposite to the end to which the transistor 81 is connected is connected to the ground via the transistor 25. A control signal SR2 is supplied to the gate of the transistor 25.
　さらにトランジスタ８１およびトランジスタ８２からなるインバータの出力側の端は、ノードN14を介して不揮発性記憶部２８に接続されている。 Further, the output side end of the inverter composed of the transistor 81 and the transistor 82 is connected to the nonvolatile storage unit 28 via the node N14.
　不揮発性記憶部２８は、不揮発性の記憶部であり、ストア（書き込み）時には記憶ノードN11および記憶ノードN12における電圧レベルの状態、すなわち記憶データが不揮発性記憶部２８に書き込まれる。 The non-volatile storage unit 28 is a non-volatile storage unit, and at the time of storing (writing), voltage level states at the storage node N11 and the storage node N12, that is, storage data is written into the non-volatile storage unit 28.
　また、リストア（読み出し）時には不揮発性記憶部２８に保持されている記憶データ、すなわち保持されている電圧レベルの状態が、ストア時の経路とは異なる経路で記憶ノードN11および記憶ノードN12へと読み出される。 Further, at the time of restoration (reading), the storage data held in the nonvolatile storage unit 28, that is, the state of the held voltage level is read to the storage node N11 and the storage node N12 through a path different from the path at the time of storage. It is.
　不揮発性記憶部２８は、記憶素子９１および記憶素子９２を有している。 The nonvolatile storage unit 28 includes a storage element 91 and a storage element 92.
　記憶素子９１および記憶素子９２は、例えば磁気抵抗素子であるMTJや、抵抗変化型メモリであるReRAM（Resistive Random Access Memory）などの不揮発性の記憶素子からなる。 The storage element 91 and the storage element 92 are composed of nonvolatile storage elements such as MTJ which is a magnetoresistive element and ReRAM (Resistive Random Access Memory) which is a resistance change type memory.
　なお、以下では、記憶素子９１および記憶素子９２がMTJである場合を例として説明を続ける。 In the following, description will be continued by taking as an example the case where the memory element 91 and the memory element 92 are MTJ.
　MTJは、固定層（p層）およびフリー層（f層）と、それらの固定層およびフリー層の間に形成されたバリア層とからなり、印加される電圧によって抵抗を高抵抗状態または低抵抗状態に変化させることができる不揮発性の記憶素子である。 MTJ consists of a fixed layer (p layer) and a free layer (f layer) and a barrier layer formed between the fixed layer and the free layer. It is a nonvolatile memory element that can be changed to a state.
　したがって、例えば高抵抗状態に対してはより高い電圧レベルであるHレベル、換言すれば記憶データとしての「１」を対応させ、低抵抗状態に対してはより低い電圧レベルであるLレベル、換言すれば記憶データとしての「０」を対応させてMTJに情報を記憶させることができる。 Therefore, for example, an H level that is a higher voltage level is associated with a high resistance state, in other words, “1” as stored data, and an L level that is a lower voltage level is associated with a low resistance state. Then, information can be stored in the MTJ in correspondence with “0” as stored data.
　この実施の形態では、MTJの低抵抗状態をParallel状態（以下、P状態とも称する）と呼び、高抵抗状態をAnti-Parallel状態（以下、AP状態とも称する）と呼ぶこととする。 In this embodiment, the low resistance state of the MTJ is referred to as a Parallel state (hereinafter also referred to as a P state), and the high resistance state is referred to as an Anti-Parallel state (hereinafter also referred to as an AP state).
　不揮発性記憶部２８では、記憶素子９１のフリー層が制御線L11に接続されており、そのフリー層とは反対側、つまり記憶素子９１の固定層がノードN14に接続されている。 In the nonvolatile storage unit 28, the free layer of the storage element 91 is connected to the control line L11, and the side opposite to the free layer, that is, the fixed layer of the storage element 91 is connected to the node N14.
　ノードN14は、ストア用ドライバ２４の出力側の端に接続されているとともに、トランジスタ２６を介して記憶ノードN11にも接続されている。 The node N14 is connected to the output-side end of the store driver 24 and is also connected to the storage node N11 via the transistor 26.
　同様に、記憶素子９２のフリー層は制御線L11に接続されており、記憶素子９２の固定層はノードN13に接続されている。 Similarly, the free layer of the storage element 92 is connected to the control line L11, and the fixed layer of the storage element 92 is connected to the node N13.
　ノードN13は、ストア用ドライバ２２の出力側の端に接続されているとともに、トランジスタ２７を介して記憶ノードN12にも接続されている。 The node N13 is connected to the output-side end of the store driver 22 and is also connected to the storage node N12 via the transistor 27.
　トランジスタ２６およびトランジスタ２７のゲートには制御信号SR1が供給される。 The control signal SR1 is supplied to the gates of the transistor 26 and the transistor 27.
　また、記憶素子９１および記憶素子９２に接続された制御線L11には、その制御線L11における電圧レベルを制御するための制御ドライバ２９が接続されている。 Further, a control driver 29 for controlling a voltage level in the control line L11 is connected to the control line L11 connected to the storage element 91 and the storage element 92.
　制御ドライバ２９は、反転素子であるインバータからなる。すなわち、制御ドライバ２９はpMOSトランジスタであるトランジスタ１０１と、nMOSトランジスタであるトランジスタ１０２とを有している。 The control driver 29 is an inverter that is an inverting element. That is, the control driver 29 includes a transistor 101 that is a pMOS transistor and a transistor 102 that is an nMOS transistor.
　制御ドライバ２９では、トランジスタ１０１の一方の端が電源に接続されており、トランジスタ１０１の他方の端にはトランジスタ１０２および制御線L11が接続されている。 In the control driver 29, one end of the transistor 101 is connected to the power source, and the transistor 102 and the control line L11 are connected to the other end of the transistor 101.
　また、トランジスタ１０２における、トランジスタ１０１および制御線L11が接続されている端とは反対側の端は、トランジスタ３１を介してグランドに接続されている。 Further, the end of the transistor 102 opposite to the end to which the transistor 101 and the control line L11 are connected is connected to the ground via the transistor 31.
　制御ドライバ２９の入力側の端、すなわちトランジスタ１０１のゲート、およびトランジスタ１０２のゲートには、制御信号CTRLが供給される。 The control signal CTRL is supplied to the input side end of the control driver 29, that is, the gate of the transistor 101 and the gate of the transistor 102.
　トランジスタ３１のゲートには、OR回路３０の出力側の端が接続されており、OR回路３０の入力側の端には、制御信号SR1および制御信号SR2が供給される。 The output side end of the OR circuit 30 is connected to the gate of the transistor 31, and the control signal SR1 and the control signal SR2 are supplied to the input side end of the OR circuit 30.
　なお、例えば１つのNVDFF回路１１がメモリを構成する１つのセルとされ、メモリ内に複数のセルが設けられている場合には、ストアモードおよびリストアモードで各NVDFF回路１１内のトランジスタ３１がオン状態となるようにされる。 For example, when one NVDFF circuit 11 is one cell constituting the memory and a plurality of cells are provided in the memory, the transistor 31 in each NVDFF circuit 11 is turned on in the store mode and the restore mode. To be in a state.
　このとき、トランジスタ３１をオン状態とするためのOR回路３０として、複数の全てのセル、すなわち複数の全てのNVDFF回路１１で共通の１つのOR回路を設けるようにしてもよい。 At this time, as the OR circuit 30 for turning on the transistor 31, one OR circuit common to all the plurality of cells, that is, all of the plurality of NVDFF circuits 11, may be provided.
〈NVDFF回路の動作について〉
　次に、図１に示したNVDFF回路１１の動作について説明する。 <Operation of NVDFF circuit>
Next, the operation of the NVDFF circuit 11 shown in FIG. 1 will be described.
　NVDFF回路１１では、動作モードとしてアクティブモード、ストアモード、スリープモード、およびリストアモードの４つの動作モードがある。そして、NVDFF回路１１の動作時にはアクティブモードから順番に、ストアモード、スリープモード、およびリストアモードへと動作モードが遷移していく。 In the NVDFF circuit 11, there are four operation modes, an active mode, a store mode, a sleep mode, and a restore mode. When the NVDFF circuit 11 is operated, the operation mode transitions from the active mode to the store mode, the sleep mode, and the restore mode in order.
　まず、アクティブモードでは、図示せぬPSがオンされる。また、制御信号SR1がHレベルとされてトランジスタ２６およびトランジスタ２７がオンされる。すなわち、トランジスタ２６およびトランジスタ２７がオン状態（導通状態）とされる。このとき、制御信号SR2はLレベルとされる。 First, in the active mode, PS (not shown) is turned on. Further, the control signal SR1 is set to H level, and the transistors 26 and 27 are turned on. That is, the transistor 26 and the transistor 27 are turned on (conductive state). At this time, the control signal SR2 is set to the L level.
　このような状態で、例えばインバータ４１に記憶データとしてLレベルが入力されると、インバータ４１の出力はHレベルとなる。このHレベルは、クロック信号CLKが立ち下がるタイミング、つまり伝送ゲート４２がオンされたタイミングでインバータ５１に入力される。 In this state, for example, when the L level is input as the storage data to the inverter 41, the output of the inverter 41 becomes the H level. This H level is input to the inverter 51 at the timing when the clock signal CLK falls, that is, when the transmission gate 42 is turned on.
　そして、次にクロック信号CLKが立ち上がるタイミングでは、伝送ゲート５３および伝送ゲート４４がオンとなるので、インバータ５１およびインバータ５２のループによって、インバータ５１の出力がLレベルとなる。このLレベルが記憶データとして伝送ゲート４４を介して記憶ノードN11に供給される。 Then, at the timing when the clock signal CLK rises next, the transmission gate 53 and the transmission gate 44 are turned on, so that the output of the inverter 51 becomes L level by the loop of the inverter 51 and the inverter 52. This L level is supplied as storage data to the storage node N11 via the transmission gate 44.
　これにより、記憶ノードN11に接続されたインバータ６１の出力はHレベルとなり、記憶ノードN12に接続されたインバータ４６の出力はLレベルとなる。 Thereby, the output of the inverter 61 connected to the storage node N11 becomes H level, and the output of the inverter 46 connected to the storage node N12 becomes L level.
　その後、クロック信号CLKが立ち下がるタイミングとなると、伝送ゲート５３および伝送ゲート４４がオフされるとともに、伝送ゲート４２および伝送ゲート６３がオンされる。すると、インバータ６１およびインバータ６２からなるループにより、記憶ノードN11に記憶データを示すLレベルが保持（記憶）されるとともに、記憶ノードN12に、記憶データを反転させたHレベルが保持される。 Thereafter, at the timing when the clock signal CLK falls, the transmission gate 53 and the transmission gate 44 are turned off, and the transmission gate 42 and the transmission gate 63 are turned on. Then, the loop composed of inverter 61 and inverter 62 holds (stores) the L level indicating the stored data at storage node N11, and holds the H level obtained by inverting the stored data at storage node N12.
　このようにして入力された記憶データがスレーブラッチ４５にラッチされると、クロック信号CLKのトグルが停止される。 When the storage data input in this way is latched by the slave latch 45, the toggle of the clock signal CLK is stopped.
　続いて、ストアモードでは、制御信号SR1がLレベルとされてトランジスタ２６およびトランジスタ２７がオフ状態とされるとともに、制御信号SR2がHレベルとされてトランジスタ２３およびトランジスタ２５がオン状態とされる。 Subsequently, in the store mode, the control signal SR1 is set to L level and the transistors 26 and 27 are turned off, and the control signal SR2 is set to H level and the transistors 23 and 25 are turned on.
　このとき、制御信号SR1と制御信号SR2が供給（入力）されるOR回路３０の出力はHレベルとなるので、そのHレベルがゲートに供給されるトランジスタ３１はオン状態となる。 At this time, since the output of the OR circuit 30 to which the control signal SR1 and the control signal SR2 are supplied (input) becomes the H level, the transistor 31 to which the H level is supplied to the gate is turned on.
　すると、記憶ノードN11の状態はLレベルであるので、その記憶ノードN11に接続されたストア用ドライバ２２では、トランジスタ７１がオン状態となって、ストア用ドライバ２２の出力端、すなわちノードN13はHレベルとなる。 Then, since the state of the storage node N11 is L level, the transistor 71 is turned on in the store driver 22 connected to the storage node N11, and the output terminal of the store driver 22, that is, the node N13 is H Become a level.
　これに対して、記憶ノードN12の状態はHレベルであるので、その記憶ノードN12に接続されたストア用ドライバ２４では、トランジスタ８２がオン状態となって、ストア用ドライバ２４の出力端、すなわちノードN14はLレベルとなる。 On the other hand, since the state of the storage node N12 is at the H level, in the store driver 24 connected to the storage node N12, the transistor 82 is turned on, and the output terminal of the store driver 24, that is, the node N14 becomes L level.
　さらに、このタイミングで、例えば制御信号CTRLをLレベルとすると、制御ドライバ２９ではトランジスタ１０１がオン状態とされて、制御ドライバ２９の出力端、すなわち制御線L11がHレベルとなる。 Further, at this timing, for example, when the control signal CTRL is set to the L level, the transistor 101 is turned on in the control driver 29, and the output terminal of the control driver 29, that is, the control line L11 is set to the H level.
　このとき、制御線L11はHレベルであり、ノードN14はLレベルであるから、制御ドライバ２９に接続された電源から、制御ドライバ２９、制御線L11、記憶素子９１、ノードN14、トランジスタ８２、およびトランジスタ２５を通ってグランドへとストア電流が流れる。 At this time, since the control line L11 is at the H level and the node N14 is at the L level, the control driver 29, the control line L11, the storage element 91, the node N14, the transistor 82, and the power supply connected to the control driver 29 Store current flows through transistor 25 to ground.
　この場合、記憶素子９１では、制御線L11側に接続されたフリー層から、ノードN14側に接続された固定層へと電流（ストア電流）が流れるので、記憶素子９１は低抵抗状態、すなわちP状態となる。 In this case, in the storage element 91, current (store current) flows from the free layer connected to the control line L11 side to the fixed layer connected to the node N14 side, so that the storage element 91 is in a low resistance state, that is, P It becomes a state.
　これにより、記憶ノードN12に保持されている状態「Hレベル」が、ストア用ドライバ２４により反転されて記憶素子９１に保持（記憶）されたことになる。換言すれば、記憶ノードN12に保持されている状態「Hレベル」が反転されて記憶素子９１に書き込まれた（ストアされた）ことになる。 Thus, the state “H level” held in the storage node N12 is inverted by the store driver 24 and held (stored) in the storage element 91. In other words, the state “H level” held in the storage node N12 is inverted and written (stored) in the storage element 91.
　その後、さらに制御信号CTRLがLレベルである状態からHレベルである状態へと切り替えられると、制御ドライバ２９ではトランジスタ１０１がオフされて、トランジスタ１０２がオン状態とされる。その結果、制御ドライバ２９の出力端、すなわち制御線L11がグランドに接続されてLレベルとなる。 Thereafter, when the control signal CTRL is further switched from the L level to the H level, the control driver 29 turns off the transistor 101 and turns on the transistor 102. As a result, the output terminal of the control driver 29, that is, the control line L11 is connected to the ground and becomes L level.
　すると、制御線L11がLレベルであり、ノードN13はHレベルであるから、ストア用ドライバ２２に接続された電源から、トランジスタ７１、ノードN13、記憶素子９２、制御線L11、トランジスタ１０２、およびトランジスタ３１を通ってグランドへとストア電流が流れる。 Then, since the control line L11 is at the L level and the node N13 is at the H level, the transistor 71, the node N13, the storage element 92, the control line L11, the transistor 102, and the transistor are connected from the power source connected to the store driver 22. Store current flows through 31 to ground.
　この場合、記憶素子９２では、ノードN13側に接続された固定層から、制御線L11側に接続されたフリー層へと電流（ストア電流）が流れるので、記憶素子９２は高抵抗状態、すなわちAP状態となる。 In this case, in the memory element 92, a current (store current) flows from the fixed layer connected to the node N13 side to the free layer connected to the control line L11 side, so that the memory element 92 is in a high resistance state, that is, AP It becomes a state.
　これにより、記憶ノードN11に保持されている状態「Lレベル」が、ストア用ドライバ２２により反転されて記憶素子９２に保持されたことになる。換言すれば、記憶ノードN11に保持されている状態「Lレベル」が反転されて記憶素子９２に書き込まれたことになる。 Thus, the state “L level” held in the storage node N11 is inverted by the store driver 22 and held in the storage element 92. In other words, the state “L level” held in the storage node N11 is inverted and written to the storage element 92.
　このようにして記憶ノードN11および記憶ノードN12における電圧レベルの状態が記憶素子９２および記憶素子９１にストアされると、その後、制御信号CTRLがLレベルとされてストア動作が終了する。 When the voltage level states at the storage node N11 and the storage node N12 are stored in the storage element 92 and the storage element 91 in this way, the control signal CTRL is then set to the L level, and the store operation ends.
　以上において説明したストア動作では、例えば図２に示す経路でストア電流が流れる。なお、図２において図１における場合と対応する部分には同一の符号を付してあり、その説明は適宜省略する。 In the store operation described above, for example, a store current flows through the path shown in FIG. In FIG. 2, the same reference numerals are given to the portions corresponding to those in FIG. 1, and the description thereof will be omitted as appropriate.
　図２の例では、上述のストア動作時におけるストア電流の経路（以下、ストア経路とも称する）が示されている。 In the example of FIG. 2, a store current path (hereinafter also referred to as a store path) during the above-described store operation is shown.
　特に、折れ線L21は、制御信号CTRLをLレベルとしたタイミングでの記憶素子９１への情報（状態）のストア時のストア経路を示している。この折れ線L21により示されるストア経路上には、トランジスタ１０１、記憶素子９１、トランジスタ８２、およびトランジスタ２５が配置されている。 Particularly, the broken line L21 indicates a store path when information (state) is stored in the storage element 91 at the timing when the control signal CTRL is set to the L level. The transistor 101, the storage element 91, the transistor 82, and the transistor 25 are arranged on the store path indicated by the broken line L21.
　これに対して、折れ線L22は、制御信号CTRLをHレベルとしたタイミングでの記憶素子９２への情報（状態）のストア時のストア経路を示している。この折れ線L22により示されるストア経路上には、トランジスタ７１、記憶素子９２、トランジスタ１０２、およびトランジスタ３１が配置されている。 On the other hand, the broken line L22 indicates a store path at the time of storing information (state) to the storage element 92 at the timing when the control signal CTRL is set to the H level. The transistor 71, the storage element 92, the transistor 102, and the transistor 31 are arranged on the store path indicated by the broken line L22.
　ところで、例えば国際公開第２０１６／１８５９０３号（以下、文献１とも称する）では、ストア経路とリストア経路が互いに異なるNVDFF回路が提案されている。 Incidentally, for example, International Publication No. 2016/185903 (hereinafter also referred to as Document 1) proposes NVDFF circuits having different store paths and restore paths.
　そのようなNVDFF回路では、NVDFF回路１１におけるトランジスタ２３やトランジスタ２５、トランジスタ３１、OR回路３０は設けられていない。また、そのNVDFF回路では、ストア経路上である、ストア用ドライバ２２と記憶素子９２の間に相当する位置、およびストア用ドライバ２４と記憶素子９１の間に相当する位置にトランジスタが設けられている。 In such an NVDFF circuit, the transistor 23, the transistor 25, the transistor 31, and the OR circuit 30 in the NVDFF circuit 11 are not provided. In the NVDFF circuit, transistors are provided on the store path at a position corresponding to between the store driver 22 and the storage element 92 and at a position corresponding to between the store driver 24 and the storage element 91. .
　この場合、それらの２つのトランジスタの何れか一方は、必ずトランジスタに対してグランド側にMTJが接続されたソース接続となってしまう。 In this case, either one of these two transistors will always be a source connection in which the MTJ is connected to the ground side with respect to the transistor.
　そのため、ソース接続となっているトランジスタを介してMTJにストア電流が流れるときに、バックバイアス効果によりストア電流が小さくなってしまう。したがって、十分な大きさのストア電流を確保しようとすると、トランジスタのゲート幅を広くしなければならなくなり、回路規模が大きくなってしまう。 Therefore, when the store current flows through the MTJ through the source-connected transistor, the store current is reduced due to the back bias effect. Therefore, if a sufficiently large store current is to be ensured, the gate width of the transistor must be increased, resulting in an increase in circuit scale.
　これに対して、NVDFF回路１１では、ストア用ドライバ２２、ストア用ドライバ２４、および制御ドライバ２９のそれぞれと、グランドとの間にトランジスタ２３、トランジスタ２５、およびトランジスタ３１のそれぞれが設けられている。 On the other hand, in the NVDFF circuit 11, the transistor 23, the transistor 25, and the transistor 31 are provided between the store driver 22, the store driver 24, and the control driver 29 and the ground, respectively.
　そのため、NVDFF回路１１では、ストア用ドライバ２２と記憶素子９２の間や、ストア用ドライバ２４と記憶素子９１の間にトランジスタを設ける必要がない。 Therefore, in the NVDFF circuit 11, it is not necessary to provide a transistor between the store driver 22 and the storage element 92 or between the store driver 24 and the storage element 91.
　結果として、NVDFF回路１１では、ストア経路にはソース接続のトランジスタが配置されておらず、ストア経路にあるトランジスタは、全てトランジスタに対してグランド側とは反対側に記憶素子が接続されたドレイン接続となっている。 As a result, in the NVDFF circuit 11, no source-connected transistors are arranged in the store path, and all the transistors in the store path are connected to the drain connected to the storage element on the opposite side to the ground side. It has become.
　具体的には、例えば折れ線L21により示されるストア経路に配置されたトランジスタ２５は、ドレイン側（電源側）に記憶素子９１が接続されたドレイン接続となっている。 Specifically, for example, the transistor 25 arranged in the store path indicated by the broken line L21 has a drain connection in which the storage element 91 is connected to the drain side (power supply side).
　同様に、折れ線L22により示されるストア経路に配置されたトランジスタ３１もドレイン側に記憶素子９２が接続されたドレイン接続となっている。さらに、ストア時においてトランジスタ２３にストア電流が流れる場合には、記憶素子９２からトランジスタ２３を通ってグランドへとストア電流が流れるので、この場合にはトランジスタ２３はドレイン接続となる。 Similarly, the transistor 31 arranged in the store path indicated by the broken line L22 also has a drain connection in which the storage element 92 is connected to the drain side. Further, when a store current flows through the transistor 23 during storage, the store current flows from the storage element 92 through the transistor 23 to the ground. In this case, the transistor 23 is connected to the drain.
　したがって、NVDFF回路１１では、バックバイアス効果によりストア電流が小さくなってしまうことがないので、ゲート幅の狭いトランジスタを用いても十分なストア電流を確保することができ、NVDFF回路１１全体の回路規模も小さく抑えることができる。 Therefore, in the NVDFF circuit 11, the store current is not reduced due to the back bias effect, so that a sufficient store current can be ensured even if a transistor having a narrow gate width is used, and the circuit scale of the entire NVDFF circuit 11 is ensured. Can be kept small.
　しかも、NVDFF回路１１では、ストア時にスレーブラッチ４５の記憶ノードの電圧レベルをストア用ドライバで受けて、その出力を記憶ノードの電圧レベルに影響を与えない経路で記憶素子に書き込む構造となっているため、ラッチ破壊が生じない。つまり、安定した書き込みを行うことができる。 Moreover, the NVDFF circuit 11 has a structure in which the voltage level of the storage node of the slave latch 45 is received by the store driver at the time of store, and the output is written to the storage element through a path that does not affect the voltage level of the storage node. Therefore, latch breakdown does not occur. That is, stable writing can be performed.
　これらのことから、NVDFF回路１１によれば、安定な書き込みを維持しつつ、小型で消費電力の低いNVDFF回路１１が得られることが分かる。 From these facts, it can be seen that the NVDFF circuit 11 can provide a small NVDFF circuit 11 with low power consumption while maintaining stable writing.
　NVDFF回路１１の動作の説明に戻り、ストアモードで記憶素子９１および記憶素子９２に記憶ノードN12および記憶ノードN11の状態がストアされると、その後、適切なタイミングでスリープモードへと遷移する。 Returning to the description of the operation of the NVDFF circuit 11, when the states of the storage node N12 and the storage node N11 are stored in the storage element 91 and the storage element 92 in the store mode, the state transits to the sleep mode at an appropriate timing.
　スリープモードでは、図示せぬPSがオフされて、NVDFF回路１１へと供給される電源が遮断される。これにより、インバータ４６の出力側の電圧レベルはLレベルとなる。 In the sleep mode, the PS (not shown) is turned off, and the power supplied to the NVDFF circuit 11 is shut off. As a result, the voltage level on the output side of the inverter 46 becomes L level.
　その後、スリープ状態から復帰する際に、リストアモードでの動作（リストア動作）が行われる。 After that, when returning from the sleep state, the operation in the restore mode (restore operation) is performed.
　リストアモードでは、制御信号SR1がHレベルとされてトランジスタ２６およびトランジスタ２７がオン状態とされるとともに、制御信号SR2がLレベルとされてトランジスタ２３およびトランジスタ２５がオフ状態（非導通状態）とされる。 In the restore mode, the control signal SR1 is set to H level to turn on the transistors 26 and 27, and the control signal SR2 is set to L level to turn off the transistors 23 and 25 (non-conductive state). The
　このとき、制御信号SR1がHレベルであり、制御信号SR2がLレベルであるのでOR回路３０の出力はHレベルとなり、トランジスタ３１はオン状態となる。 At this time, since the control signal SR1 is at the H level and the control signal SR2 is at the L level, the output of the OR circuit 30 is at the H level, and the transistor 31 is turned on.
　さらに制御信号CTRLはHレベルとされて制御ドライバ２９のトランジスタ１０２がオン状態とされ、制御線L11がグランドに接続される。すなわち、制御線L11がLレベルとなる。 Further, the control signal CTRL is set to H level, the transistor 102 of the control driver 29 is turned on, and the control line L11 is connected to the ground. That is, the control line L11 becomes L level.
　このような状態からPSがオンされると、電源電圧の供給されたスレーブラッチ４５側から記憶素子９１および記憶素子９２を通って制御線L11へとリストア電流が流れる。 When PS is turned on from such a state, a restore current flows from the slave latch 45 supplied with the power supply voltage to the control line L11 through the storage element 91 and the storage element 92.
　ここでは、上述の例のように記憶素子９１が低抵抗状態、すなわちP状態であり、記憶素子９２が高抵抗状態、すなわちAP状態であるとする。 Here, it is assumed that the storage element 91 is in the low resistance state, that is, the P state, and the storage element 92 is in the high resistance state, that is, the AP state, as in the above example.
　そのような場合、図３に示すように折れ線L41乃至折れ線L44の４つの経路（以下、リストア経路とも称する）を通ってリストア電流が流れることになる。 In such a case, as shown in FIG. 3, a restore current flows through four paths (hereinafter also referred to as a restore path) of broken lines L41 to L44.
　図３では、折れ線L41により示されるリストア経路は、電源からトランジスタ８１、ノードN14、記憶素子９１、制御線L11、トランジスタ１０２、およびトランジスタ３１を通ってグランドへとリストア電流が流れる経路である。 In FIG. 3, the restore path indicated by the broken line L41 is a path through which a restore current flows from the power source to the ground through the transistor 81, the node N14, the storage element 91, the control line L11, the transistor 102, and the transistor 31.
　折れ線L42により示されるリストア経路は、インバータ６２から伝送ゲート６３、トランジスタ２６、ノードN14、記憶素子９１、制御線L11、トランジスタ１０２、およびトランジスタ３１を通ってグランドへとリストア電流が流れる経路である。 The restore path indicated by the broken line L42 is a path through which a restore current flows from the inverter 62 to the ground through the transmission gate 63, the transistor 26, the node N14, the storage element 91, the control line L11, the transistor 102, and the transistor 31.
　また、折れ線L43により示されるリストア経路は、電源からトランジスタ７１、ノードN13、記憶素子９２、制御線L11、トランジスタ１０２、およびトランジスタ３１を通ってグランドへとリストア電流が流れる経路である。 The restore path indicated by the broken line L43 is a path through which a restore current flows from the power source to the ground through the transistor 71, the node N13, the storage element 92, the control line L11, the transistor 102, and the transistor 31.
　折れ線L44により示されるリストア経路は、インバータ６１からトランジスタ２７、ノードN13、記憶素子９２、制御線L11、トランジスタ１０２、およびトランジスタ３１を通ってグランドへとリストア電流が流れる経路である。 The restore path indicated by the broken line L44 is a path through which a restore current flows from the inverter 61 to the ground through the transistor 27, the node N13, the storage element 92, the control line L11, the transistor 102, and the transistor 31.
　このようにして各リストア経路でリストア電流が流れると、記憶素子９１と記憶素子９２の電気抵抗の差により、ノードN13の電圧はノードN14の電圧よりも上昇する。 Thus, when a restore current flows through each restore path, the voltage at the node N13 rises higher than the voltage at the node N14 due to the difference in electrical resistance between the memory element 91 and the memory element 92.
　そうすると、トランジスタ２７はトランジスタ２６よりもソース電圧上昇によるコンダクタンス低下が著しく現れることになる。そのため、記憶素子９１と記憶素子９２の抵抗の差以上に、トランジスタ２７を流れる電流はトランジスタ２６を流れる電流よりも小さくなる。 As a result, the transistor 27 has a significantly lower conductance than the transistor 26 due to an increase in the source voltage. Therefore, the current flowing through the transistor 27 is smaller than the current flowing through the transistor 26 more than the difference in resistance between the memory element 91 and the memory element 92.
　その結果、記憶ノードN12の電圧は記憶ノードN11の電圧よりも上昇し、スレーブラッチ４５内のインバータ６１とインバータ６２からなるループで正帰還がかかって、記憶ノードN12は電源電圧（Hレベル）となり、記憶ノードN11はグランドレベル（Lレベル）となる。すなわち、ストア時における記憶ノードN11および記憶ノードN12の電圧レベルの状態と同じ状態に復帰する。 As a result, the voltage at the storage node N12 rises higher than the voltage at the storage node N11, positive feedback is applied in the loop composed of the inverter 61 and the inverter 62 in the slave latch 45, and the storage node N12 becomes the power supply voltage (H level). The storage node N11 is at the ground level (L level). That is, the storage node N11 and the storage node N12 are restored to the same voltage level state at the time of storage.
　例えば文献１に記載のNVDFF回路では、NVDFF回路１１におけるトランジスタ２３やトランジスタ２５に相当する素子は設けられていない。これに対してNVDFF回路１１では、トランジスタ２３やトランジスタ２５を設けることで、リストア時に無駄な電力消費をせずに、リストア時間を短縮できるようになっている。 For example, in the NVDFF circuit described in Document 1, elements corresponding to the transistor 23 and the transistor 25 in the NVDFF circuit 11 are not provided. On the other hand, the NVDFF circuit 11 is provided with the transistor 23 and the transistor 25, so that the restoration time can be shortened without wasteful power consumption during restoration.
　例えば、仮にNVDFF回路１１においてトランジスタ２３が設けられていないとする。そのような場合、リストア時に、図３の折れ線L42により示される経路でリストア電流が流れると、ストア用ドライバ２２の入力端は電源電圧とグランドレベルとの中間の電圧となってしまい、トランジスタ７１およびトランジスタ７２の両方がオン状態となってしまう。 For example, assume that the transistor 23 is not provided in the NVDFF circuit 11. In such a case, when a restore current flows through the path indicated by the broken line L42 in FIG. 3 at the time of restoration, the input terminal of the store driver 22 becomes an intermediate voltage between the power supply voltage and the ground level. Both transistors 72 are turned on.
　そうすると、ストア用ドライバ２２では、電源からトランジスタ７１およびトランジスタ７２を通ってグランドへと大きな電流が流れることになり、消費電力が増大してしまうことになる。 Then, in the store driver 22, a large current flows from the power source through the transistor 71 and the transistor 72 to the ground, and the power consumption increases.
　しかし、実際には、NVDFF回路１１にはトランジスタ２３が設けられており、リストア動作時にはトランジスタ２３はオフ状態とされている。そのため、ストア用ドライバ２２では電源からグランドへと無駄な電流が流れてしまうことはなく、電源からは折れ線L43により示される経路で電流が流れ、その電流はリストア電流となる。 However, actually, the NVDFF circuit 11 is provided with the transistor 23, and the transistor 23 is in the off state during the restore operation. For this reason, in the store driver 22, useless current does not flow from the power source to the ground, but current flows from the power source along the path indicated by the broken line L 43, and the current becomes a restore current.
　このようなストア用ドライバ２２における場合と同様のことがストア用ドライバ２４でも生じ、ストア用ドライバ２４では折れ線L41により示される経路で流れる電流がリストア電流となる。 The same thing as in the store driver 22 occurs in the store driver 24. In the store driver 24, the current flowing through the path indicated by the broken line L41 becomes the restore current.
　したがって、NVDFF回路１１では、従来は折れ線L42および折れ線L44により示される経路でのみリストア電流が流れていたところを、さらにそれらに加えて折れ線L41および折れ線L43により示される経路でもリストア電流が流れるようになる。 Therefore, in the NVDFF circuit 11, the restore current flows only in the path indicated by the polygonal line L 42 and the polygonal line L 44 in the related art so that the restore current also flows in the path indicated by the polygonal line L 41 and the polygonal line L 43 in addition to them. Become.
　その結果、全体としてリストア電流がより大きくなるので、記憶ノードN11および記憶ノードN12の電圧レベルがストア時の状態に復帰するまでの時間をより短くすることができる。換言すれば、リストア時のショートサーキットが記憶ノードの充電に利用されるようになるので、無駄な電力消費を低減させ、かつリストア時間を短縮することができる。 As a result, since the restore current becomes larger as a whole, the time until the voltage levels of the storage node N11 and the storage node N12 return to the store state can be further shortened. In other words, since the short circuit at the time of restoration is used for charging the storage node, useless power consumption can be reduced and the restoration time can be shortened.
　以上のようにしてリストアが完了すると、その後は、以上において説明したアクティブモード、ストアモード、スリープモード、およびリストアモードの各モードの動作が、入力される記憶データに応じて行われる。 When the restoration is completed as described above, the operations of the active mode, the store mode, the sleep mode, and the restore mode described above are performed according to the input storage data.
　以上のように、NVDFF回路１１によれば、安定な書き込みを維持しつつ、小型化を実現し、消費電力を低く抑えることができる。 As described above, according to the NVDFF circuit 11, it is possible to achieve downsizing and keep power consumption low while maintaining stable writing.
〈第２の実施の形態〉
〈NVDFF回路の構成例〉
　なお、以上においては、本技術をヘッダ型のSSR-NVFF回路方式のNVDFF回路に適用する例について説明したが、本技術はフッタ型のSSR-NVFF回路方式のNVDFF回路にも適用することが可能である。 <Second Embodiment>
<Configuration example of NVDFF circuit>
In the above, an example in which the present technology is applied to a header type SSR-NVFF circuit type NVDFF circuit has been described. However, the present technology can also be applied to a footer type SSR-NVFF circuit type NVDFF circuit. It is.
　そのような場合、NVDFF回路は、例えば図４に示すように構成される。なお、図４において図１における場合と対応する部分には同一の符号を付してあり、その説明は適宜省略する。 In such a case, the NVDFF circuit is configured as shown in FIG. 4, for example. In FIG. 4, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted as appropriate.
　図４に示すNVDFF回路２０１は、フッタ型のSSR-NVFF回路方式のNVDFF回路である。 The NVDFF circuit 201 shown in FIG. 4 is an NVDFF circuit of a footer type SSR-NVFF circuit system.
　NVDFF回路２０１では、PGにはPSとして図示せぬnMOSトランジスタが用いられる。具体的には、例えばPSがオンされるとNVDFF回路２０１の各部は、nMOSトランジスタを介してグランドに接続され、PSがオフされるとNVDFF回路２０１の各部はグランドから電気的に切り離されてPGが実現される。 In the NVDFF circuit 201, an nMOS transistor (not shown) is used for PG. Specifically, for example, when the PS is turned on, each part of the NVDFF circuit 201 is connected to the ground via the nMOS transistor, and when the PS is turned off, each part of the NVDFF circuit 201 is electrically disconnected from the ground and PG Is realized.
　NVDFF回路２０１は、揮発性記憶部２１、ストア用ドライバ２２、トランジスタ２３、ストア用ドライバ２４、トランジスタ２５、トランジスタ２１１、トランジスタ２１２、不揮発性記憶部２１３、制御ドライバ２９、XNOR回路２１４、およびトランジスタ３１を有している。 The NVDFF circuit 201 includes a volatile storage unit 21, a store driver 22, a transistor 23, a store driver 24, a transistor 25, a transistor 211, a transistor 212, a nonvolatile storage unit 213, a control driver 29, an XNOR circuit 214, and a transistor 31. have.
　NVDFF回路２０１の回路構成は、NVDFF回路１１におけるトランジスタ２６、トランジスタ２７、不揮発性記憶部２８、およびOR回路３０に代えて、トランジスタ２１１、トランジスタ２１２、不揮発性記憶部２１３、およびXNOR回路２１４を設けた構成となっている。 The circuit configuration of the NVDFF circuit 201 includes a transistor 211, a transistor 212, a nonvolatile memory unit 213, and an XNOR circuit 214 instead of the transistor 26, the transistor 27, the nonvolatile memory unit 28, and the OR circuit 30 in the NVDFF circuit 11. It becomes the composition.
　また、不揮発性記憶部２１３は、MTJやReRAMなどからなる記憶素子２２１および記憶素子２２２を有している。以下では、記憶素子２２１および記憶素子２２２がMTJであるものとして説明を続ける。 The nonvolatile storage unit 213 includes a storage element 221 and a storage element 222 made of MTJ, ReRAM, or the like. Hereinafter, the description will be continued assuming that the memory element 221 and the memory element 222 are MTJ.
　NVDFF回路２０１においては、記憶ノードN11とノードN14の間にトランジスタ２１１が設けられており、記憶ノードN12とノードN13の間にトランジスタ２１２が設けられている。これらのトランジスタ２１１およびトランジスタ２１２は、pMOSトランジスタであり、トランジスタ２１１およびトランジスタ２１２のゲートには制御信号SR1が供給される。 In the NVDFF circuit 201, a transistor 211 is provided between the storage node N11 and the node N14, and a transistor 212 is provided between the storage node N12 and the node N13. The transistors 211 and 212 are pMOS transistors, and a control signal SR1 is supplied to the gates of the transistors 211 and 212.
　また、記憶素子２２１の固定層（p層）は制御線L11に接続されており、記憶素子２２１のフリー層（f層）はノードN14に接続されている。さらに、記憶素子２２２の固定層が制御線L11に接続されており、記憶素子２２２のフリー層はノードN13に接続されている。 Further, the fixed layer (p layer) of the storage element 221 is connected to the control line L11, and the free layer (f layer) of the storage element 221 is connected to the node N14. Further, the fixed layer of the storage element 222 is connected to the control line L11, and the free layer of the storage element 222 is connected to the node N13.
　NVDFF回路２０１においても、NVDFF回路１１における場合と同様に、ストア経路にあるトランジスタは全てドレイン接続となっている。 In the NVDFF circuit 201, as in the NVDFF circuit 11, all transistors in the store path are connected to the drain.
　すなわち、ストア経路に配置されたトランジスタ２５およびトランジスタ２３はドレイン側に記憶素子２２１および記憶素子２２２が接続されたドレイン接続となっている。同様に、ストア経路に配置されたトランジスタ３１もドレイン側に記憶素子２２１や記憶素子２２２が接続されたドレイン接続となっている。 That is, the transistor 25 and the transistor 23 arranged in the store path have a drain connection in which the storage element 221 and the storage element 222 are connected to the drain side. Similarly, the transistor 31 arranged in the store path has a drain connection in which the storage element 221 and the storage element 222 are connected to the drain side.
　また、XNOR回路２１４の入力端には制御信号SR1および制御信号SR2が供給され、XNOR回路２１４の出力端はトランジスタ３１に接続されている。 Further, the control signal SR1 and the control signal SR2 are supplied to the input terminal of the XNOR circuit 214, and the output terminal of the XNOR circuit 214 is connected to the transistor 31.
〈NVDFF回路の動作について〉
　次に、図４に示したNVDFF回路２０１の動作について説明する。 <Operation of NVDFF circuit>
Next, the operation of the NVDFF circuit 201 shown in FIG. 4 will be described.
　NVDFF回路２０１では、アクティブモード時には上述したNVDFF回路１１と同様の動作が行われる。 The NVDFF circuit 201 performs the same operation as that of the NVDFF circuit 11 described above in the active mode.
　また、ストアモードでは、制御信号SR1がHレベルとされてトランジスタ２１１およびトランジスタ２１２がオフ状態とされるとともに、制御信号SR2がHレベルとされてトランジスタ２３およびトランジスタ２５がオン状態とされる。 In the store mode, the control signal SR1 is set to H level to turn off the transistors 211 and 212, and the control signal SR2 is set to H level to turn on the transistors 23 and 25.
　このとき、制御信号SR1と制御信号SR2が供給されるXNOR回路２１４の出力はHレベルとなるので、そのHレベルがゲートに供給されるトランジスタ３１はオン状態となる。 At this time, since the output of the XNOR circuit 214 to which the control signal SR1 and the control signal SR2 are supplied becomes H level, the transistor 31 to which the H level is supplied to the gate is turned on.
　さらに、例えば制御信号CTRLがHレベルとされ、その後、制御信号CTRLがLレベルとされて記憶ノードの状態が不揮発性記憶部２１３にストアされる。 Further, for example, the control signal CTRL is set to H level, and then the control signal CTRL is set to L level, and the state of the storage node is stored in the nonvolatile storage unit 213.
　すなわち、例えば記憶ノードN11の状態がLレベルであり、記憶ノードN12の状態がHレベルであったとする。 That is, for example, it is assumed that the state of the storage node N11 is L level and the state of the storage node N12 is H level.
　このような状態では、ストア用ドライバ２２のトランジスタ７１がオン状態となってノードN13はHレベルとなり、ストア用ドライバ２４のトランジスタ８２がオン状態となってノードN14はLレベルとなる。 In such a state, the transistor 71 of the store driver 22 is turned on and the node N13 becomes H level, and the transistor 82 of the store driver 24 is turned on and the node N14 becomes L level.
　このとき、制御信号CTRLがHレベルとされて制御線L11がLレベルとなると、記憶素子２２２ではノードN13側から制御線L11側へとストア電流が流れて記憶素子２２２が低抵抗状態（P状態）となる。これにより、記憶ノードN11の電圧レベルの状態がストア用ドライバ２２によりそのまま記憶素子２２２に保持（ストア）されたことになる。 At this time, when the control signal CTRL is set to H level and the control line L11 is set to L level, a storage current flows from the node N13 side to the control line L11 side in the storage element 222, and the storage element 222 is in a low resistance state (P state). ) As a result, the voltage level state of the storage node N11 is held (stored) in the storage element 222 as it is by the store driver 22.
　また、制御信号CTRLがLレベルとされて制御線L11がHレベルとなると、記憶素子２２１では制御線L11側からノードN14側へとストア電流が流れて記憶素子２２１が高抵抗状態（AP状態）となる。これにより、記憶ノードN12の電圧レベルの状態がストア用ドライバ２４によりそのまま記憶素子２２１に保持（ストア）されたことになる。 Further, when the control signal CTRL is set to the L level and the control line L11 is set to the H level, the storage current flows from the control line L11 side to the node N14 side in the storage element 221, and the storage element 221 is in the high resistance state (AP state). It becomes. As a result, the state of the voltage level of the storage node N12 is held (stored) in the storage element 221 as it is by the store driver 24.
　NVDFF回路２０１においてもNVDFF回路１１における場合と同様に、ストア経路にはソース接続のトランジスタが配置されておらず、ストア経路にあるトランジスタは、全てドレイン接続となっている。すなわち、トランジスタ２３、トランジスタ２５、およびトランジスタ３１はドレイン接続となっている。 In the NVDFF circuit 201, similarly to the case of the NVDFF circuit 11, no source-connected transistors are arranged in the store path, and all the transistors in the store path are drain-connected. That is, the transistor 23, the transistor 25, and the transistor 31 are drain connected.
　ストアモードでの動作が終了し、スリープモードへと遷移すると図示せぬPSがオフされてPGが実現される。そして、その後、スリープ状態から復帰する際に、リストアモードでの動作が行われる。 When the operation in the store mode is completed and the mode is changed to the sleep mode, the PS (not shown) is turned off and the PG is realized. After that, when returning from the sleep state, the operation in the restore mode is performed.
　リストアモードでは、制御信号SR1がLレベルとされてトランジスタ２１１およびトランジスタ２１２がオン状態とされるとともに、制御信号SR2がLレベルとされてトランジスタ２３およびトランジスタ２５がオフ状態とされる。 In the restore mode, the control signal SR1 is set to the L level and the transistors 211 and 212 are turned on, and the control signal SR2 is set to the L level and the transistors 23 and 25 are turned off.
　このとき、制御信号SR1がLレベルであり、制御信号SR2がLレベルであるのでXNOR回路２１４の出力はHレベルとなり、トランジスタ３１はオン状態となる。 At this time, since the control signal SR1 is at the L level and the control signal SR2 is at the L level, the output of the XNOR circuit 214 is at the H level, and the transistor 31 is turned on.
　さらに制御信号CTRLはLレベルとされて制御ドライバ２９のトランジスタ１０１がオン状態とされ、制御線L11が電源に接続される。すなわち、制御線L11がHレベルとなる。 Further, the control signal CTRL is set to L level, the transistor 101 of the control driver 29 is turned on, and the control line L11 is connected to the power source. That is, the control line L11 becomes H level.
　このような状態からPSがオンされるとリストア電流が流れる。 When the PS is turned on from such a state, a restore current flows.
　ここでは、上述の例のように記憶素子２２１が高抵抗状態（AP状態）であり、記憶素子２２２が低抵抗状態（P状態）であるとする。 Here, it is assumed that the memory element 221 is in the high resistance state (AP state) and the memory element 222 is in the low resistance state (P state) as in the above example.
　スリープ状態では、グランドへの電流経路が遮断されているため、回路内部のノードの電圧はリークによって電源電圧に近い電圧まで上昇しているが、PSをオンすると、スレーブラッチ４５にグランドの電圧が供給される。これにより、制御線L11から記憶素子２２１および記憶素子２２２を通ってスレーブラッチ４５側へと、リストア電流が流れる。 In the sleep state, since the current path to the ground is interrupted, the voltage of the node inside the circuit rises to a voltage close to the power supply voltage due to leakage, but when the PS is turned on, the ground voltage is applied to the slave latch 45. Supplied. Thereby, a restore current flows from the control line L11 through the storage element 221 and the storage element 222 to the slave latch 45 side.
　この例では、記憶素子２２１が高抵抗状態であり、記憶素子２２２が低抵抗状態であるので、リストア電流が流れると記憶素子２２１と記憶素子２２２の電気抵抗の差により、ノードN14の電圧はノードN13の電圧よりも低下する。 In this example, since the memory element 221 is in the high resistance state and the memory element 222 is in the low resistance state, the voltage of the node N14 is set to the node due to the difference in electrical resistance between the memory element 221 and the memory element 222 when the restore current flows. Lower than the voltage of N13.
　そのため、トランジスタ２１１はトランジスタ２１２よりもソース電圧低下によるコンダクタンス低下が著しく現れることになる。これにより、記憶素子２２１と記憶素子２２２の抵抗の差以上に、トランジスタ２１１を流れる電流はトランジスタ２１２を流れる電流よりも小さくなる。 Therefore, in the transistor 211, a decrease in conductance due to a decrease in source voltage appears more significantly than in the transistor 212. Accordingly, the current flowing through the transistor 211 is smaller than the current flowing through the transistor 212 more than the difference between the resistances of the memory element 221 and the memory element 222.
　その結果、記憶ノードN11の電圧は記憶ノードN12の電圧よりも低下し、スレーブラッチ４５内のインバータ６１とインバータ６２からなるループで正帰還がかかって、記憶ノードN12は電源電圧（Hレベル）となり、記憶ノードN11はグランドレベル（Lレベル）となる。すなわち、ストア時における記憶ノードN11および記憶ノードN12の電圧レベルの状態と同じ状態に復帰する。 As a result, the voltage at the storage node N11 is lower than the voltage at the storage node N12, positive feedback is applied in the loop composed of the inverter 61 and the inverter 62 in the slave latch 45, and the storage node N12 becomes the power supply voltage (H level). The storage node N11 is at the ground level (L level). That is, the storage node N11 and the storage node N12 are restored to the same voltage level state at the time of storage.
　この場合、NVDFF回路１１における場合と同様に、トランジスタ２３およびトランジスタ２５はオフ状態とされているので、それらのトランジスタ２３やトランジスタ２５からグランドへとリストア電流が流れることはなく、無駄な電力消費が抑制される。 In this case, as in the case of the NVDFF circuit 11, the transistor 23 and the transistor 25 are in an off state, so that a restore current does not flow from the transistor 23 or the transistor 25 to the ground, and wasteful power consumption occurs. It is suppressed.
　リストアが完了すると、その後は、アクティブモード、ストアモード、スリープモード、およびリストアモードの各モードの動作が、入力される記憶データに応じて行われる。 When the restoration is completed, the operation in each of the active mode, the store mode, the sleep mode, and the restore mode is performed according to the input storage data.
　以上のようなNVDFF回路２０１においてもNVDFF回路１１における場合と同様に、安定な書き込みを維持しつつ、小型化を実現し、消費電力を低く抑えることができる。 In the NVDFF circuit 201 as described above, as in the case of the NVDFF circuit 11, it is possible to achieve downsizing and keep power consumption low while maintaining stable writing.
　以上のように、本技術によれば、安定な書き込みを維持しつつ、小型で消費電力の低い不揮発性記憶回路を実現することができる。 As described above, according to the present technology, it is possible to realize a small nonvolatile memory circuit with low power consumption while maintaining stable writing.
　なお、本技術の実施の形態は、上述した実施の形態に限定されるものではなく、本技術の要旨を逸脱しない範囲において種々の変更が可能である。 Note that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.
　さらに、本技術は、以下の構成とすることも可能である。 Furthermore, the present technology can be configured as follows.
（１）
　情報を記憶する揮発性記憶部と、
　ストア動作により前記揮発性記憶部の前記情報が書き込まれるとともに、リストア動作により、前記ストア動作時のストア経路とは異なるリストア経路で前記情報が前記揮発性記憶部へと読み出される不揮発性記憶部と
　を備え、
　前記ストア経路上に配置された全てのトランジスタがドレイン接続となっている
　不揮発性記憶回路。
（２）
　前記ストア経路上に配置され、前記情報を前記不揮発性記憶部へと書き込むためのストア用ドライバと、
　前記ストア用ドライバとグランドとの間に配置された第１のトランジスタと
　をさらに備える（１）に記載の不揮発性記憶回路。
（３）
　前記ストア用ドライバは反転素子である
　（２）に記載の不揮発性記憶回路。
（４）
　前記第１のトランジスタはnMOSトランジスタである
　（２）または（３）に記載の不揮発性記憶回路。
（５）
　前記ストア経路上に配置され、前記不揮発性記憶部に対して前記ストア用ドライバ側とは反対側に接続された制御線のレベルを制御する制御ドライバをさらに備える
　（２）乃至（４）の何れか一項に記載の不揮発性記憶回路。
（６）
　前記制御ドライバとグランドとの間に配置された第２のトランジスタをさらに備える
　（５）に記載の不揮発性記憶回路。
（７）
　前記制御ドライバは反転素子である
　（６）に記載の不揮発性記憶回路。
（８）
　前記第２のトランジスタはnMOSトランジスタである
　（６）または（７）に記載の不揮発性記憶回路。
（９）
　前記揮発性記憶部は、第１の記憶ノードおよび第２の記憶ノードを有し、
　前記不揮発性記憶部は、第１の記憶素子および第２の記憶素子を有し、
　前記第１の記憶ノードと前記第１の記憶素子とが第３のトランジスタを介して接続され、
　前記第２の記憶ノードと前記第２の記憶素子とが第４のトランジスタを介して接続されている
　（２）乃至（８）の何れか一項に記載の不揮発性記憶回路。
（１０）
　前記第１の記憶ノードと前記第２の記憶素子とが前記ストア用ドライバを介して接続され、
　前記第２の記憶ノードと前記第１の記憶素子とが他の前記ストア用ドライバを介して接続されている
　（９）に記載の不揮発性記憶回路。
（１１）
　前記第１の記憶素子および前記第２の記憶素子はMTJである
　（９）または（１０）に記載の不揮発性記憶回路。 (1)
A volatile storage unit for storing information;
A non-volatile storage unit in which the information in the volatile storage unit is written by a store operation, and the information is read to the volatile storage unit by a restore path different from the store path at the time of the store operation by a restore operation; With
A non-volatile memory circuit in which all the transistors arranged on the store path are connected to the drain.
(2)
A store driver arranged on the store path for writing the information into the nonvolatile storage unit;
The nonvolatile memory circuit according to (1), further comprising: a first transistor disposed between the store driver and the ground.
(3)
The nonvolatile memory circuit according to (2), wherein the store driver is an inverting element.
(4)
The nonvolatile memory circuit according to (2) or (3), wherein the first transistor is an nMOS transistor.
(5)
Any one of (2) to (4), further comprising a control driver that is disposed on the store path and that controls a level of a control line connected to the non-volatile storage unit on the opposite side to the store driver side The nonvolatile memory circuit according to claim 1.
(6)
The nonvolatile memory circuit according to (5), further comprising a second transistor disposed between the control driver and the ground.
(7)
The nonvolatile memory circuit according to (6), wherein the control driver is an inverting element.
(8)
The nonvolatile memory circuit according to (6) or (7), wherein the second transistor is an nMOS transistor.
(9)
The volatile storage unit has a first storage node and a second storage node,
The nonvolatile storage unit includes a first storage element and a second storage element,
The first storage node and the first storage element are connected via a third transistor;
The non-volatile memory circuit according to any one of (2) to (8), wherein the second memory node and the second memory element are connected via a fourth transistor.
(10)
The first storage node and the second storage element are connected via the store driver;
The nonvolatile memory circuit according to (9), wherein the second storage node and the first storage element are connected via the other store driver.
(11)
The nonvolatile memory circuit according to (9) or (10), wherein the first memory element and the second memory element are MTJs.
　１１　NVDFF回路，　２１　揮発性記憶部，　２２　ストア用ドライバ，　２３　トランジスタ，　２４　ストア用ドライバ，　２５　トランジスタ，　２８　不揮発性記憶部，　２９　制御ドライバ，　３０　OR回路，　３１　トランジスタ，　９１　記憶素子，　９２　記憶素子 11 NVDFF circuit, 21 volatile storage unit, 22 store driver, 23 transistor, 24 store driver, 25 transistor, 28 non-volatile storage unit, 29 control driver, 30 OR circuit, 31 transistor, 91 storage element, 92 storage element

Claims (11)

  1. 　情報を記憶する揮発性記憶部と、
    　ストア動作により前記揮発性記憶部の前記情報が書き込まれるとともに、リストア動作により、前記ストア動作時のストア経路とは異なるリストア経路で前記情報が前記揮発性記憶部へと読み出される不揮発性記憶部と
    　を備え、
    　前記ストア経路上に配置された全てのトランジスタがドレイン接続となっている
    　不揮発性記憶回路。     A volatile storage unit for storing information;
    A non-volatile storage unit in which the information in the volatile storage unit is written by a store operation, and the information is read to the volatile storage unit by a restore path different from the store path at the time of the store operation by a restore operation; With
    A non-volatile memory circuit in which all the transistors arranged on the store path are connected to the drain.
  2. 　前記ストア経路上に配置され、前記情報を前記不揮発性記憶部へと書き込むためのストア用ドライバと、
    　前記ストア用ドライバとグランドとの間に配置された第１のトランジスタと
    　をさらに備える請求項１に記載の不揮発性記憶回路。     A store driver arranged on the store path for writing the information into the nonvolatile storage unit;
    The nonvolatile memory circuit according to claim 1, further comprising: a first transistor disposed between the store driver and the ground.
  3. 　前記ストア用ドライバは反転素子である
    　請求項２に記載の不揮発性記憶回路。     The nonvolatile memory circuit according to claim 2, wherein the store driver is an inverting element.
  4. 　前記第１のトランジスタはnMOSトランジスタである
    　請求項２に記載の不揮発性記憶回路。     The nonvolatile memory circuit according to claim 2, wherein the first transistor is an nMOS transistor.
  5. 　前記ストア経路上に配置され、前記不揮発性記憶部に対して前記ストア用ドライバ側とは反対側に接続された制御線のレベルを制御する制御ドライバをさらに備える
    　請求項２に記載の不揮発性記憶回路。     The nonvolatile memory according to claim 2, further comprising a control driver that is disposed on the store path and that controls a level of a control line connected to a side opposite to the store driver side with respect to the nonvolatile memory unit. circuit.
  6. 　前記制御ドライバとグランドとの間に配置された第２のトランジスタをさらに備える
    　請求項５に記載の不揮発性記憶回路。     The nonvolatile memory circuit according to claim 5, further comprising a second transistor disposed between the control driver and ground.
  7. 　前記制御ドライバは反転素子である
    　請求項６に記載の不揮発性記憶回路。     The nonvolatile memory circuit according to claim 6, wherein the control driver is an inverting element.
  8. 　前記第２のトランジスタはnMOSトランジスタである
    　請求項６に記載の不揮発性記憶回路。     The nonvolatile memory circuit according to claim 6, wherein the second transistor is an nMOS transistor.
  9. 　前記揮発性記憶部は、第１の記憶ノードおよび第２の記憶ノードを有し、
    　前記不揮発性記憶部は、第１の記憶素子および第２の記憶素子を有し、
    　前記第１の記憶ノードと前記第１の記憶素子とが第３のトランジスタを介して接続され、
    　前記第２の記憶ノードと前記第２の記憶素子とが第４のトランジスタを介して接続されている
    　請求項２に記載の不揮発性記憶回路。     The volatile storage unit has a first storage node and a second storage node,
    The nonvolatile storage unit includes a first storage element and a second storage element,
    The first storage node and the first storage element are connected via a third transistor;
    The nonvolatile memory circuit according to claim 2, wherein the second storage node and the second storage element are connected via a fourth transistor.
  10. 　前記第１の記憶ノードと前記第２の記憶素子とが前記ストア用ドライバを介して接続され、
    　前記第２の記憶ノードと前記第１の記憶素子とが他の前記ストア用ドライバを介して接続されている
    　請求項９に記載の不揮発性記憶回路。     The first storage node and the second storage element are connected via the store driver;
    The nonvolatile memory circuit according to claim 9, wherein the second storage node and the first storage element are connected via another store driver.
  11. 　前記第１の記憶素子および前記第２の記憶素子はMTJである
    　請求項９に記載の不揮発性記憶回路。     The nonvolatile memory circuit according to claim 9, wherein the first memory element and the second memory element are MTJs.
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