WO2019201327A1 - 一种线性恒流驱动芯片及多芯片并联led照明电路 - Google Patents

一种线性恒流驱动芯片及多芯片并联led照明电路 Download PDF

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Publication number
WO2019201327A1
WO2019201327A1 PCT/CN2019/083364 CN2019083364W WO2019201327A1 WO 2019201327 A1 WO2019201327 A1 WO 2019201327A1 CN 2019083364 W CN2019083364 W CN 2019083364W WO 2019201327 A1 WO2019201327 A1 WO 2019201327A1
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constant current
resistor
linear constant
light emitting
terminal
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PCT/CN2019/083364
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English (en)
French (fr)
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邵蕴奇
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上海路傲电子科技有限公司
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Publication of WO2019201327A1 publication Critical patent/WO2019201327A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/345—Current stabilisation; Maintaining constant current
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Definitions

  • the invention relates to an LED lighting circuit, in particular to a linear constant current driving chip and a multi-chip parallel LED lighting circuit.
  • a conventional multi-chip parallel LED lighting circuit including three linear constant current driving chips includes a rectifier circuit, three linear constant current driving chips connected in parallel, and a series lighting group formed by connecting three LEDs in series.
  • the rectifier circuit is a bridge rectifier circuit composed of four diodes. The input end of the rectifier circuit is connected to the mains, the anode of the output of the rectifier circuit is connected to the cathode of the series illumination group, and the cathode of the output end of the rectifier circuit is grounded and connected to the anode of the series illumination group.
  • the grounding ends of the three linear constant current driving chips are grounded; the eight linear constant current driving chips have 8 pins connected to each other, 7 pins are connected to each other, and 6 pins are connected to each other; the linear constant current driving chip has 8 pins and 7 pins. The pin and the 6 pin are respectively connected to the positive electrodes of the three LEDs.
  • the multi-chip parallel LED lighting circuit In the existing multi-chip parallel LED lighting circuit, three linear constant current driving chips ensure that the current flowing through each of the light emitting diodes is a constant current.
  • the multi-chip parallel LED lighting circuit is usually soldered on the same single-sided copper-clad aluminum substrate, so that the intersections of the wires in the multi-chip parallel LED lighting circuit are It needs to be realized by jumpers, which increases the cost and the board area, and reduces the reliability of the multi-chip parallel LED lighting circuit, which is prone to short circuit.
  • the present invention provides a linear constant current driving chip including a linear constant current driving circuit, a metal substrate, and at least 8 pins; the metal substrate is exposed outside the linear constant current driving chip; Pins are symmetrically distributed on both sides of the metal base plate; the pin includes a first power end and a second power end; the pin further includes at least one intermediate power end disposed on one side of the metal base plate, and Having the same number of additional intermediate power terminals on the other side of the metal backplane; the intermediate power end and the additional intermediate power end are in one-to-one correspondence in the same arrangement order, corresponding to the intermediate power end and the The additional intermediate power terminals are connected to each other; the first power terminal, the intermediate power terminal, the second power terminal, and the additional intermediate power terminal are sequentially arranged around the metal base plate.
  • the metal base plate, at least one pin on a side of the intermediate power end, and at least one pin on a side of the additional intermediate power end serve as first, second, and third ground ends, respectively.
  • intermediate power end and the additional intermediate power end are located on the same side of the second ground end and the third ground end connection; the first power end and the second power end are located in the first The two grounding ends and the third grounding end are connected to different sides of the line.
  • the linear constant current driving circuit includes an enabling unit, a control circuit, and at least one MOS transistor;
  • the MOS transistor includes a first MOS transistor, a second MOS transistor, and at least one intermediate MOS transistor; and the control circuit a resistor and an operational amplifier;
  • the resistor includes a first resistor, a second resistor, a sampling resistor, and at least one intermediate resistor;
  • the operational amplifier includes a first operational amplifier, a second operational amplifier, and at least one intermediate operational amplifier;
  • the first resistor, the intermediate resistor and the second resistor are connected in series to each other to form a resistor series group, and the first resistor and the second resistor are located at two ends of the resistor series group;
  • the first resistor is not One end connected to the intermediate resistor is connected to a common ground;
  • an input terminal of the first operational amplifier is positively connected to an end of the first resistor not connected to the common ground; and an input terminal of the second operational amplifier is positively connected An end of the second resistor that is not
  • FIG. 1 is a schematic structural view of a conventional multi-chip parallel LED lighting circuit
  • Embodiment 1 of a linear constant current driving chip of the present invention
  • FIG. 3 is a schematic structural view of a linear constant current driving circuit of a linear constant current driving chip of the present invention
  • Embodiment 4 is a schematic structural view of Embodiment 1 of a multi-chip parallel LED lighting circuit of the present invention.
  • Embodiment 2 of a linear constant current driving chip of the present invention
  • FIG. 6 is a schematic structural view of a linear constant current driving circuit of a second embodiment of the linear constant current driving chip of the present invention.
  • FIG. 7 is a schematic structural view of a second embodiment of a multi-chip parallel LED lighting circuit of the present invention.
  • the linear constant current driving chip of the present invention comprises eight pins, a metal substrate 2 and a linear constant current driving circuit 308 pins symmetrically distributed on both sides of the metal substrate 2, one side of which is left side. The other side is the right side, and the four pins on the left side of the metal base plate 2 are the first pin 11, the second pin 12, the third pin 13, and the fourth pin 14 from top to bottom. The four pins on the right side of the metal substrate 2 are the fifth pin 15, the sixth pin 16, the seventh pin 17, and the eighth pin 18 from bottom to top.
  • the linear constant current driving circuit 3 is fixed on the metal base plate 2, and the metal base plate 2 is exposed outside the linear constant current driving chip.
  • the linear constant current driving circuit 3 includes a control circuit M1, an enabling unit 4, and three MOS transistors.
  • the three MOS transistors include a first MOS transistor Q1, a second MOS transistor Q2, and an intermediate MOS transistor Q3.
  • the control circuit M1 includes four resistors and three operational amplifiers, and the four resistors include a first resistor R1, a second resistor R2, a sampling resistor RCS, and an intermediate resistor R3.
  • the three operational amplifiers include a first operational amplifier OP1 and a second operational amplifier. OP2 and intermediate operational amplifier OP3.
  • the input terminal of the first operational amplifier OP1, the second operational amplifier OP2, and the intermediate operational amplifier OP3 and the first MOS transistor Q1, the second MOS transistor Q2, and the source of the intermediate MOS transistor are both connected to one end of the sampling resistor RCS, and are sampled.
  • the other end of the resistor RCS is connected to the common ground COM.
  • the output end of the first operational amplifier OP1 is connected to the gate of the first MOS transistor Q1
  • the output end of the intermediate operational amplifier OP3 is connected to the gate of the intermediate MOS transistor Q3, and the output end of the second operational amplifier OP2 is connected to the gate of the second MOS transistor Q2. pole.
  • One end of the first resistor R1 is connected to the positive terminal of the input terminal of the first operational amplifier OP1, and the other end is connected to the common ground COM; one end of the intermediate resistor R3 is connected to the positive terminal of the input terminal of the first operational amplifier OP1, and the other end is connected to the positive terminal of the input terminal of the intermediate operational amplifier OP3;
  • the second resistor R2 has one end connected to the positive terminal of the input terminal of the intermediate operational amplifier OP3, and the other end connected to the positive terminal of the input terminal of the second operational amplifier OP2.
  • One output of the enabling unit 3 is connected to the positive terminal of the input terminal of the second operational amplifier OP2, and the other output terminal is connected to the drain of the first MOS transistor Q1.
  • the drain of the first MOS transistor Q1 is connected to the eighth pin 18 as the first power terminal D1; the drain of the intermediate MOS transistor Q3 is connected to the seventh pin 17 as the intermediate power terminal D3B, and The drain of the intermediate MOS transistor Q3 is connected to the first pin 11 as an additional intermediate power terminal D3A; the drain of the second MOS transistor Q2 is connected to the fifth pin 15 as the second power terminal D2; the common ground of the linear constant current driving circuit 3
  • the COM is connected to the metal backplane 2 as the first ground terminal GND1; the common ground COM of the linear constant current driving circuit 3 is also connected to the sixth pin 16 as the second ground terminal GND2; the common ground COM of the linear constant current driving circuit 3 is also connected to the third Pin 13 serves as a third ground terminal GND3.
  • the voltage provided by the enabling unit 4 is divided into three voltage signals by the first resistor R1, the intermediate resistor R3 and the second resistor R2 connected in series, and the first operational amplifier OP1, the intermediate operational amplifier OP3 and the second operational amplifier OP2 are received.
  • the voltage signals of different sizes are controlled to sequentially increase the magnitude and priority of the current flowing through the sampling resistor RCS via the first MOS transistor Q1, the intermediate MOS transistor Q3, and the second MOS transistor Q2.
  • the multi-chip parallel LED lighting circuit of the present invention comprises three linear constant current driving chips, and the three linear constant current driving chips are all the linear constant current driving chips proposed by the present invention, including the first driving chip, The second driving chip U2 and the third driving chip mountain.
  • the multi-chip parallel LED lighting circuit of the invention further comprises a bridge rectifier circuit DB and three light-emitting diodes, and the three light-emitting diodes comprise a first light-emitting diode LED1, an intermediate light-emitting diode LED3 and a second light-emitting diode LED2.
  • the bridge rectifier circuit DB is a bridge rectifier circuit composed of four diodes.
  • the input terminal is connected to the mains VAC for converting AC power from the commercial VAC into DC power.
  • the positive terminal of the positive electrode bridge rectifier circuit DB of the first light emitting diode LED1 is connected to the anode of the first light emitting diode LED1, and the anode of the second light emitting diode LED2 is connected to the cathode of the intermediate light emitting diode LED3.
  • the first driving chip U1, the second driving chip U2, and the first driving terminal D1 of the third driving chip mountain are connected to the negative electrode of the first LED 131; the first driving chip U1 and the second driving The second power terminal D2 of the chip U2 and the third driver chip mountain (ie, the fifth pin 15) are connected to the negative pole of the second LED diode 2; the old intermediate power terminal D3B of the first driver chip (ie, the seventh pin 17)
  • An additional intermediate power terminal D3A (ie, the first pin 11) connected to the second driver chip mountain is connected, and an intermediate power terminal D3B (ie, the seventh pin 17) of the second driver chip mountain is connected to the additional intermediate power terminal of the third driver chip mountain.
  • the first driving chip U1, the second driving chip U2, and the first grounding terminal GND1 of the third driving chip mountain (ie, the metal substrate 2), the second grounding terminal GND2 (ie, the sixth pin 16), and the third grounding terminal GND3 ( That is, the third pin 13) is connected to each other through the printed power ground 5, and the printed power ground 5 is at the bottom of the metal base plate 2, which is a line printed on the substrate, and is a straight line, reducing the printed power ground 5 and The probability of the other lines crossing, the printed power ground 5 passes through the bottoms of the first driving chip U1, the second driving chip U2, and the third driving chip mountain.
  • the printed power ground 5 is connected to the negative terminal of the output of the bridge rectifier circuit DB and grounded.
  • the lines in the multi-chip parallel LED lighting circuit do not cross each
  • the multi-chip parallel LED lighting circuit is usually soldered on the same single-sided copper-clad aluminum substrate, as shown in FIG. 4, the multi-chip parallel LED lighting circuit of the present invention
  • the reliability is high, the circuit is simple, the cost is low, and the area is small.
  • the linear constant current driving chip of the present invention comprises 10 pins, a metal substrate 2 and a linear constant current driving circuit 3010 pins symmetrically distributed on both sides of the metal substrate 2, one side of which is left side. The other side is the right side, and the five pins on the left side of the metal base plate 2 are the first pin 11, the second pin 12, the third pin 13, the fourth pin 14 and the first from the top to the bottom. Five pins 15, five pins on the right side of the metal substrate 19 are the sixth pin 16, the seventh pin 17, the eighth pin 18, the ninth pin 19 and the tenth pin from bottom to top. 10.
  • the linear constant current driving circuit 3 is fixed on the metal base plate 2, and the metal base plate 2 is exposed outside the linear constant current driving chip.
  • the linear constant current driving circuit 3 includes a control circuit M1, an enabling unit 4, and four MOS transistors, and the four MOS transistors include a first MOS transistor Q1, a second MOS transistor Q2, and a first intermediate MOS transistor Q3. And the second intermediate MOS regulation.
  • the control circuit M1 includes five resistors and four operational amplifiers, and the five resistors include a first resistor R1, a second resistor R2, a sampling resistor RCS, a first intermediate resistor R3, and a second intermediate resistor.
  • the four operational amplifiers include the first The operational amplifier OP1, the second operational amplifier OP2, the first intermediate operational amplifier OP3, and the second intermediate operational amplifier OP4.
  • the source of the two intermediate MOS control is connected to one end of the sampling resistor RCS, and the other end of the sampling resistor RCS is connected to the common ground COM.
  • the output end of the first operational amplifier OP1 is connected to the gate of the first MOS transistor Q1, the output end of the first intermediate operational amplifier OP3 is connected to the old gate of the first intermediate MOS transistor, and the output end of the second intermediate operational amplifier OP4 is connected to the second The gate of the intermediate MOS regulation, the output of the second operational amplifier OP2 is connected to the gate of the second MOS transistor Q2.
  • the first resistor R1 is connected at one end to the positive terminal of the input terminal of the first operational amplifier OP1, and the other end is connected to the common ground COM; the first intermediate resistor R3 is connected at one end to the positive terminal of the input terminal of the first operational amplifier OP1, and the other end is connected to the first intermediate operational amplifier.
  • the input terminal of the P3 is positive; the second intermediate resistor R4 is connected to the positive terminal of the input terminal of the first intermediate operational amplifier OP3, the other terminal is connected to the positive terminal of the input terminal of the second intermediate operational amplifier OP4; and the second resistor R2 is connected to the second intermediate operational amplifier at one end.
  • the input terminal of P4 is positive, and the other end is connected to the positive terminal of the input terminal of the second operational amplifier OP2.
  • One output of the enabling unit 4 is connected to the positive terminal of the input terminal of the second operational amplifier OP3, and the other output terminal is connected to the drain of the first MOS transistor Q1.
  • the drain of the first MOS transistor Q1 is connected to the tenth pin 10 as the first power terminal D1; the old drain of the first intermediate MOS transistor is connected to the seventh pin 17 as the first intermediate power. Terminal D3B, and the old drain of the first intermediate MOS transistor is connected to the third pin 13 as the first additional intermediate power terminal D3A; the second intermediate MOS regulated drain is connected to the sixth pin 16 as the second intermediate power terminal D4B, And the second intermediate MOS regulated drain is connected to the fourth pin 14 as the second additional intermediate power terminal D4A; the drain of the second MOS transistor Q2 is connected to the fifth pin 15 as the second power terminal D2; the linear constant current driving circuit
  • the common ground COM of 3 is connected to the metal base plate 2 as the first ground terminal GND1; the common ground COM of the linear constant current drive circuit 3 is also connected to the ninth pin 19 as the second ground terminal GND2; the common ground of the linear constant current drive circuit 3
  • the second pin 12 is also connected as the third ground GND
  • the voltage provided by the enabling unit 4 is divided into four voltage signals by the first resistor R1, the first intermediate resistor R3, the second intermediate resistor R4 and the second resistor R2 connected in series, and the first operational amplifier OP1 is first intermediately operated.
  • the amplifier OP3, the second intermediate operational amplifier OP4, and the second operational amplifier OP2 receive voltage signals of different magnitudes to flow through the first MOS transistor Q1, the first intermediate MOS transistor Q3, the second intermediate MOS regulator, and the second MOS transistor Q2.
  • the magnitude and priority of the current on the oversampling resistor RCS is incremented.
  • the multi-chip parallel LED lighting circuit of the present invention comprises three linear constant current driving chips, and the three linear constant current driving chips are all the linear constant current driving chips proposed by the present invention, including the first driving chip, The second driving chip U2 and the third driving chip mountain.
  • the multi-chip parallel LED lighting circuit of the invention further comprises a bridge rectifier circuit DB and four light emitting diodes, and the four light emitting diodes comprise a first light emitting diode LED1, a first intermediate light emitting diode LED3, a second intermediate light emitting diode LED4 and a second light emitting diode.
  • the bridge rectifier circuit DB is a bridge rectifier circuit composed of four diodes.
  • a power supply unit As a power supply unit, its input terminal is connected to a mains VAC for converting alternating current from the commercial VAC into direct current.
  • the positive terminal of the positive electrode bridge rectifier circuit DB of the first light emitting diode LED1 is positive
  • the positive electrode of the first intermediate light emitting diode LED3 is connected to the negative electrode of the first light emitting diode LED1
  • the positive electrode of the second intermediate light emitting diode LED4 is connected to the first intermediate light emitting diode LED3.
  • the anode of the second light emitting diode LED2 is connected to the cathode of the second intermediate light emitting diode LED4.
  • the first driving chip U1, the second driving chip U2, and the first driving terminal D1 of the third driving chip mountain are connected to the negative electrode of the first light emitting diode LED1; the first driving chip U1 and the second driving The second power terminal D2 of the chip U2 and the third driver chip mountain (ie, the fifth pin 15) are connected to the negative pole of the second LED diode 2; the first first intermediate power terminal D3B of the first driver chip (ie, the seventh pin) 17) connecting the first additional intermediate power terminal D3A (ie, the third pin 13) of the second driver chip mountain, and the first intermediate power terminal D3B (ie, the seventh pin 17) of the second driver chip mountain is connected to the third driver chip a first additional intermediate power terminal D3A of the mountain (ie, the third pin 13), and the first intermediate power terminal D3B of the third driver chip mountain (ie, the seventh pin 17) is connected to the cathode of the first intermediate light emitting diode LED3;
  • the intermediate power terminal D4B (ie, the sixth pin 16) is connected to the second additional intermediate power terminal D4A of the third driver chip mountain (ie, The fourth pin 14), and the second intermediate power terminal D4B of the third driver chip mountain (ie, the sixth pin 16) is connected to the cathode of the second intermediate light emitting diode LED4.
  • the first driving chip U1, the second driving chip U2, and the first grounding terminal GND1 of the third driving chip mountain (ie, the metal substrate 2), the second grounding terminal GND2 (ie, the ninth pin 19), and the third grounding terminal GND3 ( That is, the second pins 12) are connected to each other through the printed power ground 5, and the printed power ground 5 is at the bottom of the metal base plate 2, which is a line printed on the substrate, and is a straight line, reducing the printed power ground 5 and The probability of the other lines crossing, the printed power ground 5 passes through the bottoms of the first driving chip U1, the second driving chip U2, and the third driving chip mountain.
  • the printed power ground 5 is connected to the negative terminal of the output of the bridge rectifier circuit DB and grounded.
  • the lines in the multi-chip parallel LED lighting circuit do not cross each other.
  • the multi-chip parallel LED lighting circuit is usually soldered on the same single-sided copper-clad aluminum substrate, as shown in FIG. 7, the multi-chip parallel LED lighting circuit of the present invention
  • the reliability is high, the circuit is simple, the cost is low, and the area is small.

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Abstract

本发明公开了一种线性恒流驱动芯片及多芯片并联LED照明电路，涉及LED照明电路，所述线性恒流驱动芯片包括线性恒流驱动电路、金属底板及至少8个引脚；引脚对称分布于所述金属底板两侧；引脚包括第一功率端、第二功率端、设置在金属底板一侧的至少1个中间功率端，及设置在金属底板另一侧的相同数量的额外中间功率端；中间功率端及额外中间功率端按照相同的排列顺序一一对应，相对应的中间功率端及额外中间功率端连接；第一功率端、中间功率端、第二功率端及额外中间功率端依次围绕金属底板排司列；使用所述线性恒流驱动芯片构成多芯片并联LED照明电路时，线路无需使用跳线，电路简单，可靠性高。

Description

一种线性恒流驱动芯片及多芯片并联LED照明电路
本申请要求申请日为2018年4月20日的中国专利申请CN201810360250.4的优先权。本申请引用上述中国专利申请的全文。
技术领域
本发明涉及LED照明电路，具体为一种线性恒流驱动芯片及多芯片并联LED照明电路。
背景技术
现有的大功率LED照明驱动电路，一个线性恒流驱动芯片的额定功率通常无法满足使用需求，经常需要使用多个线性恒流驱动芯片并联组成多芯片并联LED照明电路以扩展功率。
参考图1，为现有的包括3个线性恒流驱动芯片的多芯片并联LED照明电路，包括整流电路、并联的3个线性恒流驱动芯片及3个发光二极管串联构成的串联照明组。整流电路为4个二极管组成的桥式整流电路，整流电路的输入端连接市电，整流电路输出端的正极连接串联照明组的负极，且整流电路输出端的负极接地并连接与串联照明组的正极。3个线性恒流驱动芯片的接地端均接地；3个线性恒流驱动芯片的8引脚相互连接，7引脚相互连接，6引脚相互连接；线性恒流驱动芯片的8引脚、7引脚及6引脚分别连接3个发光二极管的正极。
现有的多芯片并联LED照明电路中，3个线性恒流驱动芯片保证了流过每个发光二极管的电流为恒流。但是，考虑到发光二极管与线性恒流驱动芯片的散热，多芯片并联LED照明电路通常贴片焊接在同一个单面覆铜的铝基板上，使得多芯片并联LED照明电路中的导线交叉点都需要通过跳线来实现，增加了成本和电路板面积，同时降低了多芯片并联LED照明电路的 可靠性，容易产生短路。
发明内容
本发明的目的在于提供一种线性恒流驱动芯片及多芯片并联LED照明电路，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提出了一种线性恒流驱动芯片，包括线性恒流驱动电路、金属底板及至少8个引脚；所述金属底板裸露于所述线性恒流驱动芯片外侧；所述引脚对称分布于所述金属底板两侧；所述引脚包括第一功率端、第二功率端；所述引脚还包括设置在所述金属底板一侧的至少1个中间功率端，及设置在所述金属底板另一侧的相同数量的额外中间功率端；所述中间功率端及所述额外中间功率端按照相同的排列顺序一一对应，相对应的所述中间功率端及所述额外中间功率端相互连接；所述第一功率端、所述中间功率端、所述第二功率端及所述额外中间功率端依次围绕所述金属底板排列。
进一步的，所述金属底板、位于所述中间功率端一侧的至少一个引脚和位于所述额外中间功率端一侧的至少一个引脚分别作为第一、第二和第三接地端。
进一步的，所述中间功率端及所述额外中间功率端位于所述第二接地端及所述第三接地端连线的同一侧；所述第一功率端及第二功率端位于所述第二接地端及所述第三接地端连线的不同侧。
进一步的，所述线性恒流驱动电路包括使能单元、控制电路及至少1个MOS管；所述MOS管包括第一MOS管、第二MOS管及至少1个中间MOS管；所述控制电路包括电阻及运算放大器；所述电阻包括第一电阻、第二电阻、采样电阻及至少1个中间电阻；所述运算放大器包括第一运算放大器、第二运算放大器及至少1个中间运算放大器；所述第一电阻、所述中间电阻及所述第二电阻相互串联，构成电阻串联组，所述第一电阻及所述第二电阻 位于所述电阻串联组的两端；所述第一电阻不与所述中间电阻连接的一端连接公共地；所述第一运算放大器的输入端正极连接所述第一电阻不与所述公共地连接的一端；所述第二运算放大器的输入端正极连接所述第二电阻不与所述中间电阻连接的一端；所述中间运算放大器的输入端正极依次连接所述中间电阻远离所述公共地的一端；所有所述运算放大器的输入端负极和所有所述MOS管的源极均经由所述采样电阻接公共地；所述第一运算放大器的输出端连接所述第一MOS管的栅极；所述第二运算放大器的输出端连接所述第二MOS管的栅极；所述中间运算放大器的输出端依次连接所述中|可MOS管的栅极；所述使能单元的一个输出端连接所述第二运算放大器的输入端正极，另一个输出端连接所述第一MOS管的漏极；所述第一MOS管的漏极连接所述第一功率端；所述第二MOS管的漏极连接所述第二功率端；所述中间MOS管的漏极按照次序连接所述中间功率端；所述中|可MOS管的漏极按照同样的次序连接所述额外中间功率端；所述公共地连接到所述第一接地端、第二接地端和第三接地端中的任意个。
附图说明
图1是现有多芯片并联LED照明电路的结构示意图；
图2是本发明线性恒流驱动芯片实施例一的结构示意图；
图3是本发明线性恒流驱动芯片实施例一线性恒流驱动电路的结构示意图；
图4是本发明多芯片并联LED照明电路实施例一的结构示意图；
图5是本发明线性恒流驱动芯片实施例二的结构示意图；
图6是本发明线性恒流驱动芯片实施例二线性恒流驱动电路的结构示意图；
图7是本发明多芯片并联LED照明电路实施例二的结构示意图。
附图标记中：11、第一引脚；12、第二引脚；13、第三引脚；14、第四 引脚；15、第五引脚；16、第六引脚；17、第七引脚；18、第八引脚；19、第九引脚；10、第十引脚；2、金属底板；3、线性恒流驱动电路；4、使能单元；5、印制电源地。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例1
如图2所示，本发明线性恒流驱动芯片包括8个引脚、金属底板2及线性恒流驱动电路308个引脚对称分布在金属底板2的两侧，以其中一侧为左侧，另一侧为右侧，则位于金属底板2左侧的4个引脚从上到下依次为第一引脚11、第二引脚12、第三引脚13及第四引脚14，位于金属底板2右侧的4个引脚从下到上依次为第五引脚15、第六引脚16、第七引脚17及第八号引脚18。线性恒流驱动电路3固定在金属底板2上，且金属底板2裸露在线性恒流驱动芯片外。
如图3所示，线性恒流驱动电路3包括控制电路M1、使能单元4及3个MOS管，3个MOS管包括第一MOS管Q1、第二MOS管Q2及中间MOS管Q3。控制电路M1包括4个电阻及3个运算放大器，4个电阻包括第一电阻R1、第二电阻R2、采样电阻RCS及中间电阻R3，3个运算放大器包括第一运算放大器OP1、第二运算放大器OP2及中间运算放大器OP3。第一运算放大器OP1、第二运算放大器OP2及中间运算放大器OP3的输入端负极与第一MOS管Q1、第二MOS管Q2及中间MOS管旧的源极均连接至采样电阻RCS的一端，采样电阻RCS的另一端连接公共地COM。第一 运算放大器OP1的输出端连接第一MOS管Q1的栅极，中间运算放大器OP3的输出端连接中间MOS管Q3的栅极，第二运算放大器OP2的输出端连接第二MOS管Q2的栅极。第一电阻R1一端连接第一运算放大器OP1的输入端正极，另一端连接公共地COM；中间电阻R3一端连接第一运算放大器OP1的输入端正极，另一端连接中间运算放大器OP3的输入端正极；第二电阻R2一端连接中间运算放大器OP3的输入端正极，另一端连接第二运算放大器OP2的输入端正极。使能单元3的一个输出端连接第二运算放大器OP2的输入端正极，另一个输出端连接第一MOS管Q1的漏极。
如图2及图3所示，第一MOS管Q1的漏极连接第八引脚18作为第一功率端D1；中间MOS管Q3的漏极连接第七引脚17作为中间功率端D3B，且中间MOS管Q3的漏极连接第一引脚11作为额外中间功率端D3A；第二MOS管Q2的漏极连接第五引脚15作为第二功率端D2；线性恒流驱动电路3的公共地COM连接金属底板2作为第一接地端GND1；线性恒流驱动电路3的公共地COM还连接第六引脚16作为第二接地端GND2；线性恒流驱动电路3的公共地COM还连接第三引脚13作为第三接地端GND3。
使能单元4提供的电压被串联的第一电阻R1、中间电阻R3及第二电阻R2分为3个电压信号，并使第一运算放大器OP1、中间运算放大器OP3及第二运算放大器OP2接收到大小不同的电压信号，控制经由第一MOS管Q1、中间MOS管Q3及第二MOS管Q2流过采样电阻RCS上的电流幅值和优先级依次递增。
如图4所示，为本发明多芯片并联LED照明电路包括3个线性恒流驱动芯片，3个线性恒流驱动芯片均为本发明提出的线性恒流驱动芯片，包括第一驱动芯片川、第二驱动芯片U2及第三驱动芯片山。本发明多芯片并联LED照明电路还包括桥式整流电路DB及3个发光二极管，3个发光二极管包括第一发光二极管LED1、中间发光二极管LED3及第二发光二极管LED2。桥式整流电路DB为4个二极管组成的桥式整流电路，作为供电单元，其输 入端连接市电VAC，用于将来自市电VAC的交流电转化为直流电。第一发光二极管LED1的正极连桥式整流电路DB的输出端正极，中间发光二极管LED3的正极连接第一发光二极管LED1的负极，第二发光二极管LED2的正极连接中间发光二极管LED3的负极。第一驱动芯片U1、第二驱动芯片U2及第三驱动芯片山的第一功率端D1(即第八引脚18)均连接第一发光二极管LED1的负极；第一驱动芯片U1、第二驱动芯片U2及第三驱动芯片山的第二功率端D2(即第五引脚15)均连接第二发光二极管LED2的负极；第一驱动芯片旧的中间功率端D3B(即第七引脚17)连接第二驱动芯片山的额外中间功率端D3A(即第一引脚11)，第二驱动芯片山的中间功率端D3B(即第七引脚17)连接第三驱动芯片山的额外中间功率端D3A(即第一引脚11)，且第三驱动芯片山的中间功率端D3B(即第七引脚17)连接中间发光二极管LED3的负极。第一驱动芯片U1、第二驱动芯片U2及第三驱动芯片山的第一接地端GND1(即金属底板2)、第二接地端GND2(即第六引脚16)及第三接地端GND3(即第三引脚13)均通过印制电源地5相互连接，印制电源地5在金属底板2的底部，为印制在基板上的线路，且为一条直线，减少印制电源地5与其他线路交叉的概率，印制电源地5经过第一驱动芯片U1、第二驱动芯片U2及第三驱动芯片山的底部。印制电源地5连接于桥式整流电路DB的输出端负极，并接地。所述多芯片并联LED照明电路中的线路均不交叉。
考虑到发光二极管与线性恒流驱动芯片的散热，多芯片并联LED照明电路通常贴片焊接在同一个单面覆铜的铝基板上，如图4所示，本发明多芯片并联LED照明电路的线路之间不存在交叉，各个部分线路连接无需使用跳线，可靠性高，且电路简单，成本低，面积小。
实施例2
如图5所示，本发明线性恒流驱动芯片包括10个引脚、金属底板2及线性恒流驱动电路3010个引脚对称分布在金属底板2的两侧，以其中一侧 为左侧，另一侧为右侧，则位于金属底板2左侧的5个引脚从上到下依次为第一引脚11、第二引脚12、第三引脚13、第四引脚14及第五引脚15，位于金属底板19右侧的5个引脚从下到上依次为第六引脚16、第七引脚17、第八引脚18、第九引脚19及第十引脚10。线性恒流驱动电路3固定在金属底板2上，且金属底板2裸露在线性恒流驱动芯片外。
如图6所示，线性恒流驱动电路3包括控制电路M1、使能单元4及4个MOS管，4个MOS管包括第一MOS管Q1、第二MOS管Q2、第一中间MOS管Q3及第二中间MOS管制。控制电路M1包括5个电阻及4个运算放大器，5个电阻包括第一电阻R1、第二电阻R2、采样电阻RCS、第一中间电阻R3及第二中间电阻旧，4个运算放大器包括第一运算放大器OP1、第二运算放大器OP2、第一中间运算放大器OP3及第二中间运算放大器OP4。第一运算放大器OP1、第二运算放大器OP2、第一中间运算放大器OP3及第二中间运算放大器OP4的输入端负极与第一MOS管Q1、第二MOS管Q2、第一中间MOS管Q3及第二中间MOS管制的源极均连接至采样电阻RCS的一端，采样电阻RCS的另一端接公共地COM。第一运算放大器OP1的输出端连接第一MOS管Q1的栅极，第一中间运算放大器OP3的输出端连接第一中间MOS管旧的栅极，第二中间运算放大器OP4的输出端连接第二中间MOS管制的栅极，第二运算放大器OP2的输出端连接第二MOS管Q2的栅极。第一电阻R1一端连接第一运算放大器OP1的输入端正极，另一端连接公共地COM；第一中间电阻R3一端连接第一运算放大器OP1的输入端正极，另一端连接第一中间运算放大器。P3的输入端正极；第二中间电阻R4一端连接第一中间运算放大器OP3的输入端正极，另一端连接第二中间运算放大器OP4的输入端正极；第二电阻R2一端连接第二中间运算放大器。P4的输入端正极，另一端连接第二运算放大器OP2的输入端正极。使能单元4的一个输出端连接第二运算放大器OP3的输入端正极，另一个输出端连接第一MOS管Q1的漏极。
如图5及图6所示，第一MOS管Q1的漏极连接第十引脚10作为第一功率端D1；第一中间MOS管旧的漏极连接第七引脚17作为第一中间功率端D3B，且第一中间MOS管旧的漏极连接第三引脚13作为第一额外中间功率端D3A；第二中间MOS管制的漏极连接第六引脚16作为第二中间功率端D4B，且第二中间MOS管制的漏极连接第四引脚14作为第二额外中间功率端D4A；第二MOS管Q2的漏极连接第五引脚15作为第二功率端D2；线性恒流驱动电路3的公共地COM连接金属底板2作为第一接地端GND1；线性恒流驱动电路3的公共地COM还连接第九引脚19作为第二接地端GND2；线性恒流驱动电路3的公共地COM还连接第二引脚12作为第三接地端GND3。
使能单元4提供的电压被串联的第一电阻R1、第一中间电阻R3、第二中间电阻R4及第二电阻R2分为4个电压信号，并使第一运算放大器OP1、第一中间运算放大器OP3、第二中间运算放大器OP4及第二运算放大器OP2接收到大小不同的电压信号，使经由第一MOS管Q1、第一中间MOS管Q3、第二中间MOS管制及第二MOS管Q2流过采样电阻RCS上的电流幅值和优先级递增。
如图7所示，为本发明多芯片并联LED照明电路包括3个线性恒流驱动芯片，3个线性恒流驱动芯片均为本发明提出的线性恒流驱动芯片，包括第一驱动芯片川、第二驱动芯片U2及第三驱动芯片山。本发明多芯片并联LED照明电路还包括桥式整流电路DB及4个发光二极管，4个发光二极管包括第一发光二极管LED1、第一中间发光二极管LED3、第二中间发光二极管LED4及第二发光二极管LED2。桥式整流电路DB为4个二极管组成的桥式整流电路，作为供电单元，其输入端连接市电VAC，用于将来自市电VAC的交流电转化为直流电。第一发光二极管LED1的正极连桥式整流电路DB的输出端正极，第一中间发光二极管LED3的正极连接第一发光二极管LED1的负极，第二中间发光二极管LED4的正极连接第一中间发光二极管 LED3的负极，第二发光二极管LED2的正极连接第二中间发光二极管LED4的负极。第一驱动芯片U1、第二驱动芯片U2及第三驱动芯片山的第一功率端D1(即第十引脚10)均连接第一发光二极管LED1的负极；第一驱动芯片U1、第二驱动芯片U2及第三驱动芯片山的第二功率端D2(即第五引脚15)均连接第二发光二极管LED2的负极；第一驱动芯片旧的第一中间功率端D3B(即第七引脚17)连接第二驱动芯片山的第一额外中间功率端D3A(即第三引脚13)，第二驱动芯片山的第一中间功率端D3B(即第七引脚17)连接第三驱动芯片山的第一额外中间功率端D3A(即第三引脚13)，且第三驱动芯片山的第一中间功率端D3B(即第七引脚17)连接第一中间发光二极管LED3的负极；第一驱动芯片U1的第二中间功率端D4B(即第六引脚16)连接第二驱动芯片山的第二额外中间功率端D4A(即第四引脚14)，第二驱动芯片山的第二中间功率端D4B(即第六引脚16)连接第三驱动芯片山的第二额外中间功率端D4A(即第四引脚14)，且第三驱动芯片山的第二中间功率端D4B(即第六引脚16)连接第二中间发光二极管LED4的负极。第一驱动芯片U1、第二驱动芯片U2及第三驱动芯片山的第一接地端GND1(即金属底板2)、第二接地端GND2(即第九引脚19)及第三接地端GND3(即第二引脚12)均通过印制电源地5相互连接，印制电源地5在金属底板2的底部，为印制在基板上的线路，且为一条直线，减少印制电源地5与其他线路交叉的概率，印制电源地5经过第一驱动芯片U1、第二驱动芯片U2及第三驱动芯片山的底部。印制电源地5连接于桥式整流电路DB的输出端负极，并接地。所述多芯片并联LED照明电路中的线路均不交叉。
考虑到发光二极管与线性恒流驱动芯片的散热，多芯片并联LED照明电路通常贴片焊接在同一个单面覆铜的铝基板上，如图7所示，本发明多芯片并联LED照明电路的线路之间不存在交叉，各个部分线路连接无需使用跳线，可靠性高，且电路简单，成本低，面积小。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员丽 言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员丽言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (7)

  1. 一种线性恒流驱动芯片，其特征在于：包括线性恒流驱动电路、金属底板及至少8个引脚；
    所述金属底板裸露于所述线性恒流驱动芯片外侧；
    所述引脚对称分布于所述金属底板两侧；
    所述引脚包括第一功率端、第二功率端；
    所述引脚还包括设置在所述金属底板一侧的至少1个中间功率端，及设置在所述金属底板另一侧的相同数量的额外中间功率端；
    所述中间功率端及所述额外中间功率端按照相同的排列顺序一一对应，相对应的所述中间功率端及所述额外中间功率端相互连接；
    所述第一功率端、所述中间功率端、所述第二功率端及所述额外中间功率端依次围绕所述金属底板排列。
  2. 根据权利要求1所述的一种线性恒流驱动芯片，其特征在于：
    所述金属底板、位于所述中间功率端一侧的至少一个引脚和位于所述额外中间功率端一侧的至少一个引脚分别作为第一、第二和第三接地端。
  3. 根据权利要求2所述的一种线性恒流驱动芯片，其特征在于：
    所述中间功率端及所述额外中间功率端位于所述第二接地端及所述第三接地端连线的同一侧；
    所述第一功率端及第二功率端位于所述第二接地端及所述第三接地端连线的不同侧。
  4. 根据权利要求1所述的一种线性恒流驱动芯片，其特征在于：所述线性恒流驱动电路包括使能单元、控制电路及至少1个MOS管：
    所述MOS管包括第一MOS管、第二MOS管及至少1个中间MOS管；
    所述控制电路包括电阻及运算放大器；
    所述电阻包括第一电阻、第二电阻、采样电阻及至少1个中间电阻；
    所述运算放大器包括第一运算放大器、第二运算放大器及至少1个中间运算放大器；
    所述第一电阻、所述中间电阻及所述第二电阻相互串联，构成电阻串联组，所述第一电阻及所述第二电阻位于所述电阻串联组的两端；
    所述第一电阻不与所述中间电阻连接的一端连接公共地；
    所述第一运算放大器的输入端正极连接所述第一电阻不与所述公共地连接的一端；
    所述第二运算放大器的输入端正极连接所述第二电阻不与所述中间电阻连接的一端；
    所述中间运算放大器的输入端正极依次连接所述中间电阻远离所述公共地的一端；
    所有所述运算放大器的输入端负极和所有所述MOS管的源极均经由所述采样电阻接公共地；
    所述第一运算放大器的输出端连接所述第一MOS管的栅极；
    所述第二运算放大器的输出端连接所述第二MOS管的栅极；
    所述中间运算放大器的输出端依次连接所述中|可MOS管的栅极；
    所述使能单元的一个输出端连接所述第二运算放大器的输入端正极，另一个输出端连接所述第一MOS管的漏极；
    所述第一MOS管的漏极连接所述第一功率端；
    所述第二MOS管的漏极连接所述第二功率端；
    所述中间MOS管的漏极按照次序连接所述中间功率端；
    所述中间MOS管的漏极按照同样的次序连接所述额外中间功率端；
    所述公共地连接到所述第一接地端、第二接地端和第三接地端中的任意个。
  5. 一种多芯片并联LED照明电路，其特征在于：包括至少2个如权利要求1至4中任意一项所述的线性恒流驱动芯片；
    所述多芯片并联LED照明电路还包括供电单元及发光二极管；
    所述发光二极管包括第一发光二极管、第二发光二极管及至少1个中间发光二极管，所述中间发光二极管数量与每个所述线性恒流驱动芯片中的所述中间MOS管数量相等；
    所述供电单元用于把来自市电的交流电转变为直流电后为发光二极管的发光提供能量；
    所述第一发光二极管、所述中间二极管、所述第二发光二极管依次负极与正极相互连接构成发光二极管串联组，且所述第一发光二极管及所述第二发光二极管位于所述发光二极管串联组的两端，所述第一发光二极管的负极与其中一个所述中间发光二极管的正极相连，所述第二发光二极管的正极与其中一个所述中间发光二极管的负极相连；
    所述第一发光二级管的正极连接所述供电单元的输出端正极；
    所述线性恒流驱动芯片的第一功率端均连接所述第一发光二极管的负极；
    所述线性恒流驱动芯片的第二功率端均连接所述第二发光二极管的负极；
    按照次序，每个所述线性恒流驱动芯片的中间功率端依次连接下一个线性恒流驱动芯片上对应的额外中间功率端；
    所述中间发光二极管的负极依次连接所述线性恒流驱动芯片中至少1个对应的中间功率端或额外中间功率端；
    每个所述线性恒流驱动芯片的任意个接地端均通过印制电源地相互连接，所述印制电源地为印制在基板上的线路，且经过所述线性恒流驱动芯片的底部；
    所述印制电源地连接于所述供电电路的输出端负极。
  6. 根据权利要求5所述的一种多芯片并联LED照明电路，其特征在于：所述中间发光二极管的负极依次连接最后一个线性恒流驱动芯片中对应的 中间功率端或第一个线性恒流驱动芯片中对应的额外中间功率端。
  7. 根据权利要求5所述的一种多芯片并联LED照明电路，其特征在于：所述供电单元为4个二极管组成的桥式整流电路，且输入端连接市电。
PCT/CN2019/083364 2018-04-20 2019-04-19 一种线性恒流驱动芯片及多芯片并联led照明电路 WO2019201327A1 (zh)

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