WO2019188173A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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WO2019188173A1
WO2019188173A1 PCT/JP2019/009625 JP2019009625W WO2019188173A1 WO 2019188173 A1 WO2019188173 A1 WO 2019188173A1 JP 2019009625 W JP2019009625 W JP 2019009625W WO 2019188173 A1 WO2019188173 A1 WO 2019188173A1
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unit
processing
arithmetic
semiconductor device
dedicated
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PCT/JP2019/009625
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French (fr)
Japanese (ja)
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祐次郎 谷
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株式会社デンソー
株式会社エヌエスアイテクス
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Publication of WO2019188173A1 publication Critical patent/WO2019188173A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

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  • the present disclosure relates to a semiconductor device provided with a plurality of types of arithmetic units.
  • a semiconductor device includes a plurality of basic cells having the same configuration provided in a logic region, a redundant cell having the same configuration as the plurality of basic cells, and a plurality of basic cells and redundant cells, respectively. And an output selector that switches signals output from each of the basic cell and the redundant cell. Further, the semiconductor device switches at least one of the input selector and the output selector to function the redundant cell and repair the failed cell among the plurality of basic cells.
  • Patent Document 1 redundant relief is performed by a redundant cell having the same configuration as the basic cell.
  • an accelerator is provided in order to speed up the processing of the main CPU, it is conceivable to provide a dedicated arithmetic unit specialized for specific arithmetic processing.
  • Patent Document 1 it is necessary to provide an arithmetic unit having the same configuration as that of the dedicated arithmetic unit in this case as well.
  • the circuit scale of the dedicated arithmetic unit is large, the circuit scale is compressed.
  • An object of the present disclosure is to provide a semiconductor device provided with a plurality of types of arithmetic units, and capable of increasing the possibility of redundant relief without reducing the circuit scale. .
  • the present disclosure is a semiconductor device provided with a plurality of types of arithmetic units, a fault detection unit for detecting a fault of a dedicated arithmetic unit specialized for specific arithmetic processing, and the fault detection unit is a dedicated arithmetic unit If a failure is detected, the alternative judgment unit that determines whether or not a specific arithmetic processing can be replaced by a general-purpose arithmetic unit, and the determination result of the alternative determination unit are substitutable. And an alternative mode execution unit that executes the above arithmetic processing.
  • the general-purpose arithmetic unit can perform an alternative process, so that the specific arithmetic process can be continued without reducing the circuit scale.
  • FIG. 1 is a diagram for explaining parallel processing which is a premise of the present embodiment.
  • FIG. 2 is a diagram showing a system configuration example for executing the parallel processing shown in FIG.
  • FIG. 3 is a diagram illustrating a configuration example of the DFP used in FIG.
  • FIG. 4 is a diagram for explaining an arithmetic unit constituting the execution core.
  • FIG. 5 is a flowchart for explaining the redundancy repair method of this embodiment.
  • FIG. 6 is a diagram for explaining a configuration involved in the processing of the flowchart shown in FIG. 5 in the DFP of this embodiment.
  • FIG. 7 is a diagram for explaining functional configuration blocks involved in the processing of the flowchart shown in FIG. 5 in the DFP of this embodiment.
  • FIG. 1A shows a program code having a graph structure
  • FIG. 1B shows a thread state
  • FIG. 1C shows a state of parallel processing.
  • the program to be processed in this embodiment has a graph structure in which data and processing are divided. This graph structure maintains the task parallelism and graph parallelism of the program.
  • Parallel execution as shown in FIG. 1C can be performed on a large number of threads shown in FIG. 1B by dynamic register placement and thread scheduling by hardware. By dynamically allocating register resources during execution, a plurality of threads can be executed in parallel for different instruction streams.
  • a data processing system 2 which is a system configuration example including a DFP (Data Flow Processor) 10 as an accelerator for performing dynamic register placement and thread scheduling, will be described with reference to FIG.
  • the DFP 10 corresponds to the semiconductor device of the present disclosure.
  • the data processing system 2 includes a DFP 10, an event handler 20, a host CPU 21, a ROM 22, a RAM 23, an external interface 24, and a system bus 25.
  • the host CPU 21 is an arithmetic unit that mainly performs data processing.
  • the host CPU 21 supports the OS.
  • the event handler 20 is a part that generates an interrupt process.
  • ROM 22 is a read-only memory.
  • the RAM 23 is a read / write memory.
  • the external interface 24 is an interface for exchanging information with the outside of the data processing system 2.
  • the system bus 25 is for transmitting and receiving information between the DFP 10, the host CPU 21, the ROM 22, the RAM 23, and the external interface 24.
  • the DFP 10 is positioned as an individual master provided to cope with the heavy computation load of the host CPU 21.
  • the DFP 10 is configured to support the interrupt generated by the event handler 20.
  • the DFP 10 includes a command unit 12, a thread scheduler 14, an execution core 16, and a memory subsystem 18.
  • the command unit 12 is configured to be able to communicate information with the config interface.
  • the command unit 12 also functions as a command buffer.
  • the thread scheduler 14 is a part that schedules processing of a large number of threads as exemplified in FIG.
  • the thread scheduler 14 can perform scheduling across threads.
  • the execution core 16 has four processing elements, PE # 0, PE # 1, PE # 2, and PE # 3.
  • the execution core 16 has a number of pipelines that can be scheduled independently.
  • the memory subsystem 18 includes an arbiter 181, an L1 cache 18a, and an L2 cache 18b.
  • the memory subsystem 18 is configured to allow information communication between the system bus interface and the ROM interface.
  • the execution core 16 is provided with a plurality of arithmetic units.
  • the execution core 16 includes an ALU (Arithmetic and Logic Unit) 161 that is a general-purpose arithmetic unit, a dedicated arithmetic circuit 162 that is a dedicated arithmetic unit, and another arithmetic unit 163.
  • ALU Arimetic and Logic Unit
  • the dedicated arithmetic circuit 162 that is a dedicated arithmetic unit
  • another arithmetic unit 163 In the case where the circuit scale of the dedicated arithmetic circuit 162 is large, making the dedicated arithmetic circuit 162 redundant to have a plurality leads to pressure on the circuit scale.
  • the ALU 161 is used to perform redundancy relief when the dedicated arithmetic circuit 162 fails.
  • step S001 the fault of the dedicated arithmetic circuit 162 is checked.
  • step S002 following step S001, it is determined whether a failure of the dedicated arithmetic circuit 162 has been detected. If a failure of dedicated arithmetic circuit 162 is detected (YES in step S002), the process proceeds to step S004. If a failure of dedicated arithmetic circuit 162 is not detected (NO in step S002), the process proceeds to step S003.
  • step S003 it is determined that the dedicated arithmetic circuit 162 is used until the next check, and the process returns to step S001.
  • step S004 the process proceeds to checking whether to enter the alternative mode using the ALU 161.
  • step S005 following step S004 it is determined whether or not the processing time is enough when the process using the dedicated arithmetic circuit 162 is replaced with the ALU 161. If the processing time is in time (YES in step S005), the process proceeds to step S006. If the processing time is not in time (NO in step S005), the process proceeds to step S009. In step S009, an abnormality is notified and the process ends.
  • step S006 the mode is changed to the alternative mode using the ALU 161.
  • step S007 following step S006 a program dedicated to the ALU 161 is loaded into the dedicated I $.
  • step S008 following step S007, the processing of the dedicated arithmetic circuit 162 is replaced by the ALU 161 using an alternative program.
  • the I $ 601 is a memory, and is a part that stores a small program for realizing an alternative process in the ALU 161 when the dedicated arithmetic circuit 162 fails. In this case, not only the program but also the processing time is recorded together.
  • the I $ 601 can also store a failure determination program.
  • the failure determination program is an equivalent program for performing an operation equivalent to that of the dedicated arithmetic circuit 162 in the ALU 161.
  • the instruction decoder 602 decodes and outputs an instruction for processing a program to the dedicated arithmetic circuit 162 and the ALU 161.
  • the data loader 603 loads data necessary for processing into the dedicated arithmetic circuit 162 and the ALU 161.
  • the comparison unit 604 is a part that compares the calculation result performed by the ALU 161 with the expected value. If the expected value does not match, failure detection 606 is executed.
  • the failure determination unit 605 compares the operation result of the equivalent program of the ALU 161 with the operation result of the dedicated operation circuit 162, and performs failure determination when there is a mismatch. As a result of the failure determination, if it is determined that there is a failure, a result output 607 is executed.
  • the DFP 10 includes a defect detection unit 701, an alternative determination unit 702, and an alternative mode execution unit 703.
  • the defect detection unit 701 is a part that detects a defect in the dedicated arithmetic circuit 162 that is a dedicated arithmetic unit specialized for specific arithmetic processing.
  • the defect detection unit 701 compares the calculation result of the equivalent program of the ALU 161 with the calculation result of the dedicated calculation circuit 162, and detects that a defect has occurred when there is a mismatch.
  • the substitution judgment unit 702 is a part that judges whether or not the arithmetic processing specific to the ALU 161 that is a general-purpose arithmetic unit can be substituted when the fault detection unit 701 detects a fault in the dedicated arithmetic circuit 162 that is a dedicated arithmetic unit.
  • the alternative mode execution unit 703 is a part that causes the ALU 161, which is a general-purpose arithmetic unit, to execute a specific calculation process when the determination result of the replacement determination unit 702 is replaceable.
  • the ALU 161 when a problem occurs in the dedicated arithmetic circuit 162, the ALU 161 can perform an alternative process, so that a specific arithmetic process can be continued without reducing the circuit scale.

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Abstract

This semiconductor device is provided with: a fault detection unit (701) which detects a fault in a dedicated computing unit specialized in specific arithmetic processing; an alternative determination unit (702) which, when the fault detection unit (701) has detected a fault in the dedicated computing unit, determines whether or not the specific arithmetic processing can be performed by a general computing unit alternatively; and an alternative mode execution unit (703) which, when the determination result of the alternative determination unit (702) is affirmative, causes the general computing unit to execute the specific arithmetic processing.

Description

半導体装置Semiconductor device 関連出願の相互参照Cross-reference of related applications
　本出願は、2018年3月30日に出願された日本国特許出願2018-068427号に基づくものであって、その優先権の利益を主張するものであり、その特許出願の全ての内容が、参照により本明細書に組み込まれる。 This application is based on Japanese Patent Application No. 2018-068427 filed on March 30, 2018, and claims the benefit of its priority. Which is incorporated herein by reference.
　本開示は、複数且つ複数種類の演算器が設けられてなる半導体装置に関する。 The present disclosure relates to a semiconductor device provided with a plurality of types of arithmetic units.
　半導体装置のロジック領域に冗長救済を行うものとして、下記特許文献１に記載の発明が開示されている。下記特許文献１では、半導体装置に、ロジック領域内に設けられる同一の構成を有する複数の基本セルと、複数の基本セルと同一の構成を有する冗長セルと、複数の基本セル及び冗長セルのそれぞれに入力される信号を切り替える入力セレクタと、基本セル及び冗長セルのそれぞれから出力される信号を切り替える出力セレクタとを備えている。さらに、半導体装置は、入力セレクタ及び出力セレクタのうち少なくとも一方を切り替えて、冗長セルを機能させ複数の基本セルのうち故障したセルを救済する。 The invention described in Patent Document 1 below is disclosed as performing redundant relief in the logic area of a semiconductor device. In the following Patent Document 1, a semiconductor device includes a plurality of basic cells having the same configuration provided in a logic region, a redundant cell having the same configuration as the plurality of basic cells, and a plurality of basic cells and redundant cells, respectively. And an output selector that switches signals output from each of the basic cell and the redundant cell. Further, the semiconductor device switches at least one of the input selector and the output selector to function the redundant cell and repair the failed cell among the plurality of basic cells.
特開２０１０－４１７０５号公報JP 2010-41705 A
　特許文献１では、基本セルと同一の構成を有する冗長セルによって冗長救済を行っている。ところで、メインＣＰＵの処理を高速化するためにアクセラレータを設ける場合、特定の演算処理に特化した専用演算器を設けることが考えられる。上記特許文献１によれば、この場合にも専用演算器と同一の構成を有する演算器を設ける必要があるが、専用演算器の回路規模が大きい場合、回路規模の圧迫に繋がる。 In Patent Document 1, redundant relief is performed by a redundant cell having the same configuration as the basic cell. By the way, when an accelerator is provided in order to speed up the processing of the main CPU, it is conceivable to provide a dedicated arithmetic unit specialized for specific arithmetic processing. According to Patent Document 1, it is necessary to provide an arithmetic unit having the same configuration as that of the dedicated arithmetic unit in this case as well. However, when the circuit scale of the dedicated arithmetic unit is large, the circuit scale is compressed.
　本開示は、複数且つ複数種類の演算器が設けられてなる半導体装置であって、回路規模を圧迫せずに冗長救済の可能性を高めることが可能な半導体装置を提供することを目的とする。 An object of the present disclosure is to provide a semiconductor device provided with a plurality of types of arithmetic units, and capable of increasing the possibility of redundant relief without reducing the circuit scale. .
　本開示は、複数且つ複数種類の演算器が設けられてなる半導体装置であって、特定の演算処理に特化した専用演算器の不具合を検出する不具合検出部と、不具合検出部が専用演算器の不具合を検出した場合、汎用演算器で特定の演算処理が代替可能か否かを判断する代替判断部と、代替判断部の判断結果が代替可能というものである場合に、汎用演算器に特定の演算処理を実行させる代替モード実行部と、を備える。 The present disclosure is a semiconductor device provided with a plurality of types of arithmetic units, a fault detection unit for detecting a fault of a dedicated arithmetic unit specialized for specific arithmetic processing, and the fault detection unit is a dedicated arithmetic unit If a failure is detected, the alternative judgment unit that determines whether or not a specific arithmetic processing can be replaced by a general-purpose arithmetic unit, and the determination result of the alternative determination unit are substitutable. And an alternative mode execution unit that executes the above arithmetic processing.
　本開示によれば、専用演算器に不具合が発生した場合に汎用演算器で代替処理が可能となるので、回路規模を圧迫せずに特定の演算処理を継続することができる。 According to the present disclosure, when a problem occurs in the dedicated arithmetic unit, the general-purpose arithmetic unit can perform an alternative process, so that the specific arithmetic process can be continued without reducing the circuit scale.
図１は、本実施形態の前提となる並列処理について説明するための図である。FIG. 1 is a diagram for explaining parallel processing which is a premise of the present embodiment. 図２は、図１に示される並列処理を実行するためのシステム構成例を示す図である。FIG. 2 is a diagram showing a system configuration example for executing the parallel processing shown in FIG. 図３は、図２に用いられるＤＦＰの構成例を示す図である。FIG. 3 is a diagram illustrating a configuration example of the DFP used in FIG. 図４は、実行コアを構成する演算器を説明するための図である。FIG. 4 is a diagram for explaining an arithmetic unit constituting the execution core. 図５は、本実施形態の冗長救済方法を説明するためのフローチャートである。FIG. 5 is a flowchart for explaining the redundancy repair method of this embodiment. 図６は、本実施形態のＤＦＰにおいて図５に示すフローチャートの処理に関与する構成を説明するための図である。FIG. 6 is a diagram for explaining a configuration involved in the processing of the flowchart shown in FIG. 5 in the DFP of this embodiment. 図７は、本実施形態のＤＦＰにおいて図５に示すフローチャートの処理に関与する機能的な構成ブロックについて説明するための図である。FIG. 7 is a diagram for explaining functional configuration blocks involved in the processing of the flowchart shown in FIG. 5 in the DFP of this embodiment.
　以下、添付図面を参照しながら本実施形態について説明する。説明の理解を容易にするため、各図面において同一の構成要素に対しては可能な限り同一の符号を付して、重複する説明は省略する。 Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In order to facilitate the understanding of the description, the same constituent elements in the drawings will be denoted by the same reference numerals as much as possible, and redundant description will be omitted.
　図１（Ａ）は、グラフ構造のプログラムコードを示しており、図１（Ｂ）は、スレッドの状態を示しており、図１（Ｃ）は、並列処理の状況を示している。 FIG. 1A shows a program code having a graph structure, FIG. 1B shows a thread state, and FIG. 1C shows a state of parallel processing.
　図１（Ａ）に示されるように、本実施形態が処理対象とするプログラムは、データと処理とが分割されているグラフ構造を有している。このグラフ構造は、プログラムのタスク並列性、グラフ並列性を保持している。 As shown in FIG. 1A, the program to be processed in this embodiment has a graph structure in which data and processing are divided. This graph structure maintains the task parallelism and graph parallelism of the program.
　図１（Ａ）に示されるプログラムコードに対して、コンパイラによる自動ベクトル化とグラフ構造の抽出を行うと、図１（Ｂ）に示されるような大量のスレッドを生成することができる。 1) When automatic vectorization and graph structure extraction are performed on the program code shown in FIG. 1A by a compiler, a large number of threads as shown in FIG. 1B can be generated.
　図１（Ｂ）に示される多量のスレッドに対して、ハードウェアによる動的レジスタ配置とスレッド・スケジューリングにより、図１（Ｃ）に示されるような並列実行を行うことができる。実行中にレジスタ資源を動的配置することで、異なる命令ストリームに対しても複数のスレッドを並列実行することができる。 1) Parallel execution as shown in FIG. 1C can be performed on a large number of threads shown in FIG. 1B by dynamic register placement and thread scheduling by hardware. By dynamically allocating register resources during execution, a plurality of threads can be executed in parallel for different instruction streams.
　続いて図２を参照しながら、動的レジスタ配置及びスレッド・スケジューリングを行うアクセラレータとしてのＤＦＰ（Ｄａｔａ　Ｆｌｏｗ　Ｐｒｏｃｅｓｓｏｒ）１０を含むシステム構成例である、データ処理システム２を説明する。ＤＦＰ１０は、本開示の半導体装置に相当する。 Next, a data processing system 2, which is a system configuration example including a DFP (Data Flow Processor) 10 as an accelerator for performing dynamic register placement and thread scheduling, will be described with reference to FIG. The DFP 10 corresponds to the semiconductor device of the present disclosure.
　データ処理システム２は、ＤＦＰ１０と、イベントハンドラ２０と、ホストＣＰＵ２１と、ＲＯＭ２２と、ＲＡＭ２３と、外部インターフェイス２４と、システムバス２５と、を備えている。ホストＣＰＵ２１は、データ処理を主として行う演算装置である。ホストＣＰＵ２１は、ＯＳをサポートしている。イベントハンドラ２０は、割り込み処理を生成する部分である。 The data processing system 2 includes a DFP 10, an event handler 20, a host CPU 21, a ROM 22, a RAM 23, an external interface 24, and a system bus 25. The host CPU 21 is an arithmetic unit that mainly performs data processing. The host CPU 21 supports the OS. The event handler 20 is a part that generates an interrupt process.
　ＲＯＭ２２は、読込専用のメモリである。ＲＡＭ２３は、読み書き用のメモリである。外部インターフェイス２４は、データ処理システム２外と情報授受を行うためのインターフェイスである。システムバス２５は、ＤＦＰ１０と、ホストＣＰＵ２１と、ＲＯＭ２２と、ＲＡＭ２３と、外部インターフェイス２４との間で情報の送受信を行うためのものである。 ROM 22 is a read-only memory. The RAM 23 is a read / write memory. The external interface 24 is an interface for exchanging information with the outside of the data processing system 2. The system bus 25 is for transmitting and receiving information between the DFP 10, the host CPU 21, the ROM 22, the RAM 23, and the external interface 24.
　ＤＦＰ１０は、ホストＣＰＵ２１の重い演算負荷に対処するために設けられている個別のマスタとして位置づけられている。ＤＦＰ１０は、イベントハンドラ２０が生成した割り込みをサポートするように構成されている。 The DFP 10 is positioned as an individual master provided to cope with the heavy computation load of the host CPU 21. The DFP 10 is configured to support the interrupt generated by the event handler 20.
　続いて図３を参照しながら、ＤＦＰ１０について説明する。図３に示されるように、ＤＦＰ１０は、コマンドユニット１２と、スレッドスケジューラ１４と、実行コア１６と、メモリサブシステム１８と、を備えている。 Next, the DFP 10 will be described with reference to FIG. As shown in FIG. 3, the DFP 10 includes a command unit 12, a thread scheduler 14, an execution core 16, and a memory subsystem 18.
　コマンドユニット１２は、コンフィグ・インターフェイスとの間で情報通信可能なように構成されている。コマンドユニット１２は、コマンドバッファとしても機能している。 The command unit 12 is configured to be able to communicate information with the config interface. The command unit 12 also functions as a command buffer.
　スレッドスケジューラ１４は、図１（Ｂ）に例示されるような多量のスレッドの処理をスケジューリングする部分である。スレッドスケジューラ１４は、スレッドを跨いだスケジューリングを行うことが可能である。 The thread scheduler 14 is a part that schedules processing of a large number of threads as exemplified in FIG. The thread scheduler 14 can perform scheduling across threads.
　実行コア１６は、４つのプロセッシングエレメントである、ＰＥ＃０と、ＰＥ＃１と、ＰＥ＃２と、ＰＥ＃３と、を有している。実行コア１６は、独立してスケジューリング可能な多数のパイプラインを有している。 The execution core 16 has four processing elements, PE # 0, PE # 1, PE # 2, and PE # 3. The execution core 16 has a number of pipelines that can be scheduled independently.
　メモリサブシステム１８は、アービタ１８１と、Ｌ１キャッシュ１８ａと、Ｌ２キャッシュ１８ｂと、を有している。メモリサブシステム１８は、システム・バス・インターフェイス及びＲＯＭインターフェイスとの間で情報通信可能なように構成されている。 The memory subsystem 18 includes an arbiter 181, an L1 cache 18a, and an L2 cache 18b. The memory subsystem 18 is configured to allow information communication between the system bus interface and the ROM interface.
　続いて、図４を参照しながら、実行コア１６について説明を加える。実行コア１６は、複数且つ複数種類の演算器が設けられている。実行コア１６は、汎用演算器であるＡＬＵ（Ａｒｉｔｈｍｅｔｉｃ　ａｎｄ　Ｌｏｇｉｃ　Ｕｎｉｔ）１６１と、専用演算器である専用演算回路１６２と、他の演算器１６３と、を備えている。専用演算回路１６２の回路規模が大きい場合、専用演算回路１６２を冗長化させて複数持つことは回路規模の圧迫に繋がる。しかしながら、専用演算回路１６２が故障した場合に全ての処理が停止してしまうことは極力避けるべきであり、専用演算回路１６２の故障後もしばらくの間は正しく動作を続ける必要がある。そこで、本実施形態では、ＡＬＵ１６１を活用することで、専用演算回路１６２が故障した場合の冗長救済を行うものである。 Subsequently, the execution core 16 will be described with reference to FIG. The execution core 16 is provided with a plurality of arithmetic units. The execution core 16 includes an ALU (Arithmetic and Logic Unit) 161 that is a general-purpose arithmetic unit, a dedicated arithmetic circuit 162 that is a dedicated arithmetic unit, and another arithmetic unit 163. In the case where the circuit scale of the dedicated arithmetic circuit 162 is large, making the dedicated arithmetic circuit 162 redundant to have a plurality leads to pressure on the circuit scale. However, it should be avoided as much as possible that all processing stops when the dedicated arithmetic circuit 162 fails, and it is necessary to continue to operate correctly for a while after the failure of the dedicated arithmetic circuit 162. Thus, in the present embodiment, the ALU 161 is used to perform redundancy relief when the dedicated arithmetic circuit 162 fails.
　図５を参照しながら、本実施形態の冗長救済方法について説明する。ステップＳ００１では、専用演算回路１６２の不具合をチェックする。ステップＳ００１に続くステップＳ００２では、専用演算回路１６２の不具合を検出したか否かを判断する。専用演算回路１６２の不具合を検出した場合（ステップＳ００２においてＹＥＳ）は、ステップＳ００４の処理に進む。専用演算回路１６２の不具合を検出しない場合（ステップＳ００２においてＮＯ）は、ステップＳ００３の処理に進む。 Referring to FIG. 5, the redundancy repair method of this embodiment will be described. In step S001, the fault of the dedicated arithmetic circuit 162 is checked. In step S002 following step S001, it is determined whether a failure of the dedicated arithmetic circuit 162 has been detected. If a failure of dedicated arithmetic circuit 162 is detected (YES in step S002), the process proceeds to step S004. If a failure of dedicated arithmetic circuit 162 is not detected (NO in step S002), the process proceeds to step S003.
　ステップＳ００３では、次のチェックまで専用演算回路１６２を使用することを決定し、ステップＳ００１の処理に戻る。 In step S003, it is determined that the dedicated arithmetic circuit 162 is used until the next check, and the process returns to step S001.
　ステップＳ００４では、ＡＬＵ１６１を用いた代替モードに入れるか否かのチェックに移行する。ステップＳ００４に続くステップＳ００５では、専用演算回路１６２を使用している処理をＡＬＵ１６１で代替した場合に、処理時間が間に合うか否かを判断する。処理時間が間に合えば（ステップＳ００５においてＹＥＳ）、ステップＳ００６の処理に進む。処理時間が間に合わなければ（ステップＳ００５においてＮＯ）、ステップＳ００９の処理に進む。ステップＳ００９では、異常を通知して処理を終了する。 In step S004, the process proceeds to checking whether to enter the alternative mode using the ALU 161. In step S005 following step S004, it is determined whether or not the processing time is enough when the process using the dedicated arithmetic circuit 162 is replaced with the ALU 161. If the processing time is in time (YES in step S005), the process proceeds to step S006. If the processing time is not in time (NO in step S005), the process proceeds to step S009. In step S009, an abnormality is notified and the process ends.
　ステップＳ００６では、ＡＬＵ１６１を用いる代替モードに以降する。ステップＳ００６に続くステップＳ００７では、ＡＬＵ１６１専用のプログラムを専用Ｉ＄にロードする。ステップＳ００７に続くステップＳ００８では、ＡＬＵ１６１で代替プログラムを用いて専用演算回路１６２の処理を代替する。ステップＳ００８の処理が終了するとステップＳ００６の処理に戻る。 In step S006, the mode is changed to the alternative mode using the ALU 161. In step S007 following step S006, a program dedicated to the ALU 161 is loaded into the dedicated I $. In step S008 following step S007, the processing of the dedicated arithmetic circuit 162 is replaced by the ALU 161 using an alternative program. When the process of step S008 ends, the process returns to step S006.
　図６を参照しながら、図５に示すフローチャートの処理に関与する構成を説明する。Ｉ＄６０１は、メモリであって、専用演算回路１６２が故障した際に、ＡＬＵ１６１で代替処理を実現するための小さなプログラムを格納する部分である。この場合、プログラムだけでなく、その処理時間も一緒に記録する。 The configuration involved in the processing of the flowchart shown in FIG. 5 will be described with reference to FIG. The I $ 601 is a memory, and is a part that stores a small program for realizing an alternative process in the ALU 161 when the dedicated arithmetic circuit 162 fails. In this case, not only the program but also the processing time is recorded together.
　Ｉ＄６０１は、故障判定用プログラムも格納することができる。故障判定用プログラムは、ＡＬＵ１６１において専用演算回路１６２と同等の演算を行うための等価なプログラムである。 The I $ 601 can also store a failure determination program. The failure determination program is an equivalent program for performing an operation equivalent to that of the dedicated arithmetic circuit 162 in the ALU 161.
　命令デコーダ６０２は、専用演算回路１６２及びＡＬＵ１６１に、プログラムを処理するための命令をデコードして出力する。データローダ６０３は、処理に必要なデータを専用演算回路１６２及びＡＬＵ１６１にロードする。 The instruction decoder 602 decodes and outputs an instruction for processing a program to the dedicated arithmetic circuit 162 and the ALU 161. The data loader 603 loads data necessary for processing into the dedicated arithmetic circuit 162 and the ALU 161.
　比較部６０４は、ＡＬＵ１６１で行った演算結果を期待値と比較する部分である。期待値と不一致であると、故障検出６０６を実行する。故障判定部６０５は、ＡＬＵ１６１の等価プログラムの演算結果と、専用演算回路１６２の演算結果とを比較し、不一致の場合に故障判定を行う。故障判定の結果故障と判断されれば、結果出力６０７を実行する。 The comparison unit 604 is a part that compares the calculation result performed by the ALU 161 with the expected value. If the expected value does not match, failure detection 606 is executed. The failure determination unit 605 compares the operation result of the equivalent program of the ALU 161 with the operation result of the dedicated operation circuit 162, and performs failure determination when there is a mismatch. As a result of the failure determination, if it is determined that there is a failure, a result output 607 is executed.
　図７を参照しながら、ＤＦＰ１０の機能的な構成要素の中で、図５及び図６に関連する処理を実行する構成要素について説明する。ＤＦＰ１０は、不具合検出部７０１と、代替判断部７０２と、代替モード実行部７０３と、を備えている。 Referring to FIG. 7, among the functional components of the DFP 10, components that execute the processes related to FIGS. 5 and 6 will be described. The DFP 10 includes a defect detection unit 701, an alternative determination unit 702, and an alternative mode execution unit 703.
　不具合検出部７０１は、特定の演算処理に特化した専用演算器である専用演算回路１６２の不具合を検出する部分である。不具合検出部７０１は、ＡＬＵ１６１の等価プログラムの演算結果と、専用演算回路１６２の演算結果とを比較し、不一致の場合に不具合が発生していることを検出する。 The defect detection unit 701 is a part that detects a defect in the dedicated arithmetic circuit 162 that is a dedicated arithmetic unit specialized for specific arithmetic processing. The defect detection unit 701 compares the calculation result of the equivalent program of the ALU 161 with the calculation result of the dedicated calculation circuit 162, and detects that a defect has occurred when there is a mismatch.
　代替判断部７０２は、不具合検出部７０１が専用演算器である専用演算回路１６２の不具合を検出した場合、汎用演算器であるＡＬＵ１６１特定の演算処理が代替可能か否かを判断する部分である。 The substitution judgment unit 702 is a part that judges whether or not the arithmetic processing specific to the ALU 161 that is a general-purpose arithmetic unit can be substituted when the fault detection unit 701 detects a fault in the dedicated arithmetic circuit 162 that is a dedicated arithmetic unit.
　代替モード実行部７０３は、代替判断部７０２の判断結果が代替可能というものである場合に、汎用演算器であるＡＬＵ１６１に特定の演算処理を実行させる部分である。 The alternative mode execution unit 703 is a part that causes the ALU 161, which is a general-purpose arithmetic unit, to execute a specific calculation process when the determination result of the replacement determination unit 702 is replaceable.
　本実施形態によれば、専用演算回路１６２に不具合が発生した場合にＡＬＵ１６１で代替処理が可能となるので、回路規模を圧迫せずに特定の演算処理を継続することができる。 According to the present embodiment, when a problem occurs in the dedicated arithmetic circuit 162, the ALU 161 can perform an alternative process, so that a specific arithmetic process can be continued without reducing the circuit scale.
　本実施形態では、代替判断部７０２は、汎用演算器としてのＡＬＵ１６１で特定の演算処理を行った場合の処理時間が予め定められている予定処理時間を超えない場合に、代替可能であると判断することができる（図５のステップＳ００５）。 In this embodiment, the substitution determining unit 702 determines that substitution is possible when the processing time when the specific arithmetic processing is performed by the ALU 161 as the general-purpose arithmetic unit does not exceed a predetermined scheduled processing time. (Step S005 in FIG. 5).
　本実施形態では、代替判断部７０２は、汎用演算器としてのＡＬＵ１６１で代替不可能と判断した場合、異常通知処理を実行する（図５のステップＳ００９）。 In the present embodiment, the substitution determining unit 702 executes an abnormality notification process when the ALU 161 serving as a general-purpose computing unit determines that substitution is not possible (step S009 in FIG. 5).
　以上、具体例を参照しつつ本実施形態について説明した。しかし、本開示はこれらの具体例に限定されるものではない。これら具体例に、当業者が適宜設計変更を加えたものも、本開示の特徴を備えている限り、本開示の範囲に包含される。前述した各具体例が備える各要素およびその配置、条件、形状などは、例示したものに限定されるわけではなく適宜変更することができる。前述した各具体例が備える各要素は、技術的な矛盾が生じない限り、適宜組み合わせを変えることができる。 The embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Those in which those skilled in the art appropriately modify the design of these specific examples are also included in the scope of the present disclosure as long as they have the features of the present disclosure. Each element included in each of the specific examples described above and their arrangement, conditions, shape, and the like are not limited to those illustrated, and can be changed as appropriate. Each element included in each of the specific examples described above can be appropriately combined as long as no technical contradiction occurs.

Claims (3)

  1. 　複数且つ複数種類の演算器が設けられてなる半導体装置であって、
    　特定の演算処理に特化した専用演算器の不具合を検出する不具合検出部（７０１）と、
    　前記不具合検出部が前記専用演算器の不具合を検出した場合、汎用演算器で前記特定の演算処理が代替可能か否かを判断する代替判断部（７０２）と、
    　前記代替判断部の判断結果が代替可能というものである場合に、前記汎用演算器に前記特定の演算処理を実行させる代替モード実行部（７０３）と、を備える半導体装置。     A semiconductor device provided with a plurality of types of arithmetic units,
    A defect detection unit (701) for detecting a defect of a dedicated arithmetic unit specialized for specific calculation processing;
    An alternative determination unit (702) for determining whether or not the specific arithmetic processing can be replaced by a general-purpose arithmetic unit when the fault detection unit detects a fault of the dedicated arithmetic unit;
    A semiconductor device comprising: an alternative mode execution unit (703) that causes the general-purpose arithmetic unit to execute the specific arithmetic processing when the determination result of the alternative determination unit is substitutable.
  2. 　請求項１に記載の半導体装置であって、
    　前記代替判断部は、前記汎用演算器で前記特定の演算処理を行った場合の処理時間が予め定められている予定処理時間を超えない場合に、代替可能であると判断する、半導体装置。     The semiconductor device according to claim 1,
    The substitution determination unit determines that substitution is possible when the processing time when the specific calculation processing is performed by the general-purpose arithmetic unit does not exceed a predetermined scheduled processing time.
  3. 　請求項２に記載の半導体装置であって、
    　前記代替判断部は、前記汎用演算器で代替不可能と判断した場合、異常通知処理を実行する、半導体装置。     The semiconductor device according to claim 2,
    The substitution determination unit is a semiconductor device that executes abnormality notification processing when the general-purpose arithmetic unit determines that substitution is impossible.
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