WO2019186743A1 - Semiconductor laser element and production method therefor - Google Patents

Semiconductor laser element and production method therefor Download PDF

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Publication number
WO2019186743A1
WO2019186743A1 PCT/JP2018/012627 JP2018012627W WO2019186743A1 WO 2019186743 A1 WO2019186743 A1 WO 2019186743A1 JP 2018012627 W JP2018012627 W JP 2018012627W WO 2019186743 A1 WO2019186743 A1 WO 2019186743A1
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Prior art keywords
conductivity type
contact layer
layer
type contact
semiconductor laser
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PCT/JP2018/012627
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French (fr)
Japanese (ja)
Inventor
一誠 岸本
直幹 中村
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2020510278A priority Critical patent/JP7040604B2/en
Priority to PCT/JP2018/012627 priority patent/WO2019186743A1/en
Priority to US16/963,054 priority patent/US11870212B2/en
Priority to CN201880091705.5A priority patent/CN111903021B/en
Publication of WO2019186743A1 publication Critical patent/WO2019186743A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0208—Semi-insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04256—Electrodes, e.g. characterised by the structure characterised by the configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04256—Electrodes, e.g. characterised by the structure characterised by the configuration
    • H01S5/04257—Electrodes, e.g. characterised by the structure characterised by the configuration having positive and negative electrodes on the same side of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/12—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227—Buried mesa structure ; Striped active layer
    • H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/028—Coatings ; Treatment of the laser facets, e.g. etching, passivation layers or reflecting layers
    • H01S5/0282—Passivation layers or treatments
    • H01S5/0283—Optically inactive coating on the facet, e.g. half-wave coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/2205—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers
    • H01S5/2222—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers having special electric properties
    • H01S5/2224—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers having special electric properties semi-insulating semiconductors

Definitions

  • the present invention relates to a surface-mount type semiconductor laser device in which a cavity end face is formed by dry etching, and a method for manufacturing the same.
  • Some semiconductor laser elements integrate a plurality of DFB (Distributed Feedback) lasers in order to achieve high speed.
  • DFB Distributed Feedback
  • Patent Documents 1 and 2 describe the surface-mount type semiconductor laser element. The formation of the cavity facet of the semiconductor laser device described in these is performed by cleavage.
  • Patent Document 3 discloses a surface-mount type semiconductor laser element in which the cavity end face is formed by dry etching. This document discloses a method of performing resonator end face formation and contact layer exposure for substrate side electrode formation by one dry etching.
  • the dry etching rate has a distribution in the wafer surface, and the rate is slowed down near the etching side surface due to the shadowing of ions. Therefore, in order to reliably expose the substrate-side contact layer in a desired region on the entire surface of the wafer, it is necessary to perform overetching in consideration of the rate distribution and tailing. In this case, the thickness of the substrate-side contact layer is reduced due to over-etching, leading to an increase in element resistance. Therefore, it is necessary to increase the thickness in advance by assuming a decrease in the layer thickness. However, increasing the contact layer thickness reduces the throughput of the epi growth apparatus.
  • a monitor PD for example, is to be integrated on the same chip in addition to the DFB laser, it is desirable to suppress current leakage between both elements, and this is achieved by partially increasing the resistance of the substrate side contact layer. It will be necessary. To increase the resistance, techniques such as thermal diffusion of impurities or ion implantation are assumed. However, if the contact layer is thick, the thermal diffusion time or ion implantation energy required for increasing the resistance will increase dramatically, further increasing the resistance. Increases manufacturing throughput.
  • the present invention has been made to solve the above-described problems, and its purpose is to reduce the parasitic capacitance and device capacitance, to provide high position accuracy of the resonator end face, and to minimize the contact layer thickness to reduce the production throughput. It is to obtain a semiconductor laser device and a method for manufacturing the same that can be increased.
  • a semiconductor laser device includes a substrate and a semiconductor layer formed on the substrate and having a first conductivity type contact layer.
  • the semiconductor layer has a resonator, and both sides are sandwiched between grooves.
  • a mesa having a second conductivity type contact layer is provided, and the side surface of the mesa including at least one end face of the resonator and the upper surface of the first conductivity type contact layer form an L shape, and the bottom surface of the groove and the L Both of the letter-shaped bottom surfaces are formed by the upper surface of the first conductivity type contact layer, and the side surfaces of the grooves are located near the bottom surface of the grooves and are inclined on the first inclined surface and the first inclined surface.
  • the L-shaped side surface includes a second inclined surface that is inclined in the vicinity of the L-shaped bottom surface, and a second surface that is substantially perpendicular to the second inclined surface.
  • the first conductive type contact layer is formed on the bottom surface of at least one groove. Comprising a first electrode that is continued, and a second electrode connected to the second conductive type contact layer.
  • a method of manufacturing a semiconductor laser device is a method of manufacturing a semiconductor laser device including a mesa having a resonator, and a first conductivity type contact layer, a first conductivity type cladding layer, The step of laminating the active layer, the second conductivity type cladding layer and the second conductivity type contact layer, and the dry etching to leave a part of the first conductivity type cladding layer, thereby forming grooves on both sides of the mesa Then, a dry etching process for forming an L shape having a side surface of the mesa including an end face of the resonator, and an etching side surface formed in the dry etching process are masked to provide selectivity with respect to the first conductivity type contact layer.
  • the first conductivity type contact layer is exposed by wet-etching the first conductivity type cladding layer on the bottom surface of the groove and the L-shaped bottom surface using an etchant having An etching process; a step of forming a first electrode connected to the first conductivity type contact layer at a bottom surface of at least one groove; and a second connection connected to the second conductivity type contact layer above the active layer. Forming an electrode.
  • the semiconductor laser device according to the present invention has small parasitic capacitance and device capacitance, high position accuracy of the resonator end face, and can minimize the thickness of the contact layer.
  • the manufacturing method according to the present invention it is possible to manufacture a semiconductor laser device in which the parasitic capacitance and the element capacitance are small, the position accuracy of the cavity end face is high, and the thickness of the contact layer is minimized. In addition, the throughput of the epi growth apparatus is improved.
  • FIG. 1 is a cross-sectional view of a semiconductor laser element according to a first embodiment.
  • 2 is a top view of the semiconductor laser element according to the first embodiment.
  • FIG. 1 is a cross-sectional view of a semiconductor laser element according to a first embodiment.
  • 6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment.
  • FIG. 6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment.
  • FIG. 6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment.
  • FIG. 6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment.
  • FIG. 6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment.
  • FIG. 6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment.
  • FIG. 6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment.
  • FIG. 6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment.
  • FIG. 6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment.
  • FIG. 6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment.
  • FIG. 6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment.
  • FIG. 6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment.
  • FIG. It is sectional drawing of the semiconductor laser element used for the verification experiment of the effect of this invention. It is a figure which shows the result of the verification experiment of the effect of this invention.
  • 10 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the second embodiment.
  • FIG. FIG. 6 is a cross-sectional view of a semiconductor laser element according to a second embodiment.
  • FIG. 6 is a cross-sectional view of a semiconductor laser element according to a second embodiment.
  • Embodiment 1 FIG. The semiconductor laser device and its manufacturing method according to the first embodiment will be described.
  • FIG. 1 is a cross-sectional view of the semiconductor laser device according to the first embodiment.
  • FIG. 2 is a top view.
  • AA and BB in FIG. 2 are cut lines showing the cross sections of FIGS. 1A and 1B, respectively.
  • FIG. 3 is a view similar to FIG. 1, but for the sake of explanation, hatching is removed and some lines are thickened.
  • An n-type contact layer 12 is formed on the substrate 10.
  • An n-type cladding layer 14, an active layer 18, and a p-type cladding layer 20 are formed on the n-type contact layer 12.
  • a ridge 22 is constituted by a part of the n-type cladding layer 14, the active layer 18, and a part of the p-type cladding layer 20. The ridge 22 functions as a laser waveguide. Block layers 16 are embedded on both side surfaces of the ridge 22.
  • a p-type contact layer 24 is formed on the p-type cladding layer 20.
  • a plurality of layers from the n-type contact layer 12 to the p-type contact layer 24 are collectively referred to as a semiconductor layer 36. Note that a diffraction grating structure in which the refractive index periodically changes may be formed in the n-type cladding layer 14 or the p-type cladding layer 20.
  • the substrate 10 is made of semi-insulating InP.
  • the n-type contact layer 12 is made of n-type InGaAs having a thickness of 1.0 ⁇ m.
  • the n-type cladding layer 14 is made of n-type InP having a thickness of 3.0 ⁇ m.
  • the active layer 18 has a thickness of 0.2 ⁇ m and includes an MQW (Multiple Quantum ⁇ Well) structure made of i-type AlGaInAs.
  • the p-type cladding layer 20 is made of p-type InP having a thickness of 2.0 ⁇ m.
  • the block layer 16 is formed by sequentially stacking Fe—InP (Fe-doped InP), n-type InP, and p-type InP.
  • the p-type contact layer 24 is made of p-type InGaAs having a thickness of 0.3 ⁇ m.
  • the n-type contact layer 12 and the p-type contact layer 24 may be made of n-type InGaAsP and p-type InGaAsP, respectively.
  • grooves 32 are formed on both sides of a region including the ridge 22.
  • a mesa 34 is constituted by the n-type cladding layer 14, the active layer 18, the p-type cladding layer 20, the p-type contact layer 24, and the block layer 16 sandwiched between the grooves 32.
  • An embedded semiconductor laser current confinement structure is formed from the p-type cladding layer 20 to the n-type cladding layer 14 in the mesa 34.
  • the bottom surface 46 of the groove 32 is constituted by the upper surface of the n-type contact layer 12.
  • the side surface of the groove 32 is divided into an inclined surface 38 near the bottom surface 46 and a side surface 42 thereabove.
  • the inclined surface 38 has an inclination in a reverse mesa direction with respect to a direction perpendicular to the substrate 10.
  • the reverse mesa direction is a direction in which the n-type cladding layer 14 bites from the upper side to the lower side in the direction perpendicular to the substrate.
  • the side surface 42 is substantially perpendicular to the substrate 10.
  • top surface of the n-type contact layer 12 constituting the bottom surface 46 may have unevenness after various manufacturing processes.
  • the n-type cladding layer 14 does not exist on the bottom surface 46, but may exist in a part. However, the n-type cladding layer 14 is allowed to exist only in the vicinity of the inclined surface 38 so as not to prevent electrical connection between an n-type electrode 28 and an n-type contact layer 12 described later.
  • the mesa 34 is cut in the vicinity of the resonator end face.
  • an L-shape 50 is formed on the side surface of the mesa 34 including the end face of the resonator and the upper surface of the n-type contact layer 12.
  • the bottom surface 48 of the L-shape 50 is formed by the top surface of the n-type contact layer 12.
  • the side surface of the L-shaped 50 is divided into an inclined surface 40 in the vicinity of the bottom surface 48 and a side surface 44 thereon.
  • the inclined surface 40 has a forward mesa direction inclination with respect to a direction perpendicular to the substrate 10.
  • the forward mesa direction is a direction in which the n-type cladding layer 14 spreads from above to below in a direction perpendicular to the substrate.
  • the side surface 44 is substantially perpendicular to the substrate 10.
  • the side surface 44 has a lower end extending to the vicinity of the upper surface of the n-type contact layer 12 and functions as an end surface of the resonator.
  • the inclined surface 40 is made longer for the sake of explanation. However, it is actually preferable that the inclined surface 40 is short and the lower end of the side surface 44 extends to the vicinity of the upper surface of the n-type contact layer 12.
  • the upper surface of the n-type contact layer 12 constituting the bottom surface 48 may have unevenness after various manufacturing processes.
  • the n-type cladding layer 14 does not exist on the bottom surface 48, but may exist.
  • an insulating film 26 is formed from the bottom surface of the groove 32 through the side surface and over the p-type contact layer 24.
  • the insulating film 26 is also formed over the p-type contact layer 24 from the bottom surface to the side surface of the L-shape 50.
  • the insulating film 26 has openings on the bottom surface 46 of the groove 32 and the top of the mesa 34.
  • the n-side electrode 28 connected to the n-type contact layer 12 through the opening of the insulating film 26 on the bottom surface 46 of the left-side groove 32 of the left and right grooves 32 shown in FIGS. Are formed so as to be drawn on the insulating film 26.
  • a p-side electrode 30 connected to the p-type contact layer 24 through the opening of the insulating film 26 on the mesa 34 is formed.
  • the connection here is an electrical connection.
  • the semiconductor laser device according to the first embodiment is a surface-mounting type semiconductor laser device in which both the n-side electrode 28 and the p-side electrode 30 are formed on the surface side.
  • a (100) InP substrate is prepared as the substrate 10.
  • an n-type contact layer 12, an n-type cladding layer 14, an active layer 18, and a p-type cladding layer 20 are formed on the substrate 10 by MOCVD (Metal Laminate by Organic (Chemical Vapor Deposition) method.
  • MOCVD Metal Laminate by Organic (Chemical Vapor Deposition) method.
  • a ridge 22 extending along the ⁇ 011> direction is formed.
  • a mask 52 having a ridge pattern is formed.
  • the mask 52 is formed by, for example, forming a 0.4 ⁇ m-thick SiO (composition is arbitrary) film by plasma CVD (Chemical Vapor Deposition), and then forming a resist pattern on the SiO film using photolithography. This is possible by transferring the resist pattern to the SiO film by an RIE (Reactive Ion Etching) method using a CF 4 / O 2 mixed gas, and then removing the resist with O 2 plasma.
  • RIE Reactive Ion Etching
  • the ridge 22 is formed by etching a part of the p-type cladding layer 20, the active layer 18, and the n-type cladding layer 14 by, for example, RIE using an SiCl 4 / Ar mixed gas, using the mask 52 as an etching mask. .
  • both side surfaces of the ridge 22 are buried with the block layer 16 by MOCVD.
  • the p-type cladding layer 20 and the p-type contact layer 24 are laminated on the entire surface by MOCVD.
  • a mask 54 is formed as shown in FIG.
  • the method for forming the mask 54 is the same as that for the mask 52 described above.
  • An opening 56 and an opening 58 are formed in the mask 54.
  • the edge of the opening 56 is parallel to the ridge 22 (ie, parallel to the ⁇ 011> direction), and the edge of the opening 58 is perpendicular to the ridge 22 (ie, parallel to the ⁇ 01-1> direction).
  • dry etching is performed using a mask 54 to form a groove 32a and an L-shape 50a.
  • the L-shape 50 a is composed of the side surfaces of the p-type contact layer 24, the p-type cladding layer 20, the active layer 18, the n-type cladding layer 14, and the upper surface of the n-type cladding layer 14.
  • the L shape 50a is represented by a thick line for the sake of explanation. Dry etching is performed so that the side surfaces of the groove 32a and the L-shaped 50a are substantially perpendicular to the substrate 10. The side surface thus formed is referred to as an etching side surface.
  • the inclination angle of the etching side surface with respect to the surface perpendicular to the substrate 10 is preferably within 5 °, more preferably within 1 °.
  • a gas containing a halogen element for example, a SiCl 4 / Ar mixed gas, is preferably used as an etching gas by an ICP (Inductive Coupled Plasma) -RIE method under a low pressure and a high bias. The dry etching is stopped before the deepest portion of the bottom surface of the L-shaped 50a reaches the n-type contact layer 12.
  • the electrical resistance of the n-type contact layer 12 increases by the thickness reduction, but this is acceptable. If so, you can do that. Further, only the front end face of the resonator may be formed by this dry etching, only the rear end face may be formed, or both end faces may be formed.
  • FIG. 9B shows an enlarged view of the vicinity of the bottom surface of the L-shape 50a. This tailing is because the etching rate in the vicinity of the side surface decreases due to the shadowing effect of ions.
  • a mask 60 is formed on the entire surface including the grooves 32a and the side surfaces of the L-shape 50a.
  • SiO having a thickness of 0.2 ⁇ m formed by plasma CVD can be used as the mask 60.
  • the entire surface of the mask 60 is etched back, and the mask 60 other than the grooves 32a and the side surfaces of the L-shape 50a is removed.
  • the mask 54 on the p-type contact layer 24 can be left by appropriately adjusting the etch back time.
  • Etchback is preferably performed under low pressure conditions in order to prevent the film thickness of SiO formed on the side surfaces of the groove 32a and the L-shaped 50a from being reduced by side etching.
  • a mixed gas of CF 4 / O 2 is used.
  • the ICP-RIE method used can be used.
  • the bottom surfaces of the grooves 32a and the L-shape 50a are wet-etched.
  • the n-type cladding layer 14 is immersed in an etchant having selectivity with respect to InGaAs, which is the material of the n-type contact layer, for example, a hydrochloric acid / phosphoric acid mixed solution, and is formed on the bottom surface of the groove 32a and the L-shaped 50a. Etch. In this way, the mesa 34, the groove 32, and the L shape 50 are formed.
  • InGaAs is the material of the n-type contact layer, for example, a hydrochloric acid / phosphoric acid mixed solution
  • the inclined surface 38 in the vicinity of the bottom surface 46 of the groove 32 has an inclination nearly perpendicular to the reverse mesa direction, and the n-type contact layer 12 is exposed on the bottom surface 46.
  • the inclined surface 40 in the vicinity of the L-shaped bottom surface 48 has a forward mesa direction inclination, and the n-type contact layer 12 is exposed at the bottom surface 48.
  • the etching side surface is protected from wet etching by the mask 60 formed on the side surface of the groove 32a and the L-shaped 50a, the perpendicularity of the etching side surface is maintained.
  • channel 32 and the L-shape 50 are formed simultaneously, each bottom face 46 and the bottom face 48 become equal height.
  • An etchant containing hydrogen bromide may be used. By the way, it is not essential to leave the mask 54 in the formation of the mask 60.
  • the p-type contact layer 24 is made of InGaAs, even if etching back is performed until the mask 54 disappears, the p-type contact layer 24 becomes an etching mask for wet etching, and the semiconductor surface is etched. Can be prevented.
  • the n-type cladding layer 14 on the bottom surface 46 and the bottom surface 48 is completely scraped, but a part of the n-type cladding layer 14 may remain.
  • the inclination in the reverse mesa direction and the forward mesa direction is due to the crystal orientation dependency of wet etching.
  • the mesa 34 is formed along the ⁇ 011> direction and a mixed solution of hydrochloric acid / phosphoric acid is used as the etchant, the inclined surface 38 of the mesa 34 becomes an inverted mesa that is nearly vertical, and an L-shaped 50
  • the inclined surface 40 is a forward mesa.
  • the direction of the mesa 34 may be rotated by 90 ° (that is, it may be formed along the ⁇ 01-1> direction). In this case, the forward / reverse direction of the mesa is different from that of FIG. Vice versa.
  • a liquid containing hydrogen bromide in the etchant for example, a mixed liquid of hydrogen bromide and H 2 O, and the forward / reverse mesa angle varies depending on the etching conditions.
  • the present invention does not limit the direction and angle of the mesa, and can be modified by the mesa direction and the etchant.
  • an insulating film 26 is formed as shown in FIG. Specifically, after first immersing in BHF (buffered hydrofluoric acid) and removing the mask 54 and the mask 60, for example, a plasma CVD method is used to form a 0.4 ⁇ m-thick SiO (composition is arbitrary) film over the entire surface. Form. Further, an opening 66 and an opening 68 are formed on the bottom surface 46 of the groove 32 and the mesa 34 using photolithography and RIE, respectively. The opening 66 is a contact region with the n-side electrode 28, and the opening 68 is a contact region with the p-side electrode 30.
  • the insulating film 26 defines a current injection region, functions as a protective film for protecting the semiconductor surface from contamination, and further functions as a part of the coating film for controlling the reflectance at the resonator end face.
  • the insulating film 26 may be SiN, TiO, TaO, AlO (these compositions are arbitrary) or a laminated film thereof.
  • the film formation method may be a sputtering method or an ALD (Atomic Layer Deposition) method. Good.
  • the n-side electrode 28 and the p-side electrode 30 are formed by photolithography and wet etching. Thereafter, the substrate 10 may be cleaved into a bar state, and a coat film may be formed on the side surface of the L-shaped 50 to adjust the reflectance at the resonator end face. Thereby, the formation of the semiconductor laser element is completed.
  • a diffraction grating structure made of InGaAsP having a periodic structure of, for example, a thickness of 40 nm and a pitch of 200 nm in the cavity direction may be formed in the n-type cladding layer 14 or the p-type cladding layer 20.
  • an InGaAsP layer having a thickness of 40 nm is formed in the middle of forming the InP clad layer, an SiO film having a thickness of 25 nm is formed by plasma CVD, and a diffraction grating pattern is formed using an electron beam lithography method and an RIE method. Transfer to the SiO film, etch the InGaAsP layer by the RIE method using a mixed gas of CH 4 / H 2 , and grow the cladding layer again to embed a diffraction grating made of InGaAsP.
  • this semiconductor laser element is a surface mount type, the parasitic capacitance caused by the wire wiring and the capacitance between the electrodes are small.
  • the capacitance between the electrodes is increased.
  • the capacitance between the electrodes is reduced.
  • the grooves are provided on both sides of the mesa, the element capacity can be further reduced.
  • the cavity end face is formed by dry etching, its positional accuracy is high.
  • the overlay accuracy of the resonator end face position thus formed is at a submicron level, which is the overlay accuracy of photolithography, and can be greatly improved with respect to variations of several microns when cleavage is used.
  • a multiwavelength integrated semiconductor laser element a plurality of DFB lasers having different wavelengths are integrated, and it is necessary to control the phase of the diffraction grating at the cavity end face of these DFBs in order to improve the SMSR yield. For this reason, in addition to pattern formation so that the phase of the diffraction grating is aligned at the intended position, the resonator end face must be accurately formed at that position. Therefore, the present invention is also suitable for a multiwavelength integrated semiconductor laser device.
  • the mirror loss is small. If this lower end approaches the active layer, the mirror loss due to the inclined surface below it increases, but this problem can be suppressed in this semiconductor laser device.
  • FIGS. 15A and 15B are cross-sectional views of the FP laser used in the experiment.
  • D b of FIG. 15 (a) d a and 15 in (b) in represents the distance to the upper end of the inclined surface from the lower end of the active layer, has a d a> d b.
  • FIG. 16 shows measurement results showing current (I F ) dependence (PI characteristics) on the optical output (P O ) of the FP laser, and (a) and (b) in FIG. , (B).
  • the FP laser of FIG. 15A has better PI characteristics. This is due to the condition of d a > d b , and indicates that the mirror loss is smaller as the inclined surface is farther from the active layer.
  • dry etching may be performed as long as possible until just before reaching the n-type cladding layer, or the n-type cladding layer may be thickened.
  • the cavity facet and the groove are formed at the same time, so that the semiconductor laser element can be formed with fewer steps.
  • the wet etching selectivity allows exposure without reducing the film thickness of the substrate-side contact layer, it is possible to prevent an increase in element resistance due to a decrease in the contact layer thickness. Therefore, it is sufficient to secure a minimum film thickness for obtaining a desired element resistance in advance, and the throughput of the epi growth apparatus is improved.
  • Embodiment 2 A method for manufacturing the semiconductor laser element according to the second embodiment will be described. Here, steps similar to those in the manufacturing method of the first embodiment will not be described in detail, and differences from the first embodiment will be mainly described. Differences from the first embodiment will be mainly described regarding the obtained effects.
  • the exposure of the n-type contact layer is detected by the change in the plasma emission intensity by dry etching, and the dry etching is stopped after the detection.
  • the plasma emission intensity of the constituent elements of the n-type contact layer or the n-type cladding layer changes, so that any one of these elements may be monitored.
  • the n-type contact layer is InGaAs and the n-type cladding layer is InP
  • the plasma emission intensity of any one of In, Ga, As, and P may be monitored.
  • a layer containing these elements is stacked above the n-type cladding layer, the plasma emission intensity changes during the etching of these layers. In order to prevent this change from being erroneously detected, it is only necessary to know the speed of dry etching in advance, predict the time for etching to reach the n-type cladding layer, and start monitoring after that time has elapsed.
  • FIG. 17 shows a cross-sectional view after dry etching.
  • FIG. 17 (b) shows an enlarged view of the vicinity of the corner of the L-shape 72a. From the figure, it can be seen that the deepest portion of the groove 70 a and the L-shape 72 a formed by dry etching coincides with the upper surface of the n-type contact layer 74. 17B, it can be seen that the side surface of the L-shape 72a substantially perpendicular to the substrate 10 extends to the vicinity of the lower end of the n-type cladding layer 76. The lower end of the substantially vertical side surface is maximally below the constraint that the dry etching does not overcut the n-type contact layer 74.
  • FIGS. 18 and 19 correspond to these drawings, respectively. 19 and FIG. 3, it can be seen that the lower end of the side surface 84 and the side surface 86 of the semiconductor laser device manufactured using the manufacturing method of the second embodiment extends further downward.
  • mirror loss due to the inclined surface can be suppressed.
  • the dry etching is performed until the n-type contact layer 74 is exposed, so that the side surface 86 of the L-shape 72 extends downward to the maximum. Therefore, mirror loss due to the inclined surface 82 under the side surface 86 can be reduced.

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Abstract

In this invention, a mesa (34) comprises a resonator and a second conduction type contact layer (24), grooves (32) are formed on both sides of the mesa (34), an L-shape (50) is formed by a first conduction type contact layer (12) and a side surface of the mesa (34) which includes an end surface of the resonator. The upper surfaces of both the L-shape (50) and the grooves (32) are constituted from the first conduction type contact layer (12). Each of the side surfaces in each of the grooves (32) is constituted from a sloped surface (38) near a bottom surface (46), and a side surface (42) thereabove. The side surface of the L-shape (50) is constituted from a sloped surface (40) near the bottom surface (48) and a side surface (44) thereabove. A first electrode (28) is provided, which is connected to the first conduction contact layer (12) at the bottom surface (46) of the groove (32). A second electrode (30) is provided, which is connected to the second conduction type contact layer (24) at the top of the mesa (34).

Description

半導体レーザ素子およびその製造方法Semiconductor laser device and manufacturing method thereof
　この発明は、ドライエッチングで共振器端面を形成する表面実装型の半導体レーザ素子、およびその製造方法に関する。 The present invention relates to a surface-mount type semiconductor laser device in which a cavity end face is formed by dry etching, and a method for manufacturing the same.
　光通信ネットワークでやり取りされるデータ量は増大を続けているため、光通信ネットワークで使用される半導体レーザ素子には動作速度の高速化が継続的に要求されている。 Since the amount of data exchanged over the optical communication network continues to increase, semiconductor laser elements used in the optical communication network are continuously required to increase the operating speed.
　半導体レーザ素子の中には高速化を実現するために複数のＤＦＢ（Distributed Feedback）レーザを集積したものがある。一例として、波長が異なる４つの２５Ｇｂｐｓ　ＤＦＢレーザを集積し、これらから出射されるレーザ光を内部で合波して１００Ｇｂｐｓの光信号を出力するものが挙げられる。 Some semiconductor laser elements integrate a plurality of DFB (Distributed Feedback) lasers in order to achieve high speed. As an example, there is an example in which four 25 Gbps DFB lasers having different wavelengths are integrated, and laser beams emitted from these are combined internally to output a 100 Gbps optical signal.
　このような多波長集積半導体レーザ素子の実現には電気容量の低減と共振器端面の位置精度向上が重要である。電気容量の低減は、半導体レーザ素子を変調する電気信号の高速化に寄与する。共振器端面の位置精度向上は、共振器端面における回折格子の位相制御を容易にし、ＳＭＳＲ（Side Mode Suppression Ratio）歩留まり向上につながる。 In order to realize such a multi-wavelength integrated semiconductor laser device, it is important to reduce the electric capacity and improve the position accuracy of the resonator end face. Reduction of the electric capacity contributes to speeding up of an electric signal for modulating the semiconductor laser element. Improvement of the position accuracy of the resonator end face facilitates phase control of the diffraction grating at the end face of the resonator and leads to an improvement in SMSR (Side Mode Suppression Ratio) yield.
　電気容量を低減するには表面実装型構造の適用が有効である。表面実装型でない半導体レーザ素子では２つの電極がそれぞれ素子表面と裏面にあるため、素子容量が大きくなる。一方、表面実装型では２つの電極をどちらも素子表面側に形成するため、素子容量が低減される。加えて、フリップチップ実装が可能になるためワイヤ配線に起因する寄生容量の低減が可能になる。 ∙ Application of surface mount type structure is effective for reducing electric capacity. In a semiconductor laser device that is not a surface mount type, the two electrodes are on the front surface and the back surface of the device, respectively, so that the device capacity is increased. On the other hand, since the two electrodes are formed on the element surface side in the surface mount type, the element capacitance is reduced. In addition, since flip chip mounting is possible, it is possible to reduce parasitic capacitance due to wire wiring.
　共振器端面の位置精度を向上するには端面形成にドライエッチングを用いるのが有効である。端面形成にドライエッチングでなくへき開を用いると機械的ばらつきにより位置精度が悪くなる。一方、ドライエッチングは位置精度がフォトリソグラフの重ね合わせ精度で決まり、その値はサブミクロンレベルであるため、端面形成にドライエッチングを用いれば位置精度を向上できる。 It is effective to use dry etching to form the end face in order to improve the position accuracy of the cavity end face. When cleavage is used instead of dry etching for forming the end face, the positional accuracy is deteriorated due to mechanical variation. On the other hand, since the position accuracy of dry etching is determined by the overlay accuracy of photolithography, and the value is at a submicron level, the position accuracy can be improved by using dry etching for end face formation.
　表面実装型の半導体レーザ素子について記載したものに特許文献１、２がある。これらに記載の半導体レーザ素子の共振器端面形成はへき開で実施している。 Patent Documents 1 and 2 describe the surface-mount type semiconductor laser element. The formation of the cavity facet of the semiconductor laser device described in these is performed by cleavage.
　また、表面実装型であって、共振器端面の形成をドライエッチングで実施した半導体レーザ素子について記載したものに特許文献３がある。この文献では共振器端面形成と、基板側電極形成のためのコンタクト層露出とを１度のドライエッチングで実施する方法が開示されている。 Further, Patent Document 3 discloses a surface-mount type semiconductor laser element in which the cavity end face is formed by dry etching. This document discloses a method of performing resonator end face formation and contact layer exposure for substrate side electrode formation by one dry etching.
特開平７－１３５３６９号公報JP 7-135369 A 特開２０１２－２０９４８９号公報JP 2012-209489 A 特開２００４－２８８８７６号公報JP 2004-288876 A
　特許文献１、２のように、共振器端面の形成にドライエッチングではなくへき開を用いた場合、機械的ばらつきによって端面位置精度が悪化してしまうという問題がある。このことは、ＤＦＢレーザにおいて高度な端面位相制御が求められる場合、特に１００Ｇｂｐｓ通信に用いる４波長集積ＤＦＢレーザを製造する場合においては、ＳＭＳＲ歩留まりを大きく低下させる要因となる。 As in Patent Documents 1 and 2, when cleaving is used instead of dry etching for forming the resonator end face, there is a problem that the end face position accuracy deteriorates due to mechanical variation. This is a factor that greatly reduces the SMSR yield when high-end facet phase control is required in the DFB laser, particularly when a 4-wavelength integrated DFB laser used for 100 Gbps communication is manufactured.
　一方、特許文献３のように、端面をドライエッチングで形成する場合、端面位置精度は改善される。このドライエッチングによる端面形成工程は、基板側電極引き出し部分を設けるための基板側コンタクト層露出を兼ねることが工程簡略化の観点から望ましいが、その場合は以下に述べるような製造上の問題がある。 On the other hand, as in Patent Document 3, when the end face is formed by dry etching, the end face position accuracy is improved. In this end face forming step by dry etching, it is desirable from the viewpoint of simplifying the process that the substrate side contact layer exposure for providing the substrate side electrode lead portion is desirable. In this case, however, there is a manufacturing problem as described below. .
　通常ドライエッチングレートはウエハ面内で分布を持つことに加えて、イオンのシャドーイングに起因してエッチング側面近傍でレートが遅くなり裾引きが生じる。したがってウエハ全面において所望の領域で基板側コンタクト層を確実に露出させるには、レート分布および裾引きを考慮してオーバーエッチングを行う必要がある。この場合、オーバーエッチングによって基板側コンタクト層の厚みが減少し、素子抵抗の増大を招くことから、今度は層厚減少を想定してあらかじめ厚膜化しておく必要が生じる。しかしながら、コンタクト層厚膜化はエピ成長装置のスループットを低下させる。さらに、同一チップ上に、ＤＦＢレーザに加えて例えばモニタＰＤを集積しようとした場合、両素子間の電流リークを抑制することが望ましく、これには基板側コンタクト層を部分的に高抵抗化することがが必要になる。高抵抗化には不純物の熱拡散、あるいはイオン注入といった手法が想定されるが、コンタクト層が厚いと高抵抗化に必要な熱拡散の時間、あるいはイオン注入エネルギーが飛躍的に増大し、更なる製造スループット増大を招く。 In general, the dry etching rate has a distribution in the wafer surface, and the rate is slowed down near the etching side surface due to the shadowing of ions. Therefore, in order to reliably expose the substrate-side contact layer in a desired region on the entire surface of the wafer, it is necessary to perform overetching in consideration of the rate distribution and tailing. In this case, the thickness of the substrate-side contact layer is reduced due to over-etching, leading to an increase in element resistance. Therefore, it is necessary to increase the thickness in advance by assuming a decrease in the layer thickness. However, increasing the contact layer thickness reduces the throughput of the epi growth apparatus. Further, when a monitor PD, for example, is to be integrated on the same chip in addition to the DFB laser, it is desirable to suppress current leakage between both elements, and this is achieved by partially increasing the resistance of the substrate side contact layer. It will be necessary. To increase the resistance, techniques such as thermal diffusion of impurities or ion implantation are assumed. However, if the contact layer is thick, the thermal diffusion time or ion implantation energy required for increasing the resistance will increase dramatically, further increasing the resistance. Increases manufacturing throughput.
　この発明は上述の問題を解決するためになされたもので、その目的は、寄生容量および素子容量が小さく、共振器端面の位置精度が高く、コンタクト層膜厚を最小限に抑えることで生産スループット増大を可能にする半導体レーザ素子およびその製造方法を得ることである。 The present invention has been made to solve the above-described problems, and its purpose is to reduce the parasitic capacitance and device capacitance, to provide high position accuracy of the resonator end face, and to minimize the contact layer thickness to reduce the production throughput. It is to obtain a semiconductor laser device and a method for manufacturing the same that can be increased.
　この発明に係る半導体レーザ素子は、基板と、基板の上に形成され、第１導電型コンタクト層を有する半導体層とを備え、半導体層には、共振器を有し、両脇が溝に挟まれ、第２導電型コンタクト層を有するメサが設けられ、共振器の少なくとも片側の端面を含むメサの側面と第１導電型コンタクト層の上面とがＬ字形状を成し、溝の底面およびＬ字形状の底面はどちらも第１導電型コンタクト層の上面で構成され、溝の側面は、溝の底面近傍にあり傾斜した第１の傾斜面、および、第１の傾斜面の上にありほぼ垂直な第１の側面で構成され、Ｌ字形状の側面は、Ｌ字形状の底面近傍にあり傾斜した第２の傾斜面、および、第２の傾斜面の上にありほぼ垂直な第２の側面で構成され、少なくとも１つの溝の底面で第１導電型コンタクト層に接続された第１の電極を備え、第２導電型コンタクト層に接続された第２の電極を備える。 A semiconductor laser device according to the present invention includes a substrate and a semiconductor layer formed on the substrate and having a first conductivity type contact layer. The semiconductor layer has a resonator, and both sides are sandwiched between grooves. A mesa having a second conductivity type contact layer is provided, and the side surface of the mesa including at least one end face of the resonator and the upper surface of the first conductivity type contact layer form an L shape, and the bottom surface of the groove and the L Both of the letter-shaped bottom surfaces are formed by the upper surface of the first conductivity type contact layer, and the side surfaces of the grooves are located near the bottom surface of the grooves and are inclined on the first inclined surface and the first inclined surface. The L-shaped side surface includes a second inclined surface that is inclined in the vicinity of the L-shaped bottom surface, and a second surface that is substantially perpendicular to the second inclined surface. The first conductive type contact layer is formed on the bottom surface of at least one groove. Comprising a first electrode that is continued, and a second electrode connected to the second conductive type contact layer.
　この発明に係る半導体レーザ素子の製造方法は、共振器を有するメサを備えた半導体レーザ素子の製造方法であって、基板の上に、順に第１導電型コンタクト層、第１導電型クラッド層、活性層、第２導電型クラッド層および第２導電型コンタクト層を積層する工程と、第１導電型クラッド層の一部を残すようにドライエッチングすることで、メサの両脇にある溝を形成し、共振器の端面を含む前記メサの側面を有するＬ字形状を形成するドライエッチング工程と、ドライエッチング工程で形成されたエッチング側面をマスクし、第１導電型コンタクト層に対して選択性を有するエッチャントを使用し、溝の底面およびＬ字形状の底面の上の第１導電型クラッド層をウェットエッチングすることで、第１導電型コンタクト層を露出させるウェットエッチング工程と、少なくとも１つの溝の底面において第１導電型コンタクト層に接続された、第１の電極を形成する工程と、第２導電型コンタクト層に活性層の上方で接続された第２の電極を形成する工程とを備える。 A method of manufacturing a semiconductor laser device according to the present invention is a method of manufacturing a semiconductor laser device including a mesa having a resonator, and a first conductivity type contact layer, a first conductivity type cladding layer, The step of laminating the active layer, the second conductivity type cladding layer and the second conductivity type contact layer, and the dry etching to leave a part of the first conductivity type cladding layer, thereby forming grooves on both sides of the mesa Then, a dry etching process for forming an L shape having a side surface of the mesa including an end face of the resonator, and an etching side surface formed in the dry etching process are masked to provide selectivity with respect to the first conductivity type contact layer. The first conductivity type contact layer is exposed by wet-etching the first conductivity type cladding layer on the bottom surface of the groove and the L-shaped bottom surface using an etchant having An etching process; a step of forming a first electrode connected to the first conductivity type contact layer at a bottom surface of at least one groove; and a second connection connected to the second conductivity type contact layer above the active layer. Forming an electrode.
　この発明に係る半導体レーザ素子は、寄生容量および素子容量が小さく、共振器端面の位置精度が高く、コンタクト層の膜厚を最小限とすることができる。 The semiconductor laser device according to the present invention has small parasitic capacitance and device capacitance, high position accuracy of the resonator end face, and can minimize the thickness of the contact layer.
　この発明に係る製造方法を用いると、寄生容量および素子容量が小さく、共振器端面の位置精度が高く、コンタクト層の膜厚を最小限に抑えた半導体レーザ素子が製造可能になる。またエピ成長装置のスループットが向上する。 When the manufacturing method according to the present invention is used, it is possible to manufacture a semiconductor laser device in which the parasitic capacitance and the element capacitance are small, the position accuracy of the cavity end face is high, and the thickness of the contact layer is minimized. In addition, the throughput of the epi growth apparatus is improved.
実施の形態１に係る半導体レーザ素子の断面図である。1 is a cross-sectional view of a semiconductor laser element according to a first embodiment. 実施の形態１に係る半導体レーザ素子の上面図である。2 is a top view of the semiconductor laser element according to the first embodiment. FIG. 実施の形態１に係る半導体レーザ素子の断面図である。1 is a cross-sectional view of a semiconductor laser element according to a first embodiment. 実施の形態１に係る半導体レーザ素子の製造方法を説明するための断面図である。6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment. FIG. 実施の形態１に係る半導体レーザ素子の製造方法を説明するための断面図である。6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment. FIG. 実施の形態１に係る半導体レーザ素子の製造方法を説明するための断面図である。6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment. FIG. 実施の形態１に係る半導体レーザ素子の製造方法を説明するための断面図である。6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment. FIG. 実施の形態１に係る半導体レーザ素子の製造方法を説明するための断面図である。6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment. FIG. 実施の形態１に係る半導体レーザ素子の製造方法を説明するための断面図である。6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment. FIG. 実施の形態１に係る半導体レーザ素子の製造方法を説明するための断面図である。6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment. FIG. 実施の形態１に係る半導体レーザ素子の製造方法を説明するための断面図である。6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment. FIG. 実施の形態１に係る半導体レーザ素子の製造方法を説明するための断面図である。6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment. FIG. 実施の形態１に係る半導体レーザ素子の製造方法を説明するための断面図である。6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment. FIG. 実施の形態１に係る半導体レーザ素子の製造方法を説明するための断面図である。6 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the first embodiment. FIG. 本発明の効果の検証実験に用いた半導体レーザ素子の断面図である。It is sectional drawing of the semiconductor laser element used for the verification experiment of the effect of this invention. 本発明の効果の検証実験の結果を示す図である。It is a figure which shows the result of the verification experiment of the effect of this invention. 実施の形態２に係る半導体レーザ素子の製造方法を説明するための断面図である。10 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser element according to the second embodiment. FIG. 実施の形態２に係る半導体レーザ素子の断面図である。FIG. 6 is a cross-sectional view of a semiconductor laser element according to a second embodiment. 実施の形態２に係る半導体レーザ素子の断面図である。FIG. 6 is a cross-sectional view of a semiconductor laser element according to a second embodiment.
実施の形態１．
　実施の形態１に係る半導体レーザ素子とその製造方法について説明する。 Embodiment 1 FIG.
The semiconductor laser device and its manufacturing method according to the first embodiment will be described.
（構造）
　実施の形態１に係る半導体レーザ素子の構造について説明する。図１は実施の形態１に係る半導体レーザ素子の断面図である。図２は上面図である。図２のＡ－Ａ、Ｂ－Ｂはそれぞれ図１（ａ）、（ｂ）の断面を示す切断線である。図３は図１と同様の図であるが、説明のためにハッチングを消し、一部の線を太くしている。 (Construction)
The structure of the semiconductor laser device according to the first embodiment will be described. FIG. 1 is a cross-sectional view of the semiconductor laser device according to the first embodiment. FIG. 2 is a top view. AA and BB in FIG. 2 are cut lines showing the cross sections of FIGS. 1A and 1B, respectively. FIG. 3 is a view similar to FIG. 1, but for the sake of explanation, hatching is removed and some lines are thickened.
　基板１０の上にｎ型コンタクト層１２が形成されている。ｎ型コンタクト層１２の上にｎ型クラッド層１４、活性層１８、ｐ型クラッド層２０が形成されている。ｎ型クラッド層１４の一部、活性層１８、ｐ型クラッド層２０の一部でリッジ２２が構成される。リッジ２２はレーザ導波路として機能する。リッジ２２の両側面にブロック層１６が埋め込まれている。ｐ型クラッド層２０の上にｐ型コンタクト層２４が形成されている。ｎ型コンタクト層１２からｐ型コンタクト層２４にかけての複数の層をまとめて半導体層３６と称する。なおｎ型クラッド層１４またはｐ型クラッド層２０内に屈折率が周期的に変化する回折格子構造が形成されていてもいい。 An n-type contact layer 12 is formed on the substrate 10. An n-type cladding layer 14, an active layer 18, and a p-type cladding layer 20 are formed on the n-type contact layer 12. A ridge 22 is constituted by a part of the n-type cladding layer 14, the active layer 18, and a part of the p-type cladding layer 20. The ridge 22 functions as a laser waveguide. Block layers 16 are embedded on both side surfaces of the ridge 22. A p-type contact layer 24 is formed on the p-type cladding layer 20. A plurality of layers from the n-type contact layer 12 to the p-type contact layer 24 are collectively referred to as a semiconductor layer 36. Note that a diffraction grating structure in which the refractive index periodically changes may be formed in the n-type cladding layer 14 or the p-type cladding layer 20.
　上記の各部材の材料を記載する。基板１０は半絶縁性のＩｎＰでできている。ｎ型コンタクト層１２は厚さが１．０μｍのｎ型ＩｎＧａＡｓでできている。ｎ型クラッド層１４は厚さが３．０μｍのｎ型ＩｎＰでできている。活性層１８は厚さが０．２μｍでｉ型ＡｌＧａＩｎＡｓからなるＭＱＷ（Multiple Quantum Well）構造を含む。ｐ型クラッド層２０は厚さが２．０μｍのｐ型ＩｎＰでできている。ブロック層１６はＦｅ－ＩｎＰ（ＦｅがドープされたＩｎＰ）、ｎ型ＩｎＰ、ｐ型ＩｎＰが順に積層されてできている。ｐ型コンタクト層２４は厚さが０．３μｍのｐ型ＩｎＧａＡｓでできている。なおｎ型コンタクト層１２、ｐ型コンタクト層２４がそれぞれｎ型ＩｎＧａＡｓＰ、ｐ型ＩｎＧａＡｓＰでできていてもいい。 Include the material for each of the above parts. The substrate 10 is made of semi-insulating InP. The n-type contact layer 12 is made of n-type InGaAs having a thickness of 1.0 μm. The n-type cladding layer 14 is made of n-type InP having a thickness of 3.0 μm. The active layer 18 has a thickness of 0.2 μm and includes an MQW (Multiple Quantum 型 Well) structure made of i-type AlGaInAs. The p-type cladding layer 20 is made of p-type InP having a thickness of 2.0 μm. The block layer 16 is formed by sequentially stacking Fe—InP (Fe-doped InP), n-type InP, and p-type InP. The p-type contact layer 24 is made of p-type InGaAs having a thickness of 0.3 μm. The n-type contact layer 12 and the p-type contact layer 24 may be made of n-type InGaAsP and p-type InGaAsP, respectively.
　図１（ａ）、３（ａ）に示すようにリッジ２２を含む領域の両脇に溝３２が形成されている。これらの溝３２に挟まれたｎ型クラッド層１４、活性層１８、ｐ型クラッド層２０、ｐ型コンタクト層２４、ブロック層１６でメサ３４が構成されている。メサ３４中のｐ型クラッド層２０からｎ型クラッド層１４にかけて埋込み型半導体レーザの電流狭窄構造が構成されている。 1 (a) and 3 (a), grooves 32 are formed on both sides of a region including the ridge 22. A mesa 34 is constituted by the n-type cladding layer 14, the active layer 18, the p-type cladding layer 20, the p-type contact layer 24, and the block layer 16 sandwiched between the grooves 32. An embedded semiconductor laser current confinement structure is formed from the p-type cladding layer 20 to the n-type cladding layer 14 in the mesa 34.
　図３（ａ）に示すように溝３２の底面４６はｎ型コンタクト層１２の上面で構成されている。溝３２の側面は、底面４６近傍の傾斜面３８と、その上の側面４２に分けられる。傾斜面３８は基板１０に鉛直な方向に対して逆メサ方向の傾斜を持つ。逆メサ方向とは基板に垂直な方向の上方から下方にかけてｎ型クラッド層１４が食い込む方向のことである。一方、側面４２は基板１０に対してほぼ垂直である。 As shown in FIG. 3A, the bottom surface 46 of the groove 32 is constituted by the upper surface of the n-type contact layer 12. The side surface of the groove 32 is divided into an inclined surface 38 near the bottom surface 46 and a side surface 42 thereabove. The inclined surface 38 has an inclination in a reverse mesa direction with respect to a direction perpendicular to the substrate 10. The reverse mesa direction is a direction in which the n-type cladding layer 14 bites from the upper side to the lower side in the direction perpendicular to the substrate. On the other hand, the side surface 42 is substantially perpendicular to the substrate 10.
　なお底面４６を構成するｎ型コンタクト層１２の上面は、各種の製造工程を経て、凹凸などが存在してもいい。 Note that the top surface of the n-type contact layer 12 constituting the bottom surface 46 may have unevenness after various manufacturing processes.
　また図３（ａ）では底面４６の上にはｎ型クラッド層１４が存在しないが、一部に存在してもいい。ただしｎ型クラッド層１４は、後述のｎ型電極２８とｎ型コンタクト層１２との電気的接続を妨げないように、傾斜面３８付近にのみ存在が許される。 In FIG. 3A, the n-type cladding layer 14 does not exist on the bottom surface 46, but may exist in a part. However, the n-type cladding layer 14 is allowed to exist only in the vicinity of the inclined surface 38 so as not to prevent electrical connection between an n-type electrode 28 and an n-type contact layer 12 described later.
　図１（ｂ）、３（ｂ）に示すように共振器端面付近においてメサ３４が削られている。この削られた領域においてＬ字形状５０が、共振器端面を含むメサ３４の側面とｎ型コンタクト層１２の上面で形成されている。 As shown in FIGS. 1B and 3B, the mesa 34 is cut in the vicinity of the resonator end face. In this shaved region, an L-shape 50 is formed on the side surface of the mesa 34 including the end face of the resonator and the upper surface of the n-type contact layer 12.
　図３（ｂ）に示すようにＬ字形状５０の底面４８はｎ型コンタクト層１２の上面で構成されている。Ｌ字形状５０の側面は、底面４８近傍の傾斜面４０と、その上の側面４４に分けられる。傾斜面４０は基板１０に鉛直な方向に対して順メサ方向の傾斜を持つ。順メサ方向とは基板に垂直な方向の上方から下方にかけてｎ型クラッド層１４が広がる方向のことである。一方、側面４４は基板１０に対してほぼ垂直である。側面４４はその下端がｎ型コンタクト層１２の上面付近まで延びており、共振器の端面として機能する。なお図では説明のために傾斜面４０を長くしたが、実際は傾斜面４０が短く、側面４４の下端がｎ型コンタクト層１２の上面付近まで延びているのが望ましい。 As shown in FIG. 3B, the bottom surface 48 of the L-shape 50 is formed by the top surface of the n-type contact layer 12. The side surface of the L-shaped 50 is divided into an inclined surface 40 in the vicinity of the bottom surface 48 and a side surface 44 thereon. The inclined surface 40 has a forward mesa direction inclination with respect to a direction perpendicular to the substrate 10. The forward mesa direction is a direction in which the n-type cladding layer 14 spreads from above to below in a direction perpendicular to the substrate. On the other hand, the side surface 44 is substantially perpendicular to the substrate 10. The side surface 44 has a lower end extending to the vicinity of the upper surface of the n-type contact layer 12 and functions as an end surface of the resonator. In the drawing, the inclined surface 40 is made longer for the sake of explanation. However, it is actually preferable that the inclined surface 40 is short and the lower end of the side surface 44 extends to the vicinity of the upper surface of the n-type contact layer 12.
　なお底面４８を構成するｎ型コンタクト層１２の上面は、各種の製造工程を経て、凹凸などが存在してもいい。 Note that the upper surface of the n-type contact layer 12 constituting the bottom surface 48 may have unevenness after various manufacturing processes.
　また図３（ａ）では底面４８の上にはｎ型クラッド層１４が存在しないが、存在してもいい。 In FIG. 3A, the n-type cladding layer 14 does not exist on the bottom surface 48, but may exist.
　図１、３に示すように溝３２の底面から側面を通り、ｐ型コンタクト層２４の上にかけて絶縁膜２６が形成されている。この絶縁膜２６はＬ字形状５０の底面から側面を通り、ｐ型コンタクト層２４の上にかけても形成されている。絶縁膜２６には溝３２の底面４６とメサ３４の上部に開口がある。 As shown in FIGS. 1 and 3, an insulating film 26 is formed from the bottom surface of the groove 32 through the side surface and over the p-type contact layer 24. The insulating film 26 is also formed over the p-type contact layer 24 from the bottom surface to the side surface of the L-shape 50. The insulating film 26 has openings on the bottom surface 46 of the groove 32 and the top of the mesa 34.
　図１（ａ）、３（ａ）に示した左右の溝３２のうち左側の溝３２の底面４６にある絶縁膜２６の開口を通じてｎ型コンタクト層１２と接続されたｎ側電極２８が溝３２の側面を通り、絶縁膜２６の上に引き出されるように形成されている。またメサ３４の上の絶縁膜２６の開口を通じてｐ型コンタクト層２４と接続されたｐ側電極３０が形成されている。なおここでいう接続とは電気的な接続のことである。このように実施の形態１に係る半導体レーザ素子はｎ側電極２８とｐ側電極３０がどちらも表面側に形成された表面実装型の半導体レーザ素子である。 The n-side electrode 28 connected to the n-type contact layer 12 through the opening of the insulating film 26 on the bottom surface 46 of the left-side groove 32 of the left and right grooves 32 shown in FIGS. Are formed so as to be drawn on the insulating film 26. A p-side electrode 30 connected to the p-type contact layer 24 through the opening of the insulating film 26 on the mesa 34 is formed. In addition, the connection here is an electrical connection. Thus, the semiconductor laser device according to the first embodiment is a surface-mounting type semiconductor laser device in which both the n-side electrode 28 and the p-side electrode 30 are formed on the surface side.
（製造方法）
　実施の形態１に係る半導体レーザ素子の製造方法を説明する。以下、図４～１４を参照しながら説明する。これらの図の（ａ）、（ｂ）はそれぞれ図２のＡ－Ａ、Ｂ－Ｂにおける断面図である。 (Production method)
A method for manufacturing the semiconductor laser element according to the first embodiment will be described. This will be described below with reference to FIGS. In these drawings, (a) and (b) are cross-sectional views taken along lines AA and BB in FIG. 2, respectively.
　まず、基板１０として（１００）ＩｎＰ基板を用意し、図４に示すように基板１０の上にｎ型コンタクト層１２、ｎ型クラッド層１４、活性層１８、ｐ型クラッド層２０をＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition）法によって積層する。 First, a (100) InP substrate is prepared as the substrate 10. As shown in FIG. 4, an n-type contact layer 12, an n-type cladding layer 14, an active layer 18, and a p-type cladding layer 20 are formed on the substrate 10 by MOCVD (Metal Laminate by Organic (Chemical Vapor Deposition) method.
　次いで、図５に示すように＜０１１＞方向に沿って伸びるリッジ２２を形成する。そのためにはまずリッジパターンを有するマスク５２を形成する。マスク５２の形成は、例えばプラズマＣＶＤ（Chemical Vapor Deposition）法により膜厚０．４μｍのＳｉＯ（組成は任意）膜を成膜し、その後フォトリソグラフィを用いてレジストパターンをＳｉＯ膜上に形成し、ＣＦ4／Ｏ２混合ガスを用いたＲＩＥ（Reactive Ion Etching）法によってレジストパターンをＳｉＯ膜に転写したあと、Ｏ２プラズマによりレジストを除去すれば可能である。続いて例えばＳｉＣｌ4／Ａｒ混合ガスを用いたＲＩＥ法により、マスク５２をエッチングマスクとしてｐ型クラッド層２０、活性層１８、そしてｎ型クラッド層１４の一部をエッチングしてリッジ２２を形成する。 Next, as shown in FIG. 5, a ridge 22 extending along the <011> direction is formed. For this purpose, first, a mask 52 having a ridge pattern is formed. The mask 52 is formed by, for example, forming a 0.4 μm-thick SiO (composition is arbitrary) film by plasma CVD (Chemical Vapor Deposition), and then forming a resist pattern on the SiO film using photolithography. This is possible by transferring the resist pattern to the SiO film by an RIE (Reactive Ion Etching) method using a CF 4 / O 2 mixed gas, and then removing the resist with O 2 plasma. Subsequently, the ridge 22 is formed by etching a part of the p-type cladding layer 20, the active layer 18, and the n-type cladding layer 14 by, for example, RIE using an SiCl 4 / Ar mixed gas, using the mask 52 as an etching mask. .
　次いで、図６に示すようにマスク５２を選択成長マスクとして、ＭＯＣＶＤ法によりリッジ２２の両側面をブロック層１６で埋め込む。 Next, as shown in FIG. 6, using the mask 52 as a selective growth mask, both side surfaces of the ridge 22 are buried with the block layer 16 by MOCVD.
　次いで、図７に示すようにマスク５２をフッ酸で除去したあと、全面にｐ型クラッド層２０、ｐ型コンタクト層２４をＭＯＣＶＤ法により積層する。 Next, as shown in FIG. 7, after removing the mask 52 with hydrofluoric acid, the p-type cladding layer 20 and the p-type contact layer 24 are laminated on the entire surface by MOCVD.
　次いで、図８に示すようにマスク５４を形成する。マスク５４の形成方法は上述のマスク５２と同様である。マスク５４には開口５６と開口５８が形成されている。開口５６のエッジ部はリッジ２２に対して平行（すなわち＜０１１＞方向に平行）であり、開口５８のエッジはリッジ２２に対して垂直（すなわち＜０１－１＞方向に平行）になるように形成する。 Next, a mask 54 is formed as shown in FIG. The method for forming the mask 54 is the same as that for the mask 52 described above. An opening 56 and an opening 58 are formed in the mask 54. The edge of the opening 56 is parallel to the ridge 22 (ie, parallel to the <011> direction), and the edge of the opening 58 is perpendicular to the ridge 22 (ie, parallel to the <01-1> direction). Form.
　次いで、図９に示すようにマスク５４を用いてドライエッチングし、溝３２ａとＬ字形状５０ａを形成する。Ｌ字形状５０ａは、ｐ型コンタクト層２４、ｐ型クラッド層２０、活性層１８、ｎ型クラッド層１４の側面と、ｎ型クラッド層１４の上面で構成されている。なお図９（ｂ）では説明のためにＬ字形状５０ａを太い線で表現している。ドライエッチングは溝３２ａとＬ字形状５０ａの側面が基板１０に対してほぼ垂直となるように行う。このようにして形成された側面をエッチング側面と称する。エッチング側面の、基板１０に垂直な面に対する傾斜角は５°以内、さらには１°以内とするのが良い。ドライエッチング条件としては、エッチングガスにはハロゲン元素を含むガス、例えばＳｉＣｌ4／Ａｒ混合ガスを用い、低圧かつ高バイアス下でＩＣＰ（Inductive Coupled Plasma）－ＲＩＥ法により行うのがよい。ドライエッチングの停止は、Ｌ字形状５０ａの底面の最深部がｎ型コンタクト層１２に到達する前に行う。なおドライエッチングをＬ字形状５０ａの底面の最深部がｎ型コンタクト層１２に到達するまで実施した場合は、膜厚減少分だけｎ型コンタクト層１２の電気抵抗が高くなるが、これが許容できるのであれば、そのようにしてもかまわない。またこのドライエッチングで共振器の前端面だけを形成してもいいし、後端面だけを形成してもいいし、両方の端面を形成してもいい。 Next, as shown in FIG. 9, dry etching is performed using a mask 54 to form a groove 32a and an L-shape 50a. The L-shape 50 a is composed of the side surfaces of the p-type contact layer 24, the p-type cladding layer 20, the active layer 18, the n-type cladding layer 14, and the upper surface of the n-type cladding layer 14. In FIG. 9B, the L shape 50a is represented by a thick line for the sake of explanation. Dry etching is performed so that the side surfaces of the groove 32a and the L-shaped 50a are substantially perpendicular to the substrate 10. The side surface thus formed is referred to as an etching side surface. The inclination angle of the etching side surface with respect to the surface perpendicular to the substrate 10 is preferably within 5 °, more preferably within 1 °. As dry etching conditions, a gas containing a halogen element, for example, a SiCl 4 / Ar mixed gas, is preferably used as an etching gas by an ICP (Inductive Coupled Plasma) -RIE method under a low pressure and a high bias. The dry etching is stopped before the deepest portion of the bottom surface of the L-shaped 50a reaches the n-type contact layer 12. Note that when dry etching is performed until the deepest portion of the bottom surface of the L-shaped 50a reaches the n-type contact layer 12, the electrical resistance of the n-type contact layer 12 increases by the thickness reduction, but this is acceptable. If so, you can do that. Further, only the front end face of the resonator may be formed by this dry etching, only the rear end face may be formed, or both end faces may be formed.
　ドライエッチングを終えると、溝３２ａとＬ字形状５０ａの側面と底面が交わる辺りは図９に示すような裾引き形状を持つ。図９（ｂ）にはＬ字形状５０ａの底面付近を拡大した図を示している。この裾引きは、イオンのシャドーイング効果によって側面近傍でのエッチングレートが低下するためである。 When the dry etching is finished, the area where the side surface and the bottom surface of the groove 32a and the L-shape 50a intersect has a bottom shape as shown in FIG. FIG. 9B shows an enlarged view of the vicinity of the bottom surface of the L-shape 50a. This tailing is because the etching rate in the vicinity of the side surface decreases due to the shadowing effect of ions.
　次いで、図１０に示すように溝３２ａおよびＬ字形状５０ａの側面を含む全面にマスク６０を成膜する。マスク６０には、プラズマＣＶＤで成膜した厚さ０．２μｍのＳｉＯを用いることができる。 Next, as shown in FIG. 10, a mask 60 is formed on the entire surface including the grooves 32a and the side surfaces of the L-shape 50a. As the mask 60, SiO having a thickness of 0.2 μm formed by plasma CVD can be used.
　次いで、図１１に示すようにマスク６０を全面エッチバックし、溝３２ａおよびＬ字形状５０ａの側面以外のマスク６０を除去する。このときエッチバック時間を適切に調整することでｐ型コンタクト層２４上のマスク５４を残せる。エッチバックは、溝３２ａおよびＬ字形状５０ａの側面に形成されたＳｉＯの膜厚がサイドエッチングにより減少するのを防ぐため低圧条件で行うのがよく、例えばＣＦ４／Ｏ２の混合ガスを用いたＩＣＰ－ＲＩＥ法を用いることができる。 Next, as shown in FIG. 11, the entire surface of the mask 60 is etched back, and the mask 60 other than the grooves 32a and the side surfaces of the L-shape 50a is removed. At this time, the mask 54 on the p-type contact layer 24 can be left by appropriately adjusting the etch back time. Etchback is preferably performed under low pressure conditions in order to prevent the film thickness of SiO formed on the side surfaces of the groove 32a and the L-shaped 50a from being reduced by side etching. For example, a mixed gas of CF 4 / O 2 is used. The ICP-RIE method used can be used.
　次いで、図１２に示すように溝３２ａとＬ字形状５０ａの底面をウェットエッチングする。具体的にはｎ型コンタクト層の材料であるＩｎＧａＡｓに対して選択性を有するエッチャント、例えば塩酸／リン酸の混合液に浸漬し、溝３２ａとＬ字形状５０ａの底面にあるｎ型クラッド層１４をエッチングする。このようにしてメサ３４、溝３２、Ｌ字形状５０が形成される。図３にも示したように溝３２の底面４６近傍の傾斜面３８は逆メサ方向の垂直に近い傾斜を持ち、底面４６はｎ型コンタクト層１２が露出する。またＬ字形状の底面４８近傍の傾斜面４０は順メサ方向の傾斜を持ち、底面４８はｎ型コンタクト層１２が露出する。また溝３２ａとＬ字形状５０ａの側面に形成されたマスク６０によってエッチング側面がウェットエッチングから保護されるので、エッチング側面の垂直性は維持される。また溝３２とＬ字形状５０は同時に形成するため、それぞれの底面４６と底面４８は高さが等しくなる。なおエッチャントとして臭化水素を含んだものを使用してもいい。ところで、上記マスク６０の形成において、マスク５４を残すことは必須ではない。この実施例ではｐ型コンタクト層２４をＩｎＧａＡｓとしたので、仮にマスク５４が消失するまでエッチバックを行ったとしても、ｐ型コンタクト層２４がウェットエッチングに対するエッチングマスクとなり半導体表面がエッチングされるのを防ぐことができる。 Next, as shown in FIG. 12, the bottom surfaces of the grooves 32a and the L-shape 50a are wet-etched. Specifically, the n-type cladding layer 14 is immersed in an etchant having selectivity with respect to InGaAs, which is the material of the n-type contact layer, for example, a hydrochloric acid / phosphoric acid mixed solution, and is formed on the bottom surface of the groove 32a and the L-shaped 50a. Etch. In this way, the mesa 34, the groove 32, and the L shape 50 are formed. As shown in FIG. 3, the inclined surface 38 in the vicinity of the bottom surface 46 of the groove 32 has an inclination nearly perpendicular to the reverse mesa direction, and the n-type contact layer 12 is exposed on the bottom surface 46. Further, the inclined surface 40 in the vicinity of the L-shaped bottom surface 48 has a forward mesa direction inclination, and the n-type contact layer 12 is exposed at the bottom surface 48. Further, since the etching side surface is protected from wet etching by the mask 60 formed on the side surface of the groove 32a and the L-shaped 50a, the perpendicularity of the etching side surface is maintained. Moreover, since the groove | channel 32 and the L-shape 50 are formed simultaneously, each bottom face 46 and the bottom face 48 become equal height. An etchant containing hydrogen bromide may be used. By the way, it is not essential to leave the mask 54 in the formation of the mask 60. In this embodiment, since the p-type contact layer 24 is made of InGaAs, even if etching back is performed until the mask 54 disappears, the p-type contact layer 24 becomes an etching mask for wet etching, and the semiconductor surface is etched. Can be prevented.
　また、図１２に示すように、このウェットエッチング工程では底面４６および底面４８の上のｎ型クラッド層１４が完全に削られるとしたが、一部が残っていてもかまわない。 Further, as shown in FIG. 12, in this wet etching process, the n-type cladding layer 14 on the bottom surface 46 and the bottom surface 48 is completely scraped, but a part of the n-type cladding layer 14 may remain.
　逆メサ方向や順メサ方向の傾斜ができるのは、ウェットエッチングの結晶方位依存性による。この実施の形態ではメサ３４を＜０１１＞方向に沿って形成し、エッチャントに塩酸／リン酸の混合液を用いたので、メサ３４の傾斜面３８は垂直に近い逆メサとなり、Ｌ字形状５０の傾斜面４０は順メサとなる。メサ３４の方向を９０°回転しても良く（すなわち＜０１－１＞方向に沿って形成しても良く）、この場合はＩｎＰ結晶の対称性より図１２とはメサの順／逆方向が逆になる。またエッチャントに臭化水素を含む液、例えば臭化水素とＨ２Ｏの混合液を用いることも可能で、順／逆メサの角度はエッチング条件によって変わる。このように、この発明はメサの方向および角度を制限するものではなく、メサ方向、エッチャントによる変形が可能である。 The inclination in the reverse mesa direction and the forward mesa direction is due to the crystal orientation dependency of wet etching. In this embodiment, since the mesa 34 is formed along the <011> direction and a mixed solution of hydrochloric acid / phosphoric acid is used as the etchant, the inclined surface 38 of the mesa 34 becomes an inverted mesa that is nearly vertical, and an L-shaped 50 The inclined surface 40 is a forward mesa. The direction of the mesa 34 may be rotated by 90 ° (that is, it may be formed along the <01-1> direction). In this case, the forward / reverse direction of the mesa is different from that of FIG. Vice versa. It is also possible to use a liquid containing hydrogen bromide in the etchant, for example, a mixed liquid of hydrogen bromide and H 2 O, and the forward / reverse mesa angle varies depending on the etching conditions. As described above, the present invention does not limit the direction and angle of the mesa, and can be modified by the mesa direction and the etchant.
　次いで、図１４に示すように絶縁膜２６を形成する。具体的にはまずＢＨＦ（バッファードフッ酸）に浸漬し、マスク５４とマスク６０を除去したあと、例えばプラズマＣＶＤ法を用いて厚さが０．４μｍのＳｉＯ（組成は任意）膜を全面に形成する。さらにフォトリソグラフィとＲＩＥ法を用いて溝３２の底面４６およびメサ３４の上にそれぞれ開口６６、開口６８を形成する。開口６６はｎ側電極２８とのコンタクト領域、開口６８はｐ側電極３０とのコンタクト領域となる。また絶縁膜２６は電流注入領域を画定するとともに、半導体表面を汚染から保護する保護膜として機能し、さらには共振器端面における反射率制御のためのコーティング膜の一部として機能する。絶縁膜２６にはＳｉＯのほかに、ＳｉＮ、ＴｉＯ、ＴａＯ、ＡｌＯ（これらの組成は任意）やこれらの積層膜でもよく、成膜方法はスパッタ法やＡＬＤ（Atomic Layer Deposition）法であってもよい。 Next, an insulating film 26 is formed as shown in FIG. Specifically, after first immersing in BHF (buffered hydrofluoric acid) and removing the mask 54 and the mask 60, for example, a plasma CVD method is used to form a 0.4 μm-thick SiO (composition is arbitrary) film over the entire surface. Form. Further, an opening 66 and an opening 68 are formed on the bottom surface 46 of the groove 32 and the mesa 34 using photolithography and RIE, respectively. The opening 66 is a contact region with the n-side electrode 28, and the opening 68 is a contact region with the p-side electrode 30. The insulating film 26 defines a current injection region, functions as a protective film for protecting the semiconductor surface from contamination, and further functions as a part of the coating film for controlling the reflectance at the resonator end face. In addition to SiO, the insulating film 26 may be SiN, TiO, TaO, AlO (these compositions are arbitrary) or a laminated film thereof. The film formation method may be a sputtering method or an ALD (Atomic Layer Deposition) method. Good.
　次いで、全面にスパッタ法によりＴｉ／Ａｕの積層膜を形成したあと、フォトリソグラフィおよびウェットエッチングによってｎ側電極２８およびｐ側電極３０を形成する。このあと基板１０をバー状態にへき開し、Ｌ字形状５０の側面にコート膜を形成することで共振器端面における反射率調整を行っても良い。これにより半導体レーザ素子の形成を完了する。 Next, after a Ti / Au laminated film is formed on the entire surface by sputtering, the n-side electrode 28 and the p-side electrode 30 are formed by photolithography and wet etching. Thereafter, the substrate 10 may be cleaved into a bar state, and a coat film may be formed on the side surface of the L-shaped 50 to adjust the reflectance at the resonator end face. Thereby, the formation of the semiconductor laser element is completed.
　なお、上記はＦＰ（ファブリペロ）レーザへの適用例であるが、これをＤＦＢレーザに用いることもできる。この場合、ｎ型クラッド層１４またはｐ型クラッド層２０内に、例えば厚さ４０ｎｍで共振器方向に２００ｎｍピッチの周期構造を持つ、ＩｎＧａＡｓＰからなる回折格子構造を形成すればいい。具体的には、ＩｎＰクラッド層形成の途中で厚さ４０ｎｍのＩｎＧａＡｓＰ層を形成し、プラズマＣＶＤ法により厚さ２５ｎｍのＳｉＯ膜を形成し、電子ビーム描画法およびＲＩＥ法を用いて回折格子パターンをＳｉＯ膜に転写し、ＣＨ４／Ｈ２の混合ガスを用いたＲＩＥ法によってＩｎＧａＡｓＰ層をエッチングし、再度クラッド層を成長させることでＩｎＧａＡｓＰからなる回折格子を埋め込めばいい。 Although the above is an example applied to an FP (Fabry-Perot) laser, it can also be used for a DFB laser. In this case, a diffraction grating structure made of InGaAsP having a periodic structure of, for example, a thickness of 40 nm and a pitch of 200 nm in the cavity direction may be formed in the n-type cladding layer 14 or the p-type cladding layer 20. Specifically, an InGaAsP layer having a thickness of 40 nm is formed in the middle of forming the InP clad layer, an SiO film having a thickness of 25 nm is formed by plasma CVD, and a diffraction grating pattern is formed using an electron beam lithography method and an RIE method. Transfer to the SiO film, etch the InGaAsP layer by the RIE method using a mixed gas of CH 4 / H 2 , and grow the cladding layer again to embed a diffraction grating made of InGaAsP.
（効果）
　実施の形態１に係る半導体レーザ素子およびその製造方法が有する効果について述べる。 (effect)
The effects of the semiconductor laser device and the manufacturing method thereof according to the first embodiment will be described.
　この半導体レーザ素子は表面実装型であるため、ワイヤ配線に起因する寄生容量および電極間の容量が小さい。表面実装型でない場合、２つの電極がそれぞれ素子の上面と下面にあるため、電極間の容量が大きくなる。これに対し、表面実装型では２つの電極がどちらも素子表面側にあるため、電極間の容量が小さくなる。 Since this semiconductor laser element is a surface mount type, the parasitic capacitance caused by the wire wiring and the capacitance between the electrodes are small. In the case of not being a surface mount type, since the two electrodes are respectively on the upper surface and the lower surface of the element, the capacitance between the electrodes is increased. In contrast, in the surface mount type, since the two electrodes are both on the element surface side, the capacitance between the electrodes is reduced.
　また、メサの両脇に溝を設けているため、素子容量をさらに低減することができる。 Also, since the grooves are provided on both sides of the mesa, the element capacity can be further reduced.
　また、共振器端面をドライエッチングで形成しているため、その位置精度が高い。このようにして形成された共振器端面位置の重ね合わせ精度はフォトリソグラフィの重ね合わせ精度であるサブミクロンレベルであり、へき開を用いた場合の数ミクロンレベルのばらつきに対して大きく向上できる。特に多波長集積半導体レーザ素子では波長の異なるＤＦＢレーザを複数集積するが、これらＤＦＢの共振器端面における回折格子の位相を制御することがＳＭＳＲ歩留り向上のために必要となる。このため、意図した位置で回折格子の位相が揃うようにパターン形成を行うことに加え、その位置に精度よく共振器端面を形成しなければならない。従って、この発明は多波長集積半導体レーザ素子にも適している。 Also, since the cavity end face is formed by dry etching, its positional accuracy is high. The overlay accuracy of the resonator end face position thus formed is at a submicron level, which is the overlay accuracy of photolithography, and can be greatly improved with respect to variations of several microns when cleavage is used. In particular, in a multiwavelength integrated semiconductor laser element, a plurality of DFB lasers having different wavelengths are integrated, and it is necessary to control the phase of the diffraction grating at the cavity end face of these DFBs in order to improve the SMSR yield. For this reason, in addition to pattern formation so that the phase of the diffraction grating is aligned at the intended position, the resonator end face must be accurately formed at that position. Therefore, the present invention is also suitable for a multiwavelength integrated semiconductor laser device.
　また、共振器端面を含むほぼ垂直なメサ側面の下端が、活性層から離れたｎ型コンタクト層の上面付近まで延びているため、ミラー損失が小さい。もしこの下端が活性層に近づいた場合、その下の傾斜面に起因するミラー損失が大きくなるが、この半導体レーザ素子ではそのような問題を抑えられる。 In addition, since the lower end of the substantially vertical mesa side surface including the resonator end surface extends to the vicinity of the upper surface of the n-type contact layer away from the active layer, the mirror loss is small. If this lower end approaches the active layer, the mirror loss due to the inclined surface below it increases, but this problem can be suppressed in this semiconductor laser device.
　ここで、傾斜面の上端が活性層から遠いほどレーザ特性が優れることを実験結果から示す。図１５（ａ）、（ｂ）はどちらも実験に用いたＦＰレーザの断面図である。図１５（ａ）中のｄａおよび図１５（ｂ）中のｄｂは、活性層の下端から傾斜面の上端までの距離を表しており、ｄａ＞ｄｂになっている。図１６はＦＰレーザの光出力（ＰＯ）に対する電流（ＩＦ）依存性（Ｐ－Ｉ特性）を示す測定結果であり、図中の（ａ）、（ｂ）がそれぞれ図１５（ａ）、（ｂ）に対応する。図１６に示すように、図１５（ａ）のＦＰレーザのほうがＰ－Ｉ特性がいい。これはｄａ＞ｄｂという条件によるものであり、傾斜面が活性層から離れるほどミラー損失が小さいことを示している。 Here, it is shown from experimental results that the laser characteristics are more excellent as the upper end of the inclined surface is farther from the active layer. FIGS. 15A and 15B are cross-sectional views of the FP laser used in the experiment. D b of FIG. 15 (a) d a and 15 in (b) in represents the distance to the upper end of the inclined surface from the lower end of the active layer, has a d a> d b. FIG. 16 shows measurement results showing current (I F ) dependence (PI characteristics) on the optical output (P O ) of the FP laser, and (a) and (b) in FIG. , (B). As shown in FIG. 16, the FP laser of FIG. 15A has better PI characteristics. This is due to the condition of d a > d b , and indicates that the mirror loss is smaller as the inclined surface is farther from the active layer.
　傾斜面の上端を活性層から離すには、ドライエッチングをｎ型クラッド層に到達する直前までできるだけ長い時間行うか、ｎ型クラッド層を厚くすればいい。 In order to separate the upper end of the inclined surface from the active layer, dry etching may be performed as long as possible until just before reaching the n-type cladding layer, or the n-type cladding layer may be thickened.
　実施の形態１に係る製造方法では共振器端面と溝の形成を同時に行うため、少ない工程で半導体レーザ素子を形成できる。 In the manufacturing method according to the first embodiment, the cavity facet and the groove are formed at the same time, so that the semiconductor laser element can be formed with fewer steps.
　また、ウェットエッチングの選択性により基板側コンタクト層の膜厚を減少させることなく露出できるため、コンタクト層厚減少による素子抵抗の増大を防げる。したがって所望の素子抵抗が得られる最小限の膜厚をあらかじめ確保しておけばよく、エピ成長装置のスループットが向上する。 Also, since the wet etching selectivity allows exposure without reducing the film thickness of the substrate-side contact layer, it is possible to prevent an increase in element resistance due to a decrease in the contact layer thickness. Therefore, it is sufficient to secure a minimum film thickness for obtaining a desired element resistance in advance, and the throughput of the epi growth apparatus is improved.
実施の形態２．
　実施の形態２に係る半導体レーザ素子の製造方法について説明する。ここでは実施の形態１の製造方法と同様の工程については詳述せず、主に実施の形態１との違いを説明する。得られる効果についても主に実施の形態１との違いを記述する。 Embodiment 2. FIG.
A method for manufacturing the semiconductor laser element according to the second embodiment will be described. Here, steps similar to those in the manufacturing method of the first embodiment will not be described in detail, and differences from the first embodiment will be mainly described. Differences from the first embodiment will be mainly described regarding the obtained effects.
（製造方法）
　実施の形態２の製造方法は、ドライエッチング直前まで、すなわち図８の状態までは実施の形態１と同じである。以下では、実施の形態１との違いがあるドライエッチング工程について図１７～１８を参照しながら説明する。これらの図の（ａ）、（ｂ）はそれぞれ図２のＡ－Ａ、Ｂ－Ｂにおける断面図である。 (Production method)
The manufacturing method of the second embodiment is the same as that of the first embodiment until just before dry etching, that is, until the state shown in FIG. In the following, a dry etching process that is different from the first embodiment will be described with reference to FIGS. In these drawings, (a) and (b) are cross-sectional views taken along lines AA and BB in FIG. 2, respectively.
　図８のあと、ドライエッチングで溝とＬ字形状を形成する際、ドライエッチングでｎ型コンタクト層が露出したことをプラズマ発光強度の変化で検知し、その検知後にドライエッチングを停止させる。ｎ型コンタクト層が露出すると、ｎ型コンタクト層あるいはｎ型クラッド層の構成元素のプラズマ発光強度が変化するため、これらの元素のいずれかをモニタすればいい。ここではｎ型コンタクト層がＩｎＧａＡｓ、ｎ型クラッド層がＩｎＰであるため、Ｉｎ、Ｇａ、Ａｓ、Ｐのいずれかのプラズマ発光強度をモニタすればいい。なお、ｎ型クラッド層より上にもこれらの元素を含む層が積層されているため、これらの層のエッチング途中にプラズマ発光強度が変化してしまう。この変化を誤検出しないためには、ドライエッチングの速度を事前に把握しておき、エッチングがｎ型クラッド層に達する時間を予想し、その時間が経過したあとにモニタを開始すればいい。 After forming the groove and L shape by dry etching after FIG. 8, the exposure of the n-type contact layer is detected by the change in the plasma emission intensity by dry etching, and the dry etching is stopped after the detection. When the n-type contact layer is exposed, the plasma emission intensity of the constituent elements of the n-type contact layer or the n-type cladding layer changes, so that any one of these elements may be monitored. Here, since the n-type contact layer is InGaAs and the n-type cladding layer is InP, the plasma emission intensity of any one of In, Ga, As, and P may be monitored. Since a layer containing these elements is stacked above the n-type cladding layer, the plasma emission intensity changes during the etching of these layers. In order to prevent this change from being erroneously detected, it is only necessary to know the speed of dry etching in advance, predict the time for etching to reach the n-type cladding layer, and start monitoring after that time has elapsed.
　図１７にドライエッチング後の断面図を示す。図１７（ｂ）にはＬ字形状７２ａの角部付近を拡大した図を示している。図から、ドライエッチングで形成された溝７０ａとＬ字形状７２ａの最深部がｎ型コンタクト層７４の上面と一致していることが分かる。また図１７（ｂ）の拡大図を見れば、基板１０に対してほぼ垂直なＬ字形状７２ａの側面がｎ型クラッド層７６の下端付近まで延びていることが分かる。このほぼ垂直な側面の下端は、ドライエッチングがｎ型コンタクト層７４を削り過ぎないという制約の中で最大限、下方にある。 FIG. 17 shows a cross-sectional view after dry etching. FIG. 17 (b) shows an enlarged view of the vicinity of the corner of the L-shape 72a. From the figure, it can be seen that the deepest portion of the groove 70 a and the L-shape 72 a formed by dry etching coincides with the upper surface of the n-type contact layer 74. 17B, it can be seen that the side surface of the L-shape 72a substantially perpendicular to the substrate 10 extends to the vicinity of the lower end of the n-type cladding layer 76. The lower end of the substantially vertical side surface is maximally below the constraint that the dry etching does not overcut the n-type contact layer 74.
　次いで、溝７０ａおよびＬ字形状７２ａの側面を含む全面にマスクを成膜する。このマスク成膜の工程は、実施の形態１で図１０を用いて説明したのと同じである。その後の工程も、実施の形態１と同様に実施する。そのようにして図１８、１９に示した半導体レーザ素子が形成される。実施の形態１ではこれらの図に対応するのはそれぞれ図１、３である。図１９と図３を比べると、実施の形態２の製造方法を用いて製造した半導体レーザ素子のほうが、側面８４および側面８６の下端がより下方に延びていることが見て取れる。 Next, a mask is formed on the entire surface including the side surfaces of the groove 70a and the L-shape 72a. The mask film forming process is the same as that described in the first embodiment with reference to FIG. Subsequent steps are performed in the same manner as in the first embodiment. Thus, the semiconductor laser element shown in FIGS. 18 and 19 is formed. In the first embodiment, FIGS. 1 and 3 correspond to these drawings, respectively. 19 and FIG. 3, it can be seen that the lower end of the side surface 84 and the side surface 86 of the semiconductor laser device manufactured using the manufacturing method of the second embodiment extends further downward.
（効果）
　実施の形態２に係る半導体レーザ素子の製造方法を用いれば、素子抵抗の増大を防げる。この製造方法ではドライエッチング時にｎ型コンタクト層７４が露出したことを検知するため、ｎ型コンタクト層７４を削りすぎることがなく、素子抵抗の増大を防止できる。 (effect)
If the method for manufacturing a semiconductor laser device according to the second embodiment is used, an increase in device resistance can be prevented. In this manufacturing method, since the n-type contact layer 74 is detected during dry etching, the n-type contact layer 74 is not excessively etched, and an increase in element resistance can be prevented.
　また、傾斜面によるミラー損失を抑えられる。この製造方法ではｎ型コンタクト層７４が露出するぎりぎりまでドライエッチングを実施するため、Ｌ字形状７２の側面８６が下方に最大限延びることになる。そのため側面８６の下にある傾斜面８２に起因するミラー損失を低減できる。 Also, mirror loss due to the inclined surface can be suppressed. In this manufacturing method, the dry etching is performed until the n-type contact layer 74 is exposed, so that the side surface 86 of the L-shape 72 extends downward to the maximum. Therefore, mirror loss due to the inclined surface 82 under the side surface 86 can be reduced.
（変形例）
　実施の形態２の変形として、ドライエッチングがｎ型コンタクト層７４の上面に到達したことを確認したあと、一定時間経過後にドライエッチングを停止させることも可能である。ｎ型コンタクト層７４が削られることにはなるが、上記の時間を調節することで側面８６の下端をさらに下に延ばせるため、ミラー損失がより低減される。 (Modification)
As a modification of the second embodiment, after confirming that dry etching has reached the upper surface of the n-type contact layer 74, it is also possible to stop the dry etching after a lapse of a certain time. Although the n-type contact layer 74 is scraped, the lower end of the side surface 86 can be extended further downward by adjusting the above time, so that the mirror loss is further reduced.
１０　基板
１２，７４　ｎ型コンタクト層
１４，７６　ｎ型クラッド層
１６　ブロック層
１８　活性層
２０　ｐ型クラッド層
２２　リッジ
２４　ｐ型コンタクト層
２６，７８　絶縁膜
２８　ｎ側電極
３０　ｐ側電極
３２，３２ａ，７０，７０ａ　溝
３４，９２　メサ
３６，９４　半導体層
３８，４０，８０，８２　傾斜面
４２，４４，８４，８６　側面
４６，４８，８８，９０　底面
５０，５０ａ，７２，７２ａ　Ｌ字形状
５２，５４，６０　マスク
５６，５８，６６，６８　開口 10 substrate 12, 74 n-type contact layer 14, 76 n-type cladding layer 16 block layer 18 active layer 20 p-type cladding layer 22 ridge 24 p-type contact layers 26, 78 insulating film 28 n-side electrode 30 p- side electrodes 32, 32a , 70, 70a Groove 34, 92 Mesa 36, 94 Semiconductor layer 38, 40, 80, 82 Inclined surface 42, 44, 84, 86 Side surface 46, 48, 88, 90 Bottom surface 50, 50a, 72, 72a L-shaped 52 , 54, 60 Mask 56, 58, 66, 68 Opening

Claims (8)

  1. 　基板と、
    　前記基板の上に形成され、第１導電型コンタクト層を有する半導体層とを備え、
    　前記半導体層には、共振器を有し、両脇が溝に挟まれ、第２導電型コンタクト層を有するメサが設けられ、
    　前記共振器の少なくとも片側の端面を含む前記メサの側面と前記第１導電型コンタクト層の上面とがＬ字形状を成し、
    　前記溝の底面は前記第１導電型コンタクト層の上面で構成され、
    　前記溝の側面は、前記溝の底面近傍にあり傾斜した第１の傾斜面、および、前記第１の傾斜面の上にありほぼ垂直な第１の側面で構成され、
    　前記Ｌ字形状の側面は、前記Ｌ字形状の底面近傍にあり傾斜した第２の傾斜面、および、前記第２の傾斜面の上にありほぼ垂直な第２の側面で構成され、
    　少なくとも１つの前記溝の底面で前記第１導電型コンタクト層に接続された第１の電極を備え、
    　前記第２導電型コンタクト層に接続された第２の電極を備えた半導体レーザ素子。     A substrate,
    A semiconductor layer formed on the substrate and having a first conductivity type contact layer;
    The semiconductor layer has a resonator, a mesa having a second conductivity type contact layer provided on both sides between the grooves,
    A side surface of the mesa including an end face on at least one side of the resonator and an upper surface of the first conductivity type contact layer form an L shape,
    A bottom surface of the groove is formed by an upper surface of the first conductivity type contact layer;
    The side surface of the groove is composed of a first inclined surface that is inclined near the bottom surface of the groove, and a first side surface that is substantially perpendicular to the first inclined surface,
    The L-shaped side surface includes a second inclined surface that is inclined near the bottom surface of the L-shaped shape, and a second side surface that is substantially perpendicular to the second inclined surface,
    A first electrode connected to the first conductivity type contact layer at a bottom surface of at least one of the grooves;
    A semiconductor laser device comprising a second electrode connected to the second conductivity type contact layer.
  2. 　前記共振器は下から順に第１導電型クラッド層、活性層、第２導電型クラッド層を含み、
    　前記第１導電型クラッド層または前記第２導電型クラッド層に回折格子構造を備えた請求項１に記載の半導体レーザ素子。     The resonator includes a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer in order from the bottom,
    The semiconductor laser device according to claim 1, wherein the first conductivity type cladding layer or the second conductivity type cladding layer is provided with a diffraction grating structure.
  3. 　前記基板は半絶縁性のＩｎＰでできており、
    　前記第１導電型コンタクト層はｎ型ＩｎＧａＡｓまたはｎ型ＩｎＧａＡｓＰでできており、
    　前記第１導電型クラッド層はｎ型ＩｎＰでできた請求項１または２に記載の半導体レーザ素子。     The substrate is made of semi-insulating InP,
    The first conductivity type contact layer is made of n-type InGaAs or n-type InGaAsP,
    The semiconductor laser device according to claim 1, wherein the first conductivity type cladding layer is made of n-type InP.
  4. 　共振器を有するメサを備えた半導体レーザ素子の製造方法であって、
    　基板の上に、順に第１導電型コンタクト層、第１導電型クラッド層、活性層、第２導電型クラッド層および第２導電型コンタクト層を積層する工程と、
    　前記第１導電型クラッド層の一部を残すようにドライエッチングすることで、前記メサの両脇にある溝を形成し、前記共振器の端面を含む前記メサの側面を有するＬ字形状を形成するドライエッチング工程と、
    　前記ドライエッチング工程で形成されたエッチング側面をマスクし、前記第１導電型コンタクト層に対して選択性を有するエッチャントを使用し、前記溝の底面および前記Ｌ字形状の底面の上の前記第１導電型クラッド層をウェットエッチングすることで、前記第１導電型コンタクト層を露出させるウェットエッチング工程と、
    　少なくとも１つの前記溝の底面において前記第１導電型コンタクト層に接続された、第１の電極を形成する工程と、
    　前記第２導電型コンタクト層に前記メサの上方で接続された第２の電極を形成する工程とを備えた半導体レーザ素子の製造方法。     A method of manufacturing a semiconductor laser device including a mesa having a resonator,
    Laminating a first conductivity type contact layer, a first conductivity type clad layer, an active layer, a second conductivity type clad layer and a second conductivity type contact layer on a substrate in order;
    By performing dry etching so as to leave a part of the first conductivity type cladding layer, grooves on both sides of the mesa are formed, and an L shape having a side surface of the mesa including an end face of the resonator is formed. Dry etching process,
    The etching side surface formed in the dry etching process is masked, an etchant having selectivity with respect to the first conductivity type contact layer is used, and the first surface on the bottom surface of the groove and the L-shaped bottom surface is used. A wet etching step of exposing the first conductivity type contact layer by wet etching the conductivity type cladding layer;
    Forming a first electrode connected to the first conductivity type contact layer at a bottom surface of at least one of the grooves;
    Forming a second electrode connected above the mesa to the second conductivity type contact layer.
  5. 　前記ドライエッチング工程において、前記第１導電型コンタクト層または前記第１導電型クラッド層の構成元素のうち、前記第１導電型コンタクト層が露出すると強度が変化する元素のプラズマ発光強度をモニタし、前記プラズマ発光強度の変化を検出した時点あるいは前記時点から一定時間経過後に前記ドライエッチングを停止する請求項４に記載の半導体レーザ素子の製造方法。 In the dry etching step, among the constituent elements of the first conductivity type contact layer or the first conductivity type cladding layer, the plasma emission intensity of an element whose intensity changes when the first conductivity type contact layer is exposed is monitored, 5. The method of manufacturing a semiconductor laser device according to claim 4, wherein the dry etching is stopped when a change in the plasma emission intensity is detected or after a predetermined time has elapsed since the time.
  6. 　前記第１導電型クラッド層または前記第２導電型クラッド層に回折格子構造を形成する工程を備えた請求項４または５に記載の半導体レーザ素子の製造方法。 6. The method of manufacturing a semiconductor laser device according to claim 4, further comprising a step of forming a diffraction grating structure in the first conductivity type cladding layer or the second conductivity type cladding layer.
  7. 　前記基板は半絶縁性のＩｎＰでできており、
    　前記第１導電型コンタクト層はｎ型ＩｎＧａＡｓまたはｎ型ＩｎＧａＡｓＰでできており、
    　前記第１導電型クラッド層はｎ型ＩｎＰでできた請求項４～６のいずれか１項に記載の半導体レーザ素子の製造方法。     The substrate is made of semi-insulating InP,
    The first conductivity type contact layer is made of n-type InGaAs or n-type InGaAsP,
    7. The method of manufacturing a semiconductor laser device according to claim 4, wherein the first conductivity type cladding layer is made of n-type InP.
  8. 　前記エッチャントとして塩酸または臭化水素のいずれかを用いる請求項７に記載の半導体レーザ素子の製造方法。 8. The method of manufacturing a semiconductor laser element according to claim 7, wherein either hydrochloric acid or hydrogen bromide is used as the etchant.
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