WO2019186332A1 - 表示装置の動作方法 - Google Patents
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- WO2019186332A1 WO2019186332A1 PCT/IB2019/052292 IB2019052292W WO2019186332A1 WO 2019186332 A1 WO2019186332 A1 WO 2019186332A1 IB 2019052292 W IB2019052292 W IB 2019052292W WO 2019186332 A1 WO2019186332 A1 WO 2019186332A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
Definitions
- One embodiment of the present invention relates to a display device and an operation method thereof.
- one embodiment of the present invention is not limited to the above technical field.
- the technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
- one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, A driving method or a manufacturing method thereof can be given as an example.
- a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
- a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, an electronic device, or the like may be referred to as a semiconductor device.
- a semiconductor device Alternatively, it may be said that these include semiconductor devices.
- Patent Document 1 discloses a display device having a high withstand voltage capable of driving a display element with a high voltage.
- a source driver circuit capable of generating a high potential is required.
- a source driver circuit occupies a large area and is expensive.
- a potential higher than the maximum potential that can be generated by the source driver circuit and a potential lower than the minimum value that can be generated by the source driver circuit can be applied to one electrode of the display element. It is an object to provide a display device that can be used. Another object is to provide a display device capable of applying a high voltage to a display element. Another object is to provide a small display device. Another object is to provide a low-cost display device. Another object is to provide a display device capable of displaying a high-luminance image. Another object is to provide a display device with low power consumption. Another object is to provide a display device with high reliability. Another object is to provide a display device that operates at high speed. Another object is to provide a display device capable of displaying a high-quality image. Another object is to provide a novel display device.
- operation of a display device in which a potential higher than the maximum potential that can be generated by the source driver circuit and a potential lower than the minimum value that can be generated by the source driver circuit can be applied to one electrode of the display element. It is an object to provide a method. Another object is to provide a method for operating a display device in which a high voltage can be applied to a display element. Another object is to provide a method for operating a small display device. Another object is to provide an operation method of a low-cost display device. Another object is to provide a method for operating a display device capable of displaying a high-luminance image. Another object is to provide a method for operating a display device with low power consumption. Another object is to provide a method for operating a display device with high reliability. Another object is to provide a method for operating a display device that operates at high speed. Another object is to provide a method for operating a display device capable of displaying a high-quality image. Another object is to provide a novel method for operating a display device.
- One embodiment of the present invention includes a pixel provided with a display element including a pixel electrode and a common electrode, and the pixel is electrically connected to the first data line and the second data line.
- the second potential is a potential calculated based on the first potential.
- the third potential is applied to the common electrode. If the second potential is higher than the applied potential and the value of the second potential is greater than or equal to the potential applied to the common electrode, the third potential is A method of operating a lower display device than the potential applied to.
- the third potential may be a potential that is greater than or equal to the maximum value that the first potential can take, or a potential that is less than or equal to the minimum value that the first potential can take.
- the display device includes a source driver circuit, the source driver circuit is electrically connected to the first data line, and the source driver circuit is electrically connected to the second data line.
- the source driver circuit may have a function of generating the first potential and the second potential.
- One embodiment of the present invention includes a pixel provided with a display element including a pixel electrode and a common electrode, and the pixel is electrically connected to the first data line and the second data line.
- the display device is operated by a first operation and a second operation, and in the first operation, a first potential is supplied to the pixel through the first data line, and a second operation is performed.
- the second potential is supplied to the pixel through the data line in parallel, and then the third potential is supplied to the pixel through the second data line, whereby the third potential held in the pixel is supplied.
- the potential of 1 is changed to the fourth potential, the fourth potential is applied to the pixel electrode, and the second potential is calculated based on the first potential and is equal to or lower than the potential applied to the common electrode.
- the third potential is a potential higher than the potential applied to the common electrode, and the fourth potential is the common electrode.
- the fifth potential is supplied to the pixel via the first data line, and the sixth potential is supplied to the pixel via the second data line.
- the fifth potential held in the pixel is changed to the eighth potential by supplying the seventh potential to the pixel through the second data line after performing the supply of the second potential in parallel.
- the eighth potential is applied to the pixel electrode, the sixth potential is a potential that is calculated based on the fifth potential and is equal to or greater than the potential applied to the common electrode, and the seventh potential is
- the display device operating method is a potential having a value lower than the potential applied to the common electrode, and the eighth potential is a potential equal to or lower than the potential applied to the common electrode.
- the third potential may be a potential that is greater than or equal to the maximum value that the first potential can take
- the seventh potential may be a potential that is greater than or equal to the minimum value that the fifth potential can take.
- the range of values that the first potential can take and the range of values that the fifth potential can take may be equal.
- the display device includes a source driver circuit, the source driver circuit is electrically connected to the first data line, and the source driver circuit is electrically connected to the second data line.
- the source driver circuit may have a function of generating the first potential and the second potential, and the fifth potential and the sixth potential.
- the pixel includes a first transistor, a second transistor, and a capacitor, and one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor.
- the other of the source and the drain of the first transistor is electrically connected to the first data line, and one of the source and the drain of the second transistor is electrically connected to the other electrode of the capacitor.
- the other of the source and the drain of the second transistor may be electrically connected to the second data line.
- the first transistor and the second transistor each include a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).
- the display element may be a liquid crystal element.
- a potential higher than the maximum potential that can be generated by the source driver circuit and a potential lower than the minimum value that can be generated by the source driver circuit can be applied to one electrode of the display element.
- a display device that can be provided can be provided.
- a display device capable of applying a high voltage to the display element can be provided.
- a small display device can be provided.
- a low-cost display device can be provided.
- a display device that can display a high-luminance image can be provided.
- a display device with low power consumption can be provided.
- a highly reliable display device can be provided.
- a display device that operates at high speed can be provided.
- a display device that can display a high-quality image can be provided.
- a novel display device can be provided.
- operation of a display device in which a potential higher than the maximum potential that can be generated by the source driver circuit and a potential lower than the minimum value that can be generated by the source driver circuit can be applied to one electrode of the display element
- a method can be provided.
- a method for operating a display device that can apply a high voltage to a display element can be provided.
- a method for operating a small display device can be provided.
- a low-cost operation method of a display device can be provided.
- a method for operating a display device that can display a high-luminance image can be provided.
- a method for operating a display device with low power consumption can be provided.
- a method for operating a display device with high reliability can be provided.
- a method for operating a display device that operates at high speed can be provided.
- a method for operating a display device capable of displaying a high-quality image can be provided.
- a novel method for operating a display device can be provided.
- FIG. 6 illustrates an example of a display device and a diagram illustrating an example of a pixel.
- FIG. 6 is a diagram illustrating an example of operation of a pixel.
- FIG. 6 is a diagram illustrating an example of a relationship between a potential supplied to a pixel and a gradation of an image displayed by the pixel.
- FIG. 6 is a diagram illustrating an example of operation of a pixel.
- FIG. 6 is a diagram illustrating an example of a relationship between a potential supplied to a pixel and a gradation of an image displayed by the pixel.
- FIG. 11 illustrates an example of a display device.
- FIG. 6 is a diagram illustrating an example of operation of a pixel.
- FIG. 6 is a diagram illustrating an example of operation of a pixel.
- FIG. 11 illustrates an example of a display device.
- FIG. 6 is a diagram illustrating an example of operation of a pixel. The figure which shows an example of a pixel.
- Sectional drawing which shows the structural example of a display apparatus.
- FIG. 6 is a top view illustrating a structure example of a pixel.
- Sectional drawing which shows the structural example of a display apparatus.
- Sectional drawing which shows the structural example of a display apparatus.
- Sectional drawing which shows the structural example of a display apparatus Sectional drawing which shows the structural example of a display apparatus.
- Sectional drawing which shows the structural example of a display apparatus.
- FIG. 14 illustrates an example of an electronic device.
- FIG. 14 illustrates an example of an electronic device.
- FIG. 14 illustrates an example of an electronic device.
- FIG. 6 is a diagram illustrating a relationship between a potential supplied to a pixel and a gradation of an image displayed by the pixel in the embodiment.
- the figure which shows the relationship between the voltage applied to a display element, and the gradation of the image which a pixel displays in an Example.
- film and “layer” can be interchanged with each other depending on circumstances or circumstances.
- conductive layer can be changed to the term “conductive film”.
- insulating film can be changed to the term “insulating layer”.
- a metal oxide is a metal oxide in a broad sense.
- Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply OS).
- oxide semiconductors also referred to as oxide semiconductors or simply OS.
- the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing as an OS FET, it can be translated into a transistor having a metal oxide or an oxide semiconductor.
- metal oxides containing nitrogen may be collectively referred to as metal oxides.
- a metal oxide containing nitrogen may be referred to as a metal oxynitride.
- One embodiment of the present invention relates to a method for operating a display device including a pixel provided with a display element including a pixel electrode and a common electrode.
- a liquid crystal element can be used as the display element.
- the display device of one embodiment of the present invention includes a source driver circuit.
- the pixel is electrically connected to the source driver circuit via the first data line, and is electrically connected to the source driver circuit via the second data line.
- a constant potential can be applied to the common electrode.
- a potential that is an average value of the maximum value of the potential that can be generated by the source driver circuit and the minimum value of the potential that can be generated by the source driver circuit can be applied to the common electrode.
- a first potential which is a potential corresponding to image data
- a second potential which is a potential calculated based on the first potential
- the third potential is supplied to the pixel through the second data line in the same manner as the second potential.
- the second potential held in the pixel is rewritten to the third potential.
- the first potential held in the pixel is changed to the fourth potential.
- the fourth potential can be applied to the pixel electrode.
- the first to third potentials are potentials generated by, for example, a source driver circuit. Therefore, the first to third potentials cannot be higher than the maximum potential that can be generated by the source driver circuit, and can be lower than the minimum potential that can be generated by the source driver circuit. Can not.
- the fourth potential is a potential generated inside the pixel based on the first to third potentials.
- the magnitude of the difference between the fourth potential and the first potential corresponds to the magnitude of the difference between the third potential and the second potential. That is, for example, the fourth potential increases as the first potential increases and as the difference between the third potential and the second potential increases.
- the fourth potential can be higher than the maximum potential that can be generated by the source driver circuit and can be lower than the minimum potential that can be generated by the source driver circuit. Can do.
- the voltage applied to the display element can be made larger than twice the output voltage amplitude of the source driver circuit.
- the fourth potential is set to a potential of 10 V or more. Or a potential of -10 V or less.
- a voltage applied to a display element indicates an absolute value of a difference between a potential applied to one electrode of the display element and a potential applied to the other electrode of the display element.
- the absolute value of the difference between the potential applied to the pixel electrode and the potential applied to the common electrode is shown.
- the third potential can be a potential having a polarity different from that of the second potential, for example.
- the third potential can be, for example, the maximum value or the minimum value of the potential that can be generated by the source driver circuit.
- the source driver circuit can generate a potential of ⁇ 5 V or more and 5 V or less
- the third potential is ⁇ 5 V
- the second potential is a negative potential
- the third potential can be 5V.
- the potential applied to the common electrode can be a ground potential that is an average value of ⁇ 5 V and 5 V.
- the polarity of the potential can be determined based on, for example, the potential applied to the common electrode. For example, it can be said that a potential higher than a potential applied to the common electrode and a potential lower than a potential applied to the common electrode are potentials having different polarities.
- the third potential is not necessarily generated by the source driver circuit.
- a power supply circuit provided outside the source driver circuit may generate the third potential.
- the third potential is generated by a circuit other than the source driver circuit, so that the third potential is equal to or higher than the maximum potential that can be generated by the source driver circuit, or the minimum potential that can be generated by the source driver circuit.
- the following potential can be set. Thereby, the difference between the third potential and the second potential can be further increased.
- the potential higher than the maximum value that can be generated by the source driver circuit and the potential that is lower than the minimum value that can be generated by the source driver circuit are set to the fourth value.
- a potential can be applied to the pixel electrode. Accordingly, since a high voltage can be applied to the display element, a display element that is preferably applied with a high voltage during operation can be used. For example, a liquid crystal exhibiting a blue phase or a polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal) can be used as the display element.
- PDLC Polymer Dispersed Liquid Crystal
- the display device of one embodiment of the present invention can be downsized and inexpensive. .
- FIG. 1A illustrates a structural example of a display device 10 which is a display device of one embodiment of the present invention.
- the display device 10 includes a display unit 12 in which pixels 11 are arranged in a matrix of m rows and n columns, an image data generation circuit 13, a gate driver circuit 14, and a source driver circuit 15.
- the pixel 11 in the i-th row and j-th column (i is an integer of 1 to m and j is an integer of 1 to n) is indicated as a pixel 11 [i, j].
- the image data generation circuit 13 is electrically connected to the source driver circuit 15.
- the pixels 11 in the same row are electrically connected to the gate driver circuit 14 through one wiring 21 and are electrically connected to the gate driver circuit 14 through one wiring 22.
- the pixels 11 in the same column are electrically connected to the source driver circuit 15 through one wiring 41 and are electrically connected to the source driver circuit 15 through one wiring 42.
- the image data generation circuit 13 has a function of generating image data corresponding to an image displayed on the display unit 12.
- the gate driver circuit 14 has a function of generating a potential for controlling the operation of the pixel 11.
- the source driver circuit 15 has a function of generating a potential corresponding to image data.
- the wiring 21 and the wiring 22 that are electrically connected to the pixel 11 [i, 1] to the pixel 11 [i, n] are referred to as a wiring 21 [i] and a wiring 22 [i], respectively.
- the wiring 41 and the wiring 42 which are electrically connected to the pixels 11 [1, j] to 11 [m, j] are referred to as a wiring 41 [j] and a wiring 42 [j], respectively.
- the wiring 21 and the wiring 22 have a function as a scanning line.
- the wiring 41 and the wiring 42 function as data lines.
- FIG. 1B is a diagram illustrating a configuration example of the pixel 11.
- the pixel 11 includes a transistor 101, a transistor 102, a capacitor 104, a capacitor 105, and a display element 106.
- the display element 106 for example, a liquid crystal element can be used.
- One of a source and a drain of the transistor 101 is electrically connected to one electrode of the capacitor 104.
- One of a source and a drain of the transistor 102 is electrically connected to the other electrode of the capacitor 104.
- One electrode of the capacitor 104 is electrically connected to one electrode of the capacitor 105.
- One electrode of the capacitor 105 is electrically connected to one electrode of the display element 106.
- one electrode of the display element 106 can be a pixel electrode, for example.
- the other electrode of the display element 106 can be a common electrode, for example.
- a node to which one of the source and the drain of the transistor 101, one electrode of the capacitor 104, one electrode of the capacitor 105, and one electrode of the display element 106 are electrically connected is referred to as a node NM.
- a node to which one of the source and the drain of the transistor 102 and the other electrode of the capacitor 104 are electrically connected is a node NA.
- a gate of the transistor 101 is electrically connected to the wiring 21.
- a gate of the transistor 102 is electrically connected to the wiring 22.
- the other of the source and the drain of the transistor 101 is electrically connected to the wiring 41.
- the other of the source and the drain of the transistor 102 is electrically connected to the wiring 42.
- the other electrode of the capacitor 105 is electrically connected to the common wiring 32.
- the other electrode of the display element 106 is electrically connected to the common wiring 33.
- a potential V COM can be supplied to the common wiring 33.
- the potential VCOM can be a constant potential, for example.
- the potential VCOM can be, for example, a potential that is an average value of the maximum value of the potential that can be generated by the source driver circuit 15 and the minimum value of the potential that can be generated by the source driver circuit 15.
- the potential VCOM can be a ground potential, for example. Note that the potential supplied to the common line 32 also can be the potential of the same value as the potential V COM.
- a potential for controlling conduction or non-conduction of the transistor 101 is supplied to the gate of the transistor 101 through the wiring 21.
- a potential for controlling conduction or non-conduction of the transistor 102 is supplied to the gate of the transistor 102 through the wiring 22.
- a potential is supplied to the node NM through the wiring 41.
- a potential is supplied to the node NA through the wiring 42.
- the potential supplied to the node NM can be held for a long time.
- the transistor 102 has a very low off-state current
- the potential supplied to the node NA can be held for a long time.
- a transistor with extremely low off-state current for example, a transistor including a metal oxide in a channel formation region (hereinafter referred to as an OS transistor) can be given.
- a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used.
- the oxide semiconductor includes indium, for example, a CAAC-OS or a CAC-OS described later can be used.
- the CAAC-OS is a crystalline oxide semiconductor.
- a transistor including the crystalline oxide semiconductor can be improved in reliability, and thus is preferably used for the display device of one embodiment of the present invention.
- the CAC-OS exhibits high mobility characteristics, it is suitable for a transistor that performs high-speed driving.
- an OS transistor Since the OS transistor has a large energy gap, it exhibits extremely low off-state current characteristics.
- an OS transistor has characteristics different from a transistor having Si in a channel formation region (hereinafter referred to as a Si transistor), such as impact ionization, avalanche breakdown, and a short channel effect, and has a highly reliable circuit. Can be formed.
- transistors other than the OS transistor may be used as the transistor 101 and the transistor 102.
- the Si transistor include a transistor having amorphous silicon, a transistor having crystalline silicon (typically low-temperature polysilicon), and a transistor having single crystal silicon.
- the transistors 101 and 102 are n-channel transistors, even if one or both of the transistors 101 and 102 are p-channel transistors by appropriately inverting the magnitude relationship of potentials, The description of can be applied.
- FIG. 2 is a timing chart for explaining an example of an operation method of the pixel 11 [i, j].
- the display device 10 including the pixel 11 [i, j] displays one frame image by the operation from time T01 to time T04, and displays the next one frame image by the operation from time T11 to time T14. indicate.
- an operation from time T01 to time T04 is referred to as a first operation
- an operation from time T11 to time T14 is referred to as a second operation.
- the pixel 11 can perform frame inversion driving by alternately performing the first operation and the second operation.
- the potential VSDMAX indicates the maximum potential that can be generated by the source driver circuit 15.
- the potential V SDMIN indicates the minimum value of the potential that can be generated by the source driver circuit 15.
- V COM (V SDMAX + V SDMIN ) / 2 which is a potential applied to the other electrode of the display element 106.
- the capacity coupling coefficient of the node NM is 1. Further, the variation in potential due to the threshold voltage of the transistor and feedthrough is not taken into consideration.
- a node NM and a node NA provided in the pixel 11 [i, j] are denoted as a node NM [i, j] and a node NA [i, j], respectively.
- the potential of the wiring 21 [i] and the potential of the wiring 22 [i] are set high. Further, the potential of the wiring 41 [j] is a potential V S1 [i, j] corresponding to the image data, and the potential of the wiring 42 [j] is a potential V S2 [i, j].
- the transistor 101 and the transistor 102 included in the pixel 11 [i, j] are turned on, the potential of the node NM [i, j] becomes the potential V S1 [i, j], and the potential of the node NA [i, j]. Becomes the potential V S2 [i, j].
- the potential V S1 [i, j] can be generated by the source driver circuit 15, the value of the potential V S1 [i, j] can be greater than or equal to the potential V SDMIN and less than or equal to the potential V SDMAX . Further, the potential V S2 [i, j] can be calculated by the following equation, for example.
- the value of the potential V S2 [i, j] can be greater than or equal to the potential V SDMIN and less than or equal to the potential V COM .
- the potential V S2 [i, j] can be generated by the source driver circuit 15.
- the potential of the wiring 21 [i] and the potential of the wiring 22 [i] are set low. Accordingly, the transistor 101 and the transistor 102 included in the pixel 11 [i, j] are turned off, the potential V S1 [i, j] is held at the node NM [i, j], and the node NA [i, j] is held at the node NA [i, j]. The potential V S2 [i, j] is held.
- the low potential can be, for example, a ground potential or a negative potential.
- the high potential can be higher than the low potential.
- the potential of the wiring 21 [i] is set to a low potential, and the potential of the wiring 22 [i] is set to a high potential.
- the potential of the wiring 42 [j] is set to a potential VRP .
- the transistor 102 included in the pixel 11 [i, j] is turned on, and the potential of the node NA [i, j] becomes the potential VRP .
- the node NM [i, j] is in a floating state. Therefore, the potential of the node NM [i, j] is a potential V DE [i, j] expressed by the following equation.
- the potential V DE [i, j] can be calculated from the potential V S1 [i, j], the potential V S2 [i, j], and the potential V RP . Therefore, the potential V DE [i, j] is generated inside the pixel 11 [i, j] based on the potential V S1 [i, j], the potential V S2 [i, j], and the potential V RP. It can be said that the potential is applied.
- the potential V DE [i, j] can be higher than the potential “V S1 [i, j] ⁇ V S2 [i, j]”.
- the potential V S2 [i, j] because it can be lower than the potential V COM
- the potential V RP potential V S2 [i, j] and polar Can be said to be different.
- the higher the potential VRP the higher the potential V DE [i, j].
- the higher the potential V DE [i, j] is equal to or higher than the potential V COM
- the higher the potential V DE [i, j] the higher the potential “V DE [i, j] ⁇ V COM ”.
- the higher the potential V DE [i, j] the higher the voltage applied to the display element 106.
- the potential V RP since it can be generated by the source driver circuit 15, the value of the potential V RP can be less potential V SDMIN more potential V SDMAX. In FIG. 2, the value of the potential V RP is the potential V SDMAX .
- the value of the potential V DE [i, j] is set higher than the potential V SDMAX. Can do. Further, the value of the voltage “V DE [i, j] ⁇ V COM ” applied to the display element 106 can be set to be twice or more the voltage “V SDMAX ⁇ V COM ”. That is, the value of the potential V DE [i, j] can be set to the potential “2V SDMAX ⁇ V COM ” or higher. FIG. 2 shows a case where the value of the potential V DE [i, j] is higher than the potential “2V SDMAX ⁇ V COM ”.
- the output voltage amplitude of the source driver circuit 15 indicates the voltage “V SDMAX ⁇ V COM ” or the voltage “V COM ⁇ V SDMIN ”.
- An image is displayed between time T03 and time T04.
- the display element 106 is a transmissive liquid crystal element and a display device including the pixel 11 is provided with a backlight
- the potential is obtained using the pixel 11 [i, j] by turning on the backlight.
- An image corresponding to V DE [i, j] can be displayed.
- the potential of the wiring 21 and the potential of the wiring 22 are set low. Accordingly, the transistor 101 and the transistor 102 are turned off.
- the potential of the wiring 21 [i] and the potential of the wiring 22 [i] are set high.
- the potential of the wiring 41 [j] is a potential V ′ S1 [i, j] that is a potential corresponding to the image data
- the potential of the wiring 42 [j] is a potential V ′ S2 [i, j].
- the potential V ′ S1 [i, j] can be generated by the source driver circuit 15, the value of the potential V ′ S1 [i, j] is set to be equal to or higher than the potential V SDMIN and lower than or equal to the potential V SDMAX. it can. Further, the potential V ′ S2 [i, j] can be calculated by the following equation, for example.
- the value of the potential V ′ S2 [i, j] can be higher than or equal to the potential V COM and lower than or equal to the potential V SDMAX .
- the potential V ′ S2 [i, j] can be generated by the source driver circuit 15.
- the potential of the wiring 21 [i] and the potential of the wiring 22 [i] are set low. Accordingly, the transistor 101 and the transistor 102 included in the pixel 11 [i, j] are turned off, the potential V ′ S1 [i, j] is held at the node NM [i, j], and the node NA [i, j] is stored. Is held at the potential V ′ S2 [i, j].
- the potential of the wiring 21 [i] is set to a low potential, and the potential of the wiring 22 [i] is set to a high potential.
- the potential of the wiring 42 [j] is set to a potential V′RP .
- the transistor 102 included in the pixel 11 [i, j] is turned on, and the potential of the node NA [i, j] becomes the potential V′RP .
- the node NM [i, j] is in a floating state. Therefore, the potential of the node NM [i, j] is a potential V ′ DE [i, j] expressed by the following equation.
- the potential V ′ DE [i, j] can be calculated from the potential V ′ S1 [i, j], the potential V ′ S2 [i, j], and the potential V ′ RP . Therefore, the potential V ′ DE [i, j] is determined based on the potential V ′ S1 [i, j], the potential V ′ S2 [i, j], and the potential V ′ RP , and the pixel 11 [i, j]. It can be said that the potential is generated in the inside.
- the potential V ′ DE [i, j] can be made lower than the potential “V ′ S1 [i, j] ⁇ V ′ S2 [i, j]”.
- the potential V 'S2 [i, j] because it can be higher than the potential V COM, the potential V' when the RP is lower than the potential V COM, the potential V 'RP potential V' S2 [i, j] and a different polarity.
- the lower the potential V ′ RP the lower the potential V ′ DE [i, j].
- the potential V 'DE [i, j] the value of equal to or less than the potential V COM
- the potential "V COM -V 'DE [i , j] "increases.
- the lower the potential V ′ DE [i, j] the higher the voltage applied to the display element 106.
- the value of the potential V ′ RP can be greater than or equal to the potential V SDMIN and less than or equal to the potential V SDMAX .
- the value of the potential V ′ RP is set to the potential V SDMIN .
- the potential V ′ S1 [i, j] and the potential V′RP are lowered, and the potential V ′ S2 [i, j] is increased, whereby the value of the potential V ′ DE [i, j] is changed to the potential V SDMIN.
- it can be twice or more display devices 106 on the applied voltage "V COM -V 'DE [i , j]" value voltage of "V COM -V SDMIN".
- the value of the potential V ′ DE [i, j] can be set to “2V SDMIN ⁇ V COM ” or less.
- FIG. 2 shows a case where the value of the potential V ′ DE [i, j] is lower than the potential “2V SDMIN ⁇ V COM ”.
- An image is displayed between time T13 and time T14.
- the display element 106 is a transmissive liquid crystal element and a display device including the pixel 11 is provided with a backlight
- the potential is obtained using the pixel 11 [i, j] by turning on the backlight.
- An image corresponding to V ′ DE [i, j] can be displayed.
- the frame inversion driving is performed by the operation after time T11.
- the pixel 11 can perform frame inversion driving by alternately performing the first operation and the second operation, for example, every frame period.
- the display element 106 is a liquid crystal element
- the deterioration of the display element 106 can be suppressed as compared with the case of not performing frame inversion driving. Therefore, the reliability of the display device including the pixel 11 can be improved.
- the potential of the wiring 21 [i] and the potential of the wiring 22 [i] are set low. Accordingly, the transistor 101 and the transistor 102 included in the pixel 11 [i, j] are turned off.
- the potential of the wiring 41 before the time T01, from the time T02 to the time T11, and after the time T12 is set to the potential VCOM .
- the potential of the wiring 41 [j] in the period is the potential VCOM. Not only COM but any potential can be set.
- the time T01 before from time T04 to time T11, and the potential of the wiring 42 at time T14 after was the potential V COM, the potential of the wiring 42 [j] for the period is not limited to the potential V COM Any potential can be used.
- the values of the potential V S1 , the potential V S2 , and the potential V DE and the values of the potential V ′ S1 , the potential V ′ S2 , and the potential V ′ DE are different for each pixel 11. Therefore, these potentials supplied to the pixel 11 [i, j] are indicated by a symbol [i, j].
- the value of the potential V RP and the value of the potential V ′ RP can be made equal for all the pixels 11, for example. Therefore, the symbols [i, j] are not described for the potential V RP and the potential V ′ RP supplied to the pixel 11.
- the supply of the potential V S1 and the potential V S2 to the pixel 11 and the supply of the potential V ′ S1 and the potential V ′ S2 to the pixel 11 are performed for each row of pixels 11, that is, line-sequentially. It can be carried out.
- the potential V RP and the potential V ′ RP can be simultaneously supplied to all the pixels 11, for example. That is, in the display device 10, the potential V RP and the potential V ′ RP can be supplied to the pixels 11 in the surface order.
- the operation between the time T ⁇ b> 01 and the time T ⁇ b> 03 shown in FIG. 2 is performed on all the pixels 11 in a line sequential manner, and then the operation between the time T ⁇ b> 03 and the time T ⁇ b> 11 is performed. It can be performed in a frame sequential manner. Thereafter, after the operation between time T11 and time T13 is performed on all the pixels 11 in line sequential order, the operation after time T13 can be performed in frame sequential order.
- the display device 10 can be operated at a higher speed than when the potential is supplied in a line sequential manner.
- FIG. 3A is a graph illustrating the relationship between the values of the potential V S1 , the potential V S2 , the potential V RP , and the potential V DE and the gradation represented by the image data.
- the pixel 11 displays an image
- the higher the gradation the higher the luminance of the light emitted from the pixel 11 can be.
- the luminance of light emitted from the pixel 11 can be 256 types.
- a dotted line in the graph frame represents the potential V S1
- a two-dot chain line represents the potential V S2
- a broken line represents the potential V RP
- a solid line represents the potential V DE .
- the portion representing the higher potential than the potential V SDMAX, and the portion representing the potential lower than the potential V SDMIN are hatched.
- the portion representing the higher potential than the potential V SDMAX, and the portion representing the potential lower than the potential V SDMIN are denoted by the same hatching as FIG 3 (A).
- the value of the potential V S1 can be the potential V SDMIN in the case of the lowest gradation, and can be the potential V SDMAX in the case of the highest gradation.
- the value of the potential V S2 can be the potential V COM in the case of the lowest gradation, and can be the potential V SDMIN in the case of the highest gradation.
- the value of the potential V DE can be set to the potential V COM in the case of the lowest gradation, and in the case of the highest gradation.
- FIG. 3B is a graph showing the relationship between the values of the potential V ′ S1 , the potential V ′ S2 , the potential V ′ RP , and the potential V ′ DE and the gradation represented by the image data.
- the value of the potential V ′ S1 can be the potential V SDMAX in the case of the lowest gradation, and can be the potential V SDMIN in the case of the highest gradation.
- the value of the potential V ′ S2 can be the potential V COM in the case of the lowest gradation and can be the potential V SDMAX in the case of the highest gradation.
- the value of the potential V ′ DE can be set to the potential V COM in the case of the lowest gradation, and the highest gradation In this case, the potential can be set to “3V SDMIN ⁇ 2V COM ”. That is, in the case of the highest gradation, the voltage “V COM ⁇ V ′ DE ” applied to the display element 106 can be three times the output voltage amplitude “V COM ⁇ V SDMIN ” of the source driver circuit 15. .
- a potential lower than the value can be applied to one electrode of the display element 106.
- the voltage applied to the display element 106 can be higher than twice the output voltage amplitude of the source driver circuit 15.
- a display element that is preferably applied with a high voltage during operation can be used as the display element 106.
- a liquid crystal element having a liquid crystal exhibiting a blue phase or a liquid crystal element having a polymer-dispersed liquid crystal can be used. Further, even if the output voltage amplitude of the source driver circuit 15 is small, a high voltage can be applied to the display element 106, so that the power consumption of the display device 10 can be reduced. Furthermore, since a high voltage can be applied to the display element 106 without making the source driver circuit 15 have a high breakdown voltage, the display device 10 can be downsized and made inexpensive.
- the potential of the wiring 42 [j] is set to the potential V S2 [i, j] from time T01 to time T02, and the potential of the wiring 42 [j] is set to the potential V from time T03 to time T04.
- RP the potential of the wiring 42 [j] is set to the potential V ′ S2 [i, j] from time T11 to time T12, and the potential of the wiring 42 [j] is set to the potential V ′ from time T13 to time T14.
- RP .
- one embodiment of the present invention is not limited to this.
- FIG. 4 illustrates an example of an operation method of the pixel 11 [i, j] included in the display device 10 in the above case.
- FIG. 5A shows the values of the potential V S1 , the potential V S2 , the potential V RP , and the potential V DE when the pixel 11 operates by the method shown in FIG. 4 and the gradation represented by the image data. It is a graph which shows a relationship.
- the value of the potential V S1 can be the potential V SDMIN in the case of the lowest gradation, and can be the potential V SDMAX in the case of the highest gradation.
- the value of the potential V S2 is the same as that shown in FIG. 3A in that it can be set to the potential V COM in the case of the lowest gradation, but is set to the potential V SDMAX in the case of the highest gradation. This is different from the case shown in FIG. That is, for example, the potential V S2 [i, j] can be calculated by the following equation.
- the value of the potential V RP can be set to the potential V SDMIN unlike the case illustrated in FIG.
- the value of the potential V DE [i, j] can be calculated by the following equation, and is set to the potential V COM in the case of the lowest gradation as in the case shown in FIG.
- the potential can be set to “3V SDMAX ⁇ 2V COM ”. That is, in the case of the highest gradation, the voltage “V DE ⁇ V COM ” applied to the display element 106 can be three times the output voltage amplitude “V SDMAX ⁇ V COM ” of the source driver circuit 15.
- FIG. 5B shows values of the potential V ′ S1 , the potential V ′ S2 , the potential V ′ RP , and the potential V ′ DE in the case where the pixel 11 operates by the method shown in FIG. It is a graph which shows the relationship between a key.
- the value of the potential V 'S1 similarly to the case shown in FIG. 3 (B), when the lowest gradation can be a potential V SDMAX, if the maximum gray level may be a potential V SDMIN.
- the value of the potential V ′ S2 can be set to the potential V COM in the case of the lowest gradation, as in the case shown in FIG. 3B.
- the potential V SDMIN is This is different from the case shown in FIG. That is, for example, the potential V ′ S2 [i, j] can be calculated by the following equation.
- the value of the potential V ′ RP can be set to the potential V SDMAX unlike the case illustrated in FIG.
- the value of the potential V ′ DE [i, j] can be calculated by the following equation, and is set to the potential V COM in the case of the lowest gradation as in the case shown in FIG.
- the potential can be set to “3V SDMIN ⁇ 2V COM ”. That is, in the case of the highest gradation, the voltage “V COM ⁇ V ′ DE ” applied to the display element 106 can be three times the output voltage amplitude “V COM ⁇ V SDMIN ” of the source driver circuit 15. .
- FIG. 6 is a block diagram illustrating a configuration example of the display device 50 which is a modification of the display device 10. Similar to the display device 10, the display device 50 includes a display unit 12 in which pixels 11 are arranged in a matrix of m rows and n columns, an image data generation circuit 13, a gate driver circuit 14, a source driver circuit 15, Have In FIG. 6, among the pixels 11, the pixel 11 [1, j], the pixel 11 [1, j + 1], the pixel 11 [1, j + 2], the pixel 11 [1, j + 3], and the pixel 11 [m, j] , Pixel 11 [m, j + 1], pixel 11 [m, j + 2], and pixel 11 [m, j + 3] are illustrated. In FIG. 6, the gate driver circuit 14 is not shown.
- the display device 50 is different from the display device 10 in that the transistor 16 is provided.
- the transistor 16 can be provided for each column of the pixels 11, for example.
- the display device 50 can include n transistors 16.
- One of a source and a drain of the transistor 16 is electrically connected to the wiring 42.
- the transistor 16 electrically connected to the wiring 42 [j] is referred to as a transistor 16 [j].
- the other of the source and the drain of the transistors 16 [1] to 16 [n] is electrically connected to, for example, one wiring 26.
- the gates of the transistors 16 [1] to 16 [n] are electrically connected to, for example, one wiring 23.
- the wiring 26 functions as a power supply line.
- the potential of the wiring 26 can be the potential V RP or the potential V ′ RP .
- the wiring 26 is electrically connected to a power supply circuit (not shown), and the power supply circuit generates a potential VRP and a potential V′RP .
- the transistor 16 By making the transistor 16 conductive, the potential of the wiring 26 can be supplied to the wiring 42. That is, the transistor 16 functions as a switch that controls conduction / non-conduction between the wiring 26 and the wiring 42. Note that the transistor 16 may not be a transistor as long as it has a function as a switch.
- the source driver circuit 15 Since the display device 50 can supply the potential V RP or the potential V ′ RP to the wiring 42 through the wiring 26, the source driver circuit 15 has a function of generating the potential V RP and the potential V ′ RP. It does not have to be.
- FIG. 7 is a timing chart for explaining an example of an operation method of the pixel 11 [i, j] included in the display device 50, and is a modification of FIG. Note that although the transistor 16 is an n-channel transistor, the following description can be applied even if the transistor 16 is a p-channel transistor or the like by appropriately inverting the magnitude relation of the potential.
- the potential of the wiring 23 is set to a low potential from time T01 to time T03. After that, between time T03 and time T04, the potential of the wiring 23 is set to a high potential, and the potential of the wiring 26 is set to the potential VRP . Accordingly, the transistors 16 [1] to 16 [n] are turned on, and the potentials of the wirings 42 [1] to 42 [n] are the potential VRP . Further, the potential of the wiring 23 is set to a low potential between time T04 and time T11. Accordingly, the transistors 16 [1] to 16 [n] are turned off.
- the potential of the wiring 23 is set to a high potential, and the potential of the wiring 26 is set to a potential V′RP . Accordingly, the transistors 16 [1] to 16 [n] are turned on, and the potentials of the wirings 42 [1] to 42 [n] are the potential V′RP . Further, the potential of the wiring 23 is set to a low potential after time T14. Accordingly, the transistors 16 [1] to 16 [n] are turned off.
- the potential of the wiring 26 is set to the potential V RP before time T03 and from time T04 to time T13, and the potential of the wiring 26 is set to potential V ′ RP after time T14.
- the potential of the wiring 26 in the period can be an arbitrary potential.
- FIG. 3A can be referred to by replacing the value of the potential V RP with a value higher than the potential V SDMAX .
- the value of the potential V ′ RP is set to the potential.
- FIG. 3B can be referred to by replacing with a value lower than V SDMIN .
- the potential of the wiring 42 [j] is set to the potential V S2 [i, j] between the time T01 and the time T02, and the wiring between the time T03 and the time T04 is used.
- the potential of 42 [j] was set as the potential VRP .
- the potential of the wiring 42 [j] is set to the potential V ′ S2 [i, j] from time T11 to time T12, and the potential of the wiring 42 [j] is set to the potential V ′ from time T13 to time T14.
- RP a potential of the present invention is not limited to this. For example, as in the case shown in FIG.
- the potential of the wiring 42 [j] during the period from the time T01 to the time T02 and the potential V RP, the potential of the wiring 42 [j] during the period from the time T03 to time T04 The potential V S2 [i, j] may be used. Further, the potential of the wiring 42 [j] during the period from the time T11 to time T12 'and RP, the wiring 42 potential the potential of the [j] V during the period from the time T13 to time T14' potential V S2 [i, j ] May be used.
- An example of an operation method of the pixel 11 [i, j] included in the display device 50 in the above case is illustrated in FIG.
- the potential of the wiring 23 is set to a high potential, the potential of the wiring 26 to a potential V RP. Further, the potential of the wiring 23 is set to a low potential between time T02 and time T03. Further, between time T11 and time T12, the potential of the wiring 23 is set to a high potential, and the potential of the wiring 26 is set to a potential V′RP . Further, the potential of the wiring 23 is set to a low potential between time T12 and time T13.
- the potential of the wiring 26 is set to the potential V RP before time T01 and from time T02 to time T11, and the potential of the wiring 26 is set to potential V ′ RP after time T12.
- the potential of the wiring 26 in the period can be an arbitrary potential.
- the values of the potential V S1 [i, j], the potential V S2 [i, j], the potential V RP , and the potential V DE [i, j] 5A can be referred to by replacing the value of the potential V RP with a value lower than the potential V SDMIN .
- the value of the potential V ′ RP is set to the potential.
- FIG. 5B can be referred to by replacing the value with a value higher than VSDMAX .
- the potential V RP and the potential V ′ RP are higher than the potential V SDMAX that is the maximum value of the potential that can be generated by the source driver circuit 15 or the minimum value of the potential that can be generated by the source driver circuit 15.
- the potential can be lower than a certain potential V SDMIN . Therefore, a voltage higher than the voltage that can be applied to the display element 106 included in the display device 10 can be applied to the display element 106 included in the display device 50. Note that when the image displayed using the pixel 11 is an image with the lowest gradation, the voltage applied to the display element 106 included in the pixel 11 is equal to or lower than the threshold voltage of the display element 106.
- the threshold voltage of the display element 106 indicates a voltage applied to the display element 106 when, for example, the visible light transmittance of the display element 106 has a specific value.
- the potential V RP and the potential V ′ RP can be supplied to the pixels 11 in the surface order.
- FIG. 9 is a block diagram illustrating a configuration example of the display device 60, which is a modification of the display device 50.
- the pixel 11 [1, j], the pixel 11 [1, j + 1], the pixel 11 [1, j + 2], the pixel 11 [1, j + 3], and the pixel 11 [ m, j], pixel 11 [m, j + 1], pixel 11 [m, j + 2], and pixel 11 [m, j + 3] are illustrated.
- the gate driver circuit 14 is not shown, as in FIG.
- the display device 60 is different from the display device 50 in that the transistor 16 is replaced with the transistor 16a or the transistor 16b and the wiring 42 is replaced with the wiring 42a or the wiring 42b.
- the display device 60 is different from the display device 50 in that the display device 60 does not have the wiring 26 but has the wiring 26a and the wiring 26b.
- the number of transistors 16a provided in the display device 60 and the number of transistors 16b can be made equal.
- the display device 60 can be configured to have, for example, n / 2 transistors 16a and n / 2 transistors 16b.
- the number of wirings 42a can be made equal to the number of transistors 16a
- the number of wirings 42b can be made equal to the number of transistors 16b. That is, the display device 60 can be configured to have, for example, n / 2 wirings 42a and n / 2 wirings 42b.
- the transistor 16a and the transistor 16b a transistor similar to the transistor 16 can be used, and may not be a transistor as long as it has a function as a switch.
- the wiring 42 a and the wiring 42 b function as data lines like the wiring 42
- the wiring 26 a and the wiring 26 b function as power supply lines like the wiring 26.
- the pixels 11 [1, j] to 11 [m, j] are electrically connected to one wiring 42a, and the pixels 11 [1, j + 1] to 11 [m, j + 1] are one.
- the pixel 11 [1, j + 2] to pixel 11 [m, j + 2] are electrically connected to one wiring 42a, and the pixel 11 [1, j + 3] to pixel 11 [m].
- J + 3] is electrically connected to one wiring 42b. That is, the wiring 42 a is electrically connected to, for example, one of the odd-numbered pixels 11 or the even-numbered pixels 11, and the wiring 42 b is electrically connected to the other of the odd-numbered pixels 11 or the even-numbered pixels 11. ing.
- One of the source and the drain of the transistor 16a is electrically connected to the wiring 42a.
- One of a source and a drain of the transistor 16b is electrically connected to the wiring 42b.
- the other of the source and the drain of the transistor 16a is electrically connected to the wiring 26a.
- the other of the source and the drain of the transistor 16b is electrically connected to the wiring 26b.
- the gate of the transistor 16 a and the gate of the transistor 16 b are electrically connected to the wiring 23.
- the wiring 42a electrically connected to the pixels 11 [1, j] to 11 [m, j] is denoted as a wiring 42a [j].
- the wiring 42b electrically connected to the pixels 11 [1, j + 1] to 11 [m, j + 1] is denoted as a wiring 42b [j + 1].
- a transistor electrically connected to the wiring 42a [j] is denoted as a transistor 16a [j]
- a transistor electrically connected to the wiring 42b [j + 1] is denoted as a transistor 16b [j + 1]. Show.
- the potential of the wiring 26a and the potential of the wiring 26b can be the potential V RP or the potential V ′ RP .
- the potential of the wiring 26a potential V' the potential of the wiring 26b potential V when a RP potential the potential of the wiring 26b V RP .
- the potential V RP and the potential V ′ RP can be generated by a power supply circuit.
- FIG. 10 is a timing chart illustrating an example of an operation method of the pixel 11 [i, j] and the pixel 11 [i, j + 1] included in the display device 60.
- the transistors 16a and 16b are n-channel transistors, even if the transistors 16a and 16b are p-channel transistors or the like by appropriately inverting the magnitude relationship of potentials, the following description will be given. Can be applied.
- the potentials of the wiring 21 [i], the wiring 22 [i], the wiring 23, the wiring 41 [j], the node NM [i, j], and the node NA [i, j] are This is the same as the operation method shown in FIG.
- the potential of the wiring 26a is the same as the potential of the wiring 26 illustrated in FIG. 7
- the potential of the wiring 42a [j] is the same as the potential of the wiring 42 [j] illustrated in FIG. It is the same.
- the potential of the wiring 26b is a potential V RP 'in RP
- the potential V' potential V is that it replaces each RP to the potential V RP, it differs from the potential of the wiring 26a.
- the potential of the wiring 41 [j + 1] is set such that the potential V S1 [i, j] is the potential V ′ S1 [i, j + 1] and the potential V ′ S1 [i, j] is the potential V S1 [i, j + 1].
- Each of the points is different from the potential of the wiring 41 [j].
- the potential of the wiring 42b [j + 1] is set such that the potential V S2 [i, j] is the potential V ′ S2 [i, j + 1], the potential V RP is the potential V ′ RP , and the potential V ′ S2 [i, j] is Is different from the potential of the wiring 42 a [j] in that the potential V S2 [i, j + 1] is replaced with the potential V ′ RP and the potential V RP is replaced with the potential V RP .
- the potential of the node NM [i, j + 1] is such that the potential V S1 [i, j] is changed to the potential V ′ S1 [i, j + 1], and the potential V DE [i, j] is changed to the potential V ′ DE [i, j + 1]. ], The potential V ′ S1 [i, j] is replaced with the potential V S1 [i, j + 1] and the potential V ′ DE [i, j] is replaced with the potential V DE [i, j + 1]. Different from the potential of NM [i, j].
- the potential of the node NA [i, j + 1] is such that the potential V S2 [i, j] is changed to the potential V ′ S2 [i, j + 1], the potential V RP is changed to the potential V ′ RP , and the potential V ′ S2 [i, j j] is replaced with the potential V S2 [i, j + 1], and the potential V ′ RP is replaced with the potential V RP , which is different from the potential of the node NA [i, j].
- the value of the potential V DE [i, j], which is the potential of the node NM [i, j], from time T03 to time T04 can be equal to or higher than the potential V COM.
- the value of the potential V ′ DE [i, j + 1], which is the potential of NM [i, j + 1], can be equal to or lower than the potential V COM .
- the value of the potential V ′ DE [i, j], which is the potential of the node NM [i, j], from time T13 to time T14 can be equal to or lower than the potential V COM , and the node NM [i, j + 1] ],
- the value of the potential V DE [i, j + 1] can be equal to or higher than the potential V COM .
- the display device 60 can perform frame inversion driving by the column line inversion driving method, the occurrence of flicker can be suppressed and a high-quality image can be displayed. Even when the source driver circuit 15 generates the potential V RP and the potential V ′ RP as in the display device 10, the driving can be performed by the column line inversion driving method as in the display device 60.
- the above is an example of the operation method of the pixel 11 [i, j] and the pixel 11 [i, j + 1] provided in the display device 60.
- the display device 60 can supply the potential V RP and the potential V ′ RP to the pixels 11 in the order of frames, like the display device 50 and the like.
- FIG. 3A can be referred to by replacing the potential V RP with a value higher than the potential V SDMAX .
- the potential V ′ S1 [i, j] the potential V ′ S1 [i, j + 1] the potential V ′ S2 [i, j] the potential V ′ S2 [i, j + 1], the potential V ′ RP , and the potential V ′.
- FIG. 3B can be referred to by replacing the potential V ′ RP with a value higher than the potential V SDMIN .
- the potentials of the wiring 21 [i], the wiring 22 [i], the wiring 23, the wiring 41 [j], the node NM [i, j], and the node NA [i, j] are The operation method shown in FIG. 8 may be the same.
- the potential of the wiring 26a may be the same as the potential of the wiring 26 illustrated in FIG. 8, and the potential of the wiring 42a [j] is the potential of the wiring 42 [j] illustrated in FIG. The same may be applied.
- FIGS. 5A and 5B can be referred to for each potential supplied to the pixel 11.
- the structure of the pixel 11 is not limited to the structure illustrated in FIG.
- FIG. 11A is a diagram illustrating a configuration example of the pixel 11 which is different from that in FIG.
- the display element 106 can be a light-emitting element.
- the light-emitting element an organic EL element, an inorganic EL element, an LED (Light Emitting Diode) element, or the like can be used.
- the transistor 103 is provided in the pixel 11 having the structure illustrated in FIG. 11A. Further, the capacitor 105 is not provided, and the capacitor 107 is provided.
- One of a source and a drain of the transistor 101 is electrically connected to one electrode of the capacitor 104.
- One electrode of the capacitor 104 is electrically connected to the gate of the transistor 103.
- a gate of the transistor 103 is electrically connected to one electrode of the capacitor 107.
- the other electrode of the capacitor 107 is electrically connected to one electrode of the display element 106.
- One electrode of the display element 106 is electrically connected to one of a source and a drain of the transistor 103.
- the other of the source and the drain of the transistor 103 is electrically connected to the common wiring 34.
- a constant potential can be supplied to the common wiring 34.
- a potential higher than the potential VCOM can be supplied.
- a node where one of the source and the drain of the transistor 101, the gate of the transistor 103, the one electrode of the capacitor 104, and the one electrode of the capacitor 107 are electrically connected is referred to as a node NM.
- a high voltage can be applied to the display element 106. Therefore, when the pixel 11 has the structure illustrated in FIG. 11A, a large current can flow through the display element 106 which is a light-emitting element. Therefore, a high-luminance image can be displayed on the display device of one embodiment of the present invention.
- FIGS. 11B and 11C are diagrams illustrating a configuration example of the pixel 11.
- a back gate is provided for the transistor 101 and the transistor 102 included in the pixel 11 having the structure illustrated in FIG. 1B.
- FIG. 11C the structure illustrated in FIG. A back gate is provided for the transistor 101, the transistor 102, and the transistor 103 included in the pixel 11.
- the back gate is electrically connected to the front gate and has an effect of increasing the on-current.
- the back gate may be supplied with a constant potential different from that of the front gate. With this structure, the threshold voltage of the transistor can be controlled.
- FIGS. 11B and 11C illustrate a structure in which all transistors have a back gate, but a transistor without a back gate may be included.
- This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
- FIG. 12A is a cross-sectional view of a transmissive liquid crystal display device which is an example of the display device of one embodiment of the present invention.
- a liquid crystal display device illustrated in FIG. 12A includes a substrate 131, a transistor 101, a transistor 102, an insulating layer 215, a conductive layer 46, an insulating layer 44, a pixel electrode 121, an insulating layer 45, a common electrode 123, a liquid crystal layer 122, and A substrate 132 is included.
- the transistors 101 and 102 are located on the substrate 131.
- the insulating layer 215 is located over the transistor 101 and the transistor 102.
- the conductive layer 46 is located on the insulating layer 215.
- the insulating layer 44 is located over the transistor 101, the transistor 102, the insulating layer 215, and the conductive layer 46.
- the pixel electrode 121 is located on the insulating layer 44.
- the insulating layer 45 is located on the pixel electrode 121.
- the common electrode 123 is located on the insulating layer 45.
- the liquid crystal layer 122 is located on the common electrode 123.
- the common electrode 123 has a region overlapping with the conductive layer 46 with the pixel electrode 121 interposed therebetween.
- the pixel electrode 121 is electrically connected to the source or drain of the transistor 101.
- the conductive layer 46 is electrically connected to the source or drain of the transistor 102.
- the conductive layer 46, the pixel electrode 121, and the common electrode 123 each
- the pixel electrode 121 and the common electrode 123 are stacked with the insulating layer 45 interposed therebetween, and operate in an FFS (Fringe Field Switching) mode.
- the pixel electrode 121, the liquid crystal layer 122, and the common electrode 123 can function as the display element 106.
- the pixel electrode 121, the insulating layer 45, and the common electrode 123 can function as one capacitor 105.
- the conductive layer 46, the insulating layer 44, and the pixel electrode 121 can function as one capacitor 104.
- the liquid crystal display device of this embodiment includes two capacitors in a pixel.
- Each of the two capacitor elements is formed of a material that transmits visible light, and has a region overlapping each other.
- the pixel can have a high aperture ratio and further have a plurality of storage capacitors.
- the liquid crystal display device By increasing the aperture ratio of the transmissive liquid crystal display device (also referred to as the aperture ratio of a pixel), the liquid crystal display device can be made high definition. Moreover, the light extraction efficiency can be increased by increasing the aperture ratio. Thereby, the power consumption of a liquid crystal display device can be reduced.
- the capacity of the capacitor 104 is preferably larger than the capacity of the capacitor 105.
- the area of the region where the pixel electrode 121 and the conductive layer 46 overlap is preferably larger than the area of the region where the pixel electrode 121 and the common electrode 123 overlap.
- the thickness T1 of the insulating layer 44 located between the conductive layer 46 and the pixel electrode 121 is preferably thinner than the thickness T2 of the insulating layer 45 located between the pixel electrode 121 and the common electrode 123. .
- FIG. 12B illustrates an example in which the touch sensor TC is mounted on the display device illustrated in FIG.
- a detection element also referred to as a sensor element
- Various sensors that can detect the proximity or contact of an object to be detected, such as a finger or a stylus, can be applied as the detection element.
- a sensor method for example, various methods such as a capacitance method, a resistance film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure-sensitive method can be used.
- Examples of the electrostatic capacity method include a surface electrostatic capacity method and a projection electrostatic capacity method.
- examples of the projected capacitance method include a self-capacitance method and a mutual capacitance method. The mutual capacitance method is preferable because simultaneous multipoint detection is possible.
- the touch panel of one embodiment of the present invention includes a structure in which a separately manufactured display device and a detection element are bonded, a structure in which an electrode or the like that forms the detection element is provided on one or both of the substrate that supports the display element and the counter substrate, and the like Various configurations can be applied.
- FIG. 13A is a top view of a stacked structure from the gate 221a and the gate 221b to the common electrode 123a as viewed from the common electrode 123a side.
- 13B is a top view in which the common electrode 123a is removed from the stacked structure in FIG. 13A
- FIG. 13C is the common electrode 123a and the pixel electrode 121 in the stacked structure in FIG. FIG.
- the pixel has a connection portion 73 and a connection portion 74.
- the pixel electrode 121 is electrically connected to the transistor 101.
- the conductive layer 222a functioning as the source or drain of the transistor 101 is in contact with the conductive layer 46b, and the conductive layer 46b is in contact with the pixel electrode 121.
- the conductive layer 46 a is electrically connected to the transistor 102.
- the conductive layer 46 a is in contact with the conductive layer 222 c functioning as the source or drain of the transistor 102.
- FIG. 14 is a cross-sectional view of the display device. Note that the cross-sectional structure of the pixel corresponds to a cross-sectional view taken along dashed-dotted line B1-B2 in FIG.
- the backlight unit 30 is provided with a light source 39.
- the backlight unit 30 may include a light source 39 that emits red light, a light source 39 that emits green light, and a light source 39 that emits blue light.
- the light emitting device 39 that emits red light, the light source 39 that emits green light, and the light source 39 that emits blue light are sequentially emitted to operate the display device of one embodiment of the present invention in a field sequential manner. Can be made.
- the display device of one embodiment of the present invention is operated in a field sequential method, it is not necessary to provide a colored layer (color filter) as illustrated in FIG. That is, there is no light loss due to light absorption in the colored layer.
- light transmittance in the display device of one embodiment of the present invention can be improved. Further, even when the light emission intensity of the light source 39 is low, a high-luminance image can be displayed on the display device of one embodiment of the present invention, so that power consumption of the display device of one embodiment of the present invention can be reduced. it can. Note that in the case where the red light source 39, the green light source 39, and the blue light source 39 are caused to emit light simultaneously, the display device of one embodiment of the present invention can perform white display.
- the transistor 101 and the transistor 102 are located over the substrate 131.
- the transistor 101 includes a gate 221a, a gate insulating layer 211, a semiconductor layer 231a, a conductive layer 222a, a conductive layer 222b, an insulating layer 212, an insulating layer 213, a gate insulating layer 225a, and a gate 223a.
- the transistor 102 includes a gate 221b, a gate insulating layer 211, a semiconductor layer 231b, a conductive layer 222c, a conductive layer 222d, an insulating layer 212, an insulating layer 213, a gate insulating layer 225b, and a gate 223b.
- a transistor 101 and a transistor 102 illustrated in FIGS. 14A and 14B have gates above and below a channel.
- the two gates are preferably electrically connected.
- a transistor in which two gates are electrically connected can have higher field-effect mobility than another transistor, and can increase on-state current.
- the area occupied by the circuit portion can be reduced.
- signal delay in each wiring can be reduced and display unevenness can be suppressed even if the number of wirings is increased by increasing the size or definition of the display device. Is possible.
- the display device can be narrowed.
- a highly reliable transistor can be realized.
- the semiconductor layer 231 includes a pair of low resistance regions 231n and a channel formation region 231i sandwiched between the pair of low resistance regions 231n.
- the channel formation region 231 i overlaps with the gate 221 through the gate insulating layer 211 and overlaps with the gate 223 through the gate insulating layer 225.
- the semiconductor layer 231 indicates one or both of the semiconductor layer 231a and the semiconductor layer 231b.
- the gate 221 represents one or both of the gate 221a and the gate 221b
- the gate 223 represents one or both of the gate 223a and the gate 223b.
- the gate insulating layer 225 indicates one or both of the gate insulating layer 225a and the gate insulating layer 225b.
- the gate insulating layer 211 and the gate insulating layer 225 which are in contact with the channel formation region 231i are preferably oxide insulating layers. Note that in the case where the gate insulating layer 211 or the gate insulating layer 225 has a stacked structure, it is preferable that at least a layer in contact with the channel formation region 231i be an oxide insulating layer. Accordingly, generation of oxygen vacancies in the channel formation region 231i can be suppressed, and the reliability of the transistor can be improved.
- One or both of the insulating layer 213 and the insulating layer 214 is preferably a nitride insulating layer. Thus, impurities can be prevented from entering the semiconductor layer 231 and the reliability of the transistor can be increased.
- the insulating layer 215 preferably has a planarization function, and is preferably an organic insulating layer, for example. Note that one or both of the insulating layer 214 and the insulating layer 215 are not necessarily formed.
- the low resistance region 231n has a lower resistivity than the channel formation region 231i.
- the low resistance region 231n is a region in contact with the insulating layer 212 in the semiconductor layer 231.
- the insulating layer 212 preferably contains nitrogen or hydrogen. Thereby, nitrogen or hydrogen in the insulating layer 212 enters the low resistance region 231n, and the carrier concentration of the low resistance region 231n can be increased.
- the low resistance region 231n may be formed by adding an impurity using the gate 223 as a mask. Examples of the impurity include hydrogen, helium, neon, argon, fluorine, nitrogen, phosphorus, arsenic, antimony, boron, and aluminum.
- the impurity is added by an ion implantation method or an ion doping method. Can do.
- the low resistance region 231n may be formed by adding indium or the like which is one of the constituent elements of the semiconductor layer 231. By adding indium, the concentration of indium may be higher in the low resistance region 231n than in the channel formation region 231i.
- a first layer is formed so as to be in contact with part of the semiconductor layer 231, and heat treatment is performed, so that the resistance of the region is reduced.
- a resistance region 231n can be formed.
- a film containing at least one of metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium can be used.
- metal elements such as aluminum, titanium, tantalum, and tungsten is preferably included.
- a nitride containing at least one of these metal elements or an oxide containing at least one of these metal elements can be preferably used.
- a metal film such as a tungsten film or a titanium film, a nitride film such as an aluminum titanium nitride film, a titanium nitride film, or an aluminum nitride film, or an oxide film such as an aluminum titanium oxide film can be preferably used.
- the thickness of the first layer can be, for example, 0.5 nm to 20 nm, preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 10 nm, and still more preferably 1 nm to 6 nm. Typically, it can be about 5 nm or about 2 nm. Even when the first layer is thin like this, the resistance of the semiconductor layer 231 can be sufficiently reduced.
- the low resistance region 231n has a higher carrier density than the channel formation region 231i.
- the low-resistance region 231n can be a region containing more hydrogen than the channel formation region 231i or a region containing more oxygen vacancies than the channel formation region 231i.
- the low resistance region 231n can be a very low resistance region.
- the low resistance region 231n formed in this way has a feature that it is difficult to increase the resistance in a subsequent process. For example, even if a heat treatment in an atmosphere containing oxygen, a film formation treatment in an atmosphere containing oxygen, or the like is performed, the conductivity of the low resistance region 231n is not impaired, and thus the electrical characteristics are good. In addition, a highly reliable transistor can be realized.
- the first layer after the heat treatment has conductivity
- the first layer can function as a protective insulating film by remaining it.
- the conductive layer 46 b is located on the insulating layer 215, the insulating layer 44 is located on the conductive layer 46 b, and the pixel electrode 121 is located on the insulating layer 44.
- the pixel electrode 121 is electrically connected to the conductive layer 222a. Specifically, the conductive layer 222a is connected to the conductive layer 46b, and the conductive layer 46b is connected to the pixel electrode 121.
- a conductive layer 46 a is located on the insulating layer 215.
- the conductive layer 46a is electrically connected to the conductive layer 222c. Specifically, the conductive layer 46 a is in contact with the conductive layer 222 c through an opening provided in the insulating layer 214 and the insulating layer 215.
- the substrate 131 and the substrate 132 are bonded to each other with an adhesive layer 141.
- the FPC 172 is electrically connected to the conductive layer 222e. Specifically, the FPC 172 is in contact with the connection body 242, the connection body 242 is in contact with the conductive layer 123b, and the conductive layer 123b is in contact with the conductive layer 222e.
- the conductive layer 123b is formed on the insulating layer 45, and the conductive layer 222e is formed on the insulating layer 214.
- the conductive layer 123b can be formed using the same process and the same material as the common electrode 123a.
- the conductive layer 222e can be formed using the same process and the same material as the conductive layers 222a to 222d.
- the pixel electrode 121, the insulating layer 45, and the common electrode 123a can function as one capacitor 105.
- the conductive layer 46 a, the insulating layer 44, and the pixel electrode 121 can function as one capacitor 104.
- the display device of one embodiment of the present invention includes, for example, two capacitor elements in one pixel. Accordingly, the storage capacity of the pixel can be increased.
- Each of the two capacitor elements is formed of a material that transmits visible light, and has a region overlapping each other. Thereby, the pixel can achieve both a high aperture ratio and a large storage capacity.
- the capacity of the capacitor 104 is preferably larger than the capacity of the capacitor 105. Therefore, the area of the region where the pixel electrode 121 and the conductive layer 46a overlap is preferably larger than the area of the region where the pixel electrode 121 and the common electrode 123a overlap.
- the thickness of the insulating layer 44 located between the conductive layer 46a and the pixel electrode 121 is preferably thinner than the thickness of the insulating layer 45 located between the pixel electrode 121 and the common electrode 123a.
- FIG. 14 illustrates an example in which both the transistor 101 and the transistor 102 have a back gate (gate 223); however, one or both of the transistor 101 and the transistor 102 do not have to have a back gate.
- FIG. 14 illustrates an example in which the gate insulating layer 225 is formed only over the channel formation region 231i and does not overlap the low resistance region 231n. However, the gate insulating layer 225 overlaps at least part of the low resistance region 231n. May be.
- FIG. 15 illustrates an example in which the gate insulating layer 225 is formed in contact with the low-resistance region 231n and the gate insulating layer 211.
- the gate insulating layer 225 illustrated in FIGS. 15A and 15B has advantages that a step of processing the gate insulating layer 225 using the gate 223 as a mask can be reduced, and a step difference in a formation surface of the insulating layer 214 can be reduced.
- the structures of the transistors 101 and 102 are different from those in FIGS. 14 and 15.
- a transistor 101 illustrated in FIG. 16 includes a gate 221a, a gate insulating layer 211, a semiconductor layer 231a, a conductive layer 222a, a conductive layer 222b, an insulating layer 217, an insulating layer 218, an insulating layer 215, and a gate 223a.
- the transistor 102 includes a gate 221b, a gate insulating layer 211, a semiconductor layer 231b, a conductive layer 222c, a conductive layer 222d, an insulating layer 217, an insulating layer 218, an insulating layer 215, and a gate 223b.
- One of the conductive layer 222a and the conductive layer 222b functions as a source, and the other functions as a drain.
- the insulating layer 217, the insulating layer 218, and the insulating layer 215 function as gate insulating layers.
- the gate insulating layer 211 and the insulating layer 217 in contact with the semiconductor layer 231 are preferably oxide insulating layers. Note that in the case where the gate insulating layer 211 or the insulating layer 217 has a stacked structure, at least a layer in contact with the semiconductor layer 231 is preferably an oxide insulating layer. Accordingly, generation of oxygen vacancies in the semiconductor layer 231 can be suppressed, and the reliability of the transistor can be improved.
- the insulating layer 218 is preferably a nitride insulating layer. Thus, impurities can be prevented from entering the semiconductor layer 231 and the reliability of the transistor can be increased.
- the insulating layer 215 preferably has a planarization function, and is preferably an organic insulating layer, for example. Note that the insulating layer 215 is not necessarily formed, and the conductive layer 46 a may be formed in contact with the insulating layer 218.
- the conductive layer 46 b is located on the insulating layer 215, the insulating layer 44 is located on the conductive layer 46 b, and the pixel electrode 121 is located on the insulating layer 44.
- the pixel electrode 121 is electrically connected to the conductive layer 222a. Specifically, the conductive layer 222a is connected to the conductive layer 46b, and the conductive layer 46b is connected to the pixel electrode 121.
- a conductive layer 46 a is located on the insulating layer 215.
- the insulating layer 44 and the insulating layer 45 are located on the conductive layer 46a.
- a common electrode 123 a is located on the insulating layer 45.
- the display device shown in FIG. 17 is different from FIGS. 14 to 16 in that a colored layer 331 is provided.
- the colored layer 331 is a colored layer that transmits light in a specific wavelength region such as red light, green light, or blue light.
- Examples of the material that can be used for the coloring layer 331 include a metal material, a resin material, and a resin material containing a pigment or a dye.
- the light source 39 can be a light source that emits white light.
- the display device illustrated in FIG. 17 can display a color image without displaying, for example, a red image, a green image, and a blue image in a time-sharing manner. Therefore, even when the operating frequency of the display device of one embodiment of the present invention is low, generation of a color break or the like does not occur, so that a high-quality image can be displayed. Further, since the light source 39 that emits light does not have to be switched, the operation of the display device of one embodiment of the present invention can be simplified.
- the material of the substrate included in the display device there is no particular limitation on the material of the substrate included in the display device, and various substrates can be used.
- a glass substrate, a quartz substrate, a sapphire substrate, a semiconductor substrate, a ceramic substrate, a metal substrate, a plastic substrate, or the like can be used.
- the display device can be reduced in weight and thickness. Furthermore, a flexible display device can be realized by using a flexible substrate.
- liquid crystal material there are a positive liquid crystal material having a positive dielectric anisotropy ( ⁇ ) and a negative liquid crystal material having a negative dielectric constant.
- ⁇ positive dielectric anisotropy
- negative liquid crystal material having a negative dielectric constant.
- either material can be used, and an optimum liquid crystal material can be used depending on a mode to be applied and a design.
- liquid crystal elements to which various modes are applied can be used.
- FFS mode for example, an IPS mode, a TN mode, an ASM (Axial Symmetrically aligned Micro-cell) mode, an OCB (Optically Compensated BirefringenceCriff mode), and an FLC (FerroelectricLiquidFrequencyLiquidCrCF)
- ECB Electrode Controlled Birefringence
- the liquid crystal element is an element that controls transmission or non-transmission of light by an optical modulation action of liquid crystal.
- the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field).
- a thermotropic liquid crystal a low molecular liquid crystal
- a polymer liquid crystal a polymer dispersed liquid crystal
- ferroelectric liquid crystal an antiferroelectric liquid crystal, or the like
- These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.
- liquid crystal exhibiting a blue phase may be used.
- the blue phase is one of the liquid crystal phases.
- a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range.
- a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and exhibits optical isotropy.
- a liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent does not require alignment treatment and has a small viewing angle dependency.
- rubbing treatment is unnecessary, electrostatic breakdown caused by the rubbing treatment can be prevented, and defects or breakage of the display panel during the manufacturing process can be reduced.
- the display device in this embodiment is a transmissive liquid crystal display device
- a conductive material that transmits visible light is used for both of the pair of electrodes (the pixel electrode 121 and the common electrode 123a).
- the conductive layer 46b is also formed using a conductive material that transmits visible light, so that a reduction in the aperture ratio of the pixel can be suppressed even when the capacitor 104 is provided.
- a silicon nitride film is suitable for the insulating layer 44 and the insulating layer 45 that function as a dielectric of the capacitor.
- a material containing one or more selected from indium (In), zinc (Zn), and tin (Sn) may be used.
- indium oxide, indium tin oxide (ITO), indium zinc oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, and titanium oxide are included. Examples thereof include indium tin oxide, indium tin oxide containing silicon oxide (ITSO), zinc oxide, and zinc oxide containing gallium.
- a film containing graphene can also be used. The film containing graphene can be formed by, for example, reducing a film containing graphene oxide.
- the conductive film that transmits visible light can be formed using an oxide semiconductor (hereinafter also referred to as an oxide conductive layer).
- the oxide conductive layer preferably includes, for example, indium, and further includes an In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). preferable.
- An oxide semiconductor is a semiconductor material whose resistance can be controlled by at least one of oxygen vacancies in the film and impurity concentrations of hydrogen, water, and the like in the film. Therefore, the resistivity of the oxide conductive layer is controlled by selecting a treatment in which at least one of oxygen deficiency and impurity concentration is increased or a treatment in which at least one of oxygen deficiency and impurity concentration is reduced in the oxide semiconductor layer. be able to.
- an oxide conductive layer formed using an oxide semiconductor in this manner is an oxide semiconductor layer with high carrier density and low resistance, an oxide semiconductor layer with conductivity, or an oxide semiconductor with high conductivity. It can also be called a layer.
- the transistor included in the display device of this embodiment may have a top-gate structure or a bottom-gate structure.
- gate electrodes may be provided above and below the channel.
- a semiconductor material used for the transistor is not particularly limited, and examples thereof include an oxide semiconductor, silicon, and germanium.
- crystallinity of a semiconductor material used for the transistor there is no particular limitation on the crystallinity of a semiconductor material used for the transistor, and any of an amorphous semiconductor and a semiconductor having crystallinity (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor partially including a crystal region) is used. May be used. It is preferable to use a crystalline semiconductor because deterioration of transistor characteristics can be suppressed.
- a Group 14 element, a compound semiconductor, or an oxide semiconductor can be used for the semiconductor layer.
- a semiconductor containing silicon, a semiconductor containing gallium arsenide, an oxide semiconductor containing indium, or the like can be used for the semiconductor layer.
- An oxide semiconductor is preferably used as a semiconductor in which a channel of the transistor is formed.
- an oxide semiconductor having a larger band gap than silicon is preferably used. It is preferable to use a semiconductor material with a wider band gap and lower carrier density than silicon because current in an off state of the transistor can be reduced.
- the charge accumulated in the capacitor through the transistor can be held for a long time.
- the driving circuit can be stopped while maintaining the gradation of the displayed image. As a result, a display device with extremely reduced power consumption can be realized.
- the transistor preferably includes an oxide semiconductor layer that is highly purified and suppresses formation of oxygen vacancies.
- the current value (off-current value) in the off state of the transistor can be reduced. Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.
- a transistor including an oxide semiconductor can be driven at high speed because a relatively high field-effect mobility can be obtained.
- the transistor in the display portion and the transistor in the driver circuit portion can be formed over the same substrate. That is, it is not necessary to separately use a semiconductor device formed of a silicon wafer or the like as the drive circuit, so that the number of parts of the display device can be reduced.
- a high-quality image can be provided by using a transistor that can be driven at high speed.
- an organic insulating material or an inorganic insulating material can be used as an insulating material that can be used for each insulating layer, overcoat, or the like included in the display device.
- the organic insulating material include acrylic resin, epoxy resin, polyimide resin, polyamide resin, polyimide amide resin, siloxane resin, benzocyclobutene resin, and phenol resin.
- examples thereof include a film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film.
- conductive layers such as various wirings and electrodes of display devices include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten.
- metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten.
- an alloy containing this as a main component can be used as a single layer structure or a stacked structure.
- a two-layer structure in which a titanium film is laminated on an aluminum film a two-layer structure in which a titanium film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a molybdenum film, or an alloy film containing molybdenum and tungsten
- Two-layer structure in which a copper film is laminated a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a titanium film or a titanium nitride film, and an aluminum film or copper layered on the titanium film or titanium nitride film Laminating a film, and further forming a three-layer structure for forming a titanium film or a titanium nitride film thereon, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film stacked on the molybdenum film or the molybdenum nit
- the first and third layers include titanium, titanium nitride, molybdenum, tungsten, an alloy containing molybdenum and tungsten, an alloy containing molybdenum and zirconium, or a film made of molybdenum nitride.
- the second layer it is preferable to form a film made of a low resistance material such as copper, aluminum, gold or silver, or an alloy of copper and manganese.
- ITO indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, ITSO, etc. You may use the electroconductive material which has.
- the oxide conductive layer may be formed by controlling the resistivity of the oxide semiconductor.
- a curable resin such as a thermosetting resin, a photocurable resin, or a two-component mixed curable resin
- a curable resin such as a thermosetting resin, a photocurable resin, or a two-component mixed curable resin
- an acrylic resin, a urethane resin, an epoxy resin, a siloxane resin, or the like can be used.
- connection body 242 for example, an anisotropic conductive film (ACF: Anisotropic Conductive Film), an anisotropic conductive paste (ACP: Anisotropic Conductive Paste), or the like can be used.
- ACF Anisotropic Conductive Film
- ACP Anisotropic Conductive Paste
- the backlight unit 30 may be a direct type backlight, an edge light type backlight, or the like.
- As the light source an LED (Light Emitting Diode), an organic EL (Electroluminescence) element, or the like can be used.
- Thin films (insulating film, semiconductor film, conductive film, etc.) constituting the display device are respectively formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, and pulsed laser deposition (PLD: Pulsed Laser Deposition).
- CVD chemical vapor deposition
- PLD Pulsed Laser Deposition
- Method atomic layer deposition
- ALD Atomic Layer Deposition
- the CVD method include a plasma enhanced chemical vapor deposition (PECVD) method, a thermal chemical vapor deposition (PECVD) method, a thermal CVD method, and the like.
- An example of the thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.
- Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute display devices are spin coat, dip, spray coating, ink jet printing, dispensing, screen printing, offset printing, doctor knife, slit coat, roll coat, curtain, respectively. It can be formed by a method such as coating or knife coating.
- a thin film included in the display device can be processed using a photolithography method or the like.
- an island-shaped thin film may be formed by a film formation method using a shielding mask.
- the thin film may be processed by a nanoimprint method, a sand blast method, a lift-off method, or the like.
- a photolithography method a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is removed. After forming a photosensitive thin film, exposure and development are performed. And a method for processing the thin film into a desired shape.
- Examples of the light used for exposure in the photolithography method include i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), and light obtained by mixing these.
- ultraviolet light, KrF laser light, ArF laser light, or the like can be used.
- exposure may be performed by an immersion exposure technique.
- Examples of light used for exposure include extreme ultraviolet light (EUV: Extreme-violet) and X-rays.
- EUV Extreme-violet
- an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays, or an electron beam because extremely fine processing is possible. Note that a photomask is not necessary when exposure is performed by scanning a beam such as an electron beam.
- etching the thin film For etching the thin film, a dry etching method, a wet etching method, a sand blasting method, or the like can be used.
- Metal oxide A metal oxide functioning as an oxide semiconductor is preferably used for the semiconductor layer of the transistor included in the display device of this embodiment. Below, the metal oxide applicable to a semiconductor layer is demonstrated.
- the metal oxide preferably contains at least indium or zinc.
- indium and zinc are preferably included.
- aluminum, gallium, yttrium, tin, or the like is contained.
- One or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.
- the metal oxide is an In-M-Zn oxide containing indium, an element M, and zinc is considered.
- the element M is aluminum, gallium, yttrium, tin, or the like.
- Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.
- the element M may be a combination of a plurality of the aforementioned elements.
- metal oxides containing nitrogen may be collectively referred to as metal oxides.
- a metal oxide containing nitrogen may be referred to as a metal oxynitride.
- a metal oxide containing nitrogen such as zinc oxynitride (ZnON) may be used for the semiconductor layer.
- An oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor.
- the non-single-crystal oxide semiconductor for example, a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor) OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
- the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain.
- the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.
- Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons.
- the strain may have a lattice arrangement such as a pentagon and a heptagon.
- a clear crystal grain boundary also referred to as a grain boundary
- the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction, the bond distance between atoms changes due to substitution of metal elements, and the like. Because.
- the CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked.
- In layer a layer containing indium and oxygen
- M, Zn elements M, zinc, and oxygen
- indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.
- CAAC-OS is a metal oxide with high crystallinity.
- CAAC-OS impurities and defects oxygen deficiency (V O:. Oxygen vacancy also referred) etc.) with less metal It can be said that it is an oxide. Therefore, the physical properties of the metal oxide including a CAAC-OS are stable. Therefore, a metal oxide including a CAAC-OS is resistant to heat and has high reliability.
- the nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
- the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
- indium-gallium-zinc oxide which is a kind of metal oxide including indium, gallium, and zinc
- IGZO indium-gallium-zinc oxide
- a crystal smaller than a large crystal here, a crystal of several millimeters or a crystal of several centimeters
- it may be structurally stable.
- the a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor.
- the a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.
- Oxide semiconductors have various structures and have different characteristics.
- the oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
- the metal oxide film functioning as a semiconductor layer can be formed using one or both of an inert gas and an oxygen gas.
- an inert gas an oxygen gas
- oxygen gas an oxygen gas
- the flow rate ratio of oxygen (oxygen partial pressure) during the formation of the metal oxide film is preferably 0% or more and 30% or less, and 5% or more and 30% or less. Is more preferably 7% or more and 15% or less.
- the metal oxide preferably has an energy gap of 2 eV or more, more preferably 2.5 eV or more, and further preferably 3 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.
- the metal oxide film can be formed by a sputtering method.
- a PLD method a PECVD method, a thermal CVD method, an ALD method, a vacuum evaporation method, or the like may be used.
- the display device of one embodiment of the present invention since the display device of one embodiment of the present invention has two capacitors that transmit visible light overlapped with a pixel, the pixel can achieve both a high aperture ratio and a large storage capacitor. .
- This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
- the CAC-OS is one structure of a material in which an element included in an oxide semiconductor is unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. Note that in the following, in an oxide semiconductor, one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof.
- the state mixed with is also referred to as mosaic or patch.
- the oxide semiconductor preferably contains at least indium.
- One kind selected from the above or a plurality of kinds may be included.
- a CAC-OS in In-Ga-Zn oxide is an indium oxide (hereinafter referred to as InO).
- X1 (X1 is greater real than 0) and.), or indium zinc oxide (hereinafter, in X2 Zn Y2 O Z2 ( X2, Y2, and Z2 is larger real than 0) and a.) or the like, Gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic InO X1, or in X2 Zn Y2 O Z2 is configured uniformly distributed in the film (hereinafter, cloud Also referred to.) A.
- CAC-OS includes a region GaO X3 is the main component, In X2 Zn Y2 O Z2, or InO X1 there is a region which is a main component, a composite oxide semiconductor having a structure that is mixed.
- the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.
- IGZO is a common name and sometimes refers to one compound of In, Ga, Zn, and O.
- ZnO ZnO
- the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure.
- the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.
- CAC-OS relates to a material structure of an oxide semiconductor.
- CAC-OS refers to a region that is observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn, and O, and nanoparticles that are partially composed mainly of In.
- the region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.
- the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions.
- a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.
- a region GaO X3 is the main component, In X2 Zn Y2 O Z2, or the region InO X1 is the main component, it may clear boundary can not be observed.
- the CAC-OS includes a region observed in a part of a nanoparticle mainly including the metal element and a nano part mainly including In.
- the region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.
- the CAC-OS can be formed by a sputtering method under a condition where the substrate is not intentionally heated, for example.
- a CAC-OS is formed by a sputtering method
- any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas.
- the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible.
- the flow rate ratio of the oxygen gas is 0% or more and less than 30%, preferably 0% or more and 10% or less. .
- the CAC-OS has a feature that a clear peak is not observed when measurement is performed using a ⁇ / 2 ⁇ scan by an out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods.
- XRD X-ray diffraction
- a CAC-OS includes a ring-shaped region having a high luminance (ring region) in an electron beam diffraction pattern obtained by irradiating an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam), and the ring region.
- a probe diameter of 1 nm also referred to as a nanobeam electron beam
- the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
- a region in which GaO X3 is a main component is obtained by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component is unevenly distributed and mixed.
- EDX energy dispersive X-ray spectroscopy
- the CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, in the CAC-OS, a region in which GaO X3 or the like is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component are phase-separated from each other, and each region has a main component. Has a mosaic structure.
- the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component is a region having higher conductivity than a region containing GaO X3 or the like as a main component. That, In X2 Zn Y2 O Z2, or InO X1 is a region which is a main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Accordingly, a region where In X2 Zn Y2 O Z2 or InO X1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility ( ⁇ ) can be realized.
- regions GaO X3, etc. are the main component, In X2 Zn Y2 O Z2, or InO X1 is compared to region which is a main component, has a high area insulation. That is, the region whose main component is GaO X3 or the like is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.
- CAC-OS when CAC-OS is used for a semiconductor element, the insulating property caused by GaO X3 or the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act in a complementary manner.
- An on-current (I on ) and high field effect mobility ( ⁇ ) can be realized.
- CAC-OS is optimal for various semiconductor devices including a display.
- This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
- the electronic device of this embodiment includes the display device of one embodiment of the present invention in the display portion. Thereby, an electronic device can be made inexpensive and the power consumption of the electronic device can be reduced.
- the display portion of the electronic device of this embodiment can display an image having a resolution of, for example, full high vision, 2K, 4K, 8K, 16K, or higher.
- the screen size of the display unit can be 20 inches or more diagonal, 30 inches or more diagonal, 50 inches diagonal, 60 inches diagonal, or 70 inches diagonal.
- Examples of electronic devices that can use the display device of one embodiment of the present invention include a television set, a desktop or notebook personal computer, a monitor for a computer, a digital signage (digital signage), a pachinko machine, and the like.
- a television set a desktop or notebook personal computer
- a monitor for a computer a digital signage (digital signage), a pachinko machine, and the like.
- electronic devices having a relatively large screen such as a large game machine such as a game machine, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, an audio reproduction device, and the like can be given. .
- the display device of one embodiment of the present invention can be favorably used for a portable electronic device, a wearable electronic device (wearable device), a VR (Virtual Reality) device, an AR (Augmented Reality) device, and the like. .
- the electronic device of one embodiment of the present invention may include a secondary battery, and it is preferable that the secondary battery can be charged using non-contact power transmission.
- Secondary batteries include, for example, lithium ion secondary batteries such as lithium polymer batteries (lithium ion polymer batteries) using gel electrolyte, nickel metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead storage batteries, air secondary batteries, nickel A zinc battery, a silver zinc battery, etc. are mentioned.
- lithium ion secondary batteries such as lithium polymer batteries (lithium ion polymer batteries) using gel electrolyte, nickel metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead storage batteries, air secondary batteries, nickel A zinc battery, a silver zinc battery, etc. are mentioned.
- the electronic device of one embodiment of the present invention may include an antenna. By receiving a signal with an antenna, video, information, and the like can be displayed on the display unit.
- the antenna may be used for non-contact power transmission.
- the electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared).
- the electronic device of one embodiment of the present invention can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on a display unit, a touch panel function, a function for displaying a calendar, date or time, a function for executing various software (programs), and wireless communication It can have a function, a function of reading a program or data recorded in a recording medium, and the like.
- an electronic apparatus having a plurality of display units
- a function of displaying a stereoscopic image can be provided.
- an electronic device having an image receiving unit a function for photographing a still image or a moving image, a function for automatically or manually correcting the photographed image, and a function for saving the photographed image in a recording medium (externally or incorporated in the electronic device)
- a function of displaying the photographed image on the display portion can be provided.
- the functions of the electronic device of one embodiment of the present invention are not limited thereto, and the electronic device can have various functions.
- FIG. 18A illustrates a television device 1810.
- a television device 1810 includes a display portion 1811, a housing 1812, a speaker 1813, and the like. Furthermore, an LED lamp, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, and the like can be provided.
- the television device 1810 can be operated by a remote controller 1814.
- broadcast radio waves examples include terrestrial waves and radio waves transmitted from satellites.
- Broadcast radio waves include analog broadcasts, digital broadcasts, etc., and video and audio, or audio-only broadcasts.
- broadcast radio waves transmitted in a specific frequency band in the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz) can be received.
- the transfer rate can be increased and more information can be obtained. Accordingly, an image having a resolution exceeding full high-definition can be displayed on the display unit 1811. For example, an image having a resolution of 4K, 8K, 16K, or higher can be displayed.
- FIG. 18B shows a digital signage 1820 attached to a cylindrical column 1822.
- the digital signage 1820 has a display portion 1821.
- the display portion 1821 As the display portion 1821 is wider, the amount of information that can be provided at a time can be increased. Moreover, the wider the display portion 1821 is, the easier it is to be noticed by humans. For example, the advertising effect of advertisement can be enhanced.
- a touch panel By applying a touch panel to the display portion 1821, not only a still image or a moving image is displayed on the display portion 1821 but also a user can operate intuitively, which is preferable. In addition, when used for the purpose of providing information such as route information or traffic information, usability can be improved by an intuitive operation.
- FIG. 18C illustrates a laptop personal computer 1830.
- the personal computer 1830 includes a display portion 1831, a housing 1832, a touch pad 1833, a connection port 1834, and the like.
- the touch pad 1833 functions as an input unit such as a pointing device or a pen tablet, and can be operated with a finger, a stylus, or the like.
- a display element is incorporated in the touch pad 1833.
- the touch pad 1833 can be used as a keyboard.
- a vibration module may be incorporated in the touch pad 1833 in order to realize tactile sensation by vibration.
- FIG. 19A and 19B show a portable information terminal 800.
- the portable information terminal 800 includes a housing 801, a housing 802, a display portion 803, a display portion 804, a hinge portion 805, and the like.
- the housing 801 and the housing 802 are connected by a hinge portion 805.
- the portable information terminal 800 can open the housing 801 and the housing 802 as illustrated in FIG. 19B from the folded state as illustrated in FIG.
- document information can be displayed on the display portion 803 and the display portion 804, and can be used as an electronic book terminal.
- still images and moving images can be displayed on the display portion 803 and the display portion 804.
- the portable information terminal 800 can be folded when being carried, it is excellent in versatility.
- housing 801 and the housing 802 may include a power button, an operation button, an external connection port, a speaker, a microphone, and the like.
- FIG. 19C illustrates an example of a portable information terminal.
- a portable information terminal 810 illustrated in FIG. 19C includes a housing 811, a display portion 812, operation buttons 813, an external connection port 814, a speaker 815, a microphone 816, a camera 817, and the like.
- the portable information terminal 810 includes a touch sensor in the display unit 812. All operations such as making a call or inputting characters can be performed by touching the display portion 812 with a finger, a stylus, or the like.
- the operation of the operation button 813 can switch the power ON / OFF operation and the type of image displayed on the display unit 812.
- the mail creation screen can be switched to the main menu screen.
- the orientation (portrait or landscape) of the portable information terminal 810 is determined, and the screen display orientation of the display unit 812 is changed. It can be switched automatically.
- the screen display orientation can also be switched by touching the display portion 812, operating the operation buttons 813, or inputting voice using the microphone 816.
- the portable information terminal 810 has one or a plurality of functions selected from, for example, a telephone, a notebook, an information browsing device, or the like. Specifically, it can be used as a smartphone.
- the portable information terminal 810 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, video playback, Internet communication, and games.
- FIG. 19D illustrates an example of a camera.
- the camera 820 includes a housing 821, a display portion 822, operation buttons 823, a shutter button 824, and the like.
- a removable lens 826 is attached to the camera 820.
- the camera 820 is configured such that the lens 826 can be removed from the housing 821 and replaced, but the lens 826 and the housing may be integrated.
- the camera 820 can capture a still image or a moving image by pressing the shutter button 824.
- the display portion 822 has a function as a touch panel and can capture an image by touching the display portion 822.
- the camera 820 can be separately attached with a strobe device, a viewfinder, and the like. Alternatively, these may be incorporated in the housing 821.
- FIG. 19E illustrates an example in which the display device of one embodiment of the present invention is mounted as a vehicle-mounted display.
- the display unit 832 and the display unit 833 can provide various information by displaying navigation information, a speedometer, a tachometer, a travel distance, a fuel gauge, a gear state, an air conditioner setting, and the like.
- the display items and layout can be appropriately changed according to the user's preference.
- an electronic device can be obtained by using the display device of one embodiment of the present invention.
- the application range of the display device is extremely wide and can be applied to electronic devices in all fields.
- This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
- the potential applied to the display element provided in the pixel included in the display device of one embodiment of the present invention was measured.
- the display device 50 was operated under conditions 1 and 2 described below. Under condition 1, the pixel 11 was operated by the method shown at time T01 to time T04 in FIG. Under condition 2, the pixel 11 was operated by the method shown at time T01 to time T04 in FIG.
- Potential V S1 was supplied to the pixel 11 in the condition 1, the potential V S2, and the potential V RP shown in FIG. 20 (A), the potential V S1 was supplied to the pixel 11 in the condition 2, the potential V S2, and the potential V RP As shown in FIG. In both conditions 1 and 2, the pixel 11 was operated with a minimum gradation of 0 and a maximum gradation of 255.
- the display element 106 is a transmissive liquid crystal element, and the rubbing angle is 20 °. Further, the potential V COM of the common wiring 32 and the common wiring 33 is 4.5 V, the capacitance value C 1 of the capacitor 104 is 30 pF, the capacitance C 2 of the capacitor 105 is 3 pF, and the capacitance C LC of the display element 106 is 3 pF. It was.
- the potential V SDMIN that is the minimum potential that can be generated by the source driver circuit 15 is 1 V
- the potential V SDMAX that is the maximum potential that the source driver circuit 15 can generate is 8 V.
- the potential V COM is 4.5V
- the voltage applied to the display element 106 is 3.5V.
- the value of the potential V S1 is 1 V that is the potential V SDMIN in the case of the gradation 0, and 8 V that is the potential V SDMAX in the case of the gradation 255.
- the potential V S2 is a value calculated by Formula 5 shown in Embodiment 1, and is set to 4.5 V that is the potential V COM in the case of the gradation 0 and 8 V that is the potential V SDMAX in the case of the gradation 255. .
- the potential V RP was 0 V regardless of the gradation, and was 4.5 V lower than the potential V COM .
- the value of the potential V S1 is 4.5 V which is the potential V COM in the case of the gradation 0, and 8 V which is the potential V SDMAX in the case of the gradation 255.
- the potential V S2 is a value calculated by the following equation, and is 4.5 V that is the potential V COM in the case of gradation 0, and 1 V that is the potential V SDMIN in the case of gradation 255.
- the potential V RP is set to 4.5 V regardless of the gradation, and is equal to the potential V COM .
- the voltage “V DE ⁇ V COM ” applied to the display element 106 was measured for each of the conditions 1 and 2. Specifically, the backlight was turned on, the luminance of the light emitted from the display element 106 was measured, and the voltage “V DE ⁇ V COM ” was calculated based on the measurement result.
- FIG. 21 shows the measurement result of the voltage “V DE ⁇ V COM ” under the conditions 1 and 2. Further, the voltage “V SDMAX ⁇ V COM ” is indicated.
- condition 1 it was confirmed that a voltage higher than that in condition 2 could be applied to the display element 106.
- the voltage “V DE ⁇ V COM ” in the condition 1 is 8.90 V, and a voltage exceeding twice the voltage “V SDMAX ⁇ V COM ” can be applied to the display element 106 in the condition 1.
- V SDMAX ⁇ V COM twice the voltage “V SDMAX ⁇ V COM ”
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Abstract
Description
本実施の形態では、本発明の一態様である表示装置、及びその動作方法について図面を用いて説明する。
<表示装置の構成例>
本実施の形態では、本発明の一態様の表示装置の構成例について図面を用いて説明する。
図13(A)乃至(C)に、画素の上面図を示す。図13(A)は、ゲート221a及びゲート221bから共通電極123aまでの積層構造を共通電極123a側から見た上面図である。図13(B)は、図13(A)の積層構造から共通電極123aを除いた上面図であり、図13(C)は、図13(A)の積層構造から共通電極123a及び画素電極121を除いた上面図である。
図14に、表示装置の断面図を示す。なお、画素の断面構造については、図13(A)に示す一点鎖線B1−B2間の断面図に相当する。
次に、本実施の形態の表示装置の各構成要素に用いることができる材料等の詳細について、説明を行う。
本実施の形態の表示装置が有するトランジスタの半導体層には、酸化物半導体として機能する金属酸化物を用いることが好ましい。以下では、半導体層に適用可能な金属酸化物について説明する。
本実施の形態では、本発明の一態様で開示されるトランジスタに用いることができるCAC(Cloud−Aligned Composite)−OSの構成について説明する。
本実施の形態では、本発明の一態様の電子機器について図面を用いて説明する。
Claims (11)
- 画素電極及び共通電極を有する表示素子が設けられた画素を有し、前記画素は第1のデータ線、及び第2のデータ線と電気的に接続された表示装置の動作方法であって、
前記第1のデータ線を介した前記画素への第1の電位の供給と、前記第2のデータ線を介した前記画素への第2の電位の供給と、を並行して行った後、前記第2のデータ線を介して前記画素に第3の電位を供給することにより、前記画素に保持された前記第1の電位を前記第4の電位に変化させ、前記第4の電位を前記画素電極に印加し、
前記第2の電位は、前記第1の電位を基に算出される電位であり、
前記第2の電位の値が、前記共通電極に印加される電位以下である場合は、前記第3の電位は、前記共通電極に印加される電位より高く、
前記第2の電位の値が、前記共通電極に印加される前記電位以上である場合は、前記第3の電位は、前記共通電極に印加される前記電位より低い表示装置の動作方法。 - 請求項1において、
前記第3の電位は、前記第1の電位が取り得る最大値以上の電位、又は前記第1の電位が取り得る最小値以下の電位である表示装置の動作方法。 - 請求項1又は2において、
前記表示装置は、ソースドライバ回路を有し、
前記ソースドライバ回路は、前記第1のデータ線と電気的に接続され、
前記ソースドライバ回路は、前記第2のデータ線と電気的に接続され、
前記ソースドライバ回路は、前記第1の電位、及び前記第2の電位を生成する機能を有する表示装置の動作方法。 - 画素電極及び共通電極を有する表示素子が設けられた画素を有し、前記画素は第1のデータ線、及び第2のデータ線と電気的に接続された表示装置の動作方法であって、
前記表示装置は、第1の動作及び第2の動作によって動作し、
前記第1の動作では、前記第1のデータ線を介した前記画素への第1の電位の供給と、前記第2のデータ線を介した前記画素への第2の電位の供給と、を並行して行った後、前記第2のデータ線を介して前記画素に第3の電位を供給することにより、前記画素に保持された前記第1の電位を前記第4の電位に変化させ、前記第4の電位を前記画素電極に印加し、
前記第2の電位は、前記第1の電位を基に算出される、前記共通電極に印加される電位以下の値の電位であり、
前記第3の電位は、前記共通電極に印加される前記電位より高い値の電位であり、
前記第4の電位は、前記共通電極に印加される前記電位以上の値の電位であり、
前記第2の動作では、前記第1のデータ線を介した前記画素への第5の電位の供給と、前記第2のデータ線を介した前記画素への第6の電位の供給と、を並行して行った後、前記第2のデータ線を介して前記画素に第7の電位を供給することにより、前記画素に保持された前記第5の電位を前記第8の電位に変化させ、前記第8の電位を前記画素電極に印加し、
前記第6の電位は、前記第5の電位を基に算出される、前記共通電極に印加される前記電位以上の値の電位であり、
前記第7の電位は、前記共通電極に印加される前記電位より低い値の電位であり、
前記第8の電位は、前記共通電極に印加される前記電位以下の値の電位である表示装置の動作方法。 - 請求項4において、
前記第3の電位は、前記第1の電位が取り得る最大値以上の電位であり、
前記第7の電位は、前記第5の電位が取り得る最小値以上の電位である表示装置の動作方法。 - 請求項4又は5において、
前記第1の電位が取り得る値の範囲と、前記第5の電位が取り得る値の範囲と、は等しい表示装置の動作方法。 - 請求項4乃至6のいずれか一項において、
前記第1の動作による動作と、前記第2の動作による動作と、を1フレーム期間毎に交互に行う表示装置の動作方法。 - 請求項4乃至7のいずれか一項において、
前記表示装置は、ソースドライバ回路を有し、
前記ソースドライバ回路は、前記第1のデータ線と電気的に接続され、
前記ソースドライバ回路は、前記第2のデータ線と電気的に接続され、
前記ソースドライバ回路は、前記第1の電位及び前記第2の電位、並びに前記第5の電位及び前記第6の電位を生成する機能を有する表示装置の動作方法。 - 請求項1乃至8のいずれか一項において、
前記画素は、第1のトランジスタと、第2のトランジスタと、容量素子と、を有し、
前記第1のトランジスタのソース又はドレインの一方は、前記容量素子の一方の電極と電気的に接続され、
前記第1のトランジスタのソース又はドレインの他方は、前記第1のデータ線と電気的に接続され、
前記第2のトランジスタのソース又はドレインの一方は、前記容量素子の他方の電極と電気的に接続され、
前記第2のトランジスタのソース又はドレインの他方は、前記第2のデータ線と電気的に接続されている表示装置の動作方法。 - 請求項9において、
前記第1のトランジスタと、前記第2のトランジスタと、は、チャネル形成領域に金属酸化物を有し、
前記金属酸化物は、Inと、Znと、M(MはAl、Ti、Ga、Sn、Y、Zr、La、Ce、Nd又はHf)と、を有する表示装置の動作方法。 - 請求項1乃至10のいずれか一項において、
前記表示素子は、液晶素子である表示装置の動作方法。
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