WO2019163529A1 - Semiconductor element production method, electronic device production method, semiconductor element, and electronic device - Google Patents

Semiconductor element production method, electronic device production method, semiconductor element, and electronic device Download PDF

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Publication number
WO2019163529A1
WO2019163529A1 PCT/JP2019/004384 JP2019004384W WO2019163529A1 WO 2019163529 A1 WO2019163529 A1 WO 2019163529A1 JP 2019004384 W JP2019004384 W JP 2019004384W WO 2019163529 A1 WO2019163529 A1 WO 2019163529A1
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Prior art keywords
protective layer
layer
organic semiconductor
manufacturing
substrate
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PCT/JP2019/004384
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French (fr)
Japanese (ja)
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小泉翔平
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株式会社ニコン
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to a method for manufacturing a semiconductor element, a method for manufacturing an electronic device, a semiconductor element, and an electronic device for forming a passivation film as a protective layer on an organic semiconductor layer formed on a substrate on which an electrode is formed. About.
  • Thin film transistors known as a kind of semiconductor element include organic thin film transistors and inorganic thin film transistors.
  • Organic thin-film transistors can be manufactured at a lower temperature than conventional inorganic thin-film transistors using inorganic materials (such as silicon), and the material has flexibility. Therefore, organic thin-film transistors are organically formed on a flexible resin substrate such as PET (polyethylene terephthalate). Thin film transistors can be formed.
  • an organic thin film transistor can be formed by a solution process that is inexpensive and suitable for upsizing, a roll that is subjected to a predetermined treatment on a substrate supplied from a supply roll obtained by winding the substrate in a roll shape and wound by a recovery roll
  • the production of organic thin-film transistors in the production system of the two-roll (Roll To Roll) method is expected, and research is being conducted as the core of next-generation flexible electronics.
  • a passivation film (protective layer) is formed in order to eliminate damage to the organic semiconductor layer due to the organic thin film transistor manufacturing process (such as a photolithography process).
  • the organic thin film transistor manufacturing process such as a photolithography process.
  • JP 2013-504186 discloses a passivation layer (a first passivation layer and a second passivation layer) on which two layers that can be formed by a solution process are deposited.
  • the first passivation layer protects the organic semiconductor layer using a resin that dissolves in water or a fluorine-based solvent, and the second passivation layer is stacked on the first passivation layer using a chemical-resistant resin.
  • the deterioration of the organic semiconductor layer due to the post-process is suppressed.
  • a first film formation step of forming an organic semiconductor layer on a substrate on which an electrode is formed, and a second film formation of forming a first protective layer on the surface of the organic semiconductor layer A first pattern forming step of forming a predetermined pattern on the first protective layer by exposing the first protective layer by irradiating the first protective layer with light; and forming the predetermined pattern And a second pattern forming step of forming the predetermined pattern on the organic semiconductor layer by etching the organic semiconductor layer using the first protective layer as a mask.
  • a second aspect of the present invention is a method for manufacturing an electronic device, and includes the method for manufacturing the semiconductor element of the first aspect.
  • a third aspect of the present invention covers an organic semiconductor layer formed on a substrate on which an electrode is formed, a first protective layer formed on the surface of the organic semiconductor layer, and the first protective layer.
  • the first protective layer is made of a first resin that is cured by light.
  • the organic semiconductor layer formed on the substrate on which the electrode is formed, the first protective layer formed on the surface of the organic semiconductor layer, and the first protective layer are covered.
  • the second protective layer is formed as described above, and the second protective layer has lower solubility in the first solvent than the first protective layer.
  • a fifth aspect of the present invention is an electronic device having the semiconductor element of the third or fourth aspect.
  • FIG. 1A to 1C are diagrams showing a process of forming a gate electrode layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor.
  • 2A to 2C are diagrams showing a process of forming a gate electrode layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor.
  • FIG. 3A to FIG. 3C are diagrams showing a process of forming an insulator layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor after forming a gate electrode layer.
  • 4A to 4C are diagrams showing a process of forming a source / drain electrode layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor after the formation of the insulator layer.
  • FIGS. 5C are views showing a process of forming a source / drain electrode layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor after forming an insulator layer.
  • 6A to 6C are diagrams showing a process of forming an organic semiconductor layer and a first protective layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor after the formation of the source / drain electrode layers.
  • FIG. 7A to FIG. 7C are diagrams showing a process of forming an organic semiconductor layer and a first protective layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor after the formation of the source / drain electrode layers.
  • FIG. 8A to 8C are diagrams illustrating a process of forming a second protective layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor after the formation of the organic semiconductor layer and the first protective layer.
  • FIG. 9A is a diagram showing an optical microscope image of the first protective layer on which a pattern is formed
  • FIG. 9B is a diagram showing an optical microscope image of the patterned organic semiconductor layer.
  • FIG. 10A is a diagram showing a photograph of a gate electrode fabricated on a substrate
  • FIG. 10B is a diagram showing an optical microscope image of the gate electrode.
  • FIG. 11A is a diagram showing a photograph of an insulator layer formed by patterning on a gate electrode
  • FIG. 11A is a diagram showing a photograph of an insulator layer formed by patterning on a gate electrode
  • FIG. 11B is a diagram showing an optical microscope image of the insulator layer near the gate electrode.
  • FIG. 12A is a diagram showing a photograph of the source electrode and the drain electrode formed on the insulator layer
  • FIG. 12B is a diagram showing an optical microscope image near the gate electrode.
  • it is a figure which shows the optical microscope image of the board
  • it it is a figure which shows the optical microscope image of the board
  • Example 2 it is a figure which shows the optical microscope image of the board
  • FIG. 18A to FIG. 18C are diagrams showing a process of forming a source / drain electrode layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor.
  • FIG. 19A to FIG. 19C are diagrams showing a process of forming a source / drain electrode layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor.
  • FIG. 20A to 20C are views showing a process of forming an organic semiconductor layer and a first protective layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor after the formation of the source / drain electrode layers.
  • FIG. 21A to FIG. 21C are diagrams showing a process of forming an organic semiconductor layer and a first protective layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor after the formation of the source / drain electrode layers.
  • FIG. 22A to FIG. 22C are views showing a process of forming a second protective layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor after the formation of the organic semiconductor layer and the first protective layer.
  • 23C are diagrams showing a process of forming a gate electrode layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor after the formation of the second protective layer.
  • 24A and 24B are diagrams illustrating a process of forming a gate electrode layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor after the formation of the second protective layer.
  • a manufacturing method of a semiconductor element an organic thin film transistor with a passivation film having a bottom gate / bottom contact type organic thin film transistor (organic TFT) will be described.
  • a gate electrode layer, an insulator layer, a source / drain electrode layer, an organic semiconductor layer, a first protective layer, and a second protective layer are stacked on the substrate in the order described above. Has a structured.
  • a roll-to-roll (Roll To Roll) that performs a predetermined process on a substrate supplied from a supply roll obtained by winding the substrate in a roll shape and winds the substrate with a recovery roll.
  • Method of manufacturing semiconductor devices Therefore, the substrate on which the semiconductor element is formed needs to be a flexible, that is, a sheet-like substrate having flexibility.
  • a foil (foil) made of a metal or an alloy such as a resin film or stainless steel is used for the substrate.
  • the resin film material include polyethylene resin, polypropylene resin, polyester resin, ethylene vinyl copolymer resin, polyvinyl chloride resin, cellulose resin, polyamide resin, polyimide resin, polycarbonate resin, polystyrene resin, and vinyl acetate resin. Among these, those containing at least one or more are listed.
  • the thickness and rigidity (Young's modulus) of the substrate may be in a range that does not cause folds or irreversible wrinkles due to buckling in the substrate when passing through a conveyance path such as an exposure apparatus.
  • a film such as PET (polyethylene terephthalate) or PEN (polyethylene naphthalate) having a thickness of about 25 ⁇ m to 200 ⁇ m is typical of a suitable sheet substrate.
  • the substrate may receive heat in the process applied to the substrate, it is preferable to select a substrate made of a material that does not have a significantly large thermal expansion coefficient.
  • the thermal expansion coefficient can be suppressed by mixing an inorganic filler with a resin film.
  • the inorganic filler may be, for example, titanium oxide, zinc oxide, alumina, or silicon oxide.
  • the substrate may be a single layer of ultrathin glass having a thickness of about 100 ⁇ m manufactured by a float process or the like, or a laminate in which the above resin film, foil, or the like is bonded to the ultrathin glass. There may be.
  • the flexibility of a substrate means a property that the substrate can be bent without being sheared or broken even if a force of its own weight is applied to the substrate.
  • flexibility includes a property of bending by a force of about its own weight.
  • the degree of flexibility varies depending on the material, size and thickness of the substrate, the layer structure formed on the substrate, the environment such as temperature and humidity, and the like. In any case, when the substrate is correctly wound around various conveying rollers, rotating drums, and other members for conveying direction provided in the conveying path in the roll-to-roll manufacturing system, the folds are buckled. If the substrate can be smoothly transported without being attached or damaged (breaking or cracking), it can be said to be in the range of flexibility.
  • formation of each layer of the semiconductor element will be described.
  • an amine layer 10 is first formed on the substrate P as shown in FIG. 1A.
  • the amine layer 10 is a silane coupling agent layer having a primary or secondary amino group. That is, an amine solution obtained by adding a solvent to a silane coupling agent (amine molecule) having a primary or secondary amino group is applied to the surface of the substrate P.
  • a coating method a generally known method such as spin coating, dip coating, spray coating, roll coating, brush coating, flexographic printing, or screen printing can be used.
  • the solvent is volatilized by heat treatment to form the amine layer 10.
  • the amine layer 10 is an extremely thin silane coupling agent layer, there is no light scattering and it is a transparent film. Therefore, the amine layer 10 may be formed on the entire surface when forming the gate electrode layer, and it is also advantageous that the film formation is easy.
  • a positive type photoresist layer 12 is formed on the amine layer 10.
  • the photoresist layer 12 is formed by applying a photoresist material on the amine layer 10 and prebaking.
  • light in this embodiment, UV light (ultraviolet light)
  • a mask M1 a mask M1 having an opening ma1 in a region where the gate electrode G is formed
  • a predetermined pattern is formed.
  • the photoresist layer 12 is exposed.
  • a developing solution for example, TMAH or the like
  • a portion of the photoresist layer 12 irradiated with UV light (exposed portion). Dissolves and is removed. As a result, a predetermined pattern corresponding to the gate electrode G is formed in the photoresist layer 12. That is, a pattern having the opening 12a is formed in a region where the gate electrode G is formed.
  • a catalyst solution containing a catalyst (Pd) 14 used for electroless plating is applied on the substrate P. Since the photoresist layer 12 having a predetermined pattern is laminated on the amine layer 10, the catalyst 14 is applied on the amine layer 10 in the region exposed by the opening 12a.
  • the primary or secondary amino group contained in the amine layer 10 has a property of reducing Pd ions contained in the catalyst solution to Pd metal and capturing them. Therefore, the activation process for reducing Pd ions, which is normally required, can be omitted, and the process can be made ecological.
  • the gate electrode layer 16 is formed on the substrate P. Since the amine layer 10 is very thin, it can be formed without roughening the surface of the substrate P, and a highly flat gate electrode layer 16 can be obtained. Therefore, it is possible to produce a multilayer metal structure with little leakage. Note that the gate electrode layer 16 can also be formed by a method of etching a metal film such as aluminum or a patterning by a printing method.
  • the insulator layer 18 is made of an insulating photo-curing photosensitive resin, for example, UV photo-curing acrylic resin, UV photo-curing epoxy resin, UV photo-curing en-thiol resin, or UV photo-curing. Type silicone resin. Since the photocurable resin is used, the insulator layer 18 can be patterned by irradiation with UV light.
  • an insulating photo-curing photosensitive resin for example, UV photo-curing acrylic resin, UV photo-curing epoxy resin, UV photo-curing en-thiol resin, or UV photo-curing.
  • Type silicone resin Since the photocurable resin is used, the insulator layer 18 can be patterned by irradiation with UV light.
  • an insulator layer solution is applied onto a substrate P on which a gate electrode layer 16 is formed to form an insulator layer 18, and a mask M2 (insulator) on which a predetermined pattern is formed.
  • the insulator layer 18 is irradiated with UV light through a mask M2) having an opening ma2 in a region where the layer 18 is to be formed.
  • the insulator layer 18 in the region irradiated with UV light (the region where the insulator layer 18 is to be formed) is cured.
  • the hardened part is represented by dots, and the uncured part is hatched.
  • the insulator layer 18 can be selectively cured by using the mask M2. In this case, it is more preferable to add a heat treatment for promoting a chemical reaction in a region irradiated with UV light.
  • a portion that is not irradiated with UV light is removed by dissolving with a developing solution to form a predetermined pattern according to the mask M2.
  • a body layer 18 is formed. That is, the portion of the insulator layer 18 that has been cured by being irradiated with UV light remains.
  • the insulator layer 18 is formed on the gate electrode layer 16.
  • the insulator layer 18 needs to have a thickness of several hundred nm.
  • the thickness of the insulator layer 18 can be controlled by the resin concentration and application conditions. It is also possible to form the insulator layer 18 by patterning a material such as a photocurable resin or a thermosetting resin, such as a printing method. Therefore, any applicable material having insulating properties can be applied.
  • the source / drain electrode layer can be manufactured through a process substantially similar to the above-described manufacturing procedure of the gate electrode layer 16.
  • an amine layer 20 is formed on the insulator layer 18.
  • a positive photoresist layer 22 is formed on the amine layer 20, and a mask M3 (an opening is formed in a region where the source electrode S and the drain electrode D are formed) on which a predetermined pattern is formed.
  • the photoresist layer 22 is exposed by irradiating UV light through a mask M3) having ma3. Thereafter, by immersing the photoresist layer 22 (substrate P) in a developing solution, as shown in FIG.
  • the photoresist layer 22 in the portion irradiated with UV light (exposed portion) is dissolved and removed.
  • a pattern corresponding to the source electrode S and the drain electrode D is formed in the photoresist layer 22. That is, a pattern having the opening 22a is formed in a region where the source electrode S and the drain electrode D are formed.
  • the surface of the source / drain electrode layer 26 is covered with gold 28 as shown in FIG.
  • the source electrode S and the drain electrode D are covered with the gold 28.
  • an organic semiconductor layer having a high HOMO level such as pentacene is formed on the surface of the source / drain electrode layer 26 (see FIG. 6A)
  • money 28 what is necessary is just to coat
  • the source / drain electrode layer 26 is formed on the insulator layer 18. According to this method, since the source / drain electrode layer 26 with high flatness can be produced without roughening the surface of the insulator layer 18, the organic semiconductor layer 30 and the insulating film interface described later The flatness can be maintained. Therefore, an organic thin film transistor can be manufactured by a wet process without increasing carrier transfer resistance. In addition, since a highly flat metal layer can be obtained, a multilayer metal structure having two or more layers with less leakage can be manufactured.
  • the insulating film interface refers to a surface portion of the insulator layer 18 between the source electrode S and the drain electrode D.
  • An organic semiconductor layer 30 is formed on the substrate P on which the gate electrode layer 16, the insulator layer 18, and the source / drain electrode layer 26 are formed.
  • Organic semiconductors such as soluble pentacene typified by TIPS pentacene (6,13-bis (triisopropylsilylethynyl) pentacene) and organic semiconductor polymers such as P3HT (poly (3-hexylthiophene-2,5-diyl)) Soluble in organic solvents such as toluene.
  • FIG. 6A shows the organic semiconductor layer 30 formed on the substrate P.
  • the organic semiconductor layer 30 is manufactured by a wet method, the organic semiconductor layer 30 may be formed by a sublimation method, a transfer method, or the like. The organic semiconductor layer 30 is formed by the above process.
  • the first protective layer 32 as the first passivation film is made of a photosensitive resin. Therefore, the first protective layer 32 can be patterned by irradiation with UV light.
  • a first resin, a photopolymerization initiator (first photopolymerization initiator) for curing the first resin with UV light, a first resin and a photopolymerization initiator are prepared.
  • a first protective layer solution (first solution) containing a first solvent to be dissolved is applied to form a first protective layer 32 on the surface of the organic semiconductor layer 30.
  • the first resin for example, a resin that dissolves in water or a fluorine-based solvent (water-soluble resin or fluorine-based solvent-soluble resin) can be used.
  • water-soluble resin or fluorine-based solvent-soluble resin for example, water or a fluorine-based solvent can be used. These solvents can be used.
  • the water-soluble resin is used as the first resin and water is used as the first solvent, the water contact angle of the first protective layer 32 is, for example, 62 degrees.
  • the 1st resin or the 1st solvent has the property of a photoinitiator, the 1st protective layer solution does not need to contain a photoinitiator.
  • UV light is applied to the first protective layer 32 through a mask M4 (a mask M4 having an opening ma4 in a region where the first protective layer 32 is to be formed) on which a predetermined pattern is formed. Irradiate.
  • a mask M4 a mask M4 having an opening ma4 in a region where the first protective layer 32 is to be formed
  • the first protective layer 32 in the region irradiated with UV light is cured.
  • the direction of hatching in the hardened part and the non-hardened part is shown differently.
  • the 1st protective layer 32 can be selectively hardened by using mask M4.
  • a predetermined pattern corresponding to the mask M4 is formed by dissolving and removing the portion not irradiated with UV light with a first solvent (water or a fluorine-based solvent or the like).
  • the first protective layer 32 is formed. That is, the portion of the first protective layer 32 that has been cured by being irradiated with UV light remains.
  • the region where the first protective layer 32 is to be formed includes a region between the source electrode S and the drain electrode D.
  • the first protective layer solution a solution obtained by diluting BIOSURFINE (registered trademark) -AWP-MRH manufactured by Toyo Gosei Co., Ltd. with water to 3 wt% can be used.
  • a water-soluble resin of vinyl alcohol / vinyl oxide copolymer and acetal of 3- [4-azidophenyl] -N- (3-formyl) propyl-2- [morpholinomethylphenylcarbonylamino] propenamide You may use the 1st protective layer solution which has a photoinitiator of a chemical compound.
  • FIG. 7C By immersing the substrate P on which the first protective layer 32 having a predetermined pattern is formed in an organic solvent in which the organic semiconductor layer 30 can be dissolved (toluene or the like when TIPS pentacene is used as the organic semiconductor), FIG. As shown in FIG. 7C, using the first protective layer 32 as a mask, the portion of the organic semiconductor layer 30 that is not covered with the first protective layer 32, that is, the exposed portion, is etched. That is, the exposed portion of the organic semiconductor layer 30 is dissolved and removed. As a result, the organic semiconductor layer 30 is formed between the source electrode S and the drain electrode D, and the target organic semiconductor layer 30 can be obtained.
  • an organic solvent in which the organic semiconductor layer 30 can be dissolved toluene or the like when TIPS pentacene is used as the organic semiconductor
  • the gate electrode layer 16 (gate electrode G), the insulator layer 18, the source / drain electrode layer 26 (source electrode S and drain electrode D), and the organic semiconductor layer 30 constitute an organic thin film transistor.
  • the organic semiconductor can be reused by recovering the organic semiconductor by purification from the organic solvent in which the exposed organic semiconductor layer 30 is dissolved.
  • the second protective layer 34 as the second passivation film is made of a photosensitive resin (photo-curable photosensitive resin). Therefore, the second protective layer 34 can be patterned by irradiation with UV light.
  • a second protective layer solution (second solution) in which a photosensitive resin is dissolved in a solvent is applied on the substrate P so as to cover the first protective layer 32, and then the second protective layer. 34 is formed.
  • the contact angle of the second protective layer 34 with respect to the first solvent is larger than the contact angle of the first protective layer 32 with respect to the first solvent.
  • the water contact angle of the second protective layer 34 is larger than the water contact angle of the first protective layer 32 (for example, 62 degrees). (For example, 73 degrees).
  • the second protective layer solution dissolves the second resin, a photopolymerization initiator (second photopolymerization initiator) that cures the second resin with UV light, the second resin, and the photopolymerization initiator.
  • a second solvent for example, a resin that dissolves in an organic solvent (organic solvent-soluble resin) can be used.
  • organic solvent-soluble resin for example, an organic solvent can be used.
  • the second protective layer solution for example, SU-8 3005 manufactured by Nippon Kayaku Co., Ltd. diluted 2.5 times with cyclohexanone can be used.
  • the second protective layer solution may not contain the photopolymerization initiator.
  • the second protective layer 34 is formed so as to cover at least the first protective layer 32 and the organic semiconductor layer 30 (side surface of the organic semiconductor layer 30). Then, the second protective layer 34 is irradiated with UV light through a mask M5 (a mask M5 having an opening ma5 in a region where the second protective layer 34 is to be formed) on which a predetermined pattern is formed. As a result, as shown in FIG. 8B, the second protective layer 34 in the region irradiated with UV light (the region where the second protective layer 34 is to be formed) is cured. In FIG. 8B, the direction of hatching in the hardened
  • a portion (second protective layer 34) that has not been irradiated with UV light is dissolved and removed with a second solvent (such as an organic solvent) to remove a predetermined amount corresponding to the mask M5.
  • a second protective layer 34 having a pattern is formed. That is, the portion of the second protective layer 34 that has been cured by being irradiated with UV light remains.
  • the region where the second protective layer 34 is to be formed is a region necessary to cover the organic semiconductor layer 30 and the first protective layer 32. Therefore, a portion of the second protective layer 34 that is not necessary to cover the organic semiconductor layer 30 and the first protective layer 32 is removed.
  • the organic semiconductor layer 30 (side surface of the organic semiconductor layer 30) and the first protective layer 32 are covered with the second protective layer 34. Since the second protective layer 34 has a larger contact angle with the first solvent than the first protective layer 32, the second protective layer 34 is more liquid repellent with respect to the first solvent than the first protective layer 32. Have. Therefore, the second protective layer 34 has a lower solubility in the first solvent than the first protective layer 32 and a low liquid absorbency.
  • a predetermined pattern may be formed on the second protective layer 34 so that the second protective layer 34 does not cover the organic semiconductor layer 30.
  • the passivation film is divided into two layers of the first protective layer 32 and the second protective layer 34 .
  • the first protective layer 32 is formed using a solution that does not dissolve the organic semiconductor (for example, a solution dissolved in water or a fluorine-based solvent).
  • the protective layer 32 needs to be formed on the organic semiconductor layer 30. That is, when the second protective layer 34 is formed directly on the organic semiconductor layer 30 with an organic solvent solution without using the first protective layer 32, the organic semiconductor layer 30 is dissolved with the organic solvent solution. Because it ends up.
  • a first resin such as a water-soluble resin or a fluorine-based solvent-soluble resin
  • Example 1 optical patterning of the high-definition organic semiconductor layer 30 will be examined by the process of the first embodiment.
  • a PET film manufactured by Toyobo Co., Ltd. (without Cosmo Shine A-4100 coating) is used for the substrate P, TIPS pentacene is used for the organic semiconductor layer 30, and the first protective layer 32 is used.
  • BIOSURFINE registered trademark
  • BIOSURFINE registered trademark
  • BIOSURFINE registered trademark
  • BIOSURFINE (registered trademark) -AWP-MRH contains a water-soluble resin (first resin) and a photopolymerization initiator that cures the water-soluble resin with UV light.
  • the water contact angle of the water-soluble photosensitive resin (BIOSURFINE (registered trademark) -AWP-MRH) constituting the first protective layer 32 is 62 degrees.
  • the organic semiconductor layer 30 on the substrate P For forming the organic semiconductor layer 30 on the substrate P, a dip coating method was used. The substrate P is dipped in an organic semiconductor solution (a solution obtained by diluting an organic semiconductor to 2 wt%) in which an organic semiconductor of TIPS pentacene is dissolved in a toluene solution (organic solvent), pulled up 1 mm at a lifting speed of 30 mm / s, and held for 10 seconds. Repeated. Then, in order to volatilize the toluene solution used for the organic solvent, the organic semiconductor layer 30 was formed on the substrate P by performing heat treatment at 105 ° C. for 10 minutes.
  • organic semiconductor solution a solution obtained by diluting an organic semiconductor to 2 wt% in which an organic semiconductor of TIPS pentacene is dissolved in a toluene solution (organic solvent), pulled up 1 mm at a lifting speed of 30 mm / s, and held for 10 seconds.
  • the organic semiconductor layer 30 was formed on
  • FIG. 9A shows an optical microscope image of the first protective layer 32 on which a pattern is formed. The pattern size is 100 ⁇ m.
  • the substrate P on which the first protective layer 32 is produced is immersed in toluene (organic solvent), and the portion of the organic semiconductor layer 30 that is not covered with the first protective layer 32 is etched using the first protective layer 32 as a mask.
  • a pattern was formed on the organic semiconductor layer 30.
  • An optical microscope image of the patterned organic semiconductor layer 30 is shown in FIG. 9B. It was confirmed that the organic semiconductor layer 30 was patterned in the same shape as the first protective layer 32.
  • the degree of side etching is low, and it has been proved that patterning can be easily performed with a size of about 100 ⁇ m. If patterning can be performed with this size (100 ⁇ m), it is sufficiently applicable to electronic devices such as displays.
  • Example 2 In Example 2, the formation of an organic transistor will be examined.
  • the organic semiconductor solution used for the substrate P, the organic semiconductor layer 30, and the first protective layer solution used for the first protective layer 32 are the same as those in Example 1.
  • KBE-903 manufactured by Shin-Etsu Chemical Co., Ltd.
  • N-PHENY LaminoNOPROPYLTRIMETHOXYSILANE manufactured by Amax Co., Ltd.
  • MIBK methyl isobutyl ketone
  • the amine solution was applied onto the substrate P by dip coating.
  • the lifting speed of the dip coat was 1 mm / s.
  • heat processing was performed for 15 minutes at 105 degreeC, and the amine layer 10 was formed into a film.
  • a photoresist (SUMIRESIST PFI-34A6) manufactured by Sumitomo Chemical Co., Ltd. is applied to the substrate P on which the amine layer 10 is formed on the entire surface by a dip coating method, and prebaked at 105 ° C. for 5 minutes. 12 was formed.
  • the lifting speed of the dip coat was 1 mm / s, and a photoresist layer 12 having a thickness of about 1 ⁇ m was formed.
  • UV light having an intensity of 43 mW / cm 2 is exposed for 3 seconds through the mask M1, heated at 105 ° C. for 5 minutes (post-baked), and then immersed in an aqueous solution (developer) containing 2.38 wt% TMAH for 150 seconds.
  • a predetermined pattern having openings 12 a was formed in the photoresist layer 12.
  • the pattern formed on the photoresist layer 12 is a pattern corresponding to the mask M1.
  • FIG. 10A shows a photograph of the gate electrode G formed on the substrate P
  • FIG. 10B shows an optical microscope image of the gate electrode G.
  • the produced gate electrode G was washed with an alkaline solution and 2-propanol, and further washed with UV to remove organic residues on the surface.
  • the insulator layer solution was applied by a dip coating method.
  • As the insulator layer solution SU-8 3005 manufactured by Nippon Kayaku Co., Ltd. was diluted 2.5 times with cyclohexanone, and the dip coat lifting speed was 1 mm / s.
  • the insulator layer 18 was formed by pre-baking at 105 ° C. for 10 minutes. Then, UV light having an intensity of 43 mW / cm 2 was exposed for 5 seconds through the mask M2, and heated at 105 ° C. for 60 minutes.
  • FIG. 11A shows a photograph of the insulator layer 18 formed by patterning on the gate electrode G
  • FIG. 11B shows an optical microscope image of the insulator layer 18 in the vicinity of the gate electrode G.
  • the source / drain electrode layer 26 is formed so as to have a desired shape in the same procedure as the fabrication of the gate electrode layer 16. Briefly, after the amine layer 20 is formed, a photoresist layer 22 is formed, and UV light is exposed through the mask M3, whereby a predetermined pattern corresponding to the mask M3 is formed on the photoresist layer 22 To do. Thereafter, the substrate P is immersed in a catalyst colloid solution for electroless plating, and the catalyst (Pd) 24 is adhered to the amine layer 20 exposed from the opening 22a of the photoresist layer 22.
  • the substrate P is immersed in electroless plating to deposit nickel phosphorus on the catalyst 14 exposed from the opening 22a of the photoresist layer 22 to form the source / drain electrode layer 26.
  • the amine layer 20, the photoresist layer 22, the catalyst colloid solution, the electroless plating material, and other conditions are the same as the formation of the gate electrode G. That is, the difference between the formation of the gate electrode layer 16 and the source / drain electrode layer 26 is that the mask M to be used is different, and the other procedures are the same.
  • the substrate P is immersed in a displacement gold plating bath for 1 minute in order to cover the gold 28 on the surface of the metal (nickel phosphorus) forming the source electrode S and the drain electrode D and the like. Then, it was immersed in a reduced gold plating bath for 3 minutes. Next, it was washed with water and dried at 105 ° C. for 30 minutes to coat the source / drain electrode layer 26 with gold 28.
  • FIG. 12A shows a photograph of the source electrode S and the drain electrode D formed on the insulator layer 18, and FIG. 12B shows an optical microscope image near the gate electrode G.
  • FIG. The wiring 40 in FIG. 12B is a part of the source electrode S, and the wiring 42 is a part of the drain electrode D.
  • both wirings 40 and 42 are arranged via a gap (gap), and the gap (5 ⁇ m) forms a channel portion 44.
  • the line width of the wirings 40 and 42 is about 10 ⁇ m.
  • the channel length of the channel portion 44 (length in the vertical direction in FIG. 12B) is 500 ⁇ m.
  • the channel portion 44 is a region between the source electrode S and the drain electrode D and is a region where the organic semiconductor layer 30 is formed.
  • the organic semiconductor layer 30 was formed by dipping the substrate P on which the source / drain electrode layer 26 was produced in an organic semiconductor solution and performing a dip coating method.
  • FIG. 13 shows an optical microscope image of the substrate P on which an organic semiconductor (TIPS pentacene) is formed by dip coating.
  • the material and film formation conditions used for forming the organic semiconductor layer 30 are the same as those in the first embodiment.
  • the first protective layer 32 was formed by spin coating, and a predetermined pattern was formed on the first protective layer 32 by optical patterning.
  • FIG. 14 the optical microscope image of the board
  • the material and film forming conditions used for forming the first protective layer 32 are the same as those in the first embodiment (however, the pattern is larger than that in the first embodiment).
  • Example 2 About patterning of organic semiconductor layers
  • the substrate P on which the first protective layer 32 is patterned is immersed in toluene (organic solvent), and the portion of the organic semiconductor that is not covered with the first protective layer 32 using the first protective layer 32 as a mask.
  • the layer 30 was etched to form a pattern in the organic semiconductor layer 30.
  • FIG. 15 the optical microscope image of the board
  • the second protective layer solution was applied by a dip coating method and prebaked at 105 ° C. for 10 minutes to form a second protective layer 34.
  • the second protective layer solution SU-8 3005 manufactured by Nippon Kayaku Co., Ltd. was diluted 2.5 times with cyclohexanone, and the dip coat lifting speed was 1 mm / s.
  • SU-8 3005 contains an organic solvent-soluble resin (second resin) that dissolves in an organic solvent and a photopolymerization initiator that cures the organic solvent-soluble resin with UV light.
  • Cyclohexanone contains an organic solvent ( Second solvent).
  • the water contact angle of the organic solvent soluble photosensitive resin (SU-8 3005) constituting the second protective layer 34 is 73 degrees.
  • Figure 17 is a graph showing the evaluation results of characteristics of the gate voltage V G and the drain current I D of the passivation film with an organic thin film transistor manufactured by the above steps. It was confirmed that the fabricated organic thin film transistor with a passivation film operated as an n-type transistor.
  • the thin film transistor with a passivation thin film had a carrier mobility of 7 ⁇ 10 ⁇ 3 cm 2 / Vs and an on / off ratio of 1.5 ⁇ 10 7 , indicating good characteristics.
  • the drain-source voltage is -30V.
  • the temperature applied to the substrate P is a relatively low temperature region of about 100 ° C.
  • this process is performed with the substrate P held at 100 ° C. or lower or 120 ° C. or lower. For this reason, even if it is a case where a PET board
  • the organic semiconductor constituting the organic semiconductor layer 30 does not deteriorate within the temperature range, application to a roll-to-roll manufacturing system can be expected.
  • the organic semiconductor layer 30, the first protective layer 32, and the second protective layer 34 are formed only by a wet process, at least one of the organic semiconductor layer 30, the first protective layer 32, and the second protective layer 34 is formed.
  • the uniformity (flatness) of the two surfaces can be improved, and high-definition patterning of the organic semiconductor layer 30 can be performed. That is, at least one of the organic semiconductor layer 30, the first protective layer 32, and the second protective layer 34 of the semiconductor element manufactured by obtaining this process has a flat surface.
  • the bottom gate / bottom contact type has been described as an example of the organic thin film transistor.
  • a top gate / bottom contact type or a bottom gate / top contact type may be used.
  • a method of manufacturing an organic thin film transistor with a top gate / bottom contact type passivation film as a semiconductor element will be briefly described.
  • the source / drain electrode layer, the organic semiconductor layer, the first protective layer, the second protective layer, and the gate electrode layer are stacked on the substrate P in the order described above. It has a structure.
  • formation of each layer of the semiconductor element will be described.
  • the source / drain electrode layer can be manufactured through a process similar to the manufacturing procedure of the source / drain electrode layer 26 described in the first embodiment.
  • the amine layer 50 is formed on the substrate P.
  • a positive photoresist layer 52 is formed on the amine layer 50, and a mask M6 in which a predetermined pattern is formed (openings in regions where the source electrode S and the drain electrode D are formed).
  • the photoresist layer 52 is exposed by irradiating UV light (light) through a mask M6) having ma6.
  • the photoresist layer 52 (substrate P) in a developing solution, as shown in FIG. 18C, the photoresist layer 52 in the portion irradiated with UV light (exposed portion) was dissolved and removed. Thereafter, a catalyst solution containing a catalyst (Pd) 54 used for electroless plating is applied on the substrate P.
  • a catalyst solution containing a catalyst (Pd) 54 used for electroless plating is applied on the substrate P.
  • a pattern corresponding to the source electrode S and the drain electrode D is formed in the photoresist layer 52. That is, a pattern having the opening 52a is formed in a region where the source electrode S and the drain electrode D are formed.
  • the catalyst 54 is applied on the amine layer 50 exposed by the opening 52a.
  • the substrate P by immersing the substrate P in an electroless plating solution such as nickel phosphorus, metal ions are reduced and deposited on the surface of the catalyst 54 as shown in FIG. 19A.
  • the deposited metal layer becomes the source / drain electrode layer 56. Therefore, the source / drain electrode layer (metal layer) 56 having the source electrode S and the drain electrode D is selectively formed on the substrate P.
  • the entire surface of the remaining photoresist layer 52 is exposed to UV light, and the photoresist layer 52 (substrate P) is immersed in a developer to remove the photoresist layer 52 as shown in FIG. 19B.
  • the surface of the source / drain electrode layer 56 is covered with the gold 58 as shown in FIG. As a result, the source electrode S and the drain electrode D are covered with the gold 58.
  • the source / drain electrode layer 56 is formed on the substrate P.
  • the organic semiconductor layer 60 can be manufactured through a process similar to the manufacturing procedure of the organic semiconductor layer 30 described in the first embodiment. That is, an organic semiconductor liquid in which an organic semiconductor is dissolved in an organic solvent is applied on the substrate P, and then heated to evaporate (volatilize) the solvent, whereby the organic semiconductor layer 60 is formed.
  • FIG. 20A shows the organic semiconductor layer 60 formed on the substrate P.
  • the first protective layer 62 as the first passivation film can be manufactured through a process similar to the manufacturing procedure of the first protective layer 62 described in the first embodiment.
  • a first resin, a photopolymerization initiator (first photopolymerization initiator) for curing the first resin with UV light, a first resin and a photopolymerization initiator are added.
  • a first protective layer solution containing a first solvent to be dissolved is applied to form a first protective layer 62 on the surface of the organic semiconductor layer 60.
  • the water contact angle of the first protective layer 62 when water-soluble resin is used as the first resin and water is used as the first solvent is, for example, 62 degrees.
  • the 1st protective layer solution does not need to contain a photoinitiator.
  • UV light is applied to the first protective layer 62 through a mask M7 (a mask M7 having an opening ma7 in a region where the first protective layer 62 is to be formed) on which a predetermined pattern is formed. Irradiate.
  • a mask M7 a mask M7 having an opening ma7 in a region where the first protective layer 62 is to be formed
  • the first protective layer 62 in the region irradiated with UV light is cured.
  • the direction of hatching in the hardened part and the non-hardened part is shown differently.
  • the 1st protective layer 62 can be selectively hardened by using mask M7.
  • a predetermined pattern corresponding to the mask M7 is formed by dissolving and removing a portion not irradiated with UV light with a first solvent (water or a fluorine-based solvent or the like).
  • the first protective layer 62 thus formed is formed. That is, the hardened portion of the first protective layer 62 irradiated with UV light remains.
  • the region where the first protective layer 62 is to be formed includes a region between the source electrode S and the drain electrode D.
  • the patterning of the organic semiconductor layer 60 can be performed through the same process as the patterning of the organic semiconductor layer 30 described in the first embodiment. That is, the substrate P on which the first protective layer 62 having a predetermined pattern is formed is immersed in an organic solvent in which the organic semiconductor layer 60 can be dissolved, so that the first protective layer 62 is masked as shown in FIG. 21C. As a result, the portion of the organic semiconductor layer 60 that is not covered with the first protective layer 62, that is, the exposed portion of the organic semiconductor layer 60 is dissolved and removed. As a result, the organic semiconductor layer 60 is formed between the source electrode S and the drain electrode D, and the target organic semiconductor layer 60 can be obtained.
  • the organic semiconductor can be reused by collecting the organic semiconductor by purification from the organic solvent in which the exposed organic semiconductor layer 60 is dissolved.
  • the second protective layer 64 as the second passivation film can be manufactured through a process similar to the manufacturing procedure of the second protective layer 64 described in the first embodiment.
  • a second protective layer solution in which a photosensitive resin is dissolved in a solvent is applied on the substrate P so as to cover the organic semiconductor layer 60 and the first protective layer 62, and the second protective layer 64. Is deposited.
  • the second protective layer solution dissolves the second resin, a photopolymerization initiator (second photopolymerization initiator) that cures the second resin with UV light, the second resin, and the photopolymerization initiator. And a second solvent.
  • the contact angle of the second protective layer 64 with respect to the first solvent is larger than the contact angle of the first protective layer 62 with respect to the first solvent.
  • the water contact angle of the second protective layer 64 is larger than the water contact angle (for example, 62 degrees) of the first protective layer 62 (for example, 62 degrees). 73 degrees).
  • the second protective layer solution may not contain the photopolymerization initiator.
  • the second protective layer 64 is irradiated with UV light through a mask M8 (a mask M8 having an opening ma8 in a region where the second protective layer 64 is to be formed) on which a predetermined pattern is formed.
  • a mask M8 a mask M8 having an opening ma8 in a region where the second protective layer 64 is to be formed
  • the second protective layer 64 in the region irradiated with UV light is cured.
  • the direction of hatching in the hardened part and the non-hardened part is shown differently.
  • the second protective layer 64 can be selectively cured by using the mask M8. In this case, it is more preferable to add a heat treatment for promoting a chemical reaction in a region irradiated with UV light.
  • a portion (second protective layer 64) that has not been irradiated with UV light is dissolved and removed with a second solvent (such as an organic solvent), so that a predetermined amount corresponding to the mask M8 is obtained.
  • a second protective layer 64 on which a pattern is formed is formed. That is, the portion of the second protective layer 64 that has been cured by being irradiated with UV light remains.
  • a region where the second protective layer 64 is to be formed is a region necessary to cover the organic semiconductor layer 60 and the first protective layer 62. Accordingly, the second protective layer 64 that is not necessary to cover the organic semiconductor layer 60 and the first protective layer 62 is removed.
  • the second protective layer 64 Since the second protective layer solution has a larger contact angle with the first solvent than the first protective layer solution, the second protective layer 64 is more liquid repellent with respect to the first solvent than the first protective layer 62. Have. Therefore, the second protective layer 64 has a lower solubility in the first solvent than the first protective layer 62 and has a low liquid absorbency. In the second embodiment, the second protective layer 64 also has a function as an insulator layer.
  • the gate electrode layer can be manufactured through a process similar to the manufacturing procedure of the gate electrode layer 16 described in the first embodiment.
  • an amine layer 66 is formed on the second protective layer 64.
  • a positive photoresist layer 68 is formed on the amine layer 66, and a mask M9 having a predetermined pattern (a mask M9 having an opening ma9 in a region where the gate electrode G is formed).
  • the photoresist layer 68 is exposed by irradiating it with UV light.
  • the photoresist layer 68 (substrate P) in a developing solution (for example, TMAH or the like), as shown in FIG. 23C, the photoresist layer 68 in the portion irradiated with UV light (exposed portion). Dissolves and is removed. As a result, a predetermined pattern corresponding to the gate electrode G is formed in the photoresist layer 68. That is, a pattern having the opening 68a is formed in a region where the gate electrode G is formed.
  • a developing solution for example, TMAH or the like
  • a catalyst solution containing a catalyst (Pd) 70 used for electroless plating is applied on the amine layer 66 exposed by the opening 68a of the photoresist layer 68, and the substrate P is used as a developer.
  • metal ions are reduced and deposited on the surface of the catalyst 70.
  • This deposited metal layer becomes the gate electrode layer 72. Therefore, the gate electrode layer 72 having the gate electrode G is selectively formed on the substrate P.
  • the photoresist layer 68 is immersed in a developer, thereby removing the photoresist layer 68 as shown in FIG. 24B.
  • the gate electrode layer 72 is formed on the second protective layer 64.
  • a top gate / bottom contact type organic thin film transistor with a passivation film can be manufactured only by a wet process.
  • the organic semiconductor layer 60, the first protective layer 62, and the second protective layer 64 are formed only by a wet process, at least one of the organic semiconductor layer 60, the first protective layer 62, and the second protective layer 64 is formed.
  • the uniformity (flatness) of the two surfaces can be improved, and high-definition patterning of the organic semiconductor layer 60 can be performed. Note that the manufacturing method of the bottom gate / top contact type organic transistor with a passivation film is not described in detail, but it can be manufactured through the same steps.
  • the manufacturing method of the electronic device is the same as that of each of the above embodiments.
  • the method for manufacturing a semiconductor element described in the embodiment may be included.
  • the electronic device manufacturing method may manufacture the semiconductor element of the electronic device using the manufacturing method described in the above embodiments.
  • the mask M (M1 to M9) is used to irradiate the photoresist layer, the protective layer, etc. with light, and a predetermined pattern is formed.
  • a predetermined pattern may be formed.
  • a predetermined pattern may be formed on the photoresist layer or the protective layer by switching light applied to the photoresist layer or the protective layer using a seed light source or an electro-optic modulator.
  • a predetermined pattern is formed by irradiating light to the photoresist layer (12, 22, 52, 68), the protective layer (32, 34, 62, 64), etc. using a digital micromirror device (DMD). May be formed.
  • DMD digital micromirror device

Abstract

This semiconductor element production method comprises: a first film-forming step of forming a film of an organic semiconductor layer (30, 60) on a substrate (P) whereon an electrode has been formed; a second film-forming step of forming a film of a first protective layer (32, 62) on the surface of the organic semiconductor layer; a first pattern-forming step of irradiating light onto the first protective layer to expose the first protective layer, thereby forming a predetermined pattern in the first protective layer; and a second pattern-forming step of etching the organic semiconductor layer while the first protective layer wherein the predetermined pattern has been formed serves as a mask, thereby forming the predetermined pattern in the organic semiconductor layer.

Description

半導体素子の製造方法、電子デバイスの製造方法、半導体素子、および、電子デバイスSemiconductor device manufacturing method, electronic device manufacturing method, semiconductor device, and electronic device
　本発明は、電極が形成された基板上に成膜された有機半導体層上に保護層としてのパッシベーション膜を成膜する半導体素子の製造方法、電子デバイスの製造方法、半導体素子、および、電子デバイスに関する。 The present invention relates to a method for manufacturing a semiconductor element, a method for manufacturing an electronic device, a semiconductor element, and an electronic device for forming a passivation film as a protective layer on an organic semiconductor layer formed on a substrate on which an electrode is formed. About.
　半導体素子の一種として知られている薄膜トランジスタには、有機薄膜トランジスタと無機薄膜トランジスタとがある。有機薄膜トランジスタは、従来の無機物（シリコン等）を用いた無機薄膜トランジスタと比較して低温での作製が可能であり、素材に柔軟性を有するので、ＰＥＴ（ポリエチレンテレフタレート）等のフレキシブル樹脂基板上に有機薄膜トランジスタを形成することが可能である。また、安価で大型化に向いている溶液プロセスで有機薄膜トランジスタを形成できるため、基板をロール状に巻いた供給ロールから供給された基板に対して所定の処理を施して回収ロールで巻き取るロール・ツー・ロール（Ｒｏｌｌ　Ｔｏ　Ｒｏｌｌ）方式の製造システムでの有機薄膜トランジスタの製造が期待され、次世代のフレキシブルエレクトロニクスの核として研究が行われている。 Thin film transistors known as a kind of semiconductor element include organic thin film transistors and inorganic thin film transistors. Organic thin-film transistors can be manufactured at a lower temperature than conventional inorganic thin-film transistors using inorganic materials (such as silicon), and the material has flexibility. Therefore, organic thin-film transistors are organically formed on a flexible resin substrate such as PET (polyethylene terephthalate). Thin film transistors can be formed. In addition, since an organic thin film transistor can be formed by a solution process that is inexpensive and suitable for upsizing, a roll that is subjected to a predetermined treatment on a substrate supplied from a supply roll obtained by winding the substrate in a roll shape and wound by a recovery roll The production of organic thin-film transistors in the production system of the two-roll (Roll To Roll) method is expected, and research is being conducted as the core of next-generation flexible electronics.
　有機薄膜トランジスタを電子ペーパや有機ＥＬディスプレイ等のデバイスに応用するためには、有機薄膜トランジスタ作製工程（フォトリソグラフィ工程等）による有機半導体層へのダメージを無くすためにパッシベーション膜（保護層）を成膜する必要がある。パッシベーション膜を形成する方法としては、有機薄膜トランジスタの溶液プロセスが可能であることや柔軟性を有する等の利点を活かすために溶液プロセスにより成膜することが望まれる。 In order to apply organic thin film transistors to devices such as electronic paper and organic EL displays, a passivation film (protective layer) is formed in order to eliminate damage to the organic semiconductor layer due to the organic thin film transistor manufacturing process (such as a photolithography process). There is a need. As a method for forming the passivation film, it is desired to form the film by a solution process in order to make use of advantages such as being capable of a solution process of an organic thin film transistor and having flexibility.
　特表２０１３－５０４１８６号公報には、溶液プロセスで成膜可能な２層が堆積されたパッシベーション層（第１のパッシベーション層と第２のパッシベーション層）が開示されている。第１のパッシベーション層は、水またはフッ素系の溶媒で溶解する樹脂を用いて有機半導体層を保護し、第２のパッシベーション層は、耐化学性の樹脂を用いて第１のパッシベーション層に積層することで、後工程の処理による有機半導体層の劣化を抑制している。このような有機薄膜トランジスタにおいては、有機半導体層を所望のパターンに形成することが望まれている。 JP 2013-504186 discloses a passivation layer (a first passivation layer and a second passivation layer) on which two layers that can be formed by a solution process are deposited. The first passivation layer protects the organic semiconductor layer using a resin that dissolves in water or a fluorine-based solvent, and the second passivation layer is stacked on the first passivation layer using a chemical-resistant resin. Thus, the deterioration of the organic semiconductor layer due to the post-process is suppressed. In such an organic thin film transistor, it is desired to form an organic semiconductor layer in a desired pattern.
　本発明の第１の態様は、電極が形成された基板上に有機半導体層を成膜する第１成膜工程と、前記有機半導体層の表面に第１保護層を成膜する第２成膜工程と、前記第１保護層に光を照射して前記第１保護層を露光することで、前記第１保護層に所定のパターンを形成する第１パターン形成工程と、前記所定のパターンが形成された前記第１保護層をマスクとして前記有機半導体層をエッチングすることで、前記有機半導体層に前記所定のパターンを形成する第２パターン形成工程と、を含む。 According to a first aspect of the present invention, a first film formation step of forming an organic semiconductor layer on a substrate on which an electrode is formed, and a second film formation of forming a first protective layer on the surface of the organic semiconductor layer A first pattern forming step of forming a predetermined pattern on the first protective layer by exposing the first protective layer by irradiating the first protective layer with light; and forming the predetermined pattern And a second pattern forming step of forming the predetermined pattern on the organic semiconductor layer by etching the organic semiconductor layer using the first protective layer as a mask.
　本発明の第２の態様は、電子デバイスの製造方法であって、第１の態様の前記半導体素子の製造方法を含む。 A second aspect of the present invention is a method for manufacturing an electronic device, and includes the method for manufacturing the semiconductor element of the first aspect.
　本発明の第３の態様は、電極が形成された基板上に成膜された有機半導体層と、前記有機半導体層の表面に成膜された第１保護層と、前記第１保護層を覆うように成膜された第２保護層と、を備えた半導体素子であって、前記第１保護層は、光によって硬化された第１の樹脂で構成される。 A third aspect of the present invention covers an organic semiconductor layer formed on a substrate on which an electrode is formed, a first protective layer formed on the surface of the organic semiconductor layer, and the first protective layer. The first protective layer is made of a first resin that is cured by light.
　本発明の第４の態様は、電極が形成された基板上に成膜された有機半導体層と、前記有機半導体層の表面に成膜された第１保護層と、前記第１保護層を覆うように成膜された第２保護層と、を備えた半導体素子であって、前記第２保護層は、前記第１保護層に比べ第１の溶媒に対する溶解度が低い。 According to a fourth aspect of the present invention, the organic semiconductor layer formed on the substrate on which the electrode is formed, the first protective layer formed on the surface of the organic semiconductor layer, and the first protective layer are covered. The second protective layer is formed as described above, and the second protective layer has lower solubility in the first solvent than the first protective layer.
　本発明の第５の態様は、電子デバイスであって、第３または第４の態様の半導体素子を有する。
　上記の目的、特徴及び利点は、添付した図面を参照して説明される以下の実施の形態の説明から容易に了解されるであろう。 A fifth aspect of the present invention is an electronic device having the semiconductor element of the third or fourth aspect.
The above objects, features and advantages will be readily understood from the following description of embodiments with reference to the accompanying drawings.
図１Ａ～図１Ｃは、ボトムゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子のゲート電極層の形成工程を示す図である。1A to 1C are diagrams showing a process of forming a gate electrode layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor. 図２Ａ～図２Ｃは、ボトムゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子のゲート電極層の形成工程を示す図である。2A to 2C are diagrams showing a process of forming a gate electrode layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor. 図３Ａ～図３Ｃは、ゲート電極層の形成後に、ボトムゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子の絶縁体層の形成工程を示す図である。FIG. 3A to FIG. 3C are diagrams showing a process of forming an insulator layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor after forming a gate electrode layer. 図４Ａ～図４Ｃは、絶縁体層の形成後に、ボトムゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子のソース・ドレイン電極層の形成工程を示す図である。4A to 4C are diagrams showing a process of forming a source / drain electrode layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor after the formation of the insulator layer. 図５Ａ～図５Ｃは、絶縁体層の形成後に、ボトムゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子のソース・ドレイン電極層の形成工程を示す図である。FIG. 5A to FIG. 5C are views showing a process of forming a source / drain electrode layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor after forming an insulator layer. 図６Ａ～図６Ｃは、ソース・ドレイン電極層の形成後に、ボトムゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子の有機半導体層および第１保護層の形成工程を示す図である。6A to 6C are diagrams showing a process of forming an organic semiconductor layer and a first protective layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor after the formation of the source / drain electrode layers. 図７Ａ～図７Ｃは、ソース・ドレイン電極層の形成後に、ボトムゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子の有機半導体層および第１保護層の形成工程を示す図である。FIG. 7A to FIG. 7C are diagrams showing a process of forming an organic semiconductor layer and a first protective layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor after the formation of the source / drain electrode layers. 図８Ａ～図８Ｃは、有機半導体層および第１保護層の形成後に、ボトムゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子の第２保護層の形成工程を示す図である。FIGS. 8A to 8C are diagrams illustrating a process of forming a second protective layer of a semiconductor element having a bottom gate / bottom contact type organic thin film transistor after the formation of the organic semiconductor layer and the first protective layer. 実施例１において、図９Ａは、パターンが形成された第１保護層の光学顕微鏡像を示す図、図９Ｂは、パターニングされた有機半導体層の光学顕微鏡像を示す図である。In Example 1, FIG. 9A is a diagram showing an optical microscope image of the first protective layer on which a pattern is formed, and FIG. 9B is a diagram showing an optical microscope image of the patterned organic semiconductor layer. 実施例２において、図１０Ａは、基板上に作製したゲート電極の写真を示す図、図１０Ｂは、ゲート電極の光学顕微鏡像を示す図である。In Example 2, FIG. 10A is a diagram showing a photograph of a gate electrode fabricated on a substrate, and FIG. 10B is a diagram showing an optical microscope image of the gate electrode. 実施例２において、図１１Ａは、ゲート電極上にパターニング成膜した絶縁体層の写真を示す図、図１１Ｂは、ゲート電極付近の絶縁体層の光学顕微鏡像を示す図である。In Example 2, FIG. 11A is a diagram showing a photograph of an insulator layer formed by patterning on a gate electrode, and FIG. 11B is a diagram showing an optical microscope image of the insulator layer near the gate electrode. 実施例２において、図１２Ａは、絶縁体層上に形成したソース電極およびドレイン電極の写真を示す図、図１２Ｂは、ゲート電極付近の光学顕微鏡像を示す図である。In Example 2, FIG. 12A is a diagram showing a photograph of the source electrode and the drain electrode formed on the insulator layer, and FIG. 12B is a diagram showing an optical microscope image near the gate electrode. 実施例２において、ＴＩＰＳペンタセンの有機半導体をディップコートにより成膜した基板の光学顕微鏡像を示す図である。In Example 2, it is a figure which shows the optical microscope image of the board | substrate which formed the organic semiconductor of TIPS pentacene into the film by dip coating. 実施例２において、第１保護層をパターン形成した基板の光学顕微鏡像を示す図である。In Example 2, it is a figure which shows the optical microscope image of the board | substrate which patterned the 1st protective layer. 実施例２において、有機半導体層をパターニングした基板の光学顕微鏡像を示す図である。In Example 2, it is a figure which shows the optical microscope image of the board | substrate which patterned the organic-semiconductor layer. 実施例２において、第２保護層をパターン形成した基板の光学顕微鏡像を示す図である。In Example 2, it is a figure which shows the optical microscope image of the board | substrate which patterned the 2nd protective layer. 実施例２において作製されたパッシベーション膜付き有機薄膜トランジスタの特性の評価結果を示すグラフである。It is a graph which shows the evaluation result of the characteristic of the organic thin-film transistor with a passivation film produced in Example 2. 図１８Ａ～図１８Ｃは、トップゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子のソース・ドレイン電極層の形成工程を示す図である。FIG. 18A to FIG. 18C are diagrams showing a process of forming a source / drain electrode layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor. 図１９Ａ～図１９Ｃは、トップゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子のソース・ドレイン電極層の形成工程を示す図である。FIG. 19A to FIG. 19C are diagrams showing a process of forming a source / drain electrode layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor. 図２０Ａ～図２０Ｃは、ソース・ドレイン電極層の形成後に、トップゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子の有機半導体層および第１保護層の形成工程を示す図である。20A to 20C are views showing a process of forming an organic semiconductor layer and a first protective layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor after the formation of the source / drain electrode layers. 図２１Ａ～図２１Ｃは、ソース・ドレイン電極層の形成後に、トップゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子の有機半導体層および第１保護層の形成工程を示す図である。FIG. 21A to FIG. 21C are diagrams showing a process of forming an organic semiconductor layer and a first protective layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor after the formation of the source / drain electrode layers. 図２２Ａ～図２２Ｃは、有機半導体層および第１保護層の形成後に、トップゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子の第２保護層の形成工程を示す図である。FIG. 22A to FIG. 22C are views showing a process of forming a second protective layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor after the formation of the organic semiconductor layer and the first protective layer. 図２３Ａ～図２３Ｃは、第２保護層の形成後に、トップゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子のゲート電極層の形成工程を示す図である。FIG. 23A to FIG. 23C are diagrams showing a process of forming a gate electrode layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor after the formation of the second protective layer. 図２４Ａ、図２４Ｂは、第２保護層の形成後に、トップゲート・ボトムコンタクト型の有機薄膜トランジスタを有する半導体素子のゲート電極層の形成工程を示す図である。24A and 24B are diagrams illustrating a process of forming a gate electrode layer of a semiconductor element having a top gate / bottom contact type organic thin film transistor after the formation of the second protective layer.
　本発明の態様に係る半導体素子の製造方法、その半導体素子の製造方法を含む電子デバイスの製造方法、半導体素子、および、その半導体素子を有する電子デバイスについて、好適な実施の形態を掲げ、添付の図面を参照しながら以下、詳細に説明する。なお、本発明の態様は、これらの実施の形態に限定されるものではなく、多様な変更または改良を加えたものも含まれる。つまり、以下に記載した構成要素には、当業者が容易に想定できるもの、実質的に同一のものが含まれ、以下に記載した構成要素は適宜組み合わせることが可能である。また、本発明の要旨を逸脱しない範囲で構成要素の種々の省略、置換または変更を行うことができる。 DESCRIPTION OF EXEMPLARY EMBODIMENTS A method for manufacturing a semiconductor element according to an aspect of the present invention, a method for manufacturing an electronic device including the method for manufacturing the semiconductor element, a semiconductor element, and an electronic device having the semiconductor element are described with reference to preferred embodiments. Hereinafter, it will be described in detail with reference to the drawings. In addition, the aspect of this invention is not limited to these embodiment, What added the various change or improvement is included. That is, the constituent elements described below include those that can be easily assumed by those skilled in the art and substantially the same elements, and the constituent elements described below can be appropriately combined. In addition, various omissions, substitutions, or changes of the components can be made without departing from the scope of the present invention.
［第１の実施の形態］
　第１の実施の形態では、ボトムゲート・ボトムコンタクト型の有機薄膜トランジスタ（有機ＴＦＴ）を有する半導体素子（パッシベーション膜付き有機薄膜トランジスタ）の製造方法について説明する。第１の実施の形態の半導体素子は、基板上に、ゲート電極層、絶縁体層、ソース・ドレイン電極層、有機半導体層、第１保護層、および、第２保護層が前記の順で積層された構造を有する。 [First Embodiment]
In the first embodiment, a manufacturing method of a semiconductor element (an organic thin film transistor with a passivation film) having a bottom gate / bottom contact type organic thin film transistor (organic TFT) will be described. In the semiconductor element of the first embodiment, a gate electrode layer, an insulator layer, a source / drain electrode layer, an organic semiconductor layer, a first protective layer, and a second protective layer are stacked on the substrate in the order described above. Has a structured.
　本第１の実施の形態では、図示しないが、基板をロール状に巻いた供給ロールから供給された基板に対して所定の処理を施して回収ロールで巻き取るロール・ツー・ロール（Ｒｏｌｌ　Ｔｏ　Ｒｏｌｌ）方式の製造システムによって半導体素子を製造するものとする。したがって、半導体素子が形成される基板は、フレキシブルな、つまり、可撓性を有するシート状の基板である必要がある。 In the first embodiment, although not shown, a roll-to-roll (Roll To Roll) that performs a predetermined process on a substrate supplied from a supply roll obtained by winding the substrate in a roll shape and winds the substrate with a recovery roll. ) Method of manufacturing semiconductor devices. Therefore, the substrate on which the semiconductor element is formed needs to be a flexible, that is, a sheet-like substrate having flexibility.
　この基板は、例えば、樹脂フィルムやステンレス鋼等の金属または合金からなる箔（フォイル）等が用いられる。樹脂フィルムの材質としては、例えば、ポリエチレン樹脂、ポリプロピレン樹脂、ポリエステル樹脂、エチレンビニル共重合体樹脂、ポリ塩化ビニル樹脂、セルロース樹脂、ポリアミド樹脂、ポリイミド樹脂、ポリカーボネート樹脂、ポリスチレン樹脂、および、酢酸ビニル樹脂のうち、少なくとも１つ以上を含んだものが挙げられる。また、基板の厚みや剛性（ヤング率）は、露光装置等の搬送路を通る際に、基板に座屈による折れ目や非可逆的なシワが生じないような範囲であればよい。基板の母材として、厚みが２５μｍ～２００μｍ程度のＰＥＴ（ポリエチレンテレフタレート）やＰＥＮ（ポリエチレンナフタレート）等のフィルムは、好適なシート基板の典型である。 For example, a foil (foil) made of a metal or an alloy such as a resin film or stainless steel is used for the substrate. Examples of the resin film material include polyethylene resin, polypropylene resin, polyester resin, ethylene vinyl copolymer resin, polyvinyl chloride resin, cellulose resin, polyamide resin, polyimide resin, polycarbonate resin, polystyrene resin, and vinyl acetate resin. Among these, those containing at least one or more are listed. Further, the thickness and rigidity (Young's modulus) of the substrate may be in a range that does not cause folds or irreversible wrinkles due to buckling in the substrate when passing through a conveyance path such as an exposure apparatus. As a base material of the substrate, a film such as PET (polyethylene terephthalate) or PEN (polyethylene naphthalate) having a thickness of about 25 μm to 200 μm is typical of a suitable sheet substrate.
　基板は、基板に施される処理において熱を受ける場合があるため、熱膨張係数が顕著に大きくない材質からなるものを選定することが好ましい。例えば、無機フィラーを樹脂フィルムに混合することによって熱膨張係数を抑えることができる。無機フィラーは、例えば、酸化チタン、酸化亜鉛、アルミナ、または、酸化ケイ素等でもよい。また、基板は、フロート法等で製造された厚さ１００μｍ程度の極薄ガラスの単層体であってもよいし、この極薄ガラスに上記の樹脂フィルム、箔等を貼り合わせた積層体であってもよい。 Since the substrate may receive heat in the process applied to the substrate, it is preferable to select a substrate made of a material that does not have a significantly large thermal expansion coefficient. For example, the thermal expansion coefficient can be suppressed by mixing an inorganic filler with a resin film. The inorganic filler may be, for example, titanium oxide, zinc oxide, alumina, or silicon oxide. Further, the substrate may be a single layer of ultrathin glass having a thickness of about 100 μm manufactured by a float process or the like, or a laminate in which the above resin film, foil, or the like is bonded to the ultrathin glass. There may be.
　ところで、基板の可撓性とは、基板に自重程度の力を加えてもせん断したり破断したりすることはなく、その基板を撓ませることが可能な性質をいう。また、自重程度の力によって湾曲する性質も可撓性に含まれる。また、基板の材質、大きさ、厚さ、基板上に成膜される層構造、温度、湿度等の環境等に応じて、可撓性の程度は変わる。いずれにしろ、ロール・ツー・ロール方式の製造システム内の搬送路に設けられる各種の搬送用ローラ、回転ドラム等の搬送方向転換用の部材に基板を正しく巻き付けた場合に、座屈して折り目がついたり、破損（破れや割れが発生）したりせずに、基板を滑らかに搬送できれば、可撓性の範囲と言える。以下、半導体素子の各層の形成について説明する。 By the way, the flexibility of a substrate means a property that the substrate can be bent without being sheared or broken even if a force of its own weight is applied to the substrate. In addition, flexibility includes a property of bending by a force of about its own weight. The degree of flexibility varies depending on the material, size and thickness of the substrate, the layer structure formed on the substrate, the environment such as temperature and humidity, and the like. In any case, when the substrate is correctly wound around various conveying rollers, rotating drums, and other members for conveying direction provided in the conveying path in the roll-to-roll manufacturing system, the folds are buckled. If the substrate can be smoothly transported without being attached or damaged (breaking or cracking), it can be said to be in the range of flexibility. Hereinafter, formation of each layer of the semiconductor element will be described.
　（ゲート電極層の形成について）
　ＰＥＴ等のフレキシブルな基板Ｐは難めっき部材であるため、図１Ａに示すように、まず基板Ｐにアミン層１０を形成する。アミン層１０は、１級または２級アミノ基を有するシランカップリング剤層である。つまり、基板Ｐの表面に、１級または２級アミノ基を有するシランカップリング剤（アミン分子）に溶媒を加えたアミン溶液を塗布する。塗布の方法としては、スピンコート、ディップコート、スプレーコート、ロールコート、刷毛塗り、フレキソ印刷、または、スクリーン印刷等の通常知られた方法を用いることができる。次いで、熱処理により溶媒を揮発させてアミン層１０を成膜する。アミン層１０は、極薄のシランカップリング剤層であるため光散乱はなく、透明な皮膜である。そのため、ゲート電極層を作製する際にアミン層１０を全面に成膜すればよく、成膜が容易であることも利点となる。 (Regarding the formation of the gate electrode layer)
Since a flexible substrate P such as PET is a difficult-to-plate member, an amine layer 10 is first formed on the substrate P as shown in FIG. 1A. The amine layer 10 is a silane coupling agent layer having a primary or secondary amino group. That is, an amine solution obtained by adding a solvent to a silane coupling agent (amine molecule) having a primary or secondary amino group is applied to the surface of the substrate P. As a coating method, a generally known method such as spin coating, dip coating, spray coating, roll coating, brush coating, flexographic printing, or screen printing can be used. Next, the solvent is volatilized by heat treatment to form the amine layer 10. Since the amine layer 10 is an extremely thin silane coupling agent layer, there is no light scattering and it is a transparent film. Therefore, the amine layer 10 may be formed on the entire surface when forming the gate electrode layer, and it is also advantageous that the film formation is easy.
　そして、図１Ｂに示すように、アミン層１０の上にポジ型のフォトレジスト層１２を形成する。なお、フォトレジスト層１２は、アミン層１０の上にフォトレジスト材料を塗布して、プリベイクすることで形成される。次に、所定のパターンが形成されたマスクＭ１（ゲート電極Ｇを形成する領域に開口部ｍａ１を有するマスクＭ１）を介して光（本実施の形態ではＵＶ光（紫外線光）とする）を照射することで、フォトレジスト層１２を露光する。その後、フォトレジスト層１２（基板Ｐ）を現像液（例えば、ＴＭＡＨ等）に浸漬することで、図１Ｃに示すように、ＵＶ光が照射された部分（露光された部分）のフォトレジスト層１２が溶解して除去される。これにより、フォトレジスト層１２には、ゲート電極Ｇに応じた所定のパターンが形成される。つまり、ゲート電極Ｇを形成する領域に開口部１２ａを有するパターンが形成される。 Then, as shown in FIG. 1B, a positive type photoresist layer 12 is formed on the amine layer 10. The photoresist layer 12 is formed by applying a photoresist material on the amine layer 10 and prebaking. Next, light (in this embodiment, UV light (ultraviolet light)) is irradiated through a mask M1 (a mask M1 having an opening ma1 in a region where the gate electrode G is formed) on which a predetermined pattern is formed. As a result, the photoresist layer 12 is exposed. Thereafter, by immersing the photoresist layer 12 (substrate P) in a developing solution (for example, TMAH or the like), as shown in FIG. 1C, a portion of the photoresist layer 12 irradiated with UV light (exposed portion). Dissolves and is removed. As a result, a predetermined pattern corresponding to the gate electrode G is formed in the photoresist layer 12. That is, a pattern having the opening 12a is formed in a region where the gate electrode G is formed.
　次に、図２Ａに示すように、無電解めっきに用いる触媒（Ｐｄ）１４を含む触媒溶液を基板Ｐ上に付与する。アミン層１０の上には所定のパターンが形成されたフォトレジスト層１２が積層されているので、開口部１２ａによって露出した領域のアミン層１０上に触媒１４が付与される。アミン層１０に含まれている１級または２級アミノ基は、触媒溶液に含まれているＰｄイオンをＰｄ金属に還元し、これを捕捉する性質を有する。そのため、通常は必要となる、Ｐｄイオンを還元する活性化処理を省くことができ、プロセスをエコ化することができる。その後、ニッケルリン等の無電解めっき液に基板Ｐ全体を浸漬することにより、図２Ｂに示すように、触媒１４表面に金属イオンを還元して析出させる。この析出した金属層がゲート電極層１６となる。したがって、基板Ｐ上にゲート電極Ｇを有するゲート電極層１６が選択的に形成される。その後、残存するフォトレジスト層１２の全面にＵＶ光を露光して、フォトレジスト層１２（基板Ｐ）を現像液に浸漬することで、図２Ｃに示すように、フォトレジスト層１２を除去する。 Next, as shown in FIG. 2A, a catalyst solution containing a catalyst (Pd) 14 used for electroless plating is applied on the substrate P. Since the photoresist layer 12 having a predetermined pattern is laminated on the amine layer 10, the catalyst 14 is applied on the amine layer 10 in the region exposed by the opening 12a. The primary or secondary amino group contained in the amine layer 10 has a property of reducing Pd ions contained in the catalyst solution to Pd metal and capturing them. Therefore, the activation process for reducing Pd ions, which is normally required, can be omitted, and the process can be made ecological. Then, by immersing the entire substrate P in an electroless plating solution such as nickel phosphorus, metal ions are reduced and deposited on the surface of the catalyst 14 as shown in FIG. 2B. This deposited metal layer becomes the gate electrode layer 16. Therefore, the gate electrode layer 16 having the gate electrode G is selectively formed on the substrate P. Thereafter, the entire surface of the remaining photoresist layer 12 is exposed to UV light, and the photoresist layer 12 (substrate P) is immersed in a developer to remove the photoresist layer 12 as shown in FIG. 2C.
　以上の工程により、基板Ｐ上にゲート電極層１６を形成する。アミン層１０は、非常に薄いため基板Ｐの表面をほとんど粗化することなく成膜可能であり、高平坦性のゲート電極層１６が得られる。そのため、リークの少ない多層金属構造の作製が可能である。なお、ゲート電極層１６を、アルミ等の金属膜をエッチングする手法や印刷法のパターニングによって形成することも可能である。 Through the above steps, the gate electrode layer 16 is formed on the substrate P. Since the amine layer 10 is very thin, it can be formed without roughening the surface of the substrate P, and a highly flat gate electrode layer 16 can be obtained. Therefore, it is possible to produce a multilayer metal structure with little leakage. Note that the gate electrode layer 16 can also be formed by a method of etching a metal film such as aluminum or a patterning by a printing method.
　（絶縁体層の形成について）
　絶縁体層１８は、絶縁性を有する光硬化型感光性樹脂から構成され、例えば、ＵＶ光硬化型アクリル樹脂、ＵＶ光硬化型エポキシ樹脂、ＵＶ光硬化型エン・チオール樹脂、または、ＵＶ光硬化型シリコーン樹脂等で構成される。光硬化型樹脂を用いるため、ＵＶ光の照射によって絶縁体層１８のパターニングを行うことができる。 (About formation of insulator layer)
The insulator layer 18 is made of an insulating photo-curing photosensitive resin, for example, UV photo-curing acrylic resin, UV photo-curing epoxy resin, UV photo-curing en-thiol resin, or UV photo-curing. Type silicone resin. Since the photocurable resin is used, the insulator layer 18 can be patterned by irradiation with UV light.
　まず、図３Ａに示すように、絶縁体層溶液をゲート電極層１６が形成された基板Ｐ上に塗布して絶縁体層１８を成膜し、所定のパターンが形成されたマスクＭ２（絶縁体層１８を形成したい領域に開口部ｍａ２を有するマスクＭ２）を介して絶縁体層１８にＵＶ光を照射する。その結果、図３Ｂに示すように、ＵＶ光が照射された領域（絶縁体層１８を形成したい領域）の絶縁体層１８が硬化する。図３Ｂでは、硬化した部分をドットで表し、硬化していない部分をハッチングで示している。このように、マスクＭ２を用いることで、絶縁体層１８を選択的に硬化させることができる。なお、この際に、ＵＶ光が照射される領域の化学反応を促進させるための熱処理を加えると一層好適である。次いで、図３Ｃに示すように、ＵＶ光が照射されていない部分（ハッチングで表された部分）を現像液で溶解させて除去することで、マスクＭ２に応じた所定のパターンが形成された絶縁体層１８が形成される。つまり、ＵＶ光が照射されて硬化した部分の絶縁体層１８が残る。 First, as shown in FIG. 3A, an insulator layer solution is applied onto a substrate P on which a gate electrode layer 16 is formed to form an insulator layer 18, and a mask M2 (insulator) on which a predetermined pattern is formed. The insulator layer 18 is irradiated with UV light through a mask M2) having an opening ma2 in a region where the layer 18 is to be formed. As a result, as shown in FIG. 3B, the insulator layer 18 in the region irradiated with UV light (the region where the insulator layer 18 is to be formed) is cured. In FIG. 3B, the hardened part is represented by dots, and the uncured part is hatched. Thus, the insulator layer 18 can be selectively cured by using the mask M2. In this case, it is more preferable to add a heat treatment for promoting a chemical reaction in a region irradiated with UV light. Next, as shown in FIG. 3C, a portion that is not irradiated with UV light (portion represented by hatching) is removed by dissolving with a developing solution to form a predetermined pattern according to the mask M2. A body layer 18 is formed. That is, the portion of the insulator layer 18 that has been cured by being irradiated with UV light remains.
　以上の工程により、ゲート電極層１６上に絶縁体層１８を形成する。なお、ゲート電極Ｇとソース・ドレイン電極Ｓ、Ｄ（図５Ａ参照）との間でのリークを抑制するためには、絶縁体層１８は、数１００ｎｍの厚みが必要となる。絶縁体層１８の厚みは、樹脂の濃度や塗布条件により制御することができる。また、絶縁体層１８を、光硬化型樹脂や熱硬化型樹脂等の材料を印刷法等のパターニングによって形成することも可能である。そのため、絶縁性を有している塗布可能な材料であれば適用可能である。 Through the above steps, the insulator layer 18 is formed on the gate electrode layer 16. In order to suppress leakage between the gate electrode G and the source / drain electrodes S and D (see FIG. 5A), the insulator layer 18 needs to have a thickness of several hundred nm. The thickness of the insulator layer 18 can be controlled by the resin concentration and application conditions. It is also possible to form the insulator layer 18 by patterning a material such as a photocurable resin or a thermosetting resin, such as a printing method. Therefore, any applicable material having insulating properties can be applied.
　（ソース・ドレイン電極層の形成について）
　ソース・ドレイン電極層は、上述したゲート電極層１６の作製手順と略同様のプロセスを経ることで作製できる。まず、図４Ａに示すように、絶縁体層１８上にアミン層２０を形成する。そして、図４Ｂに示すように、アミン層２０の上にポジ型のフォトレジスト層２２を形成し、所定のパターンが形成されたマスクＭ３（ソース電極Ｓおよびドレイン電極Ｄを形成する領域に開口部ｍａ３を有するマスクＭ３）を介してＵＶ光を照射することで、フォトレジスト層２２を露光する。その後、フォトレジスト層２２（基板Ｐ）を現像液に浸漬することで、図４Ｃに示すように、ＵＶ光が照射された部分（露光された部分）のフォトレジスト層２２が溶解して除去される。これにより、フォトレジスト層２２には、ソース電極Ｓおよびドレイン電極Ｄに応じたパターンが形成される。つまり、ソース電極Ｓおよびドレイン電極Ｄを形成する領域に開口部２２ａを有するパターンが形成される。 (About formation of source / drain electrode layers)
The source / drain electrode layer can be manufactured through a process substantially similar to the above-described manufacturing procedure of the gate electrode layer 16. First, as shown in FIG. 4A, an amine layer 20 is formed on the insulator layer 18. Then, as shown in FIG. 4B, a positive photoresist layer 22 is formed on the amine layer 20, and a mask M3 (an opening is formed in a region where the source electrode S and the drain electrode D are formed) on which a predetermined pattern is formed. The photoresist layer 22 is exposed by irradiating UV light through a mask M3) having ma3. Thereafter, by immersing the photoresist layer 22 (substrate P) in a developing solution, as shown in FIG. 4C, the photoresist layer 22 in the portion irradiated with UV light (exposed portion) is dissolved and removed. The Thereby, a pattern corresponding to the source electrode S and the drain electrode D is formed in the photoresist layer 22. That is, a pattern having the opening 22a is formed in a region where the source electrode S and the drain electrode D are formed.
　次に、無電解めっきに用いる触媒（Ｐｄ）２４を含む触媒溶液を基板Ｐ上に付与し、ニッケルリン等の無電解めっき液に基板Ｐ全体を浸漬することにより、図５Ａに示すように、触媒２４の表面に金属イオンを還元して析出させる。アミン層２０の上には所定のパターンが形成されたフォトレジスト層２２が積層されているので、開口部２２ａに露出した領域のアミン層２０上に触媒２４が付与され、この触媒２４の表面に金属が析出する。この析出した金属層がソース・ドレイン電極層２６となる。したがって、基板Ｐ上（絶縁体層１８上）に、ソース電極Ｓおよびドレイン電極Ｄを有するソース・ドレイン電極層（金属層）２６が選択的に形成される。その後、残存するフォトレジスト層２２の全面にＵＶ光を露光して、フォトレジスト層２２（基板Ｐ）を現像液に浸漬することで、図５Ｂに示すように、フォトレジスト層２２を除去する。 Next, by applying a catalyst solution containing the catalyst (Pd) 24 used for electroless plating onto the substrate P and immersing the entire substrate P in an electroless plating solution such as nickel phosphorus, as shown in FIG. 5A, Metal ions are reduced and deposited on the surface of the catalyst 24. Since a photoresist layer 22 having a predetermined pattern is laminated on the amine layer 20, a catalyst 24 is applied on the amine layer 20 in a region exposed to the opening 22a, and the surface of the catalyst 24 is applied. Metal is deposited. The deposited metal layer becomes the source / drain electrode layer 26. Therefore, the source / drain electrode layer (metal layer) 26 having the source electrode S and the drain electrode D is selectively formed on the substrate P (on the insulator layer 18). Thereafter, the entire surface of the remaining photoresist layer 22 is exposed to UV light, and the photoresist layer 22 (substrate P) is immersed in a developer to remove the photoresist layer 22 as shown in FIG. 5B.
　そして、基板Ｐを置換金めっき浴に浸漬させた後、還元金めっき浴に浸漬させることで、図５Ｃに示すように、ソース・ドレイン電極層２６の表面を金２８で被覆する。これにより、ソース電極Ｓおよびドレイン電極Ｄが金２８で被覆されることになる。ペンタセン等のＨＯＭＯ準位の高い有機半導体の層をソース・ドレイン電極層２６の表面に形成する場合は（図６Ａ参照）、ソース電極Ｓおよびドレイン電極Ｄを金２８で皮膜することが望ましい。なお、金２８で被覆するようにしたが、有機半導体材料のＨＯＭＯ／ＬＵＭＯ準位に適した仕事関数を持つ金属材料で皮膜すればよい。 Then, after immersing the substrate P in the displacement gold plating bath, the surface of the source / drain electrode layer 26 is covered with gold 28 as shown in FIG. As a result, the source electrode S and the drain electrode D are covered with the gold 28. When an organic semiconductor layer having a high HOMO level such as pentacene is formed on the surface of the source / drain electrode layer 26 (see FIG. 6A), it is desirable to coat the source electrode S and the drain electrode D with gold 28. In addition, although it coat | covered with gold | metal | money 28, what is necessary is just to coat | cover with the metal material which has a work function suitable for the HOMO / LUMO level of organic-semiconductor material.
　以上の工程により、絶縁体層１８上にソース・ドレイン電極層２６を形成する。この方法によれば、絶縁体層１８の表面を粗化することなく、高平坦性のソース・ドレイン電極層２６を作製することが可能であるため、後述する有機半導体層３０と絶縁膜界面との平坦性を維持することができる。そのため、キャリア移動抵抗が増大することなく、湿式プロセスで有機薄膜トランジスタを作製することができる。また、高平坦性の金属層が得られるため、リークの少ない２層以上の多層金属構造の作製が可能である。なお、絶縁膜界面とは、ソース電極Ｓおよびドレイン電極Ｄ間の絶縁体層１８の表面部分のことをいう。 Through the above steps, the source / drain electrode layer 26 is formed on the insulator layer 18. According to this method, since the source / drain electrode layer 26 with high flatness can be produced without roughening the surface of the insulator layer 18, the organic semiconductor layer 30 and the insulating film interface described later The flatness can be maintained. Therefore, an organic thin film transistor can be manufactured by a wet process without increasing carrier transfer resistance. In addition, since a highly flat metal layer can be obtained, a multilayer metal structure having two or more layers with less leakage can be manufactured. The insulating film interface refers to a surface portion of the insulator layer 18 between the source electrode S and the drain electrode D.
　（有機半導体層の形成（成膜）について）
　ゲート電極層１６、絶縁体層１８、および、ソース・ドレイン電極層２６が形成された基板Ｐ上に有機半導体層３０を成膜する。ＴＩＰＳペンタセン（６,１３－ビス(トリイソプロピルシリルエチニル)ペンタセン）に代表される可溶性ペンタセンや、Ｐ３ＨＴ（ポリ(３－ヘキシルチオフェン－２，５－ジイル)）等の有機半導体ポリマー等の有機半導体は、トルエン等の有機溶媒に可溶である。そのため、有機半導体が有機溶媒に溶解した有機半導体溶液を、基板Ｐ上に塗布した後、加熱して溶媒を蒸発（揮発）させることにより、容易に有機半導体層３０を成膜することができる。図６Ａは、基板Ｐ上に成膜された有機半導体層３０を示す。なお、有機半導体層３０を湿式法によって作製しているが、昇華法、転写法等によって有機半導体層３０を成膜してもよい。以上の工程により、有機半導体層３０を成膜する。 (Regarding the formation (deposition) of organic semiconductor layers)
An organic semiconductor layer 30 is formed on the substrate P on which the gate electrode layer 16, the insulator layer 18, and the source / drain electrode layer 26 are formed. Organic semiconductors such as soluble pentacene typified by TIPS pentacene (6,13-bis (triisopropylsilylethynyl) pentacene) and organic semiconductor polymers such as P3HT (poly (3-hexylthiophene-2,5-diyl)) Soluble in organic solvents such as toluene. Therefore, after the organic semiconductor solution in which the organic semiconductor is dissolved in the organic solvent is applied on the substrate P, the organic semiconductor layer 30 can be easily formed by heating to evaporate (volatilize) the solvent. FIG. 6A shows the organic semiconductor layer 30 formed on the substrate P. Although the organic semiconductor layer 30 is manufactured by a wet method, the organic semiconductor layer 30 may be formed by a sublimation method, a transfer method, or the like. The organic semiconductor layer 30 is formed by the above process.
　（第１保護層の形成について）
　第１のパッシベーション膜としての第１保護層３２は、感光性樹脂から構成される。そのため、ＵＶ光の照射によって第１保護層３２のパターニングを行うことができる。まず、図６Ｂに示すように、第１の樹脂と、第１の樹脂をＵＶ光によって硬化させる光重合開始剤（第１の光重合開始剤）と、第１の樹脂および光重合開始剤を溶解する第１の溶媒とを含む第１保護層溶液（第１の溶液）を塗布し、有機半導体層３０の表面に第１保護層３２を成膜する。第１の樹脂としては、例えば、水またはフッ素系の溶媒によって溶解する樹脂（水溶性樹脂またはフッ素系溶媒溶解性樹脂）を用いることができ、第１の溶媒としては、例えば、水またはフッ素系の溶媒を用いることができる。第１の樹脂として水溶性樹脂、第１の溶媒として水を用いた場合の第１保護層３２の水接触角は、例えば、６２度である。なお、第１の樹脂または第１の溶媒が光重合開始剤の性質を有する場合は、第１保護層溶液は、光重合開始剤を含まなくてもよい。 (Regarding the formation of the first protective layer)
The first protective layer 32 as the first passivation film is made of a photosensitive resin. Therefore, the first protective layer 32 can be patterned by irradiation with UV light. First, as shown in FIG. 6B, a first resin, a photopolymerization initiator (first photopolymerization initiator) for curing the first resin with UV light, a first resin and a photopolymerization initiator are prepared. A first protective layer solution (first solution) containing a first solvent to be dissolved is applied to form a first protective layer 32 on the surface of the organic semiconductor layer 30. As the first resin, for example, a resin that dissolves in water or a fluorine-based solvent (water-soluble resin or fluorine-based solvent-soluble resin) can be used. As the first solvent, for example, water or a fluorine-based solvent can be used. These solvents can be used. When the water-soluble resin is used as the first resin and water is used as the first solvent, the water contact angle of the first protective layer 32 is, for example, 62 degrees. In addition, when the 1st resin or the 1st solvent has the property of a photoinitiator, the 1st protective layer solution does not need to contain a photoinitiator.
　そして、図６Ｃに示すように、所定のパターンが形成されたマスクＭ４（第１保護層３２を形成したい領域に開口部ｍａ４を有するマスクＭ４）を介して、第１保護層３２にＵＶ光を照射する。その結果、図７Ａに示すように、ＵＶ光が照射された領域（第１保護層３２を形成したい領域）の第１保護層３２が硬化する。図７Ａでは、硬化した部分と硬化していない部分とにおけるハッチングの向きを異ならせて表している。このように、マスクＭ４を用いることで、第１保護層３２を選択的に硬化させることができる。なお、この際に、ＵＶ光が照射される領域の化学反応を促進させるための熱処理を加えると一層好適である。次いで、図７Ｂに示すように、ＵＶ光が照射されていない部分を第１の溶媒（水またはフッ素系の溶媒等）で溶解させて除去することで、マスクＭ４に応じた所定のパターンが形成された第１保護層３２が形成される。つまり、ＵＶ光が照射されて硬化した部分の第１保護層３２が残る。この第１保護層３２を形成したい領域は、ソース電極Ｓとドレイン電極Ｄと間の領域を含む。 Then, as shown in FIG. 6C, UV light is applied to the first protective layer 32 through a mask M4 (a mask M4 having an opening ma4 in a region where the first protective layer 32 is to be formed) on which a predetermined pattern is formed. Irradiate. As a result, as shown in FIG. 7A, the first protective layer 32 in the region irradiated with UV light (the region where the first protective layer 32 is to be formed) is cured. In FIG. 7A, the direction of hatching in the hardened part and the non-hardened part is shown differently. Thus, the 1st protective layer 32 can be selectively hardened by using mask M4. In this case, it is more preferable to add a heat treatment for promoting a chemical reaction in a region irradiated with UV light. Next, as shown in FIG. 7B, a predetermined pattern corresponding to the mask M4 is formed by dissolving and removing the portion not irradiated with UV light with a first solvent (water or a fluorine-based solvent or the like). The first protective layer 32 is formed. That is, the portion of the first protective layer 32 that has been cured by being irradiated with UV light remains. The region where the first protective layer 32 is to be formed includes a region between the source electrode S and the drain electrode D.
　この第１保護層溶液としては、東洋合成工業株式会社製のＢＩＯＳＵＲＦＩＮＥ（登録商標）－ＡＷＰ－ＭＲＨを水で３ｗｔ％に希釈したものを用いることができる。また、例えば、ビニルアルコール・酸化ビニルの共重合物の水溶性樹脂と、３－［４－アジドフェニル］－Ｎ－（３－ホルミル）プロピル－２－［モルホリノメチルフェニルカルボニルアミノ］プロペンアミドのアセタール化物の光重合開始剤とを有する第１保護層溶液を用いてもよい。 As the first protective layer solution, a solution obtained by diluting BIOSURFINE (registered trademark) -AWP-MRH manufactured by Toyo Gosei Co., Ltd. with water to 3 wt% can be used. Also, for example, a water-soluble resin of vinyl alcohol / vinyl oxide copolymer and acetal of 3- [4-azidophenyl] -N- (3-formyl) propyl-2- [morpholinomethylphenylcarbonylamino] propenamide You may use the 1st protective layer solution which has a photoinitiator of a chemical compound.
　（有機半導体層の形成（パターニング）について）
　所定のパターンを有する第１保護層３２が形成された基板Ｐを、有機半導体層３０が溶解可能な有機溶媒（有機半導体としてＴＩＰＳペンタセンを用いた場合は、トルエン等）に浸漬させることで、図７Ｃに示すように、第１保護層３２をマスクとして、第１保護層３２で覆われていない部分、つまり、露出している部分の有機半導体層３０をエッチングする。つまり、露出している部分の有機半導体層３０を溶解させて除去する。これにより、ソース電極Ｓとドレイン電極Ｄとの間に有機半導体層３０が形成された状態となり、目的とする有機半導体層３０を得ることができる。このゲート電極層１６（ゲート電極Ｇ）、絶縁体層１８、ソース・ドレイン電極層２６（ソース電極Ｓおよびドレイン電極Ｄ）、および、有機半導体層３０によって有機薄膜トランジスタが構成される。なお、露出している部分の有機半導体層３０を溶解させた有機溶媒から、精製によって有機半導体を回収することで、有機半導体を再利用することもできる。 (About the formation (patterning) of organic semiconductor layers)
By immersing the substrate P on which the first protective layer 32 having a predetermined pattern is formed in an organic solvent in which the organic semiconductor layer 30 can be dissolved (toluene or the like when TIPS pentacene is used as the organic semiconductor), FIG. As shown in FIG. 7C, using the first protective layer 32 as a mask, the portion of the organic semiconductor layer 30 that is not covered with the first protective layer 32, that is, the exposed portion, is etched. That is, the exposed portion of the organic semiconductor layer 30 is dissolved and removed. As a result, the organic semiconductor layer 30 is formed between the source electrode S and the drain electrode D, and the target organic semiconductor layer 30 can be obtained. The gate electrode layer 16 (gate electrode G), the insulator layer 18, the source / drain electrode layer 26 (source electrode S and drain electrode D), and the organic semiconductor layer 30 constitute an organic thin film transistor. The organic semiconductor can be reused by recovering the organic semiconductor by purification from the organic solvent in which the exposed organic semiconductor layer 30 is dissolved.
　（第２保護層の形成について）
　第２のパッシベーション膜としての第２保護層３４は、感光性樹脂（光硬化型感光性樹脂）から構成される。そのため、ＵＶ光の照射によって第２保護層３４のパターニングを行うことができる。まず、図８Ａに示すように、感光性樹脂が溶媒に溶解した第２保護層溶液（第２の溶液）を、第１保護層３２を覆うように基板Ｐ上に塗布して第２保護層３４を成膜する。第１の溶媒に対する第２保護層３４の接触角は、第１保護層３２の第１の溶媒に対する接触角よりも大きい。例えば、第１保護層溶液の第１の溶媒として水を用いた場合は、第２保護層３４の水接触角は、第１保護層３２の水接触角（例えば、６２度）よりも大きい角度（例えば、７３度）となる。 (Regarding the formation of the second protective layer)
The second protective layer 34 as the second passivation film is made of a photosensitive resin (photo-curable photosensitive resin). Therefore, the second protective layer 34 can be patterned by irradiation with UV light. First, as shown in FIG. 8A, a second protective layer solution (second solution) in which a photosensitive resin is dissolved in a solvent is applied on the substrate P so as to cover the first protective layer 32, and then the second protective layer. 34 is formed. The contact angle of the second protective layer 34 with respect to the first solvent is larger than the contact angle of the first protective layer 32 with respect to the first solvent. For example, when water is used as the first solvent of the first protective layer solution, the water contact angle of the second protective layer 34 is larger than the water contact angle of the first protective layer 32 (for example, 62 degrees). (For example, 73 degrees).
　第２保護層溶液は、第２の樹脂と、第２の樹脂をＵＶ光によって硬化させる光重合開始剤（第２の光重合開始剤）と、第２の樹脂および前記光重合開始剤を溶解する第２の溶媒とを含む溶液から構成される。第２の樹脂としては、例えば、有機溶媒によって溶解する樹脂（有機溶媒溶解性樹脂）を用いることができ、第２の溶媒としては、例えば、有機溶媒を用いることができる。この第２保護層溶液としては、例えば、日本化薬株式会社製のＳＵ－８　３００５をシクロヘキサノンで２．５倍に希釈したものとを用いることができる。なお、第２の樹脂または第２の溶媒が光重合開始剤の性質を有する場合は、第２保護層溶液は、光重合開始剤を含まなくてもよい。 The second protective layer solution dissolves the second resin, a photopolymerization initiator (second photopolymerization initiator) that cures the second resin with UV light, the second resin, and the photopolymerization initiator. And a second solvent. As the second resin, for example, a resin that dissolves in an organic solvent (organic solvent-soluble resin) can be used. As the second solvent, for example, an organic solvent can be used. As the second protective layer solution, for example, SU-8 3005 manufactured by Nippon Kayaku Co., Ltd. diluted 2.5 times with cyclohexanone can be used. In the case where the second resin or the second solvent has a photopolymerization initiator property, the second protective layer solution may not contain the photopolymerization initiator.
　この第２保護層３４は、少なくとも第１保護層３２および有機半導体層３０（有機半導体層３０の側面）を覆うように成膜されている。そして、所定のパターンが形成されたマスクＭ５（第２保護層３４を形成したい領域に開口部ｍａ５を有するマスクＭ５）を介して第２保護層３４にＵＶ光を照射する。その結果、図８Ｂに示すように、ＵＶ光が照射された領域（第２保護層３４を形成したい領域）の第２保護層３４が硬化する。図８Ｂでは、硬化した部分と硬化していない部分とにおけるハッチングの向きを異ならせて表している。このように、マスクＭ５を用いることで、第２保護層３４を選択的に硬化させることができる。なお、この際に、ＵＶ光が照射される領域の化学反応を促進させるための熱処理を加えると一層好適である。 The second protective layer 34 is formed so as to cover at least the first protective layer 32 and the organic semiconductor layer 30 (side surface of the organic semiconductor layer 30). Then, the second protective layer 34 is irradiated with UV light through a mask M5 (a mask M5 having an opening ma5 in a region where the second protective layer 34 is to be formed) on which a predetermined pattern is formed. As a result, as shown in FIG. 8B, the second protective layer 34 in the region irradiated with UV light (the region where the second protective layer 34 is to be formed) is cured. In FIG. 8B, the direction of hatching in the hardened | cured part and the part which is not hardened is represented differently. Thus, the second protective layer 34 can be selectively cured by using the mask M5. In this case, it is more preferable to add a heat treatment for promoting a chemical reaction in a region irradiated with UV light.
　次いで、図８Ｃに示すように、ＵＶ光が照射されていない部分（第２保護層３４）を第２の溶媒（有機溶媒等）で溶解させて除去することで、マスクＭ５に応じた所定のパターンが形成された第２保護層３４が形成される。つまり、ＵＶ光が照射されて硬化した部分の第２保護層３４が残る。第２保護層３４を形成したい領域は、有機半導体層３０および第１保護層３２を覆うのに必要な領域である。したがって、有機半導体層３０および第１保護層３２を覆うのに必要がない部分の第２保護層３４が除去される。これにより、第２保護層３４に所定のパターンを形成した後においても、有機半導体層３０（有機半導体層３０の側面）および第１保護層３２は、第２保護層３４によって覆われている。第２保護層３４は、第１保護層３２よりも第１の溶媒に対する接触角が大きいので、第２保護層３４は、第１保護層３２よりも第１の溶媒に対して撥液性を有する。したがって、第２保護層３４は、第１保護層３２よりも第１の溶媒に対する溶解度が低く、吸液性が低い。なお、第２保護層３４が有機半導体層３０を覆わないように、第２保護層３４に所定のパターンを形成してもよい。 Next, as shown in FIG. 8C, a portion (second protective layer 34) that has not been irradiated with UV light is dissolved and removed with a second solvent (such as an organic solvent) to remove a predetermined amount corresponding to the mask M5. A second protective layer 34 having a pattern is formed. That is, the portion of the second protective layer 34 that has been cured by being irradiated with UV light remains. The region where the second protective layer 34 is to be formed is a region necessary to cover the organic semiconductor layer 30 and the first protective layer 32. Therefore, a portion of the second protective layer 34 that is not necessary to cover the organic semiconductor layer 30 and the first protective layer 32 is removed. Thereby, even after a predetermined pattern is formed on the second protective layer 34, the organic semiconductor layer 30 (side surface of the organic semiconductor layer 30) and the first protective layer 32 are covered with the second protective layer 34. Since the second protective layer 34 has a larger contact angle with the first solvent than the first protective layer 32, the second protective layer 34 is more liquid repellent with respect to the first solvent than the first protective layer 32. Have. Therefore, the second protective layer 34 has a lower solubility in the first solvent than the first protective layer 32 and a low liquid absorbency. A predetermined pattern may be formed on the second protective layer 34 so that the second protective layer 34 does not cover the organic semiconductor layer 30.
　以上の工程を経ることで、ボトムゲート・ボトムコンタクト型のパッシベーション膜付き有機薄膜トランジスタを製造することができる。ここで、パッシベーション膜を第１保護層３２と第２保護層３４との２層に分けた理由について説明する。有機半導体層３０を溶解させることなく、第１保護層３２を溶液によって成膜するためには、有機半導体を溶解しない溶液（例えば、水やフッ素系の溶媒に溶解した溶液）を用いて第１保護層３２を有機半導体層３０上に形成する必要がある。つまり、第１保護層３２を介さずに、有機溶媒系の溶液によって第２保護層３４を有機半導体層３０上に直接成膜すると、有機半導体層３０が、有機溶媒系の溶液によって溶解してしまうからである。また、第１保護層３２の上に、第１保護層３２および有機半導体層３０を覆うように、第１の溶媒に対する吸液性が低い第２保護層３４を成膜する理由としては、有機半導体層３０の側面が露出することを防止するとともに、パッシベーション膜としての機能を果たすためである。第１保護層３２は、第１の樹脂（水溶性樹脂またはフッ素系溶媒溶解性樹脂等）で構成されるため水またはフッ素系の溶媒等を吸収しやすい性質を有する。そのため、第１保護層３２が水やフッ素系の溶媒等を含んでしまうとパッシベーション膜としての機能としては完全ではなく、水やフッ素系の溶媒等がチャネル部に影響を与えてしまうので、第２保護層３４を成膜して、水またはフッ素系の溶媒等を完全に封印している。 Through the above steps, a bottom gate / bottom contact type organic thin film transistor with a passivation film can be manufactured. Here, the reason why the passivation film is divided into two layers of the first protective layer 32 and the second protective layer 34 will be described. In order to form the first protective layer 32 with a solution without dissolving the organic semiconductor layer 30, the first protective layer 32 is formed using a solution that does not dissolve the organic semiconductor (for example, a solution dissolved in water or a fluorine-based solvent). The protective layer 32 needs to be formed on the organic semiconductor layer 30. That is, when the second protective layer 34 is formed directly on the organic semiconductor layer 30 with an organic solvent solution without using the first protective layer 32, the organic semiconductor layer 30 is dissolved with the organic solvent solution. Because it ends up. The reason why the second protective layer 34 having a low liquid absorbency with respect to the first solvent is formed on the first protective layer 32 so as to cover the first protective layer 32 and the organic semiconductor layer 30 is organic. This is because the side surface of the semiconductor layer 30 is prevented from being exposed and functions as a passivation film. Since the first protective layer 32 is composed of a first resin (such as a water-soluble resin or a fluorine-based solvent-soluble resin), it has a property of easily absorbing water or a fluorine-based solvent. Therefore, if the first protective layer 32 contains water, a fluorine-based solvent, or the like, the function as a passivation film is not perfect, and water or a fluorine-based solvent affects the channel portion. 2 A protective layer 34 is formed and completely sealed with water or a fluorine-based solvent.
　（実施例１）
　実施例１では、本第１の実施の形態のプロセスにより高精細な有機半導体層３０の光パターニングについて検討する。本実施例１においては、基板Ｐには東洋紡株式会社製のＰＥＴフィルム（コスモシャインＡ－４１００　コートなし）を、有機半導体層３０に用いられる有機半導体にはＴＩＰＳペンタセン、第１保護層３２に用いられる第１保護層溶液として、東洋合成工業株式会社製のＢＩＯＳＵＲＦＩＮＥ（登録商標）－ＡＷＰ－ＭＲＨをそれぞれ用いた。ＢＩＯＳＵＲＦＩＮＥ（登録商標）－ＡＷＰ－ＭＲＨは、水溶性樹脂（第１の樹脂）と、水溶性樹脂をＵＶ光によって硬化させる光重合開始剤とを含むものである。この第１保護層３２を構成する水溶性感光樹脂（ＢＩＯＳＵＲＦＩＮＥ（登録商標）－ＡＷＰ－ＭＲＨ）の水接触角は、６２度である。 Example 1
In Example 1, optical patterning of the high-definition organic semiconductor layer 30 will be examined by the process of the first embodiment. In Example 1, a PET film manufactured by Toyobo Co., Ltd. (without Cosmo Shine A-4100 coating) is used for the substrate P, TIPS pentacene is used for the organic semiconductor layer 30, and the first protective layer 32 is used. As the first protective layer solution, BIOSURFINE (registered trademark) -AWP-MRH manufactured by Toyo Gosei Co., Ltd. was used. BIOSURFINE (registered trademark) -AWP-MRH contains a water-soluble resin (first resin) and a photopolymerization initiator that cures the water-soluble resin with UV light. The water contact angle of the water-soluble photosensitive resin (BIOSURFINE (registered trademark) -AWP-MRH) constituting the first protective layer 32 is 62 degrees.
　基板Ｐ上への有機半導体層３０の成膜には、ディップコート法を用いた。ＴＩＰＳペンタセンの有機半導体をトルエン溶液（有機溶媒）に溶かした有機半導体溶液（有機半導体を２ｗｔ％に希釈した溶液）に基板Ｐを漬け、引き上げ速度３０ｍｍ／ｓで１ｍｍ引き上げて１０秒間保持することを繰り返した。その後、有機溶媒に用いたトルエン溶液を揮発させるために１０５℃で１０分間熱処理を行うことで、有機半導体層３０を基板Ｐ上に成膜した。次いで、ＢＩＯＳＵＲＦＩＮＥ（登録商標）－ＡＷＰ－ＭＲＨを水（第１の溶媒）で３ｗｔ％に希釈した第１保護層溶液をスピンコート法により塗布した。スピンコートの条件は、回転速度が１０００ｒｐｍ、回転時間を６０秒とした。そして、７０℃で１０分間熱処理を行い、溶媒である水を揮発させて第１保護層３２を成膜した。次いで、マスクＭ４を介して選択的に第１保護層３２および有機半導体層３０を形成させたい領域にＵＶ光を照射し、水洗いをすることで未露光部分を洗い流して除去し、第１保護層３２にマスクＭ４に応じた所定のパターンを形成した。そして、１０５℃で第１保護層３２を３０分間乾燥させた。図９Ａに、パターンが形成された第１保護層３２の光学顕微鏡像を示す。パターンサイズは１００μｍとする。 For forming the organic semiconductor layer 30 on the substrate P, a dip coating method was used. The substrate P is dipped in an organic semiconductor solution (a solution obtained by diluting an organic semiconductor to 2 wt%) in which an organic semiconductor of TIPS pentacene is dissolved in a toluene solution (organic solvent), pulled up 1 mm at a lifting speed of 30 mm / s, and held for 10 seconds. Repeated. Then, in order to volatilize the toluene solution used for the organic solvent, the organic semiconductor layer 30 was formed on the substrate P by performing heat treatment at 105 ° C. for 10 minutes. Next, a first protective layer solution in which BIOSURFINE (registered trademark) -AWP-MRH was diluted to 3 wt% with water (first solvent) was applied by spin coating. The spin coating conditions were a rotation speed of 1000 rpm and a rotation time of 60 seconds. Then, heat treatment was performed at 70 ° C. for 10 minutes to volatilize water as a solvent, and the first protective layer 32 was formed. Next, the region where the first protective layer 32 and the organic semiconductor layer 30 are to be selectively formed is irradiated with UV light through the mask M4, and the unexposed portion is washed away and removed by washing with water. A predetermined pattern corresponding to the mask M4 was formed on 32. Then, the first protective layer 32 was dried at 105 ° C. for 30 minutes. FIG. 9A shows an optical microscope image of the first protective layer 32 on which a pattern is formed. The pattern size is 100 μm.
　その後、第１保護層３２を作製した基板Ｐをトルエン（有機溶媒）に浸漬させ、第１保護層３２をマスクとして第１保護層３２で覆われていない部分の有機半導体層３０をエッチングして、有機半導体層３０にパターンを形成した。パターニングされた有機半導体層３０の光学顕微鏡像を図９Ｂに示す。第１保護層３２と同様の形状で有機半導体層３０がパターニングされていることを確認できた。サイドエッチの程度も低く、１００μｍ程度のサイズであれば容易にパターニングできることが証明された。このサイズ（１００μｍ）でパターニングできればディスプレイ等の電子デバイスに十分適用可能である。 Thereafter, the substrate P on which the first protective layer 32 is produced is immersed in toluene (organic solvent), and the portion of the organic semiconductor layer 30 that is not covered with the first protective layer 32 is etched using the first protective layer 32 as a mask. A pattern was formed on the organic semiconductor layer 30. An optical microscope image of the patterned organic semiconductor layer 30 is shown in FIG. 9B. It was confirmed that the organic semiconductor layer 30 was patterned in the same shape as the first protective layer 32. The degree of side etching is low, and it has been proved that patterning can be easily performed with a size of about 100 μm. If patterning can be performed with this size (100 μm), it is sufficiently applicable to electronic devices such as displays.
　（実施例２）
　実施例２では、有機トランジスタの形成について検討する。なお、基板Ｐ、有機半導体層３０に用いられる有機半導体溶液、および、第１保護層３２に用いられる第１保護層溶液は、実施例１と同様のものを使用している。 (Example 2)
In Example 2, the formation of an organic transistor will be examined. The organic semiconductor solution used for the substrate P, the organic semiconductor layer 30, and the first protective layer solution used for the first protective layer 32 are the same as those in Example 1.
　（ゲート電極層の形成について）
　アミン層１０を構成するアミン材料としては、アミン系シランカップリング剤であるＫＢＥ－９０３（信越化学工業株式会社製）およびＮ－ＰＨＥＮＹＬＡＭＩＮＯＰＲＯＰＹＬＴＲＩＭＥＴＨＯＸＹＳＩＬＡＮＥ（アヅマックス株式会社製）を用いた。ＫＢＥ－９０３が０．５ｗｔ％、Ｎ－ＰＨＥＮＹＬＡＭＩＮＯＰＲＯＰＹＬＴＲＩＭＥＴＨＯＸＹＳＩＬＡＮＥが０．１５ｗｔ％となるように、メチルイソブチルケトン（ＭＩＢＫ）を加えたアミン溶液を用意した。基板Ｐを大気Ｏ2プラズマにより洗浄した後、アミン溶液をディップコート法により基板Ｐ上に塗布した。ディップコートの引き上げ速度は１ｍｍ／ｓとした。そして、溶媒であるメチルイソブチルケトン（ＭＩＢＫ）を揮発させるため、１０５℃で１５分間熱処理を施してアミン層１０を成膜した。 (Regarding the formation of the gate electrode layer)
As the amine material constituting the amine layer 10, KBE-903 (manufactured by Shin-Etsu Chemical Co., Ltd.) and N-PHENY LaminoNOPROPYLTRIMETHOXYSILANE (manufactured by Amax Co., Ltd.), which are amine-based silane coupling agents, were used. An amine solution to which methyl isobutyl ketone (MIBK) was added was prepared so that KBE-903 would be 0.5 wt% and N-PHENY LAMINOPROPYLTRIMETHOXYSILANE would be 0.15 wt%. After cleaning the substrate P with atmospheric O 2 plasma, the amine solution was applied onto the substrate P by dip coating. The lifting speed of the dip coat was 1 mm / s. And in order to volatilize methyl isobutyl ketone (MIBK) which is a solvent, heat processing was performed for 15 minutes at 105 degreeC, and the amine layer 10 was formed into a film.
　次に、アミン層１０を全面成膜した基板Ｐに住友化学株式会社製のフォトレジスト（ＳＵＭＩＲＥＳＩＳＴ ＰＦＩ－３４Ａ６）をディップコート法により塗布し、１０５℃にて５分間プリベイクすることで、フォトレジスト層１２を形成した。ディップコートの引き上げ速度は１ｍｍ／ｓであり、約１μｍの厚さのフォトレジスト層１２を形成した。その後、マスクＭ１を介して４３ｍＷ／ｃｍ2の強度のＵＶ光を３秒間露光し、１０５℃で５分間加熱（ポストベイク）した後に、ＴＭＡＨが２．３８ｗｔ％の水溶液（現像液）に１５０秒間浸漬することで、フォトレジスト層１２に開口部１２ａを有する所定のパターンを形成した。このフォトレジスト層１２に形成されたパターンは、マスクＭ１に応じたパターンである。 Next, a photoresist (SUMIRESIST PFI-34A6) manufactured by Sumitomo Chemical Co., Ltd. is applied to the substrate P on which the amine layer 10 is formed on the entire surface by a dip coating method, and prebaked at 105 ° C. for 5 minutes. 12 was formed. The lifting speed of the dip coat was 1 mm / s, and a photoresist layer 12 having a thickness of about 1 μm was formed. Thereafter, UV light having an intensity of 43 mW / cm 2 is exposed for 3 seconds through the mask M1, heated at 105 ° C. for 5 minutes (post-baked), and then immersed in an aqueous solution (developer) containing 2.38 wt% TMAH for 150 seconds. As a result, a predetermined pattern having openings 12 a was formed in the photoresist layer 12. The pattern formed on the photoresist layer 12 is a pattern corresponding to the mask M1.
　次いで、室温にて３０秒間超音波水洗を基板Ｐに対して行った後に、メルテックス株式会社製の無電解めっき用の触媒コロイド溶液（メルプレート、アクチベーター７３３１）に、室温にて６０秒間基板Ｐを浸漬し、フォトレジスト層１２の開口部１２ａから露出しているアミン層１０に触媒（Ｐｄ）１４を付着させた。そして、表面洗浄した後に、メルテックス株式会社製の無電解めっき（メルプレート　ＮＩ－６５７５）に、８３℃で２５秒間基板Ｐを浸漬し、フォトレジスト層１２の開口部１２ａから露出している触媒１４上にニッケルリンを析出させてニッケルリンめっきを行ってゲート電極層１６を形成した。次に、表面を水洗いして乾燥させた後、残存するフォトレジスト層１２を含む全面に４３ｍＷ／ｃｍ2の強度のＵＶ光を１分間露光し、さらに、エタノールに１分間浸漬することでフォトレジスト層１２を除去した。図１０Ａに、基板Ｐ上に作製したゲート電極Ｇの写真を示し、図１０Ｂに、ゲート電極Ｇの光学顕微鏡像を示す。 Next, ultrasonic cleaning with water was performed on the substrate P for 30 seconds at room temperature, and then the substrate was mixed with a catalyst colloid solution for electroless plating (Melplate, Activator 7331) manufactured by Meltex Co., Ltd. for 60 seconds at room temperature. P was immersed, and a catalyst (Pd) 14 was adhered to the amine layer 10 exposed from the opening 12a of the photoresist layer 12. After cleaning the surface, the substrate P was immersed in electroless plating (Melplate NI-6575) manufactured by Meltex Co., Ltd. for 25 seconds at 83 ° C., and the catalyst exposed from the opening 12a of the photoresist layer 12 Nickel phosphorus was deposited on 14 and nickel phosphorus plating was performed to form the gate electrode layer 16. Next, the surface is washed with water and dried, and then the entire surface including the remaining photoresist layer 12 is exposed to UV light having an intensity of 43 mW / cm 2 for 1 minute, and further immersed in ethanol for 1 minute. Layer 12 was removed. FIG. 10A shows a photograph of the gate electrode G formed on the substrate P, and FIG. 10B shows an optical microscope image of the gate electrode G.
　（絶縁体層の形成について）
　作製されたゲート電極Ｇをアルカリ溶液と２－プロパノールで洗浄し、さらにＵＶ洗浄をすることで表面の有機残渣等を除去した。次いで、絶縁体層溶液をディップコート法で塗布した。絶縁体層溶液は、日本化薬株式会社製のＳＵ－８　３００５をシクロヘキサノンで２.５倍に希釈したものを用い、ディップコートの引き上げ速度は１ｍｍ／ｓとした。その後、１０５℃で１０分間プリベイクして絶縁体層１８を成膜した。そして、マスクＭ２を介して４３ｍＷ／ｃｍ2の強度のＵＶ光を５秒間露光し、１０５℃で６０分間加熱した。次いで、基板ＰをＰＧＭＥＡ（プロピレングリコール－１－モノメチルエーテル－２－アセタート）に浸漬させて、絶縁膜のＵＶ光の未露光部分を溶解させることで、マスクＭ２の応じた所定のパターンが形成された絶縁体層１８を作製する。その後、１０５℃で３０分間ポストベイクすることで、厚さ１μｍの絶縁体層１８を形成した。図１１Ａに、ゲート電極Ｇ上にパターニング成膜した絶縁体層１８の写真を示し、図１１Ｂに、ゲート電極Ｇ付近の絶縁体層１８の光学顕微鏡像を示す。 (About formation of insulator layer)
The produced gate electrode G was washed with an alkaline solution and 2-propanol, and further washed with UV to remove organic residues on the surface. Next, the insulator layer solution was applied by a dip coating method. As the insulator layer solution, SU-8 3005 manufactured by Nippon Kayaku Co., Ltd. was diluted 2.5 times with cyclohexanone, and the dip coat lifting speed was 1 mm / s. Thereafter, the insulator layer 18 was formed by pre-baking at 105 ° C. for 10 minutes. Then, UV light having an intensity of 43 mW / cm 2 was exposed for 5 seconds through the mask M2, and heated at 105 ° C. for 60 minutes. Next, the substrate P is dipped in PGMEA (propylene glycol-1-monomethyl ether-2-acetate) to dissolve the unexposed portion of the UV light of the insulating film, whereby a predetermined pattern corresponding to the mask M2 is formed. Insulator layer 18 is produced. Thereafter, the insulator layer 18 having a thickness of 1 μm was formed by post-baking at 105 ° C. for 30 minutes. FIG. 11A shows a photograph of the insulator layer 18 formed by patterning on the gate electrode G, and FIG. 11B shows an optical microscope image of the insulator layer 18 in the vicinity of the gate electrode G.
　（ソース・ドレイン電極層の形成について）
　ゲート電極層１６の作製と同様の手順で所望の形状となるように、ソース・ドレイン電極層２６を形成する。簡単に説明すると、アミン層２０を形成した後、フォトレジスト層２２を成膜し、マスクＭ３を介してＵＶ光を露光することで、フォトレジスト層２２にマスクＭ３に応じた所定のパターンを形成する。その後、無電解めっき用の触媒コロイド溶液に基板Ｐを浸漬し、フォトレジスト層２２の開口部２２ａから露出しているアミン層２０に触媒（Ｐｄ）２４を付着させる。その後、基板Ｐを無電解めっきに浸漬させて、フォトレジスト層２２の開口部２２ａから露出している触媒１４上にニッケルリンを析出させて、ソース・ドレイン電極層２６を形成する。アミン層２０、フォトレジスト層２２、触媒コロイド溶液、および、無電解めっきの材料や、その他の条件は、ゲート電極Ｇの形成と同一である。つまり、ゲート電極層１６の形成とソース・ドレイン電極層２６との違いは、使用するマスクＭが異なるだけであって、その他の手順は同一である。そして、ソース・ドレイン電極層２６を作製した後、ソース電極Ｓおよびドレイン電極Ｄ等を形成する金属（ニッケルリン）の表面に金２８を被覆させるため、基板Ｐを置換金めっき浴に１分間浸漬させ、次いで、還元金めっき浴に３分間浸漬させた。次いで、水洗いし、１０５℃で３０分間乾燥させてソース・ドレイン電極層２６を金２８で被覆させた。 (About formation of source / drain electrode layers)
The source / drain electrode layer 26 is formed so as to have a desired shape in the same procedure as the fabrication of the gate electrode layer 16. Briefly, after the amine layer 20 is formed, a photoresist layer 22 is formed, and UV light is exposed through the mask M3, whereby a predetermined pattern corresponding to the mask M3 is formed on the photoresist layer 22 To do. Thereafter, the substrate P is immersed in a catalyst colloid solution for electroless plating, and the catalyst (Pd) 24 is adhered to the amine layer 20 exposed from the opening 22a of the photoresist layer 22. Thereafter, the substrate P is immersed in electroless plating to deposit nickel phosphorus on the catalyst 14 exposed from the opening 22a of the photoresist layer 22 to form the source / drain electrode layer 26. The amine layer 20, the photoresist layer 22, the catalyst colloid solution, the electroless plating material, and other conditions are the same as the formation of the gate electrode G. That is, the difference between the formation of the gate electrode layer 16 and the source / drain electrode layer 26 is that the mask M to be used is different, and the other procedures are the same. Then, after the source / drain electrode layer 26 is formed, the substrate P is immersed in a displacement gold plating bath for 1 minute in order to cover the gold 28 on the surface of the metal (nickel phosphorus) forming the source electrode S and the drain electrode D and the like. Then, it was immersed in a reduced gold plating bath for 3 minutes. Next, it was washed with water and dried at 105 ° C. for 30 minutes to coat the source / drain electrode layer 26 with gold 28.
　図１２Ａに、絶縁体層１８上に形成したソース電極Ｓおよびドレイン電極Ｄの写真を示し、図１２Ｂに、ゲート電極Ｇ付近の光学顕微鏡像を示す。図１２Ｂの配線４０はソース電極Ｓの一部であり、配線４２はドレイン電極Ｄの一部である。ゲート電極Ｇが形成された領域上で、両配線４０、４２が隙間（ギャップ）を介して配置されており、該隙間（５μｍ）は、チャネル部４４を形成している。この配線４０、４２の線幅は１０μｍ程度である。また、このチャネル部４４のチャネル長（図１２Ｂの上下方向の長さ）は５００μｍである。なお、チャネル部４４とは、ソース電極Ｓとドレイン電極Ｄの間の領域であって、有機半導体層３０が形成される領域である。 12A shows a photograph of the source electrode S and the drain electrode D formed on the insulator layer 18, and FIG. 12B shows an optical microscope image near the gate electrode G. FIG. The wiring 40 in FIG. 12B is a part of the source electrode S, and the wiring 42 is a part of the drain electrode D. On the region where the gate electrode G is formed, both wirings 40 and 42 are arranged via a gap (gap), and the gap (5 μm) forms a channel portion 44. The line width of the wirings 40 and 42 is about 10 μm. The channel length of the channel portion 44 (length in the vertical direction in FIG. 12B) is 500 μm. The channel portion 44 is a region between the source electrode S and the drain electrode D and is a region where the organic semiconductor layer 30 is formed.
　（有機半導体層の成膜について）
　実施例１と同様に、ソース・ドレイン電極層２６を作製した基板Ｐを有機半導体液に浸漬さえて、ディップコート法を行うことで有機半導体層３０を形成した。図１３に、有機半導体（ＴＩＰＳペンタセン）をディップコートにより成膜した基板Ｐの光学顕微鏡像を示す。なお、有機半導体層３０の成膜に用いる材料や成膜条件は、実施例１と同一である。 (About organic semiconductor layer deposition)
In the same manner as in Example 1, the organic semiconductor layer 30 was formed by dipping the substrate P on which the source / drain electrode layer 26 was produced in an organic semiconductor solution and performing a dip coating method. FIG. 13 shows an optical microscope image of the substrate P on which an organic semiconductor (TIPS pentacene) is formed by dip coating. The material and film formation conditions used for forming the organic semiconductor layer 30 are the same as those in the first embodiment.
　（第１保護層の形成について）
　実施例１と同様に、有機半導体層３０を形成した後、第１保護層３２をスピンコートにより成膜し、光パターニングにより第１保護層３２に所定のパターンを形成した。図１４に、第１保護層３２をパターン形成した基板Ｐの光学顕微鏡像を示す。なお、第１保護層３２の成膜に用いる材料や成膜条件は、実施例１と同一である（但し、実施例１と比べてサイズは大きくパターニングしている。）。 (Regarding the formation of the first protective layer)
In the same manner as in Example 1, after forming the organic semiconductor layer 30, the first protective layer 32 was formed by spin coating, and a predetermined pattern was formed on the first protective layer 32 by optical patterning. In FIG. 14, the optical microscope image of the board | substrate P which patterned the 1st protective layer 32 is shown. The material and film forming conditions used for forming the first protective layer 32 are the same as those in the first embodiment (however, the pattern is larger than that in the first embodiment).
　（有機半導体層のパターニングについて）
　実施例１と同様に、第１保護層３２をパターン形成した基板Ｐをトルエン（有機溶媒）に浸漬させ、第１保護層３２をマスクとして第１保護層３２で覆われていない部分の有機半導体層３０をエッチングして、有機半導体層３０にパターンを形成した。図１５に、有機半導体層３０をパターニングした基板Ｐの光学顕微鏡像を示す。 (About patterning of organic semiconductor layers)
Similarly to Example 1, the substrate P on which the first protective layer 32 is patterned is immersed in toluene (organic solvent), and the portion of the organic semiconductor that is not covered with the first protective layer 32 using the first protective layer 32 as a mask. The layer 30 was etched to form a pattern in the organic semiconductor layer 30. In FIG. 15, the optical microscope image of the board | substrate P which patterned the organic-semiconductor layer 30 is shown.
　（第２保護層の形成について）
　有機半導体層３０をパターニングした後、第２保護層溶液をディップコート法で塗布し、１０５℃で１０分間プリベイクして第２保護層３４を成膜した。第２保護層溶液には、日本化薬株式会社のＳＵ－８　３００５をシクロヘキサノンで２．５倍に希釈したものを用い、ディップコートの引き上げ速度は１ｍｍ／ｓとした。ＳＵ－８　３００５は、有機溶媒によって溶解する有機溶媒溶解性樹脂（第２の樹脂）と有機溶媒溶解性樹脂をＵＶ光によって硬化させる光重合開始剤とを含むものであり、シクロヘキサノンは有機溶媒（第２の溶媒）である。第２保護層３４を構成する有機溶媒溶解性感光樹脂（ＳＵ－８　３００５）の水接触角は、７３度である。 (Regarding the formation of the second protective layer)
After the organic semiconductor layer 30 was patterned, the second protective layer solution was applied by a dip coating method and prebaked at 105 ° C. for 10 minutes to form a second protective layer 34. As the second protective layer solution, SU-8 3005 manufactured by Nippon Kayaku Co., Ltd. was diluted 2.5 times with cyclohexanone, and the dip coat lifting speed was 1 mm / s. SU-8 3005 contains an organic solvent-soluble resin (second resin) that dissolves in an organic solvent and a photopolymerization initiator that cures the organic solvent-soluble resin with UV light. Cyclohexanone contains an organic solvent ( Second solvent). The water contact angle of the organic solvent soluble photosensitive resin (SU-8 3005) constituting the second protective layer 34 is 73 degrees.
　次いで、マスクＭ５を介して、４３ｍＷ／ｃｍ2の強度のＵＶ光で５秒間露光し、その後、１０５℃で６０分間加熱した。このマスクＭ５によって、第１保護層３２および有機半導体層３０を全て覆う領域でＵＶ光が露光され、露光された第２保護層３４の部分を硬化させた。次いで、基板ＰをＰＧＭＥＡ（プロピレングリコール－１－モノメチルエーテル－２-アセタート）に浸漬させて、第２保護層３４のＵＶ光が照射されていない部分を溶解させて、マスクＭ５に応じた所定のパターンの第２保護層３４を形成する。そして、１０５℃で３０分間ポストベイクした。図１６に、第２保護層３４をパターン形成した基板Ｐの光学顕微鏡像を示す。 Subsequently, it was exposed for 5 seconds with UV light having an intensity of 43 mW / cm 2 through the mask M5, and then heated at 105 ° C. for 60 minutes. With this mask M5, UV light was exposed in a region covering all of the first protective layer 32 and the organic semiconductor layer 30, and the exposed portion of the second protective layer 34 was cured. Next, the substrate P is immersed in PGMEA (propylene glycol-1-monomethyl ether-2-acetate) to dissolve the portion of the second protective layer 34 that has not been irradiated with UV light, and a predetermined amount corresponding to the mask M5 is obtained. A second protective layer 34 having a pattern is formed. And it baked for 30 minutes at 105 degreeC. In FIG. 16, the optical microscope image of the board | substrate P which patterned the 2nd protective layer 34 is shown.
　図１７は、以上の工程により製造したパッシベーション膜付き有機薄膜トランジスタのゲート電圧ＶGとドレイン電流ＩDとの特性の評価結果を示すグラフである。作製したパッシベーション膜付き有機薄膜トランジスタはｎ型のトランジスタとして動作したことを確認した。パッシベーション薄膜付き薄膜トランジスタのキャリア移動度は７×１０-3ｃｍ2／Ｖｓ、オン／オフ比は、１．５×１０7となり、良好な特性を示した。なお、ドレイン－ソース間電圧は、－３０Ｖである。 Figure 17 is a graph showing the evaluation results of characteristics of the gate voltage V G and the drain current I D of the passivation film with an organic thin film transistor manufactured by the above steps. It was confirmed that the fabricated organic thin film transistor with a passivation film operated as an n-type transistor. The thin film transistor with a passivation thin film had a carrier mobility of 7 × 10 −3 cm 2 / Vs and an on / off ratio of 1.5 × 10 7 , indicating good characteristics. The drain-source voltage is -30V.
　以上の工程により、湿式プロセスのみでパッシベーション膜付有機薄膜トランジスタを作製することに成功した。本プロセスにおいては、基板Ｐに付与される温度が１００℃程度の比較的低温領域である。例えば、基板Ｐを１００℃以下、または、１２０℃以下に保持した状態で、本プロセスを実施する。このため、ＰＥＴ基板を用いた場合であっても基板Ｐが熱収縮することが回避される。加えて、その温度領域であれば、有機半導体層３０を構成する有機半導体の劣化も起こらないため、ロール・ツー・ロール方式の製造システムへの応用が期待できる。また、湿式プロセスのみで有機半導体層３０、第１保護層３２、および、第２保護層３４を形成するので、有機半導体層３０、第１保護層３２、および、第２保護層３４の少なくとも一つの表面の均一性（平坦性）が向上するとともに、有機半導体層３０の高精細なパターニングを行うことができる。すなわち、本プロセスを得て製造された半導体素子の有機半導体層３０、第１保護層３２、第２保護層３４の少なくとも一つは、平坦な表面を有する。 Through the above steps, we succeeded in producing an organic thin film transistor with a passivation film only by a wet process. In this process, the temperature applied to the substrate P is a relatively low temperature region of about 100 ° C. For example, this process is performed with the substrate P held at 100 ° C. or lower or 120 ° C. or lower. For this reason, even if it is a case where a PET board | substrate is used, it is avoided that the board | substrate P heat-shrinks. In addition, since the organic semiconductor constituting the organic semiconductor layer 30 does not deteriorate within the temperature range, application to a roll-to-roll manufacturing system can be expected. In addition, since the organic semiconductor layer 30, the first protective layer 32, and the second protective layer 34 are formed only by a wet process, at least one of the organic semiconductor layer 30, the first protective layer 32, and the second protective layer 34 is formed. The uniformity (flatness) of the two surfaces can be improved, and high-definition patterning of the organic semiconductor layer 30 can be performed. That is, at least one of the organic semiconductor layer 30, the first protective layer 32, and the second protective layer 34 of the semiconductor element manufactured by obtaining this process has a flat surface.
［第２の実施の形態］
　上記第１の実施の形態では、有機薄膜トランジスタとして、ボトムゲート・ボトムコンタクト型を例に挙げて説明したが、トップゲート・ボトムコンタクト型であってもよく、ボトムゲート・トップコンタクト型であってもよい。本第２の実施の形態においては、半導体素子として、トップゲート・ボトムコンタクト型のパッシベーション膜付きの有機薄膜トランジスタの製造方法について簡単に説明する。第２の実施の形態の半導体素子は、基板Ｐ上に、ソース・ドレイン電極層、有機半導体層、第１保護層、第２保護層、および、ゲート電極層が、前記の順で積層された構造を有する。以下、半導体素子の各層の形成について説明する。 [Second Embodiment]
In the first embodiment, the bottom gate / bottom contact type has been described as an example of the organic thin film transistor. However, a top gate / bottom contact type or a bottom gate / top contact type may be used. Good. In the second embodiment, a method of manufacturing an organic thin film transistor with a top gate / bottom contact type passivation film as a semiconductor element will be briefly described. In the semiconductor element of the second embodiment, the source / drain electrode layer, the organic semiconductor layer, the first protective layer, the second protective layer, and the gate electrode layer are stacked on the substrate P in the order described above. It has a structure. Hereinafter, formation of each layer of the semiconductor element will be described.
　（ソース・ドレイン電極層の形成について）
　ソース・ドレイン電極層は、上記第１の実施の形態で説明したソース・ドレイン電極層２６の作製手順と同様のプロセスを経て作製することができる。まず、図１８Ａに示すように、ＰＥＴ等のフレキシブルな基板Ｐは難めっき部材であるため、基板Ｐ上にアミン層５０を形成する。そして、図１８Ｂに示すように、アミン層５０の上にポジ型のフォトレジスト層５２を形成し、所定のパターンが形成されたマスクＭ６（ソース電極Ｓおよびドレイン電極Ｄを形成する領域に開口部ｍａ６を有するマスクＭ６）を介してＵＶ光（光）を照射することで、フォトレジスト層５２を露光する。 (About formation of source / drain electrode layers)
The source / drain electrode layer can be manufactured through a process similar to the manufacturing procedure of the source / drain electrode layer 26 described in the first embodiment. First, as shown in FIG. 18A, since the flexible substrate P such as PET is a difficult-to-plat member, the amine layer 50 is formed on the substrate P. Then, as shown in FIG. 18B, a positive photoresist layer 52 is formed on the amine layer 50, and a mask M6 in which a predetermined pattern is formed (openings in regions where the source electrode S and the drain electrode D are formed). The photoresist layer 52 is exposed by irradiating UV light (light) through a mask M6) having ma6.
　その後、フォトレジスト層５２（基板Ｐ）を現像液に浸漬することで、図１８Ｃに示すように、ＵＶ光が照射された部分（露光された部分）のフォトレジスト層５２が溶解して除去した後、無電解めっきに用いる触媒（Ｐｄ）５４を含む触媒溶液を基板Ｐ上に付与する。基板Ｐを現像液に浸漬することで、フォトレジスト層５２には、ソース電極Ｓおよびドレイン電極Ｄに応じたパターンが形成される。つまり、ソース電極Ｓおよびドレイン電極Ｄを形成する領域に開口部５２ａを有するパターンが形成される。また、アミン層５０の上には所定のパターンが形成されたフォトレジスト層５２が積層されているので、開口部５２ａによって露出したアミン層５０上に触媒５４が付与される。 Thereafter, by immersing the photoresist layer 52 (substrate P) in a developing solution, as shown in FIG. 18C, the photoresist layer 52 in the portion irradiated with UV light (exposed portion) was dissolved and removed. Thereafter, a catalyst solution containing a catalyst (Pd) 54 used for electroless plating is applied on the substrate P. By immersing the substrate P in the developer, a pattern corresponding to the source electrode S and the drain electrode D is formed in the photoresist layer 52. That is, a pattern having the opening 52a is formed in a region where the source electrode S and the drain electrode D are formed. Further, since the photoresist layer 52 having a predetermined pattern is laminated on the amine layer 50, the catalyst 54 is applied on the amine layer 50 exposed by the opening 52a.
　そして、ニッケルリン等の無電解めっき液に基板Ｐを浸漬することにより、図１９Ａに示すように、触媒５４の表面に金属イオンを還元して析出させる。この析出した金属層がソース・ドレイン電極層５６となる。したがって、基板Ｐ上に、ソース電極Ｓおよびドレイン電極Ｄを有するソース・ドレイン電極層（金属層）５６が選択的に形成される。その後、残存するフォトレジスト層５２の全面にＵＶ光を露光して、フォトレジスト層５２（基板Ｐ）を現像液に浸漬することで、図１９Ｂに示すように、フォトレジスト層５２を除去する。そして、基板Ｐを置換金めっき浴に浸漬させた後、還元金めっき浴に浸漬させることで、図１９Ｃに示すように、ソース・ドレイン電極層５６の表面を金５８で被覆する。これにより、ソース電極Ｓおよびドレイン電極Ｄが金５８で被覆されることになる。以上の工程により、基板Ｐ上にソース・ドレイン電極層５６を形成する。 Then, by immersing the substrate P in an electroless plating solution such as nickel phosphorus, metal ions are reduced and deposited on the surface of the catalyst 54 as shown in FIG. 19A. The deposited metal layer becomes the source / drain electrode layer 56. Therefore, the source / drain electrode layer (metal layer) 56 having the source electrode S and the drain electrode D is selectively formed on the substrate P. Thereafter, the entire surface of the remaining photoresist layer 52 is exposed to UV light, and the photoresist layer 52 (substrate P) is immersed in a developer to remove the photoresist layer 52 as shown in FIG. 19B. Then, after immersing the substrate P in the displacement gold plating bath, the surface of the source / drain electrode layer 56 is covered with the gold 58 as shown in FIG. As a result, the source electrode S and the drain electrode D are covered with the gold 58. Through the above steps, the source / drain electrode layer 56 is formed on the substrate P.
　（有機半導体層の形成（成膜）について）
　有機半導体層６０は、上記第１の実施の形態で説明した有機半導体層３０の作製手順と同様のプロセスを経て作製することができる。つまり、有機半導体が有機溶媒に溶解した有機半導体液を、基板Ｐ上に塗布した後、加熱して溶媒を蒸発（揮発）させることにより、有機半導体層６０を成膜する。図２０Ａは、基板Ｐ上に成膜された有機半導体層６０を示す。 (Regarding the formation (deposition) of organic semiconductor layers)
The organic semiconductor layer 60 can be manufactured through a process similar to the manufacturing procedure of the organic semiconductor layer 30 described in the first embodiment. That is, an organic semiconductor liquid in which an organic semiconductor is dissolved in an organic solvent is applied on the substrate P, and then heated to evaporate (volatilize) the solvent, whereby the organic semiconductor layer 60 is formed. FIG. 20A shows the organic semiconductor layer 60 formed on the substrate P.
　（第１保護層の形成について）
　第１のパッシベーション膜としての第１保護層６２は、上記第１の実施の形態で説明した第１保護層６２の作製手順と同様のプロセスを経て作製することができる。まず、図２０Ｂに示すように、第１の樹脂と、第１の樹脂をＵＶ光によって硬化させる光重合開始剤（第１の光重合開始剤）と、第１の樹脂および光重合開始剤を溶解する第１の溶媒とを含む第１保護層溶液を塗布し、有機半導体層６０の表面に第１保護層６２を成膜する。第１の樹脂として水溶性樹脂、第１の溶媒として水を用いた場合の第１保護層６２の水接触角は、例えば、６２度である。なお、第１の樹脂または第１の溶媒が光重合開始剤の性質を有する場合は、第１保護層溶液は、光重合開始剤を含まなくてもよい。 (Regarding the formation of the first protective layer)
The first protective layer 62 as the first passivation film can be manufactured through a process similar to the manufacturing procedure of the first protective layer 62 described in the first embodiment. First, as shown in FIG. 20B, a first resin, a photopolymerization initiator (first photopolymerization initiator) for curing the first resin with UV light, a first resin and a photopolymerization initiator are added. A first protective layer solution containing a first solvent to be dissolved is applied to form a first protective layer 62 on the surface of the organic semiconductor layer 60. The water contact angle of the first protective layer 62 when water-soluble resin is used as the first resin and water is used as the first solvent is, for example, 62 degrees. In addition, when the 1st resin or the 1st solvent has the property of a photoinitiator, the 1st protective layer solution does not need to contain a photoinitiator.
　そして、図２０Ｃに示すように、所定のパターンが形成されたマスクＭ７（第１保護層６２を形成したい領域に開口部ｍａ７を有するマスクＭ７）を介して、第１保護層６２にＵＶ光を照射する。その結果、図２１Ａに示すように、ＵＶ光が照射された領域（第１保護層６２を形成したい領域）の第１保護層６２が硬化する。図２１Ａでは、硬化した部分と硬化していない部分とにおけるハッチングの向きを異ならせて表している。このように、マスクＭ７を用いることで、第１保護層６２を選択的に硬化させることができる。なお、この際に、ＵＶ光が照射される領域の化学反応を促進させるための熱処理を加えると一層好適である。次いで、図２１Ｂに示すように、ＵＶ光が照射されていない部分を第１の溶媒（水またはフッ素系の溶媒等）で溶解させて除去することで、マスクＭ７に応じた所定のパターンが形成された第１保護層６２が形成される。つまり、ＵＶ光が照射された硬化した部分の第１保護層６２が残る。この第１保護層６２を形成したい領域は、ソース電極Ｓとドレイン電極Ｄとの間の領域を含む。 Then, as shown in FIG. 20C, UV light is applied to the first protective layer 62 through a mask M7 (a mask M7 having an opening ma7 in a region where the first protective layer 62 is to be formed) on which a predetermined pattern is formed. Irradiate. As a result, as shown in FIG. 21A, the first protective layer 62 in the region irradiated with UV light (the region where the first protective layer 62 is to be formed) is cured. In FIG. 21A, the direction of hatching in the hardened part and the non-hardened part is shown differently. Thus, the 1st protective layer 62 can be selectively hardened by using mask M7. In this case, it is more preferable to add a heat treatment for promoting a chemical reaction in a region irradiated with UV light. Next, as shown in FIG. 21B, a predetermined pattern corresponding to the mask M7 is formed by dissolving and removing a portion not irradiated with UV light with a first solvent (water or a fluorine-based solvent or the like). The first protective layer 62 thus formed is formed. That is, the hardened portion of the first protective layer 62 irradiated with UV light remains. The region where the first protective layer 62 is to be formed includes a region between the source electrode S and the drain electrode D.
　（有機半導体層の形成（パターニング）について）
　有機半導体層６０のパターニングは、上記第１の実施の形態で説明した有機半導体層３０のパターニングと同様のプロセスを経て行うことができる。つまり、所定のパターンを有する第１保護層６２が形成された基板Ｐを、有機半導体層６０が溶解可能な有機溶媒に浸漬させることで、図２１Ｃに示すように、第１保護層６２をマスクとして、第１保護層６２で覆われていない部分、つまり、露出している部分の有機半導体層６０を溶解させて除去する。これにより、ソース電極Ｓとドレイン電極Ｄとの間に有機半導体層６０が形成された状態となり、目的とする有機半導体層６０を得ることができる。なお、露出している部分の有機半導体層６０を溶解させた有機溶媒から、精製によって有機半導体を回収することで、有機半導体を再利用することができる。 (About the formation (patterning) of organic semiconductor layers)
The patterning of the organic semiconductor layer 60 can be performed through the same process as the patterning of the organic semiconductor layer 30 described in the first embodiment. That is, the substrate P on which the first protective layer 62 having a predetermined pattern is formed is immersed in an organic solvent in which the organic semiconductor layer 60 can be dissolved, so that the first protective layer 62 is masked as shown in FIG. 21C. As a result, the portion of the organic semiconductor layer 60 that is not covered with the first protective layer 62, that is, the exposed portion of the organic semiconductor layer 60 is dissolved and removed. As a result, the organic semiconductor layer 60 is formed between the source electrode S and the drain electrode D, and the target organic semiconductor layer 60 can be obtained. The organic semiconductor can be reused by collecting the organic semiconductor by purification from the organic solvent in which the exposed organic semiconductor layer 60 is dissolved.
　（第２保護層の形成について）
　第２のパッシベーション膜としての第２保護層６４は、上記第１の実施の形態で説明した第２保護層６４の作製手順と同様のプロセスを経て作製することができる。まず、図２２Ａに示すように、感光性樹脂が溶媒に溶解した第２保護層溶液を、有機半導体層６０および第１保護層６２を覆うように基板Ｐ上に塗布して第２保護層６４を成膜する。第２保護層溶液は、第２の樹脂と、第２の樹脂をＵＶ光によって硬化させる光重合開始剤（第２の光重合開始剤）と、第２の樹脂および前記光重合開始剤を溶解する第２の溶媒とを含む。第１の溶媒に対する第２保護層６４の接触角は、第１保護層６２の第１の溶媒に対する接触角よりも大きい。第１保護層溶液の第１の溶媒として水を用いた場合は、第２保護層６４の水接触角は、第１保護層６２の水接触角（例えば、６２度）よりも大きい角度（例えば、７３度）となる。なお、第２の樹脂または第２の溶媒が光重合開始剤の性質を有する場合は、第２保護層溶液は、光重合開始剤を含まなくてもよい。 (Regarding the formation of the second protective layer)
The second protective layer 64 as the second passivation film can be manufactured through a process similar to the manufacturing procedure of the second protective layer 64 described in the first embodiment. First, as shown in FIG. 22A, a second protective layer solution in which a photosensitive resin is dissolved in a solvent is applied on the substrate P so as to cover the organic semiconductor layer 60 and the first protective layer 62, and the second protective layer 64. Is deposited. The second protective layer solution dissolves the second resin, a photopolymerization initiator (second photopolymerization initiator) that cures the second resin with UV light, the second resin, and the photopolymerization initiator. And a second solvent. The contact angle of the second protective layer 64 with respect to the first solvent is larger than the contact angle of the first protective layer 62 with respect to the first solvent. When water is used as the first solvent of the first protective layer solution, the water contact angle of the second protective layer 64 is larger than the water contact angle (for example, 62 degrees) of the first protective layer 62 (for example, 62 degrees). 73 degrees). In the case where the second resin or the second solvent has a photopolymerization initiator property, the second protective layer solution may not contain the photopolymerization initiator.
　そして、所定のパターンが形成されたマスクＭ８（第２保護層６４を形成したい領域に開口部ｍａ８を有するマスクＭ８）を介して第２保護層６４にＵＶ光を照射する。その結果、図２２Ｂに示すように、ＵＶ光が照射された領域（第２保護層６４を形成したい領域）の第２保護層６４が硬化する。図２２Ｂでは、硬化した部分と硬化していない部分とにおけるハッチングの向きを異ならせて表している。このように、マスクＭ８を用いることで、第２保護層６４を選択的に硬化させることができる。なお、この際に、ＵＶ光が照射される領域の化学反応を促進させるための熱処理を加えると一層好適である。 Then, the second protective layer 64 is irradiated with UV light through a mask M8 (a mask M8 having an opening ma8 in a region where the second protective layer 64 is to be formed) on which a predetermined pattern is formed. As a result, as shown in FIG. 22B, the second protective layer 64 in the region irradiated with UV light (the region where the second protective layer 64 is to be formed) is cured. In FIG. 22B, the direction of hatching in the hardened part and the non-hardened part is shown differently. Thus, the second protective layer 64 can be selectively cured by using the mask M8. In this case, it is more preferable to add a heat treatment for promoting a chemical reaction in a region irradiated with UV light.
　次いで、図２２Ｃに示すように、ＵＶ光が照射されていない部分（第２保護層６４）を第２の溶媒（有機溶媒等）で溶解させて除去することで、マスクＭ８に応じた所定のパターンが形成された第２保護層６４が形成される。つまり、ＵＶ光が照射されて硬化した部分の第２保護層６４が残る。第２保護層６４を形成したい領域は、有機半導体層６０および第１保護層６２を覆うのに必要な領域である。したがって、有機半導体層６０および第１保護層６２を覆うのに必要がない部分の第２保護層６４が除去される。第２保護層溶液は、第１保護層溶液よりも第１の溶媒に対する接触角が大きいので、第２保護層６４は、第１保護層６２よりも第１の溶媒に対して撥液性を有する。したがって、第２保護層６４は、第１保護層６２よりも第１の溶媒に対する溶解度が低く、吸液性が低い。第２の実施の形態においては、この第２保護層６４は、絶縁体層としての機能も有する。 Next, as shown in FIG. 22C, a portion (second protective layer 64) that has not been irradiated with UV light is dissolved and removed with a second solvent (such as an organic solvent), so that a predetermined amount corresponding to the mask M8 is obtained. A second protective layer 64 on which a pattern is formed is formed. That is, the portion of the second protective layer 64 that has been cured by being irradiated with UV light remains. A region where the second protective layer 64 is to be formed is a region necessary to cover the organic semiconductor layer 60 and the first protective layer 62. Accordingly, the second protective layer 64 that is not necessary to cover the organic semiconductor layer 60 and the first protective layer 62 is removed. Since the second protective layer solution has a larger contact angle with the first solvent than the first protective layer solution, the second protective layer 64 is more liquid repellent with respect to the first solvent than the first protective layer 62. Have. Therefore, the second protective layer 64 has a lower solubility in the first solvent than the first protective layer 62 and has a low liquid absorbency. In the second embodiment, the second protective layer 64 also has a function as an insulator layer.
　（ゲート電極層の形成について）
　ゲート電極層は、上記第１の実施の形態で説明したゲート電極層１６の作製手順と同様のプロセスを経て作製することができる。まず、図２３Ａに示すように、第２保護層６４上にアミン層６６を形成する。そして、図２３Ｂに示すように、アミン層６６上にポジ型のフォトレジスト層６８を形成し、所定のパターンが形成されたマスクＭ９（ゲート電極Ｇを形成する領域に開口部ｍａ９を有するマスクＭ９）を介してＵＶ光を照射することで、フォトレジスト層６８を露光する。その後、フォトレジスト層６８（基板Ｐ）を現像液（例えば、ＴＭＡＨ等）に浸漬することで、図２３Ｃに示すように、ＵＶ光が照射された部分（露光された部分）のフォトレジスト層６８が溶解して除去される。これにより、フォトレジスト層６８には、ゲート電極Ｇに応じた所定のパターンが形成される。つまり、ゲート電極Ｇを形成する領域に開口部６８ａを有するパターンが形成される。 (Regarding the formation of the gate electrode layer)
The gate electrode layer can be manufactured through a process similar to the manufacturing procedure of the gate electrode layer 16 described in the first embodiment. First, as shown in FIG. 23A, an amine layer 66 is formed on the second protective layer 64. Then, as shown in FIG. 23B, a positive photoresist layer 68 is formed on the amine layer 66, and a mask M9 having a predetermined pattern (a mask M9 having an opening ma9 in a region where the gate electrode G is formed). The photoresist layer 68 is exposed by irradiating it with UV light. Thereafter, by immersing the photoresist layer 68 (substrate P) in a developing solution (for example, TMAH or the like), as shown in FIG. 23C, the photoresist layer 68 in the portion irradiated with UV light (exposed portion). Dissolves and is removed. As a result, a predetermined pattern corresponding to the gate electrode G is formed in the photoresist layer 68. That is, a pattern having the opening 68a is formed in a region where the gate electrode G is formed.
　次に、図２４Ａに示すように、無電解めっきに用いる触媒（Ｐｄ）７０を含む触媒溶液をフォトレジスト層６８の開口部６８ａによって露出したアミン層６６上に付与し、基板Ｐを現像液に浸漬することで、触媒７０の表面に金属イオンを還元して析出させる。この析出した金属層がゲート電極層７２となる。したがって、基板Ｐ上にゲート電極Ｇを有するゲート電極層７２が選択的に形成される。その後、残存するフォトレジスト層６８の全面にＵＶ光を露光して、フォトレジスト層６８（基板Ｐ）を現像液に浸漬することで、図２４Ｂに示すように、フォトレジスト層６８を除去する。以上の工程により、第２保護層６４上にゲート電極層７２を形成する。 Next, as shown in FIG. 24A, a catalyst solution containing a catalyst (Pd) 70 used for electroless plating is applied on the amine layer 66 exposed by the opening 68a of the photoresist layer 68, and the substrate P is used as a developer. By soaking, metal ions are reduced and deposited on the surface of the catalyst 70. This deposited metal layer becomes the gate electrode layer 72. Therefore, the gate electrode layer 72 having the gate electrode G is selectively formed on the substrate P. Thereafter, the entire surface of the remaining photoresist layer 68 is exposed to UV light, and the photoresist layer 68 (substrate P) is immersed in a developer, thereby removing the photoresist layer 68 as shown in FIG. 24B. Through the above process, the gate electrode layer 72 is formed on the second protective layer 64.
　以上の工程を経ることで、湿式プロセスのみでトップゲート・ボトムコンタクト型のパッシベーション膜付き有機薄膜トランジスタを製造することができる。また、湿式プロセスのみで有機半導体層６０、第１保護層６２、および、第２保護層６４を形成するので、有機半導体層６０、第１保護層６２、および、第２保護層６４の少なくとも一つの表面の均一性（平坦性）が向上するとともに、有機半導体層６０の高精細なパターニングを行うことができる。なお、ボトムゲート・トップコンタクト型のパッシベーション膜付き有機トランジスタの製造方法については、詳しくは説明しないが、同様の工程を経ることで、製造することが可能である。 Through the above steps, a top gate / bottom contact type organic thin film transistor with a passivation film can be manufactured only by a wet process. In addition, since the organic semiconductor layer 60, the first protective layer 62, and the second protective layer 64 are formed only by a wet process, at least one of the organic semiconductor layer 60, the first protective layer 62, and the second protective layer 64 is formed. The uniformity (flatness) of the two surfaces can be improved, and high-definition patterning of the organic semiconductor layer 60 can be performed. Note that the manufacturing method of the bottom gate / top contact type organic transistor with a passivation film is not described in detail, but it can be manufactured through the same steps.
　なお、上記各実施の形態で説明した半導体素子（パッシベーション膜付き有機薄膜トランジスタ）を有する、電子ペーパや有機ＥＬディスプレイ等の電子デバイスを製造する場合でも、この電子デバイスの製造方法は、上記各実施の形態で説明した半導体素子の製造方法を含んでもよい。つまり、電子デバイスの製造方法は、上記各実施の形態で説明した製造方法を用いて電子デバイスの半導体素子を製造してもよい。 Even when manufacturing an electronic device such as an electronic paper or an organic EL display having the semiconductor element (organic thin film transistor with a passivation film) described in each of the above embodiments, the manufacturing method of the electronic device is the same as that of each of the above embodiments. The method for manufacturing a semiconductor element described in the embodiment may be included. In other words, the electronic device manufacturing method may manufacture the semiconductor element of the electronic device using the manufacturing method described in the above embodiments.
　また、上記各実施の形態では、マスクＭ（Ｍ１～Ｍ９）を用いてフォトレジスト層や保護層等に光を照射して所定のパターンを形成したが、マスクＭを用いずに、スキャン露光によって所定のパターンを形成してもよい。例えば、シード光源や電気光学変調器等を用いてフォトレジスト層や保護層等に照射する光をスイッチングさせることにより、フォトレジスト層や保護層に所定のパターンを形成してもよい。また、デジタルマイクロミラーデバイス（ＤＭＤ：Digital Micromirror Device）を用いてフォトレジスト層（１２、２２、５２、６８）や保護層（３２、３４、６２、６４）等に光を照射して所定のパターンを形成してもよい。 Further, in each of the above embodiments, the mask M (M1 to M9) is used to irradiate the photoresist layer, the protective layer, etc. with light, and a predetermined pattern is formed. A predetermined pattern may be formed. For example, a predetermined pattern may be formed on the photoresist layer or the protective layer by switching light applied to the photoresist layer or the protective layer using a seed light source or an electro-optic modulator. Further, a predetermined pattern is formed by irradiating light to the photoresist layer (12, 22, 52, 68), the protective layer (32, 34, 62, 64), etc. using a digital micromirror device (DMD). May be formed.

Claims (16)

  1. 　電極が形成された基板上に有機半導体層を成膜する第１成膜工程と、
    　前記有機半導体層の表面に第１保護層を成膜する第２成膜工程と、
    　前記第１保護層に光を照射して前記第１保護層を露光することで、前記第１保護層に所定のパターンを形成する第１パターン形成工程と、
    　前記所定のパターンが形成された前記第１保護層をマスクとして前記有機半導体層をエッチングすることで、前記有機半導体層に前記所定のパターンを形成する第２パターン形成工程と、
    　前記第２パターン形成工程後の後に、前記所定のパターンが形成された前記第１保護層を覆う第２保護層を成膜する第３成膜工程と、
    　を含む、半導体素子の製造方法。     A first film forming step of forming an organic semiconductor layer on a substrate on which an electrode is formed;
    A second film forming step of forming a first protective layer on the surface of the organic semiconductor layer;
    A first pattern forming step of forming a predetermined pattern on the first protective layer by irradiating the first protective layer with light to expose the first protective layer;
    A second pattern forming step of forming the predetermined pattern on the organic semiconductor layer by etching the organic semiconductor layer using the first protective layer on which the predetermined pattern is formed as a mask;
    A third film forming step of forming a second protective layer covering the first protective layer on which the predetermined pattern is formed after the second pattern forming step;
    A method for manufacturing a semiconductor device, comprising:
  2. 　請求項１に記載の半導体素子の製造方法であって、
    　前記第１パターン形成工程は、前記第１保護層に前記光を照射して前記第１保護層を硬化させる、半導体素子の製造方法。     A method of manufacturing a semiconductor device according to claim 1,
    The first pattern forming step is a method of manufacturing a semiconductor element, wherein the first protective layer is cured by irradiating the first protective layer with the light.
  3. 　請求項１または２に記載の半導体素子の製造方法であって、
    　前記第１パターン形成工程は、前記光を照射していない部分を第１の溶媒で溶解して、前記第１保護層に前記所定のパターンを形成する、半導体素子の製造方法。     A method of manufacturing a semiconductor device according to claim 1 or 2,
    The first pattern forming step is a method for manufacturing a semiconductor device, wherein the predetermined pattern is formed on the first protective layer by dissolving a portion not irradiated with light with a first solvent.
  4. 　請求項１～３のいずれか１項に記載の半導体素子の製造方法であって、
    　前記第２成膜工程は、第１の樹脂と前記第１の樹脂を溶解する第１の溶媒とを含む第１の溶液を用いて、前記第１保護層を成膜する、半導体素子の製造方法。     A method for manufacturing a semiconductor device according to any one of claims 1 to 3,
    In the manufacturing of a semiconductor element, the second film forming step forms the first protective layer using a first solution containing a first resin and a first solvent that dissolves the first resin. Method.
  5. 　請求項４に記載の半導体素子の製造方法であって、
    　前記第１の溶液は、前記第１の樹脂を光によって硬化させる第１の光重合開始剤をさらに含み、
    　前記第１の溶媒は、前記第１の光重合開始剤を溶解する、半導体素子の製造方法。     A method of manufacturing a semiconductor device according to claim 4,
    The first solution further includes a first photopolymerization initiator that cures the first resin with light,
    The method of manufacturing a semiconductor element, wherein the first solvent dissolves the first photopolymerization initiator.
  6. 　請求項１～５のいずれか１項に記載の半導体素子の製造方法であって、
    　前記第２パターン形成工程は、前記第１パターン形成工程で前記光を照射していない部分を第１の溶媒で溶解した後に、前記有機半導体層を溶解可能な有機溶媒を用いて、前記第１保護層で覆われていない部分の前記有機半導体層を溶解させて、有機半導体を回収する、半導体素子の製造方法。     A method of manufacturing a semiconductor device according to any one of claims 1 to 5,
    The second pattern forming step uses an organic solvent that can dissolve the organic semiconductor layer after the portion that has not been irradiated with the light in the first pattern forming step is dissolved in the first solvent, and then the first pattern forming step. A method for manufacturing a semiconductor device, comprising: dissolving a portion of the organic semiconductor layer not covered with a protective layer to recover the organic semiconductor.
  7. 　請求項１～６のいずれか１項に記載の半導体素子の製造方法であって、
    　前記第３成膜工程は、前記第１保護層に比べ第１の溶媒に対する溶解度が低い前記第２保護層を成膜する、半導体素子の製造方法。     A method of manufacturing a semiconductor device according to any one of claims 1 to 6,
    The third film formation step is a method of manufacturing a semiconductor element, wherein the second protective layer having a lower solubility in the first solvent than the first protective layer is formed.
  8. 　請求項１～７のいずれか１項に記載の半導体素子の製造方法であって、
    　前記第３成膜工程は、第２の樹脂と前記第２の樹脂を溶解する第２の溶媒とを含む第２の溶液を用いて、第２保護層を成膜する、半導体素子の製造方法。     A method of manufacturing a semiconductor device according to any one of claims 1 to 7,
    The method of manufacturing a semiconductor element, wherein the third film forming step forms the second protective layer using a second solution containing a second resin and a second solvent that dissolves the second resin. .
  9. 　請求項８に記載の半導体素子の製造方法であって、
    　前記第２の溶液は、前記第２の樹脂を光によって硬化させる第２の光重合開始剤をさらに含み、
    　前記第２の溶媒は、前記第２の光重合開始剤を溶解する、半導体素子の製造方法。     A method of manufacturing a semiconductor device according to claim 8,
    The second solution further includes a second photopolymerization initiator that cures the second resin with light,
    The method of manufacturing a semiconductor element, wherein the second solvent dissolves the second photopolymerization initiator.
  10. 　請求項１～９のいずれか１項に記載の半導体素子の製造方法であって、
    　前記第２保護層に光を照射して前記第２保護層を露光することで、前記第２保護層にパターンを形成する第３パターン形成工程をさらに含む、半導体素子の製造方法。     A method of manufacturing a semiconductor device according to any one of claims 1 to 9,
    A method of manufacturing a semiconductor device, further comprising a third pattern forming step of forming a pattern on the second protective layer by irradiating the second protective layer with light to expose the second protective layer.
  11. 　請求項１０に記載の半導体素子の製造方法であって、
    　前記第３パターン形成工程は、前記第２保護層のうち前記光が照射されていない部分を溶解して除去する、半導体素子の製造方法。     It is a manufacturing method of the semiconductor device according to claim 10,
    The third pattern forming step is a method of manufacturing a semiconductor element, wherein a portion of the second protective layer that is not irradiated with light is dissolved and removed.
  12. 　電子デバイスの製造方法であって、
    　請求項１～１１のいずれか１項に記載の半導体素子の製造方法を含む、電子デバイスの製造方法。     An electronic device manufacturing method comprising:
    A method for manufacturing an electronic device, comprising the method for manufacturing a semiconductor element according to any one of claims 1 to 11.
  13. 　電極が形成された基板上に成膜された有機半導体層と、
    　前記有機半導体層の表面に成膜された第１保護層と、
    　前記第１保護層を覆うように成膜された第２保護層と、
    　を備えた半導体素子であって、
    　前記第１保護層は、光によって硬化された第１の樹脂で構成される、半導体素子。     An organic semiconductor layer formed on a substrate on which an electrode is formed; and
    A first protective layer formed on the surface of the organic semiconductor layer;
    A second protective layer formed to cover the first protective layer;
    A semiconductor device comprising:
    The first protective layer is a semiconductor element composed of a first resin cured by light.
  14. 　請求項１３に記載の半導体素子であって、
    　前記第２保護層は、光によって硬化された第２の樹脂で構成される、半導体素子。     The semiconductor device according to claim 13,
    The second protective layer is a semiconductor element composed of a second resin cured by light.
  15. 　電極が形成された基板上に成膜された有機半導体層と、
    　前記有機半導体層の表面に成膜された第１保護層と、
    　前記第１保護層を覆うように成膜された第２保護層と、
    　を備えた半導体素子であって、
    　前記第２保護層は、前記第１保護層に比べ第１の溶媒に対する溶解度が低い、半導体素子。     An organic semiconductor layer formed on a substrate on which an electrode is formed; and
    A first protective layer formed on the surface of the organic semiconductor layer;
    A second protective layer formed to cover the first protective layer;
    A semiconductor device comprising:
    The second protective layer has a lower solubility in the first solvent than the first protective layer.
  16. 　電子デバイスであって、
    　請求項１３～１５のいずれか１項に記載の半導体素子を有する、電子デバイス。     An electronic device,
    An electronic device comprising the semiconductor element according to any one of claims 13 to 15.
PCT/JP2019/004384 2018-02-23 2019-02-07 Semiconductor element production method, electronic device production method, semiconductor element, and electronic device WO2019163529A1 (en)

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Citations (3)

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JP2012256784A (en) * 2011-06-10 2012-12-27 Dainippon Printing Co Ltd Manufacturing method of organic semiconductor element and organic semiconductor element
WO2014045543A1 (en) * 2012-09-21 2014-03-27 凸版印刷株式会社 Thin film transistor, method for manufacturing same, and image display apparatus
JP2015233044A (en) * 2014-06-09 2015-12-24 大日本印刷株式会社 Organic semiconductor element manufacturing method and organic semiconductor element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012256784A (en) * 2011-06-10 2012-12-27 Dainippon Printing Co Ltd Manufacturing method of organic semiconductor element and organic semiconductor element
WO2014045543A1 (en) * 2012-09-21 2014-03-27 凸版印刷株式会社 Thin film transistor, method for manufacturing same, and image display apparatus
JP2015233044A (en) * 2014-06-09 2015-12-24 大日本印刷株式会社 Organic semiconductor element manufacturing method and organic semiconductor element

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