WO2019157991A1 - 一种低静态电流高psrr低压差线性稳压器电路 - Google Patents
一种低静态电流高psrr低压差线性稳压器电路 Download PDFInfo
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- WO2019157991A1 WO2019157991A1 PCT/CN2019/074470 CN2019074470W WO2019157991A1 WO 2019157991 A1 WO2019157991 A1 WO 2019157991A1 CN 2019074470 W CN2019074470 W CN 2019074470W WO 2019157991 A1 WO2019157991 A1 WO 2019157991A1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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- the present invention relates to the field of integrated circuits, and more particularly to a low quiescent current high PSRR low dropout linear regulator circuit.
- Low Dropout Regulator has the advantages of low output noise, simple circuit structure, small chip area and small electric ripple. It is an important part of power management circuit.
- the low dropout linear regulator circuit provides low output ripple power and better power supply rejection ratio (PSRR, Power Supply Rejection Ratio) for low noise performance for noise sensitive circuits such as analog and RF circuits. Therefore, it is widely used in handheld devices and portable electronic products.
- PSRR Power Supply Rejection Ratio
- the prior art low dropout linear regulator circuit shown in Figure 1 the low dropout linear regulator circuit has high gain to ensure good line and load regulation, so it can attenuate the noise of the low frequency input supply. Since the bandwidth of the low-dropout linear regulator circuit is limited and the PSRR decreases as the frequency increases, the high-frequency noise outside the bandwidth of the low-dropout linear regulator circuit cannot be attenuated by the low-dropout linear regulator circuit itself. As a result, the PSRR continues to decrease, as shown in Figure 2.
- the embodiment of the invention provides a low quiescent current high PSRR low dropout linear regulator circuit.
- the circuit includes: an error amplifier for amplifying an error of a signal of a forward input terminal and a negative input terminal; wherein, the signal of the forward input terminal is a reference signal; and the adjusting component comprises a first PMOS transistor; wherein, the first a gate of the PMOS transistor is connected to an output end of the error amplifier; a drain of the first PMOS transistor provides a circuit output end of the output voltage; and a voltage dividing circuit is connected between the drain of the first PMOS transistor and the ground, Providing a voltage division signal to a negative input terminal of the error amplifier; a band enhancement circuit coupled between the substrate of the adjustment element and a power supply voltage terminal; the band enhancement circuit forming a slave power supply voltage terminal A second path to the output that is different from the first path through the adjustment element, thereby generating an additional zero in the frequency domain.
- said band enhancement circuit comprises: a first resistor, a capacitor and a gain buffer; said gain buffer comprising a second PMOS transistor;
- the first resistor is coupled between a substrate of the first PMOS transistor and a supply voltage terminal; the capacitance is coupled between a substrate of the PMOS transistor and a source of the second PMOS transistor; A gate of the second PMOS transistor is coupled to a drain output of the first PMOS transistor; the first resistor and the capacitor form the additional zero in the frequency domain.
- the frequency of the additional zero is:
- Rc is the resistance of the first resistor and Cc is the capacitance of the capacitor.
- the PSRR of the frequency point and its nearby frequency is:
- VOUT is the output voltage
- VDD is the supply voltage
- the band enhancement circuit further includes a current source connected between the power supply voltage terminal and the source of the second PMOS transistor, and the current of the current source flows from the power supply voltage terminal to the source of the second PMOS transistor.
- the voltage dividing circuit includes a second resistor and a third resistor connected in series.
- a band enhancement circuit is disposed in the original low dropout linear regulator, and the PSRR near the frequency is increased by generating an extra zero point to eliminate noise of the power supply voltage at a certain frequency point.
- the resistance of the band enhancement circuit to move the notch frequency position, it can be used to cancel the frequency of some specific interference signals to improve the PSRR at the frequency point and its vicinity, helping the low dropout linear regulator in different scenarios. Application in .
- FIG. 3 is a circuit diagram of a low quiescent current high PSRR low dropout linear regulator according to a first embodiment of the present invention
- FIG. 4 is a circuit diagram of a low quiescent current high PSRR low dropout linear regulator according to a second embodiment of the present invention.
- FIG. 5 is a PSRR graph of a low quiescent current high PSRR low dropout linear regulator circuit according to an embodiment of the present invention
- FIG. 6 is a circuit diagram of a low quiescent current high PSRR low dropout linear regulator according to a third embodiment of the present invention.
- FIG. 7 is a graph showing changes in PSR of different resistors Rc according to an embodiment of the present invention.
- FIG. 3 is a circuit diagram of a low quiescent current high PSRR low dropout linear regulator circuit according to a first embodiment of the present invention. As shown in FIG. 3, the present invention provides a low quiescent current high PSRR low dropout linear regulator circuit including: an error amplifier 10, an adjustment component 20, a voltage dividing circuit 30, and a band enhancement circuit. 40.
- the error amplifier 10 has three ports: a forward input terminal, a negative input terminal and an output terminal.
- the forward input terminal is connected to the input voltage VREF, and the negative input terminal is connected to the voltage VFB supplied from the voltage dividing circuit 30.
- the adjustment component 20 can be a power transistor or a MOS power transistor.
- the adjusting component 20 acts as an LDO output transistor, and acts like a general linear regulator to adjust the output current by the magnitude of the voltage applied to its gate according to the magnitude of the load.
- the trim element 20 is implemented by a PMOS transistor with the source of the PMOS coupled to the VDD terminal, the gate coupled to the output of the error amplifier 10, and the drain providing the VOUT output.
- the PMOS operation provides an output voltage in its linear region.
- Voltage divider circuit 30 is coupled between the VOUT output and ground and provides a divided output signal to the negative input of error amplifier 10.
- voltage divider circuit 30 is a series circuit of resistor R1 and resistor R2, and a series connection node between resistor R1 and resistor R2 provides a divided output signal.
- the error amplifier 10 compares the divided output signal as the feedback voltage VFB with the input voltage VREF, and the difference between the two is amplified by the error amplifier 10 to control the voltage drop of the adjusting element 20, thereby stabilizing the output voltage.
- the output voltage VOUT decreases, the difference between the feedback voltage VFB and the input voltage VDD increases, the drive current output from the error amplifier 10 increases, and the voltage drop of the adjustment element 20 decreases, thereby increasing the output voltage; conversely, if the output voltage VOUT exceeds The required set value, the front drive current output from the error amplifier 10 is reduced, thereby lowering the output voltage.
- the output voltage VOUT correction is continuously performed, and the adjustment time is limited only by the loop reaction speed of the error amplifier 10 and the adjustment element 20. Because of the high gain of the low dropout linear regulator circuit to ensure good line and load regulation, it is able to attenuate the noise of the low frequency supply voltage.
- a band enhancement circuit 40 is disposed in the conventional low dropout linear regulator.
- the band enhancement circuit 40 is connected at one end to the PMOS substrate in the adjustment element 20, and the other end is connected to the power supply voltage VDD.
- the power supply voltage VDD passes through the band enhancement circuit 40 and is input to the adjustment element 20.
- the band enhancement circuit 40 generates an additional zero point, which can be improved by designing the frequency value of the zero point to eliminate the noise of the power supply voltage VDD at a certain frequency point.
- the PSRR of the frequency is disposed in the conventional low dropout linear regulator.
- the significance of the band enhancement circuit 40 is that a frequency zero is inserted between the power supply and the LDO output to filter out signals from the power supply near the frequency; from the power supply to the output, the power supply is not DC but high frequency.
- the AC signal is filtered out, which is equivalent to the band resistance enhancement (or broadening effect).
- the band enhancement circuit 40' includes a resistor Rc, a capacitor Cc, and a gain buffer 41.
- One end of the resistor Rc and the capacitor Cc are connected to the substrate of the PMOS transistor in the adjustment element 20, and the other end of the resistor Rc is connected to the power supply voltage VDD; the other end of the capacitor Cc is connected to the source of the PMOS transistor in the gain buffer 41.
- the gate of the PMOS transistor in the gain buffer 41 is connected to the drain output terminal (ie, the output voltage VOUT) of the PMOS transistor in the adjustment element 20, the drain of the PMOS transistor in the gain buffer 41 is grounded, and the substrate is connected to VDD.
- the gain buffer 41 has two functions, one is the influence of the isolation capacitor Cc on the output terminal, because the output terminal does not directly see Cc; the other function is because the resistor Rc, the capacitor Cc channel output is high impedance state (because it is the Cc end) Must be superimposed to the output through the buffer so as not to affect the position of the added notch frequency zero point, otherwise the zero position is uncontrollable or invalid.
- VDD Vac + Vdc
- Vac a small AC signal, equivalent to fluctuations in the supply voltage
- Vy Va ⁇ sin (2 ⁇ ⁇ f ⁇ t)
- Vy Va ⁇ sin (2 ⁇ ⁇ f ⁇ t)
- Vy Va ⁇ sin (2 ⁇ ⁇ f ⁇ t)
- Vy Va ⁇ sin (2 ⁇ ⁇ f ⁇ t)
- Vy Va ⁇ sin (2 ⁇ ⁇ f ⁇ t)
- Vy Va ⁇ sin (2 ⁇ ⁇ f ⁇ t)
- Vy is passed through the path 2 (ie, the enhancement loop, from the power supply voltage VDD via the RcCc and the gain) Buffer 41 to output) is generated.
- Vx is the low pass filtered voltage of Vac
- Va is the voltage after Vx is phase shifted by 90 degrees
- Va is coupled to Vy through gain buffer 41.
- Rc can be adjusted to shift the notch frequency position to provide additional attenuation at that frequency, such as attenuating 1 kHz noise present on the supply voltage VDD, thereby increasing the PSRR near that frequency, which helps improve The performance of low dropout linear regulators in different application scenarios.
- the resistance Rc of the band enhancement circuit 40 and the capacitor Cc constitute an additional zero in the frequency domain, which can be used to cancel noise at the frequency and its nearby frequencies. Since the product RcCc of the resistor Rc and the capacitor Cc is usually large, a gain buffer 41 is added to prevent the capacitor Cc from being directly connected to the load, which has no effect on the zero-pole loop of the normal path of the original low-dropout linear regulator.
- FIG. 5 is a PSRR graph of a low quiescent current high PSRR low dropout linear regulator circuit according to an embodiment of the present invention.
- line 1 is the PSRR value of the prior art low dropout linear regulator at different frequencies.
- Line 2 is the PSRR value at different frequencies using the low dropout linear regulator of the embodiment of the present invention.
- the PSRR value is maintained at a stable value at BW and at a frequency point Z'x greater than BW, and the PSRR value begins to change at frequencies greater than Z'x.
- FIG. 6 is a circuit diagram of a low quiescent current high PSRR low dropout linear regulator circuit according to a third embodiment of the present invention. As shown in FIG. 6, the difference from the foregoing embodiment is that the current source 42 is further included in the band enhancement circuit 40".
- a current source 42 is coupled between the VDD terminal and the source of the PMOS transistor in the gain buffer 41 to provide a constant current to the drain of the PMOS transistor in the gain buffer 41.
- the current source 42 is for the gain buffer 41 to independently adjust the DC operating point and the bandwidth. Since the RcCc can only generate a 90-degree phase shift, by adjusting the bandwidth of the gain buffer 41, an additional phase shift can be added to achieve better. Power supply noise cancellation effect.
- FIG. 7 is a graph showing changes in PSR of different resistors Rc according to an embodiment of the present invention. As shown in Figure 7, it can be seen in the simulation experiment that the PSRR can be adjusted by the resistor Rc. For different resistances, the frequency position of the zero point varies within a certain range, showing different suppression effects at different frequencies.
- the band enhancement circuit 40 generates an additional zero point, which will eliminate or partially cancel the noise at a certain frequency point, obtain the frequency Fz of the additional zero point according to the formula (2), and adjust the Rc to move the notch frequency position, which can be used to cancel a certain
- the frequency of these specific interfering signals is used to increase the PSRR at this frequency point and its vicinity, helping the application of low dropout linear regulators in different scenarios. For example, in GSM system 217Hz, VDD noise is usually relatively large, we hope that the low dropout linear regulator provides the largest noise reduction near this frequency point.
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Abstract
一种低静态电流高PSRR低压差线性稳压器电路。所述电路包括误差放大器(10)、调整元件(20)、分压电路(30)和频带增强电路(40);调整元件(20)的漏极连接分压电路(30)的输入端,其栅极连接误差放大器(10)的输出端;分压电路(30)的一输出端连接误差放大器(10)的一输入端;频带增强电路(40)的一端连接调整元件(20)的衬底;频带增强电路(40)形成从电源电压端到输出端的不同于经过调整元件(20)的第一路径的第二路径。在原有低压差线性稳压器中设置一个频带增强电路(40),通过产生额外的零频率,消除电源电压在某个频率点的噪声,来提高该频率附近的PSRR。
Description
本发明涉及集成电路领域,尤其涉及一种低静态电流高PSRR低压差线性稳压器电路。
低压差线性稳压器(LDO,Low Dropout Regulator)具有输出噪声小、电路结构简单、占用芯片面积小和电纹波小等优点,是电源管理电路中重要组成部分。低压差线性稳压器电路能够为模拟电路和射频电路等噪声敏感电路提供低输出纹波的电源和比较好电源抑制比(PSRR,Power Supply Rejection Ratio,电源抑制比),以及较低噪声的性能,因而被广泛应用于手持设备和便携式电子产品中。
随着集成电路的快速发展,芯片工作频率不断提高,低压差线性稳压器电路的PSRR性能也随之降低。电源噪声通过低压差线性稳压器电路影响整个***的性能,导致***不能满足在高频工作环境的应用要求。例如图1所示的现有技术的低压差线性稳压器电路,低压差线性稳压器电路具有高增益以确保良好的线路和负载调整性能,因此它能够衰减低频输入电源的噪声。由于低压差线性稳压器电路的带宽有限,且PSRR随着频率提高而降低,因此低压差线性稳压器电路的带宽之外的高频噪声无法通过低压差线性稳压器电路本身进行衰减,导致PSRR不断降低,如图2所示。
因此,提高低压差线性稳压器电路的PSRR特性是目前急需解决的问题。
发明内容
本发明实施例提出了一种低静态电流高PSRR低压差线性稳压器电路。该电路包括:误差放大器,用于对其正向输入端和负向输入端的信号的误差进行放大;其中,正向输入端的信号为参考信号;调整元件,包括第一PMOS晶体管;其中,第一PMOS晶体管的栅极连接所述误差放大器的输出端;第一PMOS晶体管的漏极提供输出电压的电路输出端;分压电路,连接在所述第一PMOS晶体管的漏极和地之间,用于提供一个分压信号到误差放大器的负向输入端;频带增强电路,所述频带增强电路耦合在所述调整元件的衬底和电源电压端之间;所述频带增强电路形成从电源电压端到输出端的不同于经过调整元件的第一路径的第二路径,由此产生频域上的额外零点。
优选地,所述频带增强电路包括:第一电阻、电容和增益缓冲器;所述增益缓冲器包括第二PMOS晶体管;
所述第一电阻耦合在所述第一PMOS晶体管的衬底和电源电压端之间;所述电容耦合在所述PMOS晶体管的衬底和所述第二PMOS晶体管的源极之间;所述第二PMOS晶体管的栅极连接所述第一PMOS晶体管的漏极输出端;所述第一电阻和所述电容构成频域上的所述额外零点。
优选地,所述额外零点的频率为:
其中,Rc为第一电阻的阻值,Cc为电容的电容值。
优选地,所述消除电源电压一个频率点的噪声后,所述频率点及其附近频率的PSRR为:
PSRR=A(s)□(1+sRcCc);
优选地,所述频带增强电路还包括电流源,连接在电源电压端和第二PMOS晶体管的源极之间,电流源的电流从电源电压端流向第二PMOS晶体 管的源极。
优选地,所述分压电路包括串联的第二电阻和第三电阻。
本发明实施例在原有低压差线性稳压器中设置一个频带增强电路,通过产生额外零点,消除电源电压在某个频率点噪声,来提高该频率附近的PSRR。另外通过调节频带增强电路的电阻,来移动陷波频率位置,可以用来抵消某些特定的干扰信号的频率,来提高该频率点及其附近的PSRR,帮助低压差线性稳压器在不同场景中的应用。
图1为现有技术中的低压差线性稳压器电路;
图2为现有技术中的低压差线性稳压器电路的PSRR的曲线图;
图3为本发明第一实施例提供的低静态电流高PSRR低压差线性稳压器电路;
图4为本发明第二实施例提供的低静态电流高PSRR低压差线性稳压器电路;
图5为本发明实施例提供的低静态电流高PSRR低压差线性稳压器电路的PSRR曲线图;
图6为本发明第三实施例提供的低静态电流高PSRR低压差线性稳压器电路;
图7为本发明实施例提供的不同电阻Rc对PSRR变化曲线图。
为使本发明实施例的技术方案以及优点表达的更清楚,下面通过附图和实施例,对本发明的技术方案做进一步的详细描述。
图3为本发明第一实施例提供的低静态电流高PSRR低压差线性稳压器电路。如图3所示,本发明提出一种低静态电流高PSRR低压差线性稳压器电路,该低压差线性稳压器电路包括:误差放大器10、调整元件20、分压电路30和频带增强电路40。
误差放大器10有三个端口:正向输入端、负向输入端和输出端,正向输入端连接输入电压VREF,负向输入端连接分压电路30提供的电压VFB。
调整元件20可以是功率晶体管或MOS功率晶体管。调整元件20作为LDO输出管,作用与一般线性稳压器一样,根据负载大小,通过施加在其栅极上的电压大小以达到调整输出电流的目的。在一个例子中,调整元件20由PMOS管实现,PMOS的源极耦合到VDD端,栅极连接误差放大器10的输出端,漏极提供VOUT输出。PMOS工作在其线性区域内提供输出电压。
分压电路30耦合在VOUT输出端和地端之间,并且提供一个分压输出信号到误差放大器10的负向输入端。在一个例子中,分压电路30为电阻R1和电阻R2的串联电路,电阻R1和电阻R2之间的串联连接节点提供分压输出信号。
误差放大器10将分压输出信号作为反馈电压VFB与输入电压VREF相比较,两者的差值经误差放大器10放大后,控制调整元件20的压降,从而稳定输出电压。当输出电压VOUT降低时,反馈电压VFB与输入电压VDD的差值增加,误差放大器10输出的驱动电流增加,调整元件20压降减小,从而使输出电压升高;相反,若输出电压VOUT超过所需要的设定值,误差放大器10输出的前驱动电流减小,从而使输出电压降低。供电过程中,输出电压VOUT校正连续进行,调整时间只受误差放大器10和调整元件20回路反应速度的限制。由于低压差线性稳压器电路具有高增益以确保良好的线路和负载调整性能,因此它能够衰减低频电源电压的噪声。
本发明实施例在现有低压差线性稳压器中配置一个频带增强电路40,频 带增强电路40一端连接在调整元件20中PMOS的衬底,另一端连接电源电压VDD。电源电压VDD通过频带增强电路40后,输入到调整元件20。由此增加经过频带增强电路40到输出端的通路,这个频带增强电路40产生额外零点,可以通过设计零点的频率值,消除电源电压VDD在某个频率点的噪声,来提高该频率点及其附近频率的PSRR。频带增强电路40的意义在于按插了一个频率零点在电源与LDO输出端之间,以滤掉在该频率附近来自电源的信号;从电源对输出端看,该电源上不是直流而是高频的交流信号被滤掉,相当于带阻增强了(或拓宽作用)。
图4为本发明第二实施例提供的低静态电流高PSRR低压差线性稳压器电路。如图4所示,本发明实施例提供的电路中,频带增强电路40’中包括一个电阻Rc、一个电容器Cc和一个增益缓冲器41。
电阻Rc和电容器Cc的各自一端连接调整元件20中PMOS晶体管的衬底,电阻Rc的另一端连接电源电压VDD;电容器Cc的另一端连接增益缓冲器41中PMOS晶体管的源极。增益缓冲器41中PMOS晶体管的栅极连接调整元件20中PMOS晶体管的漏极输出端(即输出电压VOUT),增益缓冲器41中PMOS晶体管的漏极接地,其衬底接VDD。增益缓冲器41的作用有二,一是隔离电容器Cc对输出端的影响,因为输出端没有直接看到Cc;另一作用是由于电阻Rc、电容器Cc通道输出是高阻态(因为是Cc一端),必须通过缓冲器叠加至输出端才不会影响添加的陷波频率零点的位置,否则该零点位置不可控或者无效。
让VDD=Vac+Vdc,其中Vac是一个小的交流信号,相当于电源电压的波动,Vdc是直流电压。如果Vac=0时,Vx=VDD=Vdc,此时频带增强电路40没有任何影响,其PSRR和传统低压差线性稳压器的情况一样。此时的PSRR为:
如果Vac=Va·sin(2π·f·t),这时在输出端VOUT上叠加有两个信号Vy和Vz。其中,信号Vz是经过路径1(陷波环路notch loop,即从电源电压VDD经调整元件20输出端)产生;信号Vy是通过路径2(即增强环路,从电源电压VDD经RcCc和增益缓冲器41到输出端)产生。在图4中,Vx是Vac的低通滤波后的电压,Va是Vx进行90度相移后的电压,Va通过增益缓冲器41耦合到Vy。
在输出端VOUT上叠加的信号Vy和Vz将在特定频率Fz彼此抵消或部分抵消,该特定频率Fz由下式确定:
根据Fz,可以调整Rc来移动notch频率位置,以提供在该频率处的额外衰减,例如衰减存在于电源电压VDD上的1kHz噪声,由此在该频率附近的PSRR得以提高,这有助于改善低压差线性稳压器在不同应用场景下的性能。
因此,在不改变传统的低压差线性稳压器电路中零极点,通过引入额外零点,来消除电源电压VDD在某个特定频率Fz的噪声来提高该频率点及其附近的PSRR。
PSRR=A(s)·(1+sRcCc) (3)
也就是说,频带增强电路40的电阻Rc和电容器Cc构成频域上的额外零点,可以用于消除该频率及其附近频率的噪声。由于电阻Rc和电容器Cc的乘积RcCc通常比较大,因此增加一个增益缓冲器41,避免电容器Cc直接连到负载上,这样对原来低压差线性稳压器的正常通路的零极点环路没有影响。
当然,由于在不同频率下,调整元件20中PMOS晶体管出现背栅效应,当电阻Rc越大时,A(s)会受影响,但是我们感兴趣的是剔除电源电压VDD某 些频率点的电源噪声,而不是消除整个频率范围的电源电压VDD噪声(宽带噪声),所以通过调整RcCc来实现一种单点消除电源电压VDD的噪声。
图5为本发明实施例提供的低静态电流高PSRR低压差线性稳压器电路的PSRR曲线图。如图5所示,线条1为现有技术的低压差线性稳压器在不同频率下的PSRR值,在频率Z=BW处PSRR值开始变化,高于BW的频率处的PSRR值显著降低;线条2为采用本发明实施例的低压差线性稳压器在不同频率下的PSRR值。在BW和在大于BW的频率点Z'x处PSRR值维持在稳定数值,在大于Z'x的频率处PSRR值才开始变化。
图6为本发明第三实施例提供的低静态电流高PSRR低压差线性稳压器电路。如图6所示,不同于前述实施例的地方在于,频带增强电路40”中还包括有电流源42。
电流源42连接在VDD端和增益缓冲器41中PMOS晶体管的源极之间,向增益缓冲器41中PMOS晶体管的漏极提供恒定电流。
电流源42是为了增益缓冲器41可以独立调整直流工作点以及带宽,由于RcCc只能产生90度相移,通过调整增益缓冲器41的带宽,也可以额外增加一点相移,以达到更好的电源噪声消除效果。
图7为本发明实施例提供的不同电阻Rc对PSRR变化曲线图。如图7所示,在仿真实验中可以看出PSRR可以通过电阻Rc来调节。对于不同的电阻,零点的频率位置在一定范围内变化,显示出在不同频率下不同的抑制效果。
频带增强电路40产生额外零点,将消除或部分消除在特定在某个频率点的噪声,根据公式(2)得到这个额外零点的频率Fz,调整Rc来移动陷波频率位置,可以用来抵消某些特定的干扰信号的频率,来提高该频率点及其附近的PSRR,帮助低压差线性稳压器在不同场景中的应用。比如GSM***里面217Hz,VDD噪声通常比较大,我们希望低压差线性稳压器提供最大的噪声削减在该频率点附近。
以上所述的具体实施方式,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施方式而已,并不用于限定本发明的保护范围,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (6)
- 一种低压差线性稳压器电路,包括:误差放大器(10),用于对其正向输入端和负向输入端的信号的误差进行放大;其中,正向输入端的信号为参考信号;调整元件(20),包括第一PMOS晶体管;其中,第一PMOS晶体管的栅极连接所述误差放大器(10)的输出端;第一PMOS晶体管的漏极提供输出电压的电路输出端;分压电路(30),连接在所述第一PMOS晶体管的漏极和地之间,用于提供一个分压信号到误差放大器的负向输入端;频带增强电路(40),所述频带增强电路(40)耦合在所述调整元件(20)的衬底和电源电压端之间;所述频带增强电路(40)形成从电源电压端到输出端的不同于经过调整元件的第一路径的第二路径,由此产生频域上的额外零点。
- 根据权利要求1所述的低压差线性稳压器电路,其特征在于,所述频带增强电路(40)包括:第一电阻(Rc)、电容(Cc)和增益缓冲器(41);所述增益缓冲器(41)包括第二PMOS晶体管;所述第一电阻耦合在所述第一PMOS晶体管的衬底和电源电压端之间;所述电容耦合在所述PMOS晶体管的衬底和所述第二PMOS晶体管的源极之间;所述第二PMOS晶体管的栅极连接所述第一PMOS晶体管的漏极输出端;所述第一电阻和所述电容构成频域上的所述额外零点。
- 根据权利要求2所述的低压差线性稳压器电路,其特征在于,所述频带增强电路(40)还包括电流源(42),连接在电源电压端和第二PMOS晶体管的源极之间,电流源的电流从电源电压端流向第二PMOS晶体管的源极。
- 根据权利要求1所述的低压差线性稳压器电路,其特征在于,所述分压电路(30)包括串联的第二电阻(R1)和第三电阻(R2)。
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