WO2019153724A1 - Finfet device and preparation method therefor - Google Patents

Finfet device and preparation method therefor Download PDF

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Publication number
WO2019153724A1
WO2019153724A1 PCT/CN2018/102894 CN2018102894W WO2019153724A1 WO 2019153724 A1 WO2019153724 A1 WO 2019153724A1 CN 2018102894 W CN2018102894 W CN 2018102894W WO 2019153724 A1 WO2019153724 A1 WO 2019153724A1
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metal
source
drain
finfet device
fin structure
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PCT/CN2018/102894
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French (fr)
Chinese (zh)
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郭奥
刘林林
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上海集成电路研发中心有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a FinFET device and a method of fabricating the same.
  • FinFET can greatly improve the device characteristics of MOSFETs, including suppression of short-channel effects (SCE). ), reducing device leakage, increasing drive current and improving subthreshold characteristics, etc.
  • SCE short-channel effects
  • the world's leading semiconductor foundries have already produced FinFET technology in the 16/14nm process node.
  • the FinFET technology facilitates the further reduction of the size of the MOS device, the parasitic resistance and parasitic capacitance caused by the three-dimensional device structure are more serious than the planar MOS device, especially as the size of the FinFET device is further reduced to 7 nm.
  • the parasitic resistance and parasitic capacitance of the device will become the decisive factors affecting the performance of the device, which will bring great challenges to the further improvement of the performance of the FinFET device.
  • Figure 1 shows a typical parasitic resistance diagram of a FinFET device, which mainly includes the parasitic resistance R_SD of the source and drain regions, the resistance R_extension of the Si Fin extension region between the source and drain and the channel, and the contact resistance R_contact when the source and drain regions are led out through the metal M0.
  • Figure 2 shows the simulation results of the parasitic resistance of the FinFET devices at each process node. It can be seen that as the size of the FinFET device shrinks, R_SD and R_extension do not change much, but R_contact increases significantly.
  • Figure 3 shows the typical parasitic capacitance of a FinFET device, including the gates Gate and Si Fin, the source-drain lift region, and the parasitic capacitance Cgf/Cgr/Cgm between the metal leads, while Figure 4 simulates the different device structures (changes).
  • the parasitic capacitance of different Fin heights (Hfin) can be seen that the parasitic capacitances Cgf and Gate of Gate and Fin and the parasitic capacitance Cgr of the source-drain lift region dominate the parasitic capacitance by more than 90%. Therefore, reducing the parasitic resistance and parasitic capacitance of FinFET devices has become one of the key problems to be further solved by further scaling down the FinFET technology path, and is also an important direction for improving device performance.
  • the FinFET technology line is currently expected to continue the 7nm process node. How to reduce the parasitic resistance and parasitic capacitance of the device is still one of the research hotspots. Many researchers are trying to reduce the parasitic effect of FinFET devices through various ways.
  • the present invention provides a FinFET device and a method for fabricating the same, which can greatly reduce the parasitic resistance of a FinFET device by directly preparing a metal source and a metal type drain, and simultaneously form a replacement metal source/drain structure.
  • the current mainstream source-drain structure has been improved, and the edge capacitance of the FinFET device can be significantly reduced, thereby achieving the purpose of reducing parasitic capacitance.
  • a FinFET device including a fin structure over a substrate, a gate dielectric, a gate, a source, a drain, and a metal extraction layer on the fin structure,
  • the gate and the gate dielectric cover the two sides and the upper surface of the intermediate portion of the fin structure, and the source and the drain are respectively located in the recesses at both ends of the fin structure, and the recesses are formed by etching the fin structures on both sides of the gate
  • the source is a metal-type source
  • the drain is a metal-type drain
  • the metal extraction layer is used to lead the source and the drain.
  • a method of fabricating a FinFET device includes the following steps:
  • S01 preparing a fin structure on the substrate, and forming a gate dielectric and a gate at a position intermediate the fin structure;
  • S02 defining a source region and a drain region respectively at two ends of the fin structure, and etching the source recess and the drain recess in the source region and the drain region;
  • the material of the fin structure is Si or Ge or SiGe or a III-V compound semiconductor.
  • a specific process of preparing the metal source and the metal drain is: forming a conductive metal in the source recess and the drain recess by using a thin film deposition and a photolithography and etching process, and then The Schottky barrier of the metal-semiconductor contact is controlled by interface engineering to form a metal source and a metal drain of the low barrier contact.
  • the conductive metal is Ni or Al.
  • a specific process of preparing the metal source and the metal drain is: first epitaxially growing a semiconductor layer different from the fin structure in the source trench and the drain trench, and then in the semiconductor An alloy metal is deposited on the layer, and finally the semiconductor layer is completely alloyed by an alloying process to form a metal source and a metal drain.
  • the alloy metal is Ni or Co.
  • the specific process of preparing the metal source source and the metal type drain is: directly in situ growing the high conductivity nano-conductive material by using the positioning catalyst in the source groove and the drain groove, A metal source and a metal drain are formed.
  • nano conductive material is carbon nanotubes or graphene.
  • a source region and a drain region are defined by a standard photolithography process, and then the source trench and the drain trench are etched by a conventional etching process.
  • the invention has the beneficial effects that the parasitic resistance of the FinFET device can be greatly reduced by directly preparing the metal source and the metal type drain, and the replacement metal source and drain structure formed at the same time also improves the current mainstream source-drain structure, which can be remarkable Reduce the edge capacitance of the FinFET device to reduce parasitic capacitance.
  • the FinFET technology route continues to more advanced process nodes, some high mobility channel materials will likely replace conventional Si channels, and the proposed method is fully applicable to FinFETs of different channel materials.
  • the device is therefore highly compatible with the further development of the FinFET technology route and has very important application value.
  • FIG. 1 is a typical schematic diagram of a parasitic resistance of a FinFET in the prior art.
  • Figure 2 shows the typical simulation results of the FinFET parasitic resistance in different process generations.
  • FIG. 3 is a typical schematic diagram of a parasitic capacitance of a FinFET in the prior art.
  • Figure 4 shows the simulation results of parasitic capacitance of different device structures of FinFET.
  • FIG. 5 is a schematic flow chart of a method for fabricating a FinFET device according to the present invention.
  • FIG. 6 to FIG. 9 are schematic diagrams showing the step-by-step structure of a method for fabricating a FinFET device according to the present invention.
  • a method for fabricating a FinFET device of the present invention includes the following steps:
  • a fin structure 2 is prepared on the substrate 1, and a gate dielectric and a gate 3 are formed at an intermediate position of the fin structure 2.
  • a conventional FinFET device structure is prepared, a raised fin structure is etched on the substrate, and a gate dielectric and a gate are formed at intermediate positions of the fin structure to form a gate at a position intermediate the fin structure.
  • the preparation process of the present invention adopts the current mainstream FinFET process technology, and includes a series of process steps such as photolithography, etching, oxidation, deposition, epitaxy, etc. The specific process steps and details are well known to those skilled in the art.
  • FIG. 6 depicts a gate electrode simultaneously formed on two adjacent fin structures.
  • a fin structure on a substrate is used. The number and layout of the design are determined according to the actual process.
  • the channel material of the FinFET device that is, the material of the fin structure is not limited to the current mainstream Si materials, and includes other semiconductor materials that can be used for preparing MOS devices, such as Ge, SiGe, III-V compound semiconductors. For example, InGaAs, InP, and the like.
  • a source region and a drain region are respectively defined at both ends of the fin structure 2, and a source recess 41 and a drain recess 51 are etched in the source region and the drain region.
  • the source region and the drain region can be defined by a standard photolithography process, and then the fin structure of the source region and the drain region, that is, the Fin line, is etched by a conventional etching process, and the specific etching method and process parameters can be based on the fin The different material types of the structure are optimized.
  • the metal source 4 and the metal drain 5 are respectively formed in the source recess 41 and the drain recess 51.
  • the metal source and the metal drain may be one of a conductive metal, an alloy metal or a nano conductive material. It should be noted that the metal that can be used as the metal source and source leakage in the prior art can be applied to form the metal source source and drain in the present invention, and is not necessarily limited to the scope of the specific embodiment of the present invention.
  • the method for preparing the metal source and the metal drain in the present invention may include, but is not limited to, the following three types:
  • a conductive metal is formed in the source and drain recesses by thin film deposition and photolithography and etching processes, wherein the conductive metal is Ni or Al. Then, the Schottky barrier of the metal-semiconductor contact is controlled by interface engineering to form a metal source and a metal drain of the low barrier contact.
  • the substrate is an N-type semiconductor
  • the work function of the conductive metal needs to be greater than the work function of the substrate.
  • an electron barrier and a hole barrier are formed on the surface of the semiconductor, respectively. The barrier acts as a barrier to charge transport, thereby forming a Schottky contact.
  • the work function of the conductive metal needs to be smaller than the work function of the substrate.
  • an electron barrier and a hole barrier are formed on the surface of the semiconductor, respectively.
  • the barrier acts as a barrier to charge transport, thereby forming a Schottky contact.
  • a Schottky barrier formed by metal-semiconductor contact is controlled by interface engineering to form a metal-type source and a metal-type drain of a low barrier contact.
  • a semiconductor layer different from the fin structure is epitaxially grown in the source recess and the drain recess, and then an alloy metal is deposited on the semiconductor layer, wherein the alloy metal is Ni or Co. Finally, the semiconductor layer is completely alloyed by an alloy process to form a metal source and a metal drain.
  • the source and the drain are respectively taken out by the lead-out terminal 6, and are prepared by a subsequent process.
  • the metal source and the metal drain can be taken out by using the lead-out method in the prior art, and the FinFET device structure is subsequently processed according to an actual process, which will not be described in detail herein.
  • the FinFET device prepared by the above preparation method comprises a fin structure on a substrate, a gate dielectric, a gate, a source, a drain and a metal extraction layer on the fin structure, and the gate and the gate dielectric cover the fin structure
  • the source and the drain are respectively located in the grooves at both ends of the fin structure, and the grooves are obtained by etching the fin structures on both sides of the gate
  • the source is a metal source
  • the drain is a metal type.
  • the drain, metal extraction layer is used to lead the source and drain.
  • the invention can greatly reduce the parasitic resistance of the FinFET device by directly preparing the metal source and the metal type drain, and the formed metal source/drain structure is also improved by the current mainstream source/drain structure, and the edge of the FinFET device can be significantly reduced. Capacitance to achieve the purpose of reducing parasitic capacitance.
  • some high mobility channel materials will likely replace conventional Si channels, and the proposed method is fully applicable to FinFETs of different channel materials. The device is therefore highly compatible with the further development of the FinFET technology route and has very important application value.

Abstract

A preparation method for a fin field-effect transistor (FinFET) device, the method comprising the following steps: S01: preparing a fin structure (2) on a substrate (1), and forming a gate medium and a gate electrode (3) at a middle position of the fin structure; S02: defining a source electrode region and a drain electrode region at two ends of the fin structure respectively, and etching a source electrode groove (41) and a drain electrode groove (51) in the source electrode region and the drain electrode region; S03: preparing a metal source electrode (4) and a metal drain electrode (5) in the source electrode groove and the drain electrode groove respectively; S04: performing metal lead-out and rear channel processing preparation on the source electrode and the drain electrode. The present preparation method for a FinFET device may significantly reduce the parasitic resistance of a FinFET device by means of directly preparing a metal source electrode and metal drain electrode, and at the same time, the formed substitute metal source-drain structure also improves current mainstream boosting source-drain structures, which may greatly reduce the edge capacitance of a FinFET device, thereby achieving the goal of reducing parasitic resistance.

Description

一种FinFET器件及其制备方法FinFET device and preparation method thereof 技术领域Technical field
本发明涉及半导体技术领域，特别涉及一种FinFET器件及其制备方法。The present invention relates to the field of semiconductor technology, and in particular, to a FinFET device and a method of fabricating the same.
技术背景technical background
随着半导体工艺技术节点的不断缩小，传统的平面MOSFET遇到了越来越多的技术挑战，FinFET作为一种新型的三维器件结构，可以极大地提升MOSFET的器件特性，包括抑制短沟效应(SCE)、减小器件漏电、提高驱动电流以及提升亚阈值特性等等，目前，国际上领先的半导体代工厂都已经在16/14nm工艺节点中量产了FinFET技术。然而，虽然FinFET技术为MOS器件尺寸的进一步缩小提供了便利，但其三维器件结构所引起的寄生电阻和寄生电容相比平面MOS器件也更为严重，尤其是随着FinFET器件尺寸进一步缩小至7nm工艺代，器件的寄生电阻和寄生电容将会成为影响器件性能的决定性因素，这将给FinFET器件性能的进一步提升带来巨大挑战。As semiconductor process technology nodes continue to shrink, traditional planar MOSFETs encounter more and more technical challenges. As a new three-dimensional device structure, FinFET can greatly improve the device characteristics of MOSFETs, including suppression of short-channel effects (SCE). ), reducing device leakage, increasing drive current and improving subthreshold characteristics, etc. Currently, the world's leading semiconductor foundries have already produced FinFET technology in the 16/14nm process node. However, although the FinFET technology facilitates the further reduction of the size of the MOS device, the parasitic resistance and parasitic capacitance caused by the three-dimensional device structure are more serious than the planar MOS device, especially as the size of the FinFET device is further reduced to 7 nm. In the process generation, the parasitic resistance and parasitic capacitance of the device will become the decisive factors affecting the performance of the device, which will bring great challenges to the further improvement of the performance of the FinFET device.
图1所示为FinFET器件典型的寄生电阻示意图，主要包括源漏区域的寄生电阻R_SD、源漏与沟道之间Si Fin扩展区域的电阻R_extension以及源漏区域通过金属M0引出时接触电阻R_contact，图2所示为各工艺节点的FinFET器件寄生电阻的仿真结果，可以看出，随着FinFET器件尺寸的不断缩小，R_SD和R_extension变化不大，但是R_contact则显著增加。图3示意了FinFET器件典型的寄生电容，分别包括了栅极Gate与Si Fin、源漏提升区域以及金属引出之间的寄生电容Cgf/Cgr/Cgm，而图4则仿真了不同器件结构(变化不同Fin高度Hfin)的寄生电容，可以看出，Gate与Fin的寄生电容Cgf和Gate与源漏提升区域的寄生电容Cgr主导了超过90％的寄生 电容。因此，降低FinFET器件的寄生电阻和寄生电容已成为FinFET技术路线进一步按比例缩小亟需解决的关键难题之一，也是提升器件性能的重要努力方向。Figure 1 shows a typical parasitic resistance diagram of a FinFET device, which mainly includes the parasitic resistance R_SD of the source and drain regions, the resistance R_extension of the Si Fin extension region between the source and drain and the channel, and the contact resistance R_contact when the source and drain regions are led out through the metal M0. Figure 2 shows the simulation results of the parasitic resistance of the FinFET devices at each process node. It can be seen that as the size of the FinFET device shrinks, R_SD and R_extension do not change much, but R_contact increases significantly. Figure 3 shows the typical parasitic capacitance of a FinFET device, including the gates Gate and Si Fin, the source-drain lift region, and the parasitic capacitance Cgf/Cgr/Cgm between the metal leads, while Figure 4 simulates the different device structures (changes). The parasitic capacitance of different Fin heights (Hfin) can be seen that the parasitic capacitances Cgf and Gate of Gate and Fin and the parasitic capacitance Cgr of the source-drain lift region dominate the parasitic capacitance by more than 90%. Therefore, reducing the parasitic resistance and parasitic capacitance of FinFET devices has become one of the key problems to be further solved by further scaling down the FinFET technology path, and is also an important direction for improving device performance.
FinFET技术路线目前预计可延续制7nm工艺节点，如何降低器件的寄生电阻和寄生电容仍然是研究热点之一，众多的研究人员正在尝试通过各种途径降低FinFET器件的寄生效应。The FinFET technology line is currently expected to continue the 7nm process node. How to reduce the parasitic resistance and parasitic capacitance of the device is still one of the research hotspots. Many researchers are trying to reduce the parasitic effect of FinFET devices through various ways.
发明概要Summary of invention
为了解决上述技术问题，本发明提供了一种FinFET器件及其制备方法，通过直接制备金属型源极和金属型漏极可大幅降低FinFET器件的寄生电阻，同时形成的替换型金属源漏结构也改进了目前主流的提升源漏结构，可显著降低FinFET器件的边缘电容，从而达到降低寄生电容的目的。In order to solve the above technical problem, the present invention provides a FinFET device and a method for fabricating the same, which can greatly reduce the parasitic resistance of a FinFET device by directly preparing a metal source and a metal type drain, and simultaneously form a replacement metal source/drain structure. The current mainstream source-drain structure has been improved, and the edge capacitance of the FinFET device can be significantly reduced, thereby achieving the purpose of reducing parasitic capacitance.
为了实现上述目的，本发明采用如下技术方案：一种FinFET器件，包括位于衬底之上的鳍结构，位于鳍结构上的栅介质、栅极、源极、漏极以及金属引出层，所述栅极和栅介质覆盖于鳍结构中间部分的两侧和上表面，所述源极和漏极分别位于鳍结构两端的凹槽中，所述凹槽通过刻蚀栅极两侧的鳍结构得出，所述源极为金属型源极，所述漏极为金属型漏极，所述金属引出层用于将源极和漏极引出。In order to achieve the above object, the present invention adopts the following technical solution: a FinFET device including a fin structure over a substrate, a gate dielectric, a gate, a source, a drain, and a metal extraction layer on the fin structure, The gate and the gate dielectric cover the two sides and the upper surface of the intermediate portion of the fin structure, and the source and the drain are respectively located in the recesses at both ends of the fin structure, and the recesses are formed by etching the fin structures on both sides of the gate The source is a metal-type source, the drain is a metal-type drain, and the metal extraction layer is used to lead the source and the drain.
一种FinFET器件的制作方法，包括以下步骤：A method of fabricating a FinFET device includes the following steps:
S01：在衬底上制备鳍结构，并在鳍结构中间位置形成栅介质和栅极；S01: preparing a fin structure on the substrate, and forming a gate dielectric and a gate at a position intermediate the fin structure;
S02：在鳍结构两端分别定义出源极区域和漏极区域，并在源极区域和漏极区域中刻蚀出源极凹槽和漏极凹槽；S02: defining a source region and a drain region respectively at two ends of the fin structure, and etching the source recess and the drain recess in the source region and the drain region;
S03：在源极凹槽和漏极凹槽中分别制备金属型源极和金属型漏极；S03: preparing a metal source source and a metal type drain in the source recess and the drain recess respectively;
S04：对源极和漏极进行金属引出及后道工艺制备。S04: metal extraction and subsequent process preparation for source and drain.
进一步地，所述鳍结构的材料为Si或Ge或SiGe或III-V族化合物半导体。Further, the material of the fin structure is Si or Ge or SiGe or a III-V compound semiconductor.
进一步地，所述步骤S03中，制备金属型源极和金属型漏极的具体过程为：利用薄膜沉积以及光刻和刻蚀工艺在源极凹槽和漏极凹槽中形成导电金属，然后利用界面工程调控金属-半导体接触的肖特基势垒，形成低势垒接触的金属型源极和金属型漏极。Further, in the step S03, a specific process of preparing the metal source and the metal drain is: forming a conductive metal in the source recess and the drain recess by using a thin film deposition and a photolithography and etching process, and then The Schottky barrier of the metal-semiconductor contact is controlled by interface engineering to form a metal source and a metal drain of the low barrier contact.
进一步地，所述导电金属为Ni或Al。Further, the conductive metal is Ni or Al.
进一步地，所述步骤S03中，制备金属型源极和金属型漏极的具体过程为：先在源极凹槽和漏极凹槽中外延生长不同于鳍结构的半导体层，然后在该半导体层上淀积合金金属，最后通过合金工艺对该半导体层进行完全合金化，形成金属型源极和金属型漏极。Further, in the step S03, a specific process of preparing the metal source and the metal drain is: first epitaxially growing a semiconductor layer different from the fin structure in the source trench and the drain trench, and then in the semiconductor An alloy metal is deposited on the layer, and finally the semiconductor layer is completely alloyed by an alloying process to form a metal source and a metal drain.
进一步地，所述合金金属为Ni或Co。Further, the alloy metal is Ni or Co.
进一步地，所述步骤S03中，制备金属型源极和金属型漏极的具体过程为：在源极凹槽和漏极凹槽中采用定位催化剂直接原位生长高导电率的纳米导电材料，形成金属型源极和金属型漏极。Further, in the step S03, the specific process of preparing the metal source source and the metal type drain is: directly in situ growing the high conductivity nano-conductive material by using the positioning catalyst in the source groove and the drain groove, A metal source and a metal drain are formed.
进一步地，所述纳米导电材料为碳纳米管或石墨烯。Further, the nano conductive material is carbon nanotubes or graphene.
进一步地，所述步骤S02中通过标准光刻工艺定义出源极区域和漏极区域，然后通过常规刻蚀工艺刻蚀源极凹槽和漏极凹槽。Further, in the step S02, a source region and a drain region are defined by a standard photolithography process, and then the source trench and the drain trench are etched by a conventional etching process.
本发明的有益效果为：通过直接制备金属型源极和金属型漏极可大幅降低FinFET器件的寄生电阻，同时形成的替换型金属源漏结构也改进了目前主流的提升源漏结构，可显著降低FinFET器件的边缘电容，从而达到降低 寄生电容的目的。另一方面，随着FinFET技术路线进一步延续至更先进工艺节点，一些高迁移率的沟道材料将可能替换传统的Si沟道，而本发明所提出的方法完全适用于不同沟道材料的FinFET器件，因此可高度兼容FinFET技术路线的进一步发展，具有非常重要的应用价值。The invention has the beneficial effects that the parasitic resistance of the FinFET device can be greatly reduced by directly preparing the metal source and the metal type drain, and the replacement metal source and drain structure formed at the same time also improves the current mainstream source-drain structure, which can be remarkable Reduce the edge capacitance of the FinFET device to reduce parasitic capacitance. On the other hand, as the FinFET technology route continues to more advanced process nodes, some high mobility channel materials will likely replace conventional Si channels, and the proposed method is fully applicable to FinFETs of different channel materials. The device is therefore highly compatible with the further development of the FinFET technology route and has very important application value.
附图说明DRAWINGS
图1为现有技术中FinFET寄生电阻的典型示意图。FIG. 1 is a typical schematic diagram of a parasitic resistance of a FinFET in the prior art.
图2为FinFET寄生电阻在不同工艺代的典型仿真结果。Figure 2 shows the typical simulation results of the FinFET parasitic resistance in different process generations.
图3为现有技术中FinFET寄生电容的典型示意图。FIG. 3 is a typical schematic diagram of a parasitic capacitance of a FinFET in the prior art.
图4为FinFET不同器件结构的寄生电容仿真结果。Figure 4 shows the simulation results of parasitic capacitance of different device structures of FinFET.
图5为本发明所一种FinFET器件制备方法的流程示意图。FIG. 5 is a schematic flow chart of a method for fabricating a FinFET device according to the present invention.
图6至图9为本发明一种FinFET器件制备方法的分步骤结构示意图。6 to FIG. 9 are schematic diagrams showing the step-by-step structure of a method for fabricating a FinFET device according to the present invention.
1衬底，2鳍结构，3栅极，4源极，41源极凹槽，5漏极，51漏极凹槽，6引出端。1 substrate, 2 fin structure, 3 gates, 4 sources, 41 source recesses, 5 drains, 51 drain recesses, 6 terminals.
发明内容Summary of the invention
以下将结合说明书附图对本发明的内容作进一步的详细描述。应理解的是本发明能够在不同的示例上具有各种的变化，其皆不脱离本发明的范围，且其中的说明及图示在本质上当作说明之用，而非用以限制本发明。需说明的是，附图均采用非常简化的形式且均使用非精准的比率，仅用以方便、明晰地辅助说明本发明实施例的目的。The contents of the present invention will be further described in detail below with reference to the accompanying drawings. It is to be understood that the invention is not to be construed as being limited It should be noted that the drawings are in a very simplified form and both use non-precise ratios, and are merely for convenience and clarity of the purpose of the embodiments of the present invention.
如附图5所示，本发明一种FinFET器件的制备方法，包括以下步骤：As shown in FIG. 5, a method for fabricating a FinFET device of the present invention includes the following steps:
S01：如附图6所示，在衬底1上制备鳍结构2，在鳍结构2中间位置形成栅介质和栅极3。S01: As shown in FIG. 6, a fin structure 2 is prepared on the substrate 1, and a gate dielectric and a gate 3 are formed at an intermediate position of the fin structure 2.
首先制备常规FinFET器件结构，在衬底上刻蚀出凸起的鳍结构，并在鳍结构的中间位置形成栅介质和栅极，形成位于鳍结构中间位置的栅极。本发明中制备工艺采用目前主流的FinFET工艺技术，包含一系列光刻、刻蚀、氧化、淀积、外延等工艺步骤的组合，具体的工艺步骤和细节为本领域的一般技术人员所熟知，在此不作赘述，制备完常规FinFET器件结构的器件示意图如图6所示，附图6中描述了两个相邻的鳍结构上同时形成栅极，在实际生产工艺中，衬底上鳍结构的个数以及设计排布方式根据实际工艺具体确定。First, a conventional FinFET device structure is prepared, a raised fin structure is etched on the substrate, and a gate dielectric and a gate are formed at intermediate positions of the fin structure to form a gate at a position intermediate the fin structure. The preparation process of the present invention adopts the current mainstream FinFET process technology, and includes a series of process steps such as photolithography, etching, oxidation, deposition, epitaxy, etc. The specific process steps and details are well known to those skilled in the art. Without further elaboration, a schematic diagram of a device for fabricating a conventional FinFET device structure is shown in FIG. 6. FIG. 6 depicts a gate electrode simultaneously formed on two adjacent fin structures. In an actual production process, a fin structure on a substrate is used. The number and layout of the design are determined according to the actual process.
通常栅极周围及器件结构表面会覆盖各种隔离介质材料，这里为图示方便，略去各种隔离介质材料。需要说明的是，上述FinFET器件的沟道材料，即鳍结构的材料并不限于目前主流的Si材料，也包括其他可用于制备MOS器件的半导体材料，如Ge、SiGe、III-V族化合物半导体，例如InGaAs、InP等等。Generally, various isolation dielectric materials are covered around the gate and on the surface of the device structure. Here, for convenience of illustration, various isolation dielectric materials are omitted. It should be noted that the channel material of the FinFET device, that is, the material of the fin structure is not limited to the current mainstream Si materials, and includes other semiconductor materials that can be used for preparing MOS devices, such as Ge, SiGe, III-V compound semiconductors. For example, InGaAs, InP, and the like.
S02：如附图7所示，在鳍结构2两端分别定义出源极区域和漏极区域，并在源极区域和漏极区域中刻蚀出源极凹槽41和漏极凹槽51。这里通过标准光刻工艺即可定义源极区域和漏极区域，然后通过常规刻蚀工艺刻蚀源极区域和漏极区域的鳍结构，即Fin线条，具体刻蚀方法及工艺参数可根据鳍结构的不同材料类型进行优化。S02: as shown in FIG. 7, a source region and a drain region are respectively defined at both ends of the fin structure 2, and a source recess 41 and a drain recess 51 are etched in the source region and the drain region. . Here, the source region and the drain region can be defined by a standard photolithography process, and then the fin structure of the source region and the drain region, that is, the Fin line, is etched by a conventional etching process, and the specific etching method and process parameters can be based on the fin The different material types of the structure are optimized.
S03：如附图8所示，在源极凹槽41和漏极凹槽51中分别制备金属型源极4和金属型漏极5。本发明中金属型源极和金属型漏极可以为导电金属、合金金属或者纳米导电材料中的一种。值得说明的是，现有技 术中可以作为金属型源漏的金属均可应用与本发明中形成金属型源漏，并不一定局限在本发明具体实施例中的范围。S03: As shown in FIG. 8, the metal source 4 and the metal drain 5 are respectively formed in the source recess 41 and the drain recess 51. In the present invention, the metal source and the metal drain may be one of a conductive metal, an alloy metal or a nano conductive material. It should be noted that the metal that can be used as the metal source and source leakage in the prior art can be applied to form the metal source source and drain in the present invention, and is not necessarily limited to the scope of the specific embodiment of the present invention.
其中，本发明中制备金属型源极和金属型漏极的方法可以包括但不局限于如下三种：The method for preparing the metal source and the metal drain in the present invention may include, but is not limited to, the following three types:
①利用薄膜沉积以及光刻和刻蚀工艺在源极凹槽和漏极凹槽中形成导电金属，其中，导电金属为Ni或Al。然后利用界面工程调控金属-半导体接触的肖特基势垒，形成低势垒接触的金属型源极和金属型漏极。当衬底为N型半导体时，导电金属的功函数需要大于衬底的功函数，此时，导电金属和半导体接触之后，分别在半导体表面形成了电子势垒和空穴势垒，这类势垒对电荷传输都起到阻挡作用，从而形成肖特基接触。当衬底为P型半导体时，导电金属的功函数需要小于衬底的功函数，此时，导电金属和半导体接触之后，分别在半导体表面形成了电子势垒和空穴势垒，这类势垒对电荷传输都起到阻挡作用，从而形成肖特基接触。本发明中利用界面工程调控金属-半导体接触形成的肖特基势垒，从而形成低势垒接触的金属型源极和金属型漏极。A conductive metal is formed in the source and drain recesses by thin film deposition and photolithography and etching processes, wherein the conductive metal is Ni or Al. Then, the Schottky barrier of the metal-semiconductor contact is controlled by interface engineering to form a metal source and a metal drain of the low barrier contact. When the substrate is an N-type semiconductor, the work function of the conductive metal needs to be greater than the work function of the substrate. At this time, after the conductive metal and the semiconductor are in contact, an electron barrier and a hole barrier are formed on the surface of the semiconductor, respectively. The barrier acts as a barrier to charge transport, thereby forming a Schottky contact. When the substrate is a P-type semiconductor, the work function of the conductive metal needs to be smaller than the work function of the substrate. At this time, after the conductive metal and the semiconductor are in contact, an electron barrier and a hole barrier are formed on the surface of the semiconductor, respectively. The barrier acts as a barrier to charge transport, thereby forming a Schottky contact. In the present invention, a Schottky barrier formed by metal-semiconductor contact is controlled by interface engineering to form a metal-type source and a metal-type drain of a low barrier contact.
②先在源极凹槽和漏极凹槽中外延生长不同于鳍结构的半导体层，然后在该半导体层上淀积合金金属，其中，合金金属为Ni或Co。最后通过合金工艺对该半导体层进行完全合金化，形成金属型源极和金属型漏极。2 First, a semiconductor layer different from the fin structure is epitaxially grown in the source recess and the drain recess, and then an alloy metal is deposited on the semiconductor layer, wherein the alloy metal is Ni or Co. Finally, the semiconductor layer is completely alloyed by an alloy process to form a metal source and a metal drain.
③在源极凹槽和漏极凹槽中采用定位催化剂直接原位生长高导电率的纳米导电材料，其中，纳米导电材料为碳纳米管或石墨烯，从而形成金属型源极和金属型漏极。3 In-situ growth of high conductivity nano-conducting materials by using a positioning catalyst in the source and drain recesses, wherein the nano-conducting material is carbon nanotubes or graphene, thereby forming metal-type source and metal-type drain pole.
S04：如附图9所示，采用引出端6分别对源极和漏极进行金属引出，并进行后道工艺制备。在本步骤中，可以采用现有技术中的引出方式将金属型源极和金属型漏极引出，并根据实际工艺对上述FinFET器件结构进行后续处理，在此不做详细介绍。S04: As shown in FIG. 9, the source and the drain are respectively taken out by the lead-out terminal 6, and are prepared by a subsequent process. In this step, the metal source and the metal drain can be taken out by using the lead-out method in the prior art, and the FinFET device structure is subsequently processed according to an actual process, which will not be described in detail herein.
利用上述制备方法制备出的FinFET器件，包括位于衬底之上的鳍结构，位于鳍结构上的栅介质、栅极、源极、漏极以及金属引出层，栅极和栅介质覆盖于鳍结构中间部分的两侧和上表面，源极和漏极分别位于鳍结构两端的凹槽中，凹槽通过刻蚀栅极两侧的鳍结构得出，源极为金属型源极，漏极为金属型漏极，金属引出层用于将源极和漏极引出。The FinFET device prepared by the above preparation method comprises a fin structure on a substrate, a gate dielectric, a gate, a source, a drain and a metal extraction layer on the fin structure, and the gate and the gate dielectric cover the fin structure On both sides and the upper surface of the middle portion, the source and the drain are respectively located in the grooves at both ends of the fin structure, and the grooves are obtained by etching the fin structures on both sides of the gate, the source is a metal source, and the drain is a metal type. The drain, metal extraction layer is used to lead the source and drain.
本发明通过直接制备金属型源极和金属型漏极可大幅降低FinFET器件的寄生电阻，同时形成的替换型金属源漏结构也改进了目前主流的提升源漏结构，可显著降低FinFET器件的边缘电容，从而达到降低寄生电容的目的。另一方面，随着FinFET技术路线进一步延续至更先进工艺节点，一些高迁移率的沟道材料将可能替换传统的Si沟道，而本发明所提出的方法完全适用于不同沟道材料的FinFET器件，因此可高度兼容FinFET技术路线的进一步发展，具有非常重要的应用价值。The invention can greatly reduce the parasitic resistance of the FinFET device by directly preparing the metal source and the metal type drain, and the formed metal source/drain structure is also improved by the current mainstream source/drain structure, and the edge of the FinFET device can be significantly reduced. Capacitance to achieve the purpose of reducing parasitic capacitance. On the other hand, as the FinFET technology route continues to more advanced process nodes, some high mobility channel materials will likely replace conventional Si channels, and the proposed method is fully applicable to FinFETs of different channel materials. The device is therefore highly compatible with the further development of the FinFET technology route and has very important application value.
以上所述的仅为本发明的实施例，所述实施例并非用以限制本发明专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明的保护范围内。The above is only the embodiment of the present invention, and the embodiment is not intended to limit the scope of the patent protection of the present invention. Therefore, equivalent structural changes made by using the description of the present invention and the contents of the drawings should be included in the same. Within the scope of protection of the invention.

Claims (10)

  1. 一种FinFET器件，其特征在于，包括位于衬底之上的鳍结构，位于鳍结构上的栅介质、栅极、源极、漏极以及金属引出层，所述栅极和栅介质覆盖于鳍结构中间部分的两侧和上表面，所述源极和漏极分别位于鳍结构两端的凹槽中，所述凹槽通过刻蚀栅极两侧的鳍结构得出，所述源极为金属型源极，所述漏极为金属型漏极，所述金属引出层用于将源极和漏极引出。A FinFET device, comprising: a fin structure over a substrate, a gate dielectric, a gate, a source, a drain, and a metal extraction layer on the fin structure, the gate and gate dielectric covering the fin On both sides and an upper surface of the middle portion of the structure, the source and the drain are respectively located in the grooves at both ends of the fin structure, and the grooves are obtained by etching the fin structures on both sides of the gate, the source being extremely metallic a source, the drain is a metal-type drain, and the metal extraction layer is used to lead the source and the drain.
  2. 一种制作权利要求1所述FinFET器件的方法，其特征在于，包括以下步骤：A method of fabricating the FinFET device of claim 1 comprising the steps of:
    S01：在衬底上制备鳍结构，并在鳍结构中间位置形成栅介质和栅极；S01: preparing a fin structure on the substrate, and forming a gate dielectric and a gate at a position intermediate the fin structure;
    S02：在鳍结构两端分别定义出源极区域和漏极区域，并在源极区域和漏极区域中刻蚀出源极凹槽和漏极凹槽；S02: defining a source region and a drain region respectively at two ends of the fin structure, and etching the source recess and the drain recess in the source region and the drain region;
    S03：在源极凹槽和漏极凹槽中分别制备金属型源极和金属型漏极；S03: preparing a metal source source and a metal type drain in the source recess and the drain recess respectively;
    S04：对源极和漏极进行金属引出及后道工艺制备。S04: metal extraction and subsequent process preparation for source and drain.
  3. 根据权利要求2所述的一种制备FinFET器件的方法，其特征在于，所述鳍结构的材料为Si或Ge或SiGe或III-V族化合物半导体。A method of fabricating a FinFET device according to claim 2, wherein the material of the fin structure is Si or Ge or a SiGe or III-V compound semiconductor.
  4. 根据权利要求2所述的一种制备FinFET器件的方法，其特征在于，所述步骤S03中，制备金属型源极和金属型漏极的具体过程为：利用薄膜沉积以及光刻和刻蚀工艺在源极凹槽和漏极凹槽中形成导电金属，然后利用界面工程调控金属-半导体接触的肖特基势垒，形成低势垒接触的金属型源极和金属型漏极。The method for fabricating a FinFET device according to claim 2, wherein in the step S03, the specific process of preparing the metal source and the metal drain is: using thin film deposition and photolithography and etching processes. A conductive metal is formed in the source and drain recesses, and then a Schottky barrier of the metal-semiconductor contact is controlled by interfacial engineering to form a metal source and a metal drain of the low barrier contact.
  5. 根据权利要求4所述的一种制备FinFET器件的方法，其特征在于，所述导电金属为Ni或Al。A method of fabricating a FinFET device according to claim 4, wherein the conductive metal is Ni or Al.
  6. 根据权利要求2所述的一种制备FinFET器件的方法，其特征在于，所述步骤S03中，制备金属型源极和金属型漏极的具体过程为：先在源极凹槽和漏极凹槽中外延生长不同于鳍结构的半导体层，然后在该半导体层上淀积合金金属，最后通过合金工艺对该半导体层进行完全合金化，形成金属型源极和金属型漏极。A method of fabricating a FinFET device according to claim 2, wherein in the step S03, the specific process of preparing the metal source and the metal drain is: first in the source recess and the drain recess A semiconductor layer different from the fin structure is epitaxially grown in the trench, and then an alloy metal is deposited on the semiconductor layer, and finally the semiconductor layer is completely alloyed by an alloy process to form a metal source and a metal drain.
  7. 根据权利要求6所述的一种制备FinFET器件的方法，其特征在于，所述合金金属为Ni或Co。A method of fabricating a FinFET device according to claim 6, wherein the alloy metal is Ni or Co.
  8. 根据权利要求2所述的一种制备FinFET器件的方法，其特征在于，所述步骤S03中，制备金属型源极和金属型漏极的具体过程为：在源极凹槽和漏极凹槽中采用定位催化剂直接原位生长高导电率的纳米导电材料，形成金属型源极和金属型漏极。A method of fabricating a FinFET device according to claim 2, wherein in the step S03, a specific process of preparing a metal source and a metal drain is: a source trench and a drain trench A high-conductivity nano-conductive material is directly grown in situ by using a positioning catalyst to form a metal-type source and a metal-type drain.
  9. 根据权利要求8所述的一种制备FinFET器件的方法，其特征在于，所述纳米导电材料为碳纳米管或石墨烯。A method of fabricating a FinFET device according to claim 8, wherein the nano-conductive material is carbon nanotubes or graphene.
  10. 根据权利要求1所述的一种制备FinFET器件的方法，其特征在于，所述步骤S02中通过标准光刻工艺定义出源极区域和漏极区域，然后通过常规刻蚀工艺刻蚀源极凹槽和漏极凹槽。A method of fabricating a FinFET device according to claim 1, wherein in the step S02, a source region and a drain region are defined by a standard photolithography process, and then the source recess is etched by a conventional etching process. Slot and drain grooves.
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