WO2019142173A1 - Voltage compensation device and method - Google Patents

Voltage compensation device and method Download PDF

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Publication number
WO2019142173A1
WO2019142173A1 PCT/IB2019/050535 IB2019050535W WO2019142173A1 WO 2019142173 A1 WO2019142173 A1 WO 2019142173A1 IB 2019050535 W IB2019050535 W IB 2019050535W WO 2019142173 A1 WO2019142173 A1 WO 2019142173A1
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WO
WIPO (PCT)
Prior art keywords
edlc
voltage
current
comment
operating
Prior art date
Application number
PCT/IB2019/050535
Other languages
Spanish (es)
French (fr)
Inventor
Daniel Alberto ARROYAVE MOLINA
Andrés Emiro DÍEZ RESTREPO
Diego Alejandro MÚNERA HOYOS
José Valentín Antonio RESTREPO LAVERDE
José Armando BOHÓRQUEZ CORTÁZAR
Mauricio FIGUEROA CARRILLO
Luis Eduardo CASTRILLÓN AGUDELO
Edison de Jesús MANRIQUE OSPINA
Carlos Arturo RODRÍGUEZ GÓMEZ
Idi Amin ISAAC MILLÁN
Original Assignee
Universidad Pontificia Bolivariana
Empresa De Trasporte Masivo Del Valle De Aburra Ltda. - Metro De Medellin Ltda
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Universidad Pontificia Bolivariana, Empresa De Trasporte Masivo Del Valle De Aburra Ltda. - Metro De Medellin Ltda filed Critical Universidad Pontificia Bolivariana
Priority to PE2020001007A priority Critical patent/PE20201180A1/en
Publication of WO2019142173A1 publication Critical patent/WO2019142173A1/en

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/125—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M3/135—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
    • H02M3/137—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Definitions

  • the present invention is related to regenerative braking devices, and more specifically, to a device and a direct current voltage compensation method for utilizing regenerative braking based on ultracapacitors.
  • Regenerative braking is a braking mechanism that allows when a vehicle slows the kinetic energy of the movement of the vehicle into electrical energy so that this energy is then stored, in a traditional braking device this energy dissipates in the form of heat and vibration, which tends to wear the same braking device.
  • the regenerative braking device not only reduces energy consumption but also prevents the generation of measurement caused by the friction of the brake and the wear of the brake pads of a vehicle.
  • the concept encompasses a variety of forms of energy storage that includes hydraulic or pneumatic, electrical or by means of a flywheel as do the vehicles of formula one. Some modern trains make use of regenerative braking devices to save energy.
  • the energy generated from regenerative braking is used to extend the battery life and, on the contrary, in train devices, the energy generated is generally injected into the same power supply device to compensate for variations in the line of transmission.
  • a regenerative braking device should not be confused with a dynamic braking device, since in the latter the kinetic energy is not stored but used for the same braking, that is, the traction motors of the moving vehicle during dynamic braking They function as a generator and are connected to a braking resistor bank that, by way of loading on the motors, reduces their rotation.
  • dynamic braking is done by short-circuiting their terminals, this is reflected in a violent braking of the motor shaft.
  • This method dissipates all the kinetic energy of the motor shaft rotation, in the form of heat in the same motor and therefore is limited to its cooling capacity, and does not allow it to be used in any way other than intermittent and with low power, it is additionally not suitable for applications where large tensile forces are required.
  • document US 5710699 A discloses a device and a method for compensating the charge of a battery in an electric power device.
  • the device disclosed in US 5710699 A is an arrangement for the compensation of the battery charge for an electrically powered device in which the battery charge is subject to intermittent demands of high currents, the device includes a coupled battery to supply power to a direct current link, a load, and a controller of the device coupled between the direct current link and the load to dose the power in the load, said arrangement for compensating the battery charge comprises a device passive energy storage, a first bidirectional converter coupled with the passive energy storage device and the direct current link to transmit electrical power between the direct current link and the energy storage device, a second bidirectional converter coupled between the battery and the direct feedback link to transfer the electrical power between the battery and the direct current link; and the means for unidirectionally coupling the battery to the polarized energy storage device to conduct current from the battery to the energy storage device whereby the battery current is coupled to the direct current link through the first bi-directional converter and of the second bi
  • the method disclosed in US 5710699 A comprises the steps of: providing current to the direct current link from the battery through direct current to direct current converters, operating a dynamic braking circuit when the motor is running in regenerative mode and the passive energy storage device is fully charged to dissipate the excess regenerated power over the limits of the capacity of the first converter.
  • the present invention corresponds to a device and method of direct voltage tension compensation.
  • the direct current voltage compensation device disclosed in the present invention comprises: an EDLC (2) with a positive terminal and a negative terminal, a first voltage meter (9A) with read speed in intervals between lps and lOps and arranged operatively in the EDLC (2), a first comment meter (8A) with read speed in intervals between lps and lOps and operatively arranged in the EDLC (2), a DC / DC converter (7A) with 3KHz switching comment , connected to the EDLC (2) and the first comment meter (8A), a computing unit (11 A) connected to the DC / DC converter (7 A), the first voltage meter (9A) and the first comment meter (8A), where the computing unit (11 A) based on the signals of the first voltage meter (9A) and the first current meter (8A) controls the DC / DC converter (7A) to compensate for the voltage in the current direct.
  • the direct current voltage compensation method disclosed in the present invention comprises the following steps: step e) verify that the line voltage is between a lower operating voltage limit and an upper operating voltage limit pre-configured by a user in a memory register of a computing unit and go to step (g); if the line voltage exceeds these operating voltage limits a stop condition is verified;
  • step g) verify that the EDLC voltage variation is less than an EDLC voltage variation limit and that the EDLC load comment variation is less than a variation limit of the EDLC load comment pre-configured by a user in a memory register of the computing unit, if said variations do not exceed said limits verify that the EDLC load comment is less than an EDLC operating comment limit to control DC / DC converter and verify operating mode of the DC / DC converter, if said variations exceed said limits then make a disconnection;
  • step h) verify if the operating mode of the DC / DC converter is Boost mode; If the operating mode of the DC / DC converter is Boost mode, check that the EDLC load voltage is in a range defined by an upper EDLC operating voltage limit and a lower EDLC operating voltage limit preprogrammed by a user in a memory register of the computing unit and keep the EDLC load comment; step i) record the changes of the EDLC current, the EDLC voltage and the voltage line, and based on these changes determine a current and voltage differential, the computation unit calculates in each interval an average voltage value and comment based on previous and current voltage values and comment;
  • stage (i) is periodically executed from stage (e) to stage (h) with an interval between 1 ps and 10 ps regardless of the other stages;
  • stage (f) is switched off if safety conditions are not met.
  • FIG. 1 shows an example of a schematic of electrical connections of the power circuit of the device disclosed in the present invention.
  • FIG. 2 shows a block diagram of an example of the connections between the different elements of the disclosed device.
  • FIG. 3 shows an example in a general flow chart of the states of the method disclosed in the present invention.
  • FIG. 4 shows an example in a flow diagram of the subprocess of measurement of comments of voltages and voltages in the method disclosed in the present invention.
  • FIG. 5 shows an example flowchart of the setup state of the method disclosed in the present invention.
  • FIG. 6 shows an example in a flow chart of the Preload state of the method disclosed in the present invention.
  • FIG. 7 shows an example in a flow chart of the Idle state of the method disclosed in the present invention.
  • FIG. 8 shows an example in a flow chart of the Quick Start state of the method disclosed in the present invention.
  • FIG. 9 shows an example in a flowchart of the states of Connection Disconnection of the method disclosed in the present invention.
  • FIG. 10 shows an example in a flowchart of the Buck / Boost mode of the method disclosed in the present invention.
  • a device is connected, coupled, coupled in relation to the current or that it can be connected to another device, it means that the device can be connected directly by a cable or alternatively, connected to through another device such as, but not limited to, a resistor, a diode, a conductive device, and this connection can be in series or in parallel.
  • the device disclosed by the present invention comprises a protection and control unit (26) connected to its input by a positive voltage transmission line (31) and a negative voltage transmission line (32); the protection and control unit (26) connects by its output to the input of a soft start device consisting of a first contact (24) and a first resistor (25) connected in parallel, the protection and control unit (26) It is in turn connected to a first fuse (3a) that connects to a first current meter formed by a first hall effect sensor (la) operatively arranged on a first inductor (34a) and a first current signal (29).
  • a protection and control unit (26) connected to its input by a positive voltage transmission line (31) and a negative voltage transmission line (32); the protection and control unit (26) connects by its output to the input of a soft start device consisting of a first contact (24) and a first resistor (25) connected in parallel, the protection and control unit (26) It is in turn connected to a first fuse (3a) that connects to a first current meter formed by
  • a first voltage meter formed by a second hall effect sensor (12a) operatively arranged on a second inductor (33a) and a first voltage signal (30) and operatively disposed at the output of the protection and control unit (26) .
  • a low-pass filter consisting of a second resistor (23) and a first capacitor (22) connected in series;
  • the negative terminal of the first capacitor (22) is connected to the first current meter, and the second resistor (23) is connected to the first resistor (25) of the soft start device.
  • An intermediate capacitor consisting of a third resistor (21) and a second capacitor (20) are connected in parallel with each other, and in turn the third resistor (21) and the second capacitor (20) are connected in parallel to the low-pass filter .
  • the anode of a first diode (13a) is connected to the emitter of the first IGBT transistor (14a), the cathode of the first diode (13a) is connected to the collector of the first IGBT transistor (14a).
  • a fourth resistor (9) and a second diode (7) are connected in parallel; the parallel cathode terminal formed by the fourth resistor (9) and the second diode (7) is connected to the positive terminal of a third capacitor (11); the negative terminal of the third capacitor (11) is connected to the emitter of the first IGBT transistor (14a); The anode of the second diode (7) connected to the fourth resistor (9) is connected to the collector of the first IGBT transistor (14a).
  • the collector of the first IGBT transistor (14a) is connected to the positive terminal of the second capacitor (20), the second resistor (23) and the output of the soft start device;
  • the emitter of the IGBT transistor (14a) connects a third inductor (6b) and to the collector of a second IGBT transistor (14b).
  • a second switching element consisting of a PWM Boost signal (18) that connects to a second IGBT driver (16) which in turn connects to the gate terminal of a second IGBT transistor (14b);
  • the anode of a third diode (13b) is connected emitter of the second IGBT transistor (14b), the cathode of the third diode (13b) is connected to the collector of the second IGBT transistor (14b).
  • a fifth resistor (8) and a fourth diode (6a) are connected in parallel; the parallel cathode terminal formed by the fifth resistor (8) and the fourth diode (6a) is connected to the positive terminal of a fourth capacitor (10); the negative terminal of the fourth capacitor (10) is connected to the emitter of the second IGBT transistor (14b); The anode of the fourth diode (6a) connected to the fifth resistor (8) is connected to the collector of the second IGBT transistor (14b).
  • the collector of the second IGBT transistor (14b) is connected to the emitter of the first IGBT transistor (14a) and the third inductor (6b);
  • the emitter of the second IGBT transistor (14b) is connected to the negative terminal of the second capacitor (20), to the negative terminal of the first capacitor (22), to a second contact (5), to the first inductor (34a) of the first current meter and to a fourth inductor (34b) of a second current meter.
  • the second current meter formed by a third hall effect sensor (lb) operatively arranged on the fourth inductor (34b) and a second current signal (28).
  • An EDLC (2) with a positive terminal and a negative terminal connects its positive terminal to the third inductor (6b) and its negative terminal to a second fuse (3b).
  • the second fuse (3b) connects the terminal that is not connected with the negative terminal of the high density element EDLC (2) to the inductor (34b) of the second current meter.
  • a second voltage meter is operatively made up of a fourth hall effect sensor (12b) operatively arranged on a fifth inductor (33b) and a second voltage signal (27).
  • the device disclosed in the present invention has a positive voltage transmission line (31) and a negative voltage transmission line (32) whose voltage difference corresponds to the direct source of the device of the present invention, said voltage difference is in the range of 400 V CD to 3000 V CD or is selected from the voltages of 400 V CD , 450 V CD , 500 V CD , 550 Veo, 600 V CD , 650 V CD , 700 V CD , 750 V CD , 800 V CD , 850 V CD , 900 V CD , 950 V CD , 1000 VDC, 1050 V CD , H00 V CD , 1150 Veo, 1200 V CD , 1250 V CD , 1300 V CD , 1350 V CD , 1400
  • the value of the voltage difference between the transmission lines positive voltage (31) and the negative voltage transmission line (32) is 1500V DC and a vacuum voltage of l650Vc D ⁇ V CD is direct voltage.
  • the idle voltage is the voltage difference between the positive voltage transmission line (31) and the negative voltage transmission line (32) when there is no electric charge connected to them .
  • the line voltage is the voltage difference between the positive voltage transmission line (31) and the negative voltage transmission line (32).
  • the device has the protection and control unit (26) which is responsible for isolating the transmission line of the first switching element and the second switching element and corresponds to the protection Primary device
  • the protection and control unit (26) is selected from the group of DC protection devices, ultrafast interruption devices, ultrafast fuses, thermo-magnetic switches, control devices in direct current, short circuit detectors, programmable relays and combinations of the above.
  • the protection and control unit (26) is responsible for isolating the transmission line of the first switching element and the second switching element.
  • the device disclosed by the present invention the protection and control unit (26) is a programmable relay.
  • the protection and control unit (26) is the primary protection of the device of the present invention and has an actuation speed between lps and 50ms.
  • the operating speed of the protection and control unit is 40ms.
  • the device disclosed in the present invention has a soft start device consisting of a first contact (24) and a first resistor (25), this comes into operation as an initial preload of the high density element EDLC (2), the Soft start device prevents a transient phenomenon with a current greater than the rated current of the EDLC element (2) from affecting the device negatively.
  • the selection of the contact (24) corresponds to a maximum current of 180A and an insulation voltage of 1850V.
  • the first voltage meter formed by a second hall effect sensor (12a) operatively disposed on a second inductor (33a) and a first voltage signal (30) and operatively arranged at the output of the protection and control unit (26) and the second voltage meter consisting of a fourth hall effect sensor (12b) operatively arranged on a fifth inductor (33b) and a second voltage signal (27) have a speed of reading between lps and 500ms.
  • the first voltage meter and the second voltage meter have a reading speed in intervals between lps and lOps.
  • initial preload as a state in which the load comment of the high density element EDLC (2) is a portion of the maximum load comment of the high density element EDLC (2).
  • the low-pass filter formed by a first capacitor (22) and a second resistor (23) connected in series with the function of mitigating, eliminating and / or filtering the contaminating electrical signals conducted, due external sources connected to the same transmission line and also due to internal sources of the same device of the present invention so as not to interfere with other devices connected to the same transmission line.
  • the low-pass filter formed by a first capacitor (22) and a second resistor (23) connected in series attenuates the harmonic signals of the frequencies external to the device of the present invention, which for example, they are of the order of 250Hz and the signals produced by the switching of the first switching element and the second switching element which, for example, have a central frequency of the order of 3kHz, thus the cut-off frequency of the low-pass filter is chosen from 3kHz
  • the low-pass filter is designed according to the type of rectification used by the transmission line.
  • the types of rectification that are used for the transmission line are selected from the uncontrolled rectifier group as two-phase half-wave rectifiers, three-phase half-wave rectifiers, hexaphase half-wave rectifiers, half-wave rectifiers with real elements, half wave rectifiers with RL load without freewheeling diode, half wave rectifiers with freewheeling diode, full wave rectifiers in two phase star, full wave rectifiers in three phase star, full wave rectifiers in star with real elements, full-wave star rectifiers with RL load, full-wave star rectifiers with C filter, full-wave rectifiers in three-phase delta, full-wave rectifiers in hexaphase delta, or controlled rectifiers as medium controlled rectifiers three-phase wave, two-phase full-wave controlled rectifiers, three-phase full-wave controlled rectifiers and combinations thereof.
  • the device is connected to a transmission line based on two three-phase controlled full-wave rectifiers or 12-pulse rectifier.
  • the device disclosed in the present invention has a second capacitor (20) and a third resistor (21) that connected in parallel with the low-pass filter form a decoupling circuit for the conformation of the return loop of all spurious signals how EMI (Electromagnetic Interference, for its acronym in English EMI) its capacitance and ability to supply energy quickly in conjunction with a physical arrangement close to the first switching element and the second switching element to ensure a low inductance associated with the separating conductors the second capacitor (20) the third resistor (21) and the first switching element and the second switching element providing a low impedance for EMI signals mitigating their effect on the device disclosed in the present invention.
  • EMI Electromagnetic Interference, for its acronym in English EMI
  • the second capacitor (20) in one example, has a capacitance value of 602pF @ 2000V with equivalent series resistance (for its acronym in English, Equivalent Series Resistance ESR) of 0.03 Ohms, however, it is practical to use a value higher the capacitance calculated, provided it is not a peak current I Pk exceeding the level of protection provided by the protection and control unit (26) response to sudden changes the input voltage Vj n occur.
  • equivalent series resistance for its acronym in English, Equivalent Series Resistance ESR
  • the switching frequencies of the first switching element and the second switching element range from 500Hz to 100kHz. In one example, in the present invention, at the discretion, it is selected to be 4 times the natural frequency of the type of rectification of the transmission line and is 2880Hz, this is done with the objective of reducing the inductance value of the third inductor (6b ).
  • the first switching element is used for operation in Buck mode and the second switching element is used for operation in Boost mode.
  • operation in Buck mode will be understood as the use of a DC / DC converter or a switching element for direct current voltage reduction, and Boost mode operation for voltage elevation. in direct current.
  • the device selects the operating mode in Buck / Boost mode and depends on the availability of energy in relation to the power demand of the transmission line. For example, if the power availability state of the transmission line is less frequent than the demand state, the operating mode in Buck mode is privileged, thus the available energy is stored;
  • the third inductor (6b) delivers its energy to the high density EDLC element (2) during the entire shutdown cycle of the first IGBT transistor (14a) of the first switching element for Buck mode operation.
  • the PWM Buck signal (19) is applied through a first IGBT driver (17) to the base of the first IGBT transistor (14a) of the first switching element and the signal PWM Boost (18) is applied through a second IGBT driver (16) to the base of a second IGBT transistor (14b) of the second switching element, this is done to electrically couple the PWM Buck signal (19) and the PWM Boost signal (18) from a computing unit.
  • a computing unit will be understood as a device that processes data, for example, microcontrollers, microprocessors, DSCs (Digital Signal Controller), FPGAs (Field Programmable Gate Array) English), CPLDs (Complex Programmable Logic Device), ASICs (Application Specific Integrated Circuit), SoCs (System on Chip), PSoCs (Programmable System on Chip) in English), computers, servers, tablets, cell phones, smart phones, and computing units known to a person moderately versed in the subject or combinations thereof.
  • DSCs Digital Signal Controller
  • FPGAs Field Programmable Gate Array
  • CPLDs Complex Programmable Logic Device
  • ASICs Application Specific Integrated Circuit
  • SoCs System on Chip
  • PSoCs Programmable System on Chip
  • the protection and control unit (26), the first voltage signal (30), the first contact (24), the first current signal (29), the PWM Boost signal (18), the PWM signal Buck (19), the second contact (5), the second voltage signal (27) and the second current signal (28) are connected to a computing unit in which the method of the present invention is implemented.
  • the voltage on the high density element EDLC (2) is governed by the duty cycle of the PWM Buck signal (19) in the following formula:
  • VEDLC DXV DC
  • D is the duty cycle of the signal that controls the first IGBT transistor (14a) of the first switching element for Buck mode operation.
  • the third inductor (6b) when delivering all its stored energy to the high density element EDLC (2) guarantees efficiency in the use of energy and avoids resonance states of the device therefore low EMI.
  • the calculation of the third inductor (6b) determines the operation in Boost mode which is selected from Boost mode in continuous sub mode or Boost mode in discontinuous sub-mode.
  • said operation in Boost mode is in discontinuity sub-mode.
  • the term continuous mode as a sub-mode of operation of the Buck and Boost switching elements where current flows through the high-density EDLC element throughout the control cycle, reaching points where a maximum or minimum current intensity is obtained, but that never gets canceled; instead in the discontinuous sub-mode, the magnitude of the converter's output current drops to zero in a portion of the cycle, so that the current value starts at zero, reaches a peak value and returns to zero in each cycle
  • the operating mode of the first switching element related to the operation in Buck mode and of the second switching element related to the operation in Boost mode have a sub-mode of operation that is selected between continuous sub-mode and discontinuous sub-mode.
  • the first switching element related to the operation in Buck mode operates in continuous sub-mode and the second switching element related to the operation in Boost mode operates in discontinuous sub-mode and thus prevents phase inversion from occurring or Exceeds the criteria for bandwidth gain in device operation.
  • the inductance of the third inductor (6b) configures the sub-mode of continuous or discontinuous operation of the first switching element associated with the operation in Buck mode and of the second switching element associated with the operation in Boost mode.
  • an inductance value for the third inductor (6b) of 118 mH configures the continuous operation sub-mode for the first switching element (Buck) and the discontinuous sub-mode for the second switching element (Boost).
  • the third inductor (6b) forms a snubber network with the high density element EDLC (2), the sixth resistor (4) and the second contact (5) to suppress the voltage peaks and dampen the transient oscillation caused by the circuit inductance when the second contact (5) opens. Therefore, it is crucial to evacuate the energy stored in the third inductor (6b), to ensure that no phase inversion occurs or the bandwidth gain criterion is exceeded in the operation of the device. For this, the discontinuous sub mode of operation is maintained in Boost mode.
  • the first diode (13a), the second diode (7), the fourth resistor (9), the third capacitor (11) are the snubber network of the first IGBT transistor (14a) to suppress the voltage peaks and dampen the transient oscillation caused by the inductance of the circuit when the IGBT transistor (14a) is opened for operation in Buck mode.
  • the third diode (13b), the fourth diode (6a), the fifth resistor (8), the fourth capacitor (10) are the snubber network of the second IGBT transistor (14b) to suppress the voltage peaks and dampen the oscillation transient caused by the inductance of the circuit when the second IGBT transistor (14b) is opened for operation in Boost mode.
  • the EDCL Electric Double-Layer Capacitor high density element is part of a family of electrochemical capacitors known as ultracapacitors or supercapacitors, these do not have a solid dielectric inside and have the ability to charge and discharge to a rat very high compared to conventional capacitors, in addition to supporting more than one million cycles of loading and unloading although a low energy storage density of around 30 Wh / kg.
  • the device has a high density EDLC element (2) selected from the group of electrolytic ultracapacitors, non-electrolytic ultracapacitors, aqueous oxide ultracapacitors, conductive polymer ultracapacitors and combinations.
  • the high density element EDLC (2) is a bank of EDLCs that is an array of serial or parallel EDLCs or combinations.
  • a bank of EDLCs consists of eight EDLCs connected in series, each with a capacitance of 63F and a nominal voltage of 125V to obtain a capacitance of 7,875F with a nominal voltage of 1000V; This value of 1000V of nominal voltage allows the voltage to be reduced or raised within an operating range; in terms of storable energy for this configuration, respecting the criterion of maximum stored energy 1.09 kWh.
  • the maximum operating comment for Buck mode or Boost mode is 180A if there is a 25% safety margin based on a maximum operating current of the high density element EDLC (2) of 240A .
  • the IGBT driver (16) is, in an example, a nominal current management module of 1500A and collector-emitter voltage of 3300V.
  • the current that is injected or absorbed from the transmission line is regulated by the source voltage continuously, due to the switching speeds of the first switching element and the second switching element.
  • the switching speeds of the first switching element and the second switching element are 3kHz.
  • a computing unit (11A) connects to the DC / DC converter circuit (7A).
  • the DC / DC converter (7A) has a switching current with a frequency ranging from 500Hz to 30kHz. For example, a switching current with a frequency of 3kHz is selected.
  • the device disclosed in the present invention has a DC / DC converter (7A) that is selected from the group of two-way magnetic DC / DC converters (see step-down (buck), Step-up (boost), SEPIC , Inverting (buck-boost), Cuk, True buck-boost, Split-pi (boost-buck), Forward, Push-pull (half bridge), Full bridge, Flyback), two-way capacitive and combinations. Additionally, the topology of the bidirectional DC / DC converter can be switched, resonant, continuous or discontinuous.
  • the disclosed device has a computing unit (11A) that connects to a protection and control unit (26), a first voltage meter (9A), a first current meter (8A), a starting device (3A), a second current meter (8A), a second voltage meter (9A), a DC / DC converter (7A).
  • the computing unit (11A) based on the signals of the first voltage meter (9A) and the first current meter (8A) controls the DC / DC converter (7A) to compensate for the direct current voltage.
  • the DC / DC converter (7A) is connected to a soft start device (3 A) and the computing unit (11 A) connected to the soft start device (3A).
  • the DC / DC converter (7A) is connected to a soft start device (3A); a protection and control unit (26) with a power input and a power output, the soft start device (3 A) connected to the output of the protection and control unit (26) and the computing unit (11A ); the protection and control unit (26) connected to the computing unit (11A).
  • the disclosed device is connected to a DC voltage source (10A) that connects to a protection and control unit (26) to which the voltage at its output is measured using a first voltage meter (9A) and current with a first current meter (8A).
  • the protection and control unit (26) is operatively connected at its power output a second voltage meter (4A) with read speed in intervals between l / rs and lO / rs and a second current meter (5 A) with read speed in intervals between l / rs and 1 Ow.v: the computing unit (11 A) is connected to the second voltage meter (4A) and the second current meter ( 5A).
  • the DC / DC converter (7A) is connected to a source conditioner (6A); a soft start device (3A) is connected to the source conditioner (6A) and the computing unit (11 A); a protection and control unit (26) is connected to the soft start device (3 A), the source conditioner (6A) and the computing unit (11 A); a second voltage meter (4A) operatively disposed in the protection and control unit (26) and is connected to the computing unit (11 A); a second comment meter (5A) operatively disposed between the protection and control unit (26) and the source conditioner (6A) and is connected to the computing unit (11A).
  • the voltage signal of the first voltage meter (4 A) is 6kV isolated and is connected to the computing unit (11A).
  • the isolation allows the signal to travel to where the computing unit (11 A) is located without interference from external signals, which in one example is 100 meters away.
  • the present invention has a source conditioner (6A) comprising active frequency filters and passive frequency filters, low-pass frequency filters (LPF), high-pass frequency filters (HPF), pass filters side and combinations of the above.
  • the DC / DC converter (7A) is connected to a source conditioner (6A) and the first current meter (8A) connected to the source conditioner (6A).
  • the first voltage signal (30) of the first voltage meter has a dielectric isolation of 6 kV, with respect to the electrical system of the transmission line and is connected to the computing unit (11 A) not illustrated in FIG. 1 but yes in FIG. two.
  • I t variable measured in the instant. For example, current
  • the method has a standby stage (34), where the system is at rest, waiting for a start signal which comes from a switch, a push button, a control unit or to be previously programmed.
  • the method disclosed in the present invention has a setup stage (35), where the system closes the protections (50) of the circuit to which the DC / DC converter is connected.
  • the system verifies that the storage voltage of the high-density EDFC element (2) is greater than the minimum line voltage (51). If the storage voltage of the EDFC high density element is greater than the minimum line voltage (51), it is verified that the storage current is less than 3 amps (52). If the storage current is less than 3 amps (52), it enters a preload state (36), but goes to the standby state (34). If the storage voltage of the EDFC high density element is not greater than the minimum line voltage (51), the standby state (34) is entered.
  • the method disclosed in the present invention has a preload stage (36), where the system verifies if the charge voltage of the high density element EDFC is equal to the minimum storage voltage of the high density element EDFC ( 53), where the minimum storage voltage of the EDFC high density element is equal to 10% of the EDFC operating voltage. If the load voltage of the high-density EDFC element is equal to the minimum storage voltage of the high-density EDFC element (53), a resistive impedance is connected at a connection stage to generate a pre-load of the high-density EDFC element (37 ).
  • the method in a connection stage (37) is expected so that the storage voltage of the high-density element EDFC is equal to the operating voltage of the high-density element EDFC plus or minus 5% ( 58).
  • the resistive impedance (59) that was connected to generate the preload is disconnected and you enter an idle state (39). Upon exiting the idle state (39), the quick start state (60) is entered.
  • the system checks whether the charging current of the high density element EDLC is less than the minimum current of EDLC high density element load (54), where the minimum load current of the EDLC high density element is equal to 5% of the maximum operating current. If the load current of the high density element EDLC is less than the minimum load current of the high density element EDLC (54), the load PWM signal of the high density element EDLC increases the pulse width (56).
  • the pulse width of the load PWM of the high density element EDLC is increased, it is checked if the load current of the high density element EDLC is greater than the minimum load current of the high density element EDLC (55).
  • the pulse width of the load PWM of the high density element EDLC is decreased.
  • the process is started again from Check if the charging voltage of the high density element EDLC is equal to the minimum storage voltage of the high density element EDLC (53).
  • the method disclosed in the present invention has an idle step (39) in which the system verifies that the storage voltage of the high density element EDLC is less than 95% of the operating voltage of the high density element EDLC ( 61). If the storage voltage of the high-density element EDLC is less than 95% to the operating voltage of the high-density element EDLC (61), a state or stage of rapid onset (60) is entered.
  • the system checks whether the storage voltage of the high density element EDLC is greater than 105 % of the operating voltage of the high density element EDLC (62). If the storage voltage of the high density element EDLC is greater than 105% operating voltage of the high density element EDLC (63), the quick start state (60) is entered. If the storage voltage of the high density element EDLC is not greater than 105% of the operating voltage of the high density element EDLC (62), it is checked whether there is a system stop condition locally or remotely (63). If there is a stop condition in the system locally or remotely (63), the disconnection state (41) is entered. If there is no stop condition in the system locally or remotely (63), the process is repeated from verifying if the storage voltage of the high density element EDLC is less than 95% of the operating voltage of the high element EDLC density (61).
  • the method disclosed in the present invention has a rapid start stage (60) where the system verifies whether the change in the current of the high density element EDLC is greater than the maximum change of the high density element EDLC (64), where the maximum change in the current of the high density element EDLC is equal to 10% of the maximum current of the high density element EDLC (2). If the change in the current of the high density element EDLC is greater than the maximum change in the current of the high density element EDLC (64), the system enters a stage or disconnection state (41).
  • the change in the current of the high density element EDLC is not greater than the maximum change in the current of the high density element EDLC (64), it is verified if the change in the storage voltage of the high density element EDLC is greater than the maximum change in the storage voltage of the high density element EDLC (65), where the maximum change in the storage voltage of the high density element EDLC is given by 5% of the maximum voltage of the high density element EDLC.
  • the disconnection state (41) is entered. If the change in the storage voltage of the high density element EDLC is not greater than the maximum change in the storage voltage of the high density element EDLC (65), it is checked whether the storage current of the high density element EDLC is smaller than 90% of the maximum operating current of the high density element EDLC (66). If the storage current of the high density element EDLC is less than 90% of the maximum operating current of the high density element EDLC (66) the device goes to Buck or Boost mode (38).
  • the storage comment of the high density element EDLC is not less than 90% of the maximum operating comment of the high density element EDLC (66), it is asked whether the system is in the form of a Boost (40). If the system is in the form of Boost (40), it is verified that the instantaneous measurement of the variable, in this case the comment is less than 1 0 (67), where 1 0 is approximately equal to zero, during a given time by 10 times the number of data in an instant of time, where the number of data in an instant of time is less than half the period of the PWM signal. This condition is referred to as "cond" for the present invention.
  • the measurement of the comment is not less than i ⁇ (67), it enters the disconnection state (41). If during this time, the measurement of the comment is less than i ⁇ (41) or if the system is not Boost (40), the process is repeated from verifying that the change in the current of the high density element EDLC is greater than maximum change of the EDLC high density element comment (64).
  • the method disclosed in the present invention has a disconnection stage (41), where the system expects the storage voltage of the high density element EDLC to be equal to 10% of the operating voltage of the high density element EDLC (69 ), when the storage voltage of the EDLC is equal to 10% of the operating voltage of the high density element EDLC (69), the system enters the standby state (34).
  • the method of the present invention has a connection stage (37) in which the line voltage is expected to be equal to a value of plus or minus 5% of the operating voltage of the high density element EDLC ( 58) to remove a load resistor (59) and enter an idle state (39)
  • the method disclosed in the present invention has a Buck or Boost mode (38), where the system checks if it is in Boost mode (40). If the system is in Boost mode (40), it is checked whether the storage voltage of the high density element EDLC is greater than 20% of the operating voltage of the high density element EDLC (69). If the storage voltage of the high density element EDLC is greater than the operating voltage of the high density element EDLC (69), the system verifies that the storage voltage of the high density element EDLC is less than 90% of the voltage of operation of the high density element EDLC (74).
  • the storage voltage of the high density element EDLC is not greater than 20% of the operating voltage of the high density element EDLC (69)
  • the system at startup 79.
  • the comment (78) by applying a ramp that lasts less than one second at a rate between 300 V / s and 900 V / s and enters the idle state (39).
  • the system is returned to the start (79). When the system is returned, it lowers the current (78) by applying a ramp that lasts less than one second at a rate between 300 V / s and 900 V / s and enters the idle state (39).
  • the PWM signal is decreased with a control ramp (76). If the “cond” condition is met (75) or the PWM signal decreases (76), it is checked if the average current of the EDLC high density element current measurements is less than the maximum operating current of the element high density EDLC (73).
  • the PWM signal is increased with a control ramp (77). If the average current of the EDLC high density element current measurements is not lower (73) or the PWM signal is increased with a control ramp (77), it is checked again if the device is in Boost mode ( 40).
  • the device is not in Boost mode (40)
  • the storage voltage of the high density element EDLC is not less than 90% of the maximum storage voltage of the high density element EDLC (70)
  • the storage voltage of the high density element EDLC is greater than the operating voltage of the high density element EDLC (71), it is checked whether the average current of the measurements of the current of the high density element EDLC is greater than the maximum operating current of the high density element EDLC (72).
  • the PWM signal is decreased with a control ramp (76). If the average current of the EDLC high-density element current measurements is not greater than the operating current (72) or the PWM signal is decreased with a control ramp (76), it is checked whether the average measurement current Current of the high density element EDLC is less than the maximum operating current of the high density element EDLC (73).
  • the PWM signal is increased with a control ramp (77). If the average current of the EDLC high density element current measurements is not lower (73) or the PWM signal is increased with a control ramp (77), it is checked again if the device is in Boost mode ( 40).
  • the device of the present invention periodically measures in the following manner as described below.
  • the method disclosed in the present invention has a new measurement of instantaneous current (44).
  • a new measurement of the instantaneous current (44) is taken, the calculation of a delta of the instantaneous current (45) is performed.
  • delta is understood as the change made from one measure to another.
  • the instantaneous current delta is calculated as the new instantaneous current measurement minus the previous instantaneous current measurement (45).
  • the average comment of the comment of the high density element EDLC (46) is updated by removing the oldest instantaneous comment measure of the vector where all the divided comment measurements are saved by 2 N (46) where N is the total number of data. For example N is a natural number between 1 and 1000.
  • the vector where the instantaneous comment measurements are saved is reorganized, removing the oldest measurement (47).
  • the average comment of the comments of the high-density element EDLC is updated again by adding the newest measure of the instantaneous comment divided by 2 N , where N is the number total data (48). For example N is a natural number between 1 and 1000.
  • This process is constantly repeated during device operation and voltage compensation method.
  • step (f) is switched off if safety conditions are not met.
  • safety conditions shall be understood as the operating conditions under the design limits of each of the elements of the voltage compensation device, for example, the line voltage V L must be between a - 5% and + 5% of the operating voltage V op pre-configured by a user, or operating comment limit between 1 ampere and 200 amps and the limits established in the method described below.
  • the method for direct voltage tension compensation comprises the following steps:
  • step (g) e- verify that the line voltage is between a lower operating voltage limit and an upper operating voltage limit pre-configured by a user in a memory register of a computing unit and go to step (g); if the line voltage exceeds these operating voltage limits a stop condition is verified;
  • g- verify that the EDLC voltage variation is less than an EDLC voltage variation limit and that the EDLC load current variation is less than a EDLC load current variation limit pre-configured by a user in a memory register of the computing unit;
  • Boost mode If the operating mode of the DC / DC converter is Boost mode, check that the EDLC load voltage is in a range defined by an upper EDLC operating voltage limit and a lower EDLC operating voltage limit preprogrammed by a user in a memory register of the computing unit and maintain the EDLC load current;
  • the computation unit calculates in each interval an average voltage value and current based on previous and current voltage and current values
  • stage (i) is periodically executed from stage (e) to stage (h) with an interval between 1 ps and 10 ps regardless of the other stages.
  • step (e) the lower limit of operating voltage is defined by a percentage from 90 percent to 95 percent of the operating voltage of the EDLC and the upper limit of operating voltage is defined by a percentage from 90 percent at 105 percent of the EDLC operating voltage.
  • step (g) the EDLC charge voltage variation limit is between 3 percent and 7 percent, the EDLC charge current variation limit is between 5 percent and 15 percent and the EDLC operating comment limit is between 85 percent and 95 percent.
  • the EDLC charge voltage variation limit is between 3 percent and 7 percent, the EDLC charge current variation limit is between 5 percent and 15 percent percent, the EDLC operating current limit is between 85 percent and 95 percent.
  • condition (D) of step (g) the pre-configured EDLC current value is in a range between 1A and 50A.
  • the EDLC voltage variation limit is between 3 percent and 7 percent and the EDLC load current variation limit is between 5 percent and 15 percent.
  • condition (B) of step (g) the pre-configured EDLC current value is between 1 A and 50 A.
  • step (g) the EDLC operating current limit is between 1 A and 200 A.
  • the upper EDLC operating voltage limit is between 85 percent and 95 percent and the lower EDLC operating voltage limit is between 15 percent and 25 percent.
  • pre-configured EDLC maximum load voltage is between 85 percent and 95 percent, the EDLC operating voltage is between 100 V and 1500 V.
  • the lower limit is a percentage of the EDLC operating voltage value between 15 percent and 20 percent and the upper limit of a percentage of the EDLC operating voltage value between 90 percent and 95 percent.
  • step (h) in condition A the pre-configured percentage of the maximum charge voltage of the EDLC is between 80 percent and 90 percent.
  • a stage (f) where the EDLC voltage is expected to be equal to a value pre-configured by a user in a memory register of the computing unit and move on to the stage (a) in which a start signal from a computing unit is expected; and in step (e) the verification of the detention condition is carried out by verifying the following conditions: condition A- if an arrest event occurs, go to stage (f); condition B- if a stop event does not occur repeat step (e);
  • step (g) said verification is performed following these conditions:
  • condition B- if the EDLC voltage and current variations do not exceed an EDLC load voltage variation limit or a current variation limit of EDLC load compare if the EDLC load comment is less than an EDLC operating current limit pre-configured by a user in a memory register to go to step (h);
  • condition C- if the load current of the EDLC is higher than the operating current limit of the EDLC pre-configured by a user, check the operating mode of the DC / DC converter, if the operating mode of the DC / DC converter is mode Boost, and
  • condition D- if the measurement of the EDLC load current is less than a value of the EDLC current pre-configured by a user in a memory register for a given time for a number K times plus a number N of data in an instant of time D ⁇ , where the number N of data in an instant D ⁇ of time is less than half the period of the PWM signal;
  • step (g) is repeated;
  • pulse duration of the PWM signal is between 0 ps and 340 ps.
  • the method of the present invention after step (e) includes a step (f) where the EDLC voltage is expected to be equal to a value pre-set by a user in a memory register of the unit of computation and go to step (a) in which a start signal from a computing unit is expected; before condition B of step (g) the following condition A- is verified if the voltage variation of the EDLC exceeds a voltage variation limit of the EDLC or if the current variation of the EDLC exceeds a current variation limit of EDLC load go to step (f).
  • step (g) the following condition E- is verified, if condition D is not met, step is passed to step (f), if condition D is met, it is repeated the stage (g).
  • step (h) if the operating mode of the DC / DC converter is Boost mode then the following conditions are verified:
  • step (h) if the average comment is less than the maximum EDLC operating comment, the useful cycle of the PWM signal of the DC / DC converter is increased and step (h) is repeated, if the average comment is greater than the maximum comment of EDLC operation then step (h) is repeated;
  • condition B if condition B is not fulfilled then the useful cycle of the PWM signal of the DC / DC converter is decreased and the average comment is compared with the maximum operating current of the EDLC;
  • step (h) F- if the average comment is less than the maximum EDLC operating comment, the useful cycle of the PWM signal of the DC / DC converter is increased and step (h) is repeated, if the average comment is greater than the maximum comment of EDLC operation is repeated step (h);
  • pulse duration of the PWM signal is between 0 ps and 340 ps.
  • the pre-configured value of the operating voltage of the EDLC in the computing unit is in the range of 1 percent to 5 percent of the operating voltage of the EDLC.
  • the pre-configured value of the maximum EDLC operating comment in the computing unit is in the range of 1 percent to 5 percent of the maximum EDLC operating comment.
  • an example of the present invention prior to step (h) includes a step (a) in which a start signal from a computing unit is expected; in step (h), before checking condition B the following condition A- is verified if the EDLC load voltage is not in the defined range an upper EDLC operating voltage limit and a lower operating voltage limit of the EDLC pre-configured by a user in a memory register, the comment is lowered by applying a ramp lasting less than one second at a rate between 300 V / s and 900 V / s and is passed to step (e); and if the charge voltage of the EDLC is in the range defined by said limits, then a measure of the charge rating of the EDLC is verified and condition B is verified;
  • step (h) if the operating mode of the DC / DC converter is not Boost mode then the verification of the following conditions is performed:
  • step (a) is included in which a start signal from a computing unit is expected; in step (h) before condition B the following condition is included A- compare the charging voltage of the EDLC with a maximum charging voltage of the EDLC pre-configured by a user in a memory register, if the charging voltage EDLC exceeds this voltage limit, then the comment is lowered by applying a ramp with a duration of less than one second at a rate between 300 V / s and 900 V / s and is passed to step (e);
  • step (h) after condition D the following condition E is included - if condition B is not met then the comment is lowered by applying a ramp lasting less than one second at a rate between 300 V / s and 900 V / s and go to step (e);
  • a step (a) is included before step (e) in which a start signal from a computing unit is expected to pass to step (e).
  • step (a) the start signal is a signal from a sensor, a touch switch, a push button, a second computing unit or is pre-configured in the computing unit.
  • a step (b) is included before step (e) to close protections in a protection and control unit, and verify that the line voltage, the load current of an EDLC are in a voltage range and comment pre-configured by a user in a memory register of a computing unit, if they are not in said range of pre-configured values it is repeated (b), otherwise step (e) is executed.
  • step (b) comprises the following sub-stages:
  • i- close protections of the protection and control unit ii- compare the line voltage and the minimum voltage of the transmission line pre-configured by a user in the computing unit, if the line voltage is less than the minimum voltage of the transmission line repeat step (b), if the line voltage is greater than the minimum voltage of the transmission line go to the sub stage (iii);
  • step (c) iii- compare the measured EDLC storage current with a current meter with a pre-configured value in the computing unit, if EDLC storage current is greater than said pre-configured value repeat step (b) and if current EDLC storage is less than said pre-configured value move to step (c);
  • the minimum voltage value of the pre-configured transmission line in the computing unit is in the range between 10 V and 500 V.
  • the value of the pre-configured EDLC storage current in the computing unit is in the range between 1 A and 50 A.
  • step (c) is included before step (e) to verify if EDLC voltage is equal to a lower EDLC operating voltage limit pre-configured in a register of memory and verify that the load current is equal to the minimum load current, these verifications are made following the following conditions:
  • condition B- if the EDLC voltage is different from said lower EDLC operating voltage limit pre-configured then verify that the EDLC load current is maintained at a value of a percentage of the maximum EDLC operating current pre configured in a memory register;
  • step (c) is repeated.
  • a step (d) is included before step (e) to operate a soft start device based on a value given by the subtraction between the line voltage and the EDLC operating voltage using the computing unit.
  • step (c) before condition B the following condition A- is verified if the EDLC voltage is equal to said lower operating voltage limit of the pre-configured EDLC then go to step (d).
  • step (d) comprises the following sub stages:
  • the percentage of the EDLC's operating value is in the range of 1 percent to 5 percent.
  • the action of removing a load resistor corresponds to activating an electrical contact connected in parallel to a load resistor.
  • step (i) comprises the following sub stages:
  • ii- calculate the change in the instantaneous current of the EDLC (DI) with the difference between the value of the previous sub-stage (h) (i t ) and the previous value of the instantaneous current measurement of the EDLC (i (t -i ) ), with the following equation implemented in the computing unit:
  • DI i t - i ti
  • v- recalculate the average current of EDLC I by adding the value of the instantaneous current measurement of the current EDLC i t-1 , with the following equation implemented in the computing unit: live back to the sub stage (i).
  • step (i) of the method that implements the present invention K
  • (t) and (N) are natural numbers from 1 to 1000.
  • a device was designed and built and a method implemented in the voltage compensation device was implemented.
  • the device has the following characteristics:
  • Nominal line voltage Vi n (nom) 1500V;
  • Vi n (Set) 1650V
  • V C (max) 1000V
  • V C (min) 150V (voltage that will be reached in the EDLCs in operation in Boost mode, which will keep a comment of at least 10% of I (max) );
  • V C (ini) 150V (preload limit voltage and corresponds to 10% of the nominal voltage of the catenary system);
  • the protection and control device (26) is a reference device SITRAS PRO as the primary protection of the device of the present invention with an actuation speed of 40ms.
  • the first voltage meter delivers a first voltage signal (30), and the conductor cable of this signal has an electrical isolation of 6kV from the transmission line.
  • the criteria for selecting the first contact (24) is:
  • the voltage compensation device starts its cycle ensuring a low current regime in the load of the EDLC element (2), until reaching a voltage of! 50V CD .
  • the first resistance (25) is 75W @ 1 lkW the first contact (24) is normally open.
  • the second resistance (23) is 3.45W @ 300W.
  • the charging process is exponentially decreasing for the current and the voltage compensating device of the present invention begins its cycle with maximum peak current regime I Pk of 11A, this in an example is achieved with a first resistance (25) formed by the series of five resistors of 30 W @ 220 V @ 1600 W whose equivalent resistance is 150 W and allows a maximum current of 7.33A.
  • V, i.nfset 1650
  • the time at which the nominal preload current is reached is 343 microseconds. It is calculated using the following formula:
  • V 0 is the transmission line voltage or line voltage
  • R 25 is the ohmic value of the resistance (25);
  • t is the time in which the nominal preload current is reached
  • t is the loading time of the high density element EDLC (2).
  • the maximum average power P 25 is that which must be dissipated by the five series resistors each with 1600 W, for a total of 8000 W, it is calculated as follows:
  • the low-pass filter is designed according to the type of rectification used by the transmission line, if there is a 12-pulse rectification, which produces a P / 6 frequency lag of a 60Hz frequency signal, the natural frequency
  • the type of rectification of the transmission line is 720Hz, however, this natural frequency means a high power dissipation on the first resistance (25).
  • a capacitance of 16pF @ 2200V is assumed for the first capacitor (22) and the second resistor (23) is calculated as follows:
  • V CE 3 2000V Transmitter collector voltage in cut. It is configured based on the maximum transmission line voltage
  • I CRM 300A @ lms (maximum repetitive collector current in reverse. This parameter is estimated as double the current Ic (nom) );
  • a pair of IGBT transistors of reference DS-FZ1500R33HE3 for the first IGBT transistor (14a) and the second IGBT transistor (14b) of the company Infineon and its driver module ISD536F2 are selected with a safety level - FZ1500R33HE3 for the first IGBT driver (17) and the second IGBT driver (16).
  • the capacitance values for the fourth capacitor (10) of the second switching element and the third capacitor (11) of the first switching element the following formula is applied:
  • the minimum capacitance value is calculated with The following formula:
  • C 20 is selected 4 times higher than C 20 (min) with a value of 2000pF @ 2250V.
  • L 6b is the inductance of the third inductor (6b);
  • D min is the minimum duty cycle on the IGBT switching element (14a);
  • V i n (set) is the input voltage of the transmission line
  • V C (max) is the maximum voltage supported by the high density element EDLC (2);
  • I buck (nom) is the nominal current in operation in Buck mode.
  • L 6min (buck) is chosen to meet the operating requirements of Buck mode in continuous mode for the first switching element and of the operation of Boost mode in discontinuous mode for the second switching element.
  • the sixth resistance (4) of the discharge element of the high density element EDLC (2) is calculated with an initial rate of 20A for 1000V. This results in a resistive value for the sixth resistance of the discharge element of the high-density EDLC element (2) of 50 W whose maximum instantaneous power supported is 20 kW.
  • the capacitance value of for the high density element EDLC (2) is 7,875 F
  • a first fuse (3a) and a second fuse (3b) of fast operation are selected with a response speed based on the current of 20ms.

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Abstract

The present invention corresponds to a voltage compensation device and method. The direct current voltage compensation device disclosed in the present invention comprises an EDLC, a first voltage meter with a reading rate at intervals of between 1 and 10µs and operationally arranged in the EDLC, a first current meter with a reading rate at intervals of between 1 and 10µs and operationally arranged in the EDLC, a DC/DC converter with a switching current of 3kHz, connected to the EDLC and to the first current meter, a computation unit connected to the DC/DC converter, to the first voltage meter and to the first current meter, whereby the computation unit based on the signals from the first voltage meter and from the first current meter controls the DC/DC converter to compensate the direct current voltage. The direct current voltage compensation method disclosed in the present invention comprises the following steps: step e) verifying that the line voltage is between a lower operating voltage limit and an upper operating voltage limit pre-configured by a user in a memory register in a computation unit and passing to step (g); if the line voltage exceeds said operating voltage limits a stop condition is verified; step g) verifying that the variation in voltage of the EDLC is lower than a voltage variation limit for the EDLC and that the variation in the load current of the EDLC is lower than a variation limit for the EDLC load current pre-configured by a user in a memory register in a computation unit, if said variations do not exceed said limits verifying that the EDLC load current is lower than an EDLC operating load current limit to control the DC/DC converter and verify the operating mode of the DC/DC converter, if said variations exceed said limits then performing a disconnection: step h) verifying whether the operating mode of the DC/DC converter is Boost mode, checking that the load voltage for the EDLC is in a range defined by an upper EDLC operating voltage limit and a lower EDLC operating voltage limit pre-programmed by a user in a memory register in a computation unit and maintaining the EDLC load current; step i) recording the changes in the EDLC current, EDLC voltage and line voltage and, on the basis of said changes, determining a current and voltage differential, the computation unit calculating an average voltage and current for each interval based in the previous and current current and voltage values; where step (i) is executed periodically from step (e) to step (h) with an interval of between 1 and 10µs irrespective of the other steps.

Description

DISPOSITIVO Y MÉTODO DE COMPENSACIÓN DE TENSIÓN  TENSION COMPENSATION DEVICE AND METHOD
Campo técnico de la invención Technical Field of the Invention
La presente invención está relacionada con dispositivos de frenado regenerativos, y más específicamente, a un dispositivo y un método de compensación de tensión en comente directa para aprovechamiento de frenado regenerativo basado en ultracapacitores.  The present invention is related to regenerative braking devices, and more specifically, to a device and a direct current voltage compensation method for utilizing regenerative braking based on ultracapacitors.
Descripción del estado de la técnica Description of the state of the art
El frenado regenerativo es un mecanismo de frenado que permite que cuando un vehículo desacelera la energía cinética del movimiento del vehículo se convierta en energía eléctrica para que luego esta energía sea almacenada, en un dispositivo de frenado tradicional esta energía se disipa en forma de calor y vibración, lo que propende en el desgaste del mismo dispositivo de frenado. El dispositivo de frenado regenerativo no solo reduce el consumo de energía sino que además evita la generación de mido ocasionado por la fricción del freno y el desgaste de las pastas de frenado de un vehículo.  Regenerative braking is a braking mechanism that allows when a vehicle slows the kinetic energy of the movement of the vehicle into electrical energy so that this energy is then stored, in a traditional braking device this energy dissipates in the form of heat and vibration, which tends to wear the same braking device. The regenerative braking device not only reduces energy consumption but also prevents the generation of measurement caused by the friction of the brake and the wear of the brake pads of a vehicle.
El concepto de abarca toda una variedad de formas de almacenamiento de energía que incluye hidráulica o neumática, eléctrica o por medio de un volante de inercia como lo hacen los vehículos de fórmula uno. Algunos trenes modernos se hacen uso de dispositivos de frenado regenerativo para ahorrar energía. The concept encompasses a variety of forms of energy storage that includes hydraulic or pneumatic, electrical or by means of a flywheel as do the vehicles of formula one. Some modern trains make use of regenerative braking devices to save energy.
Generalmente el caso de los automóviles la energía generada del frenado regenerativo se utiliza para extender la duración de la batería y por el contrario en dispositivo de trenes la energía generada generalmente se inyecta al mismo dispositivo de suministro de energía para compensar las variaciones en la línea de transmisión.  Generally, in the case of automobiles, the energy generated from regenerative braking is used to extend the battery life and, on the contrary, in train devices, the energy generated is generally injected into the same power supply device to compensate for variations in the line of transmission.
No se debe confundir un dispositivo de frenado regenerativo con un dispositivo de frenado dinámico, ya que en este último la energía cinética no se almacena sino que se utiliza para el mismo frenado, es decir los motores de tracción del vehículo en movimiento durante el frenado dinámico funcionan como generador y se conectan a un banco de resistencias de frenado que a modo de carga sobre los motores hacen que disminuya la rotación de estos mismos. En un ejemplo ilustrativo cuando se habla de motores con imán permanente, el frenado dinámico se realiza haciendo un cortocircuito en sus terminales, esto se refleja en una frenada violenta del eje del motor. Este método, sin embargo disipa toda la energía cinética de la rotación del eje del motor, en forma de calor en el mismo motor y por tanto está limitada a la capacidad de refrigeración del mismo, y no permite ser utilizado de otra forma que no sea intermitente y con baja potencia, adicionalmente no es adecuado para aplicaciones en las que se requieran grandes fuerzas de tracción. A regenerative braking device should not be confused with a dynamic braking device, since in the latter the kinetic energy is not stored but used for the same braking, that is, the traction motors of the moving vehicle during dynamic braking They function as a generator and are connected to a braking resistor bank that, by way of loading on the motors, reduces their rotation. In an illustrative example when talking about motors with permanent magnet, dynamic braking is done by short-circuiting their terminals, this is reflected in a violent braking of the motor shaft. This method, however, dissipates all the kinetic energy of the motor shaft rotation, in the form of heat in the same motor and therefore is limited to its cooling capacity, and does not allow it to be used in any way other than intermittent and with low power, it is additionally not suitable for applications where large tensile forces are required.
En el estado de la técnica se encuentran métodos y/o dispositivos como en los que se proponen formas distintas para dispositivos de frenado regenerativo como, por ejemplo, los divulgados en los documentos US 20130147441 Al y US 5710699 A.  Methods and / or devices are found in the state of the art as in which different forms are proposed for regenerative braking devices, such as those disclosed in US 20130147441 Al and US 5710699 A.
El documento US 20130147441 Al divulga un método de sintonización automática para el dispositivo de almacenamiento de energía en vehículos que se movilizan sobre rieles que comprende la operación de un aparato de almacenamiento de energía para los trenes sobre rieles, realizar una carga inicial de los súper capacitores en el aparato de almacenamiento de energía y activar un dispositivo de encendido, seleccionar un modo de carga o descarga, detener el modo de carga o descarga y el aparato de almacenamiento de energía, determinar si la condición de operación se da para conmutar entre modo de carga y modo de descarga, conmutar entre los modos de carga y descarga de acuerdo a una condición determinada, determinar si la condición de operación satisface con una condición de mantenimiento de voltaje o sintonización automática, ejecutar la operación de mantenimiento de voltaje o sintonización automática, y ejecutar un mantenimiento de voltaje o sintonización automática. Sin embargo el método divulgado en el documento US 20130147441 Al se limita sólo a vehículos sobre rieles y está enfocado a resolver el problema de las fluctuaciones de voltaje en la línea de transmisión del proveedor de energía que entrega la potencia eléctrica en corriente directa a un dispositivo de trenes.  Document US 20130147441 When disclosing an automatic tuning method for the energy storage device in vehicles that move on rails comprising the operation of an energy storage device for trains on rails, perform an initial charge of the super capacitors in the energy storage apparatus and activate an ignition device, select a charge or discharge mode, stop the charge or discharge mode and the energy storage apparatus, determine if the operating condition is given to switch between load and discharge mode, switch between the loading and unloading modes according to a certain condition, determine if the operating condition satisfies with a voltage maintenance condition or automatic tuning, execute the voltage maintenance operation or automatic tuning, and run a voltage maintenance or automatic tuning. However, the method disclosed in US 20130147441 Al is limited only to rail vehicles and is focused on solving the problem of voltage fluctuations in the transmission line of the energy supplier that delivers the direct current electric power to a device of trains.
Por otra parte el documento US 5710699 A divulga un dispositivo y un método para compensar la carga de una batería en un dispositivo eléctrico de potencia. El dispositivo divulgado en el documento US 5710699 A es un arreglo para la compensación de la carga de baterías para un dispositivo de alimentado eléctricamente en el que la carga de la batería se encuentra sometido a demandas intermitentes de corrientes elevadas, el dispositivo incluye una batería acoplada para suministrar energía a un enlace de corriente directa, una carga, y un controlador del dispositivo acoplado circuitalmente entre el enlace de corriente directa y la carga para dosificar la potencia en la carga, dicho arreglo para la compensación de la carga de baterías comprende un dispositivo pasivo de almacenamiento de energía, un primer conversor bidireccional acoplado circuitalmente con el dispositivo pasivo de almacenamiento de energía y el enlace de corriente directa para transmitir potencia eléctrica entre el enlace de corriente directa y el dispositivo de almacenamiento de energía, un segundo conversor bidireccional acoplado circuitalmente entre la batería y el enlace de comente directa para transferir la potencia eléctrica entre la batería y el enlace de corriente directa; y los medios para de forma unidireccional acoplar la batería al dispositivo de almacenamiento de energía polarizado para conducir corriente desde la batería al dispositivo de almacenamiento de energía por lo cual la corriente de la batería se acopla al enlace de corriente directa a través del primer conversor bidireccional y del segundo conversor bidireccional y donde en una de sus reivindicaciones dependientes el dispositivo de almacenamiento de energía consta de un banco de ultracapacitores. On the other hand, document US 5710699 A discloses a device and a method for compensating the charge of a battery in an electric power device. The device disclosed in US 5710699 A is an arrangement for the compensation of the battery charge for an electrically powered device in which the battery charge is subject to intermittent demands of high currents, the device includes a coupled battery to supply power to a direct current link, a load, and a controller of the device coupled between the direct current link and the load to dose the power in the load, said arrangement for compensating the battery charge comprises a device passive energy storage, a first bidirectional converter coupled with the passive energy storage device and the direct current link to transmit electrical power between the direct current link and the energy storage device, a second bidirectional converter coupled between the battery and the direct feedback link to transfer the electrical power between the battery and the direct current link; and the means for unidirectionally coupling the battery to the polarized energy storage device to conduct current from the battery to the energy storage device whereby the battery current is coupled to the direct current link through the first bi-directional converter and of the second bidirectional converter and where in one of its dependent claims the energy storage device consists of a bank of ultracapacitors.
A su vez el método divulgado en el documento US 5710699 A comprende los pasos de: proveer corriente al enlace de corriente directa desde la batería a través de los conversores de corriente directa a corriente directa, operar un circuito de frenado dinámico cuando el motor funciona en modo regenerativo y el dispositivo pasivo de almacenamiento de energía se encuentra cargado completamente para disipar el exceso de potencia regenerada sobre los límites de la capacidad del primer conversor.  In turn, the method disclosed in US 5710699 A comprises the steps of: providing current to the direct current link from the battery through direct current to direct current converters, operating a dynamic braking circuit when the motor is running in regenerative mode and the passive energy storage device is fully charged to dissipate the excess regenerated power over the limits of the capacity of the first converter.
Si bien el documento US 5710699 A divulga un dispositivo para compensar la carga de una batería en un dispositivo eléctrico de potencia este está conformado por varios conversores bidireccionales de DC a DC lo que conlleva a pérdidas de potencia y lo hace ineficiente en término energéticos aparte de incrementar los costos de fabricación, también es más susceptible de daños pues cuenta con un alto número de componentes electrónicos.  Although document US 5710699 A discloses a device to compensate for the charge of a battery in an electric power device, it is made up of several bidirectional converters from DC to DC which leads to power losses and makes it inefficient in terms of energy apart from Increasing manufacturing costs is also more susceptible to damage as it has a high number of electronic components.
Adicionalmente el método para compensar la carga de una batería en un dispositivo eléctrico de potencia divulgado en el documento US 5710699 A desperdicia la energía que podría almacenar eléctricamente en un freno dinámico además con un par de desventajas asociada a la capacidad de disipación de potencia de los motores y no ser apropiado para aplicaciones de alta tracción.  Additionally, the method for compensating the charge of a battery in an electric power device disclosed in US 5710699 A wastes energy that could be stored electrically in a dynamic brake in addition to a couple of disadvantages associated with the power dissipation capacity of the engines and not be appropriate for high traction applications.
En resumen el estado de la técnica si bien divulga tanto dispositivos como métodos relacionada con dispositivos de frenado regenerativos son ineficientes ya que desperdician energía del frenado que puede ser recuperada y también requieren múltiples etapas de conversión DC a DC que implica mayores pérdidas de eficiencia que un dispositivo con menos etapas, menos dispositivos o más compacto, desperdician la energía adicional en dispositivos de freno dinámico para frenar bruscamente lo que ocasiona desgaste en los motores por disipar la energía en exceso utilizando el propio motor como elemento disipador de energía. Breve descripción de la invención In summary, the state of the art although it discloses both devices and methods related to regenerative braking devices are inefficient since they waste energy from the braking that can be recovered and also require multiple stages of DC to DC conversion that implies greater efficiency losses than a device with fewer stages, less devices or more compact, waste the additional energy in dynamic brake devices to abruptly brake what causes wear on the motors by dissipating excess energy using the motor itself as an energy dissipating element. Brief Description of the Invention
La presente invención corresponde a un dispositivo y método de compensación de tensión en comente directa.  The present invention corresponds to a device and method of direct voltage tension compensation.
El dispositivo de compensación de tensión en comente directa divulgado en la presente invención comprende: un EDLC (2) con un terminal positivo y un terminal negativo, un primer medidor de voltaje (9A) con velocidad de lectura en intervalos entre lps y lOps y dispuesto operativamente en el EDLC (2), un primer medidor de comente (8A) con velocidad de lectura en intervalos entre lps y lOps y dispuesto operativamente en el EDLC (2), un conversor DC/DC (7A) con comente de conmutación de 3KHz, conectado al EDLC (2) y al primer medidor de comente (8A), una unidad de cómputo (11 A) conectada al conversor DC/DC (7 A), al primer medidor de voltaje (9A) y al primer medidor de comente (8A), donde la unidad de cómputo (11 A) con base en las señales del primer medidor de voltaje (9A) y del primer medidor de comente (8A) controla el conversor DC/DC (7A) para compensar la tensión en comente directa. The direct current voltage compensation device disclosed in the present invention comprises: an EDLC (2) with a positive terminal and a negative terminal, a first voltage meter (9A) with read speed in intervals between lps and lOps and arranged operatively in the EDLC (2), a first comment meter (8A) with read speed in intervals between lps and lOps and operatively arranged in the EDLC (2), a DC / DC converter (7A) with 3KHz switching comment , connected to the EDLC (2) and the first comment meter (8A), a computing unit (11 A) connected to the DC / DC converter (7 A), the first voltage meter (9A) and the first comment meter (8A), where the computing unit (11 A) based on the signals of the first voltage meter (9A) and the first current meter (8A) controls the DC / DC converter (7A) to compensate for the voltage in the current direct.
El método de compensación de tensión en comente directa divulgado en la presente invención comprende las siguientes etapas: etapa e) verificar que la tensión de línea esté entre un límite inferior de voltaje operación y un límite superior de voltaje de operación pre-configurados por un usuario en un registro de memoria de una unidad de cómputo y pasar a la etapa (g); si la tensión de línea supera dichos límites de voltaje de operación se verifica una condición de detención; The direct current voltage compensation method disclosed in the present invention comprises the following steps: step e) verify that the line voltage is between a lower operating voltage limit and an upper operating voltage limit pre-configured by a user in a memory register of a computing unit and go to step (g); if the line voltage exceeds these operating voltage limits a stop condition is verified;
etapa g) verificar que la variación de voltaje del EDLC sea inferior a un límite de variación de voltaje del EDLC y que la variación de comente de carga del EDLC sea inferior a un límite de variación de la comente de carga del EDLC pre-configurados por un usuario en un registro de memoria de la unidad de cómputo, si dichas variaciones no superan dichos límites verificar que la comente de carga del EDLC sea inferior a un límite de comente de operación del EDLC para controlar conversor DC/DC y verificar modo de funcionamiento del conversor DC/DC, si dichas variaciones superan dichos límites entonces realizar una desconexión; step g) verify that the EDLC voltage variation is less than an EDLC voltage variation limit and that the EDLC load comment variation is less than a variation limit of the EDLC load comment pre-configured by a user in a memory register of the computing unit, if said variations do not exceed said limits verify that the EDLC load comment is less than an EDLC operating comment limit to control DC / DC converter and verify operating mode of the DC / DC converter, if said variations exceed said limits then make a disconnection;
etapa h) verificar si el modo de funcionamiento del conversor DC/DC es modo Boost ; si el modo de funcionamiento del conversor DC/DC es modo Boost, comprobar que el voltaje de carga del EDLC esté en un rango definido por un límite superior de voltaje de operación del EDLC y un límite inferior de voltaje de operación del EDLC pre programados por un usuario en un registro de memoria de la unidad de cómputo y mantener la comente de carga del EDLC; etapa i) registrar los cambios de la corriente del EDLC, el voltaje del EDLC y de la línea de tensión, y con base en dichos cambios determinar un diferencial de comente y voltaje, la unidad de cómputo calcula en cada intervalo un valor promedio de voltaje y comente con base en valores anteriores y actuales de voltaje y comente; step h) verify if the operating mode of the DC / DC converter is Boost mode; If the operating mode of the DC / DC converter is Boost mode, check that the EDLC load voltage is in a range defined by an upper EDLC operating voltage limit and a lower EDLC operating voltage limit preprogrammed by a user in a memory register of the computing unit and keep the EDLC load comment; step i) record the changes of the EDLC current, the EDLC voltage and the voltage line, and based on these changes determine a current and voltage differential, the computation unit calculates in each interval an average voltage value and comment based on previous and current voltage values and comment;
donde la etapa (i) se ejecuta periódicamente de la etapa (e) a la etapa (h) con un intervalo entre 1 ps y 10 ps independientemente de las otras etapas; where stage (i) is periodically executed from stage (e) to stage (h) with an interval between 1 ps and 10 ps regardless of the other stages;
donde alternativamente en cada una de las etapas se pasa a una etapa (f) de desconexión si no se cumplen condiciones de seguridad. where alternatively in each of the stages a stage (f) is switched off if safety conditions are not met.
Breve descripción de las figuras Brief description of the figures
La FIG. 1 muestra un ejemplo de un esquemático de conexiones eléctricas del circuito de potencia del dispositivo divulgado en la presente invención.  FIG. 1 shows an example of a schematic of electrical connections of the power circuit of the device disclosed in the present invention.
La FIG. 2 enseña un diagrama de bloques de un ejemplo de las conexiones entre los diferentes elementos del dispositivo divulgado.  FIG. 2 shows a block diagram of an example of the connections between the different elements of the disclosed device.
La FIG. 3 muestra un ejemplo en un diagrama de flujo general de los estados del método divulgado en la presente invención.  FIG. 3 shows an example in a general flow chart of the states of the method disclosed in the present invention.
La FIG. 4 muestra un ejemplo en un diagrama de flujo del subproceso de toma de mediciones de comentes y voltajes en el método divulgado en la presente invención. FIG. 4 shows an example in a flow diagram of the subprocess of measurement of comments of voltages and voltages in the method disclosed in the present invention.
La FIG. 5 muestra un ejemplo en diagrama de flujo del estado setup del método divulgado en la presente invención. FIG. 5 shows an example flowchart of the setup state of the method disclosed in the present invention.
La FIG. 6 muestra un ejemplo en un diagrama de flujo del estado de Precarga del método divulgado en la presente invención.  FIG. 6 shows an example in a flow chart of the Preload state of the method disclosed in the present invention.
La FIG. 7 muestra un ejemplo en un diagrama de flujo del estado Id le del método divulgado en la presente invención.  FIG. 7 shows an example in a flow chart of the Idle state of the method disclosed in the present invention.
La FIG. 8 muestra un ejemplo en un diagrama de flujo del estado Inicio rápido del método divulgado en la presente invención.  FIG. 8 shows an example in a flow chart of the Quick Start state of the method disclosed in the present invention.
La FIG. 9 muestra un ejemplo en un diagrama de flujo de los estados de Conexión Desconexión del método divulgado en la presente invención.  FIG. 9 shows an example in a flowchart of the states of Connection Disconnection of the method disclosed in the present invention.
La FIG. 10 muestra un ejemplo en un diagrama de flujo del modo de Buck/Boost del método divulgado en la presente invención.  FIG. 10 shows an example in a flowchart of the Buck / Boost mode of the method disclosed in the present invention.
Descripción detallada Detailed description
Siempre que se diga que un dispositivo está conectado, acoplado, acoplado en relación a la corriente o que puede estar conectado a otro dispositivo, significa que el dispositivo puede conectarse directamente mediante un cable o como alternativa, conectarse a través de otro dispositivo tal como, pero no limitado a, una resistencia, un diodo, un dispositivo conductor, y esta conexión puede ser en serie o en paralelo. Whenever it is said that a device is connected, coupled, coupled in relation to the current or that it can be connected to another device, it means that the device can be connected directly by a cable or alternatively, connected to through another device such as, but not limited to, a resistor, a diode, a conductive device, and this connection can be in series or in parallel.
Haciendo referencia a la FIG. 1 el dispositivo que divulga la presente invención comprende una unidad de protección y control (26) conectada a su entrada por una línea de transmisión de tensión positiva (31) y una línea de transmisión de tensión negativa (32); la unidad de protección y control (26) conecta por su salida a la entrada de un dispositivo de arranque suave conformado por un primer contacto (24) y una primera resistencia (25) conectados en paralelo, la unidad de protección y control (26) se conecta a su vez a un primer fusible (3a) que conecta a un primer medidor de corriente conformado por un primer sensor de efecto hall (la) dispuesto operativamente sobre un primer inductor (34a) y una primera señal de corriente (29).  Referring to FIG. 1 the device disclosed by the present invention comprises a protection and control unit (26) connected to its input by a positive voltage transmission line (31) and a negative voltage transmission line (32); the protection and control unit (26) connects by its output to the input of a soft start device consisting of a first contact (24) and a first resistor (25) connected in parallel, the protection and control unit (26) It is in turn connected to a first fuse (3a) that connects to a first current meter formed by a first hall effect sensor (la) operatively arranged on a first inductor (34a) and a first current signal (29).
Un primer medidor de voltaje conformado por un segundo sensor de efecto hall (12a) dispuesto operativamente sobre un segundo inductor (33a) y una primera señal de voltaje (30) y dispuesto operativamente a la salida de la unidad de protección y control (26).  A first voltage meter formed by a second hall effect sensor (12a) operatively arranged on a second inductor (33a) and a first voltage signal (30) and operatively disposed at the output of the protection and control unit (26) .
Un filtro paso-bajo conformado por una segunda resistencia (23) y un primer condensador (22) conectados en serie; el terminal negativo del primer condensador (22) se conecta al primer medidor de corriente, y la segunda resistencia (23) se conecta a la primera resistencia (25) del dispositivo de arranque suave.  A low-pass filter consisting of a second resistor (23) and a first capacitor (22) connected in series; The negative terminal of the first capacitor (22) is connected to the first current meter, and the second resistor (23) is connected to the first resistor (25) of the soft start device.
Un condensador intermedio conformado por una tercera resistencia (21) y un segundo condensador (20) se conectan en paralelo entre sí, y a su vez la tercera resistencia (21) y el segundo condensador (20) se conectan en paralelo al filtro paso-bajo.  An intermediate capacitor consisting of a third resistor (21) and a second capacitor (20) are connected in parallel with each other, and in turn the third resistor (21) and the second capacitor (20) are connected in parallel to the low-pass filter .
Un primer elemento de conmutación conformado por una señal de PWM Buck (19) que conecta a un primer driver IGBT (17) que a su vez se conecta al terminal gate de un primer transistor IGBT (14a); el ánodo de un primer diodo (13a) se conecta emisor del primer transistor IGBT (14a), el cátodo del primer diodo (13a) se conecta al colector del primer transistor IGBT (14a).  A first switching element formed by a PWM Buck signal (19) that connects to a first IGBT driver (17) which in turn is connected to the gate terminal of a first IGBT transistor (14a); The anode of a first diode (13a) is connected to the emitter of the first IGBT transistor (14a), the cathode of the first diode (13a) is connected to the collector of the first IGBT transistor (14a).
Una cuarta resistencia (9) y un segundo diodo (7) se conectan en paralelo; el terminal del cátodo del paralelo conformado por la cuarta resistencia (9) y el segundo diodo (7) se conecta con el terminal positivo de un tercer condensador (11); el terminal negativo del tercer condensador (11) se conecta al emisor del primer transistor IGBT (14a); el ánodo del segundo diodo (7) conectado a la cuarta resistencia (9) se conecta al colector del primer transistor IGBT (14a). El colector del primer transistor IGBT (14a) se conecta al terminal positivo del segundo condensador (20), a la segunda resistencia (23) y a la salida del dispositivo de arranque suave; el emisor del transistor IGBT (14a) se conecta un tercer inductor (6b) y al colector de un segundo transistor IGBT (14b). A fourth resistor (9) and a second diode (7) are connected in parallel; the parallel cathode terminal formed by the fourth resistor (9) and the second diode (7) is connected to the positive terminal of a third capacitor (11); the negative terminal of the third capacitor (11) is connected to the emitter of the first IGBT transistor (14a); The anode of the second diode (7) connected to the fourth resistor (9) is connected to the collector of the first IGBT transistor (14a). The collector of the first IGBT transistor (14a) is connected to the positive terminal of the second capacitor (20), the second resistor (23) and the output of the soft start device; The emitter of the IGBT transistor (14a) connects a third inductor (6b) and to the collector of a second IGBT transistor (14b).
Un segundo elemento de conmutación conformado por una señal de PWM Boost (18) que conecta a un segundo driver IGBT (16) que a su vez se conecta al terminal gate de un segundo transistor IGBT (14b); el ánodo de un tercer diodo (13b) se conecta emisor del segundo transistor IGBT (14b), el cátodo del tercer diodo (13b) se conecta al colector del segundo transistor IGBT (14b).  A second switching element consisting of a PWM Boost signal (18) that connects to a second IGBT driver (16) which in turn connects to the gate terminal of a second IGBT transistor (14b); The anode of a third diode (13b) is connected emitter of the second IGBT transistor (14b), the cathode of the third diode (13b) is connected to the collector of the second IGBT transistor (14b).
Una quinta resistencia (8) y un cuarto diodo (6a) se conectan en paralelo; el terminal del cátodo del paralelo conformado por la quinta resistencia (8) y el cuarto diodo (6a) se conecta con el terminal positivo de un cuarto condensador (10); el terminal negativo del cuarto condensador (10) se conecta al emisor del segundo transistor IGBT (14b); el ánodo del cuarto diodo (6a) conectado a la quinta resistencia (8) se conecta al colector del segundo transistor IGBT (14b).  A fifth resistor (8) and a fourth diode (6a) are connected in parallel; the parallel cathode terminal formed by the fifth resistor (8) and the fourth diode (6a) is connected to the positive terminal of a fourth capacitor (10); the negative terminal of the fourth capacitor (10) is connected to the emitter of the second IGBT transistor (14b); The anode of the fourth diode (6a) connected to the fifth resistor (8) is connected to the collector of the second IGBT transistor (14b).
El colector del segundo transistor IGBT (14b) se conecta al emisor del primer transistor IGBT (14a) y al tercer inductor (6b); el emisor del segundo transistor IGBT (14b) se conecta al terminal negativo del segundo condensador (20), al terminal negativo del primer condensador (22), a un segundo contacto (5), al primer inductor (34a) del primer medidor de corriente y a un cuarto inductor (34b) de un segundo medidor de corriente. The collector of the second IGBT transistor (14b) is connected to the emitter of the first IGBT transistor (14a) and the third inductor (6b); The emitter of the second IGBT transistor (14b) is connected to the negative terminal of the second capacitor (20), to the negative terminal of the first capacitor (22), to a second contact (5), to the first inductor (34a) of the first current meter and to a fourth inductor (34b) of a second current meter.
El segundo medidor de corriente conformado por un tercer sensor de efecto hall (lb) dispuesto operativamente sobre el cuarto inductor (34b) y una segunda señal de corriente (28). The second current meter formed by a third hall effect sensor (lb) operatively arranged on the fourth inductor (34b) and a second current signal (28).
Un elemento de descarga conformado por una sexta resistencia (4) y un segundo contacto (5) que se conectan en serie; la terminal de la sexta resistencia (4) que no se conecta al segundo contacto (5) se conecta al tercer inductor (6b) y al terminal positivo de un elemento de alta densidad EDLC (2); la terminal del segundo contacto (5) que no se conecta a la sexta resistencia (4) se conecta al cuarto inductor (34b) del segundo medidor de corriente, al emisor del segundo transistor IGBT (14b), al terminal negativo del primer condensador (22), al terminal negativo del segundo condensador (20) y al primer inductor (34a) del primer medidor de corriente.  A discharge element formed by a sixth resistor (4) and a second contact (5) that are connected in series; the terminal of the sixth resistor (4) that does not connect to the second contact (5) is connected to the third inductor (6b) and to the positive terminal of a high-density element EDLC (2); The terminal of the second contact (5) that does not connect to the sixth resistor (4) is connected to the fourth inductor (34b) of the second current meter, to the emitter of the second IGBT transistor (14b), to the negative terminal of the first capacitor ( 22), to the negative terminal of the second capacitor (20) and the first inductor (34a) of the first current meter.
Para facilitar el entendimiento de la presente invención se entenderá cuando se hable de EDLC corresponderá a un elemento de alta densidad gravimétrica de potencia EDLC. Un EDLC (2) con un terminal positivo y un terminal negativo, conecta su terminal positivo al tercer inductor (6b) y su terminal negativo a un segundo fusible (3b). To facilitate the understanding of the present invention, it will be understood when talking about EDLC, it will correspond to a high density gravimetric element of EDLC power. An EDLC (2) with a positive terminal and a negative terminal connects its positive terminal to the third inductor (6b) and its negative terminal to a second fuse (3b).
El segundo fusible (3b) conecta la terminal que no está conectada con el terminal negativo del elemento de alta densidad EDLC (2) al inductor (34b) del segundo medidor de corriente.  The second fuse (3b) connects the terminal that is not connected with the negative terminal of the high density element EDLC (2) to the inductor (34b) of the second current meter.
En paralelo al elemento de alta densidad EDLC (2) se dispone operativamente un segundo medidor de voltaje conformado por un cuarto sensor de efecto hall (12b) dispuesto operativamente sobre un quinto inductor (33b) y una segunda señal de voltaje (27).  In parallel to the high-density element EDLC (2), a second voltage meter is operatively made up of a fourth hall effect sensor (12b) operatively arranged on a fifth inductor (33b) and a second voltage signal (27).
Haciendo referencia a la FIG. 1, el dispositivo divulgado en la presente invención tiene una línea de transmisión de tensión positiva (31) y una línea de transmisión de tensión negativa (32) cuya diferencia de tensión corresponde a la fuente de comente directa del dispositivo de la presente invención, dicha diferencia de tensión está en el rango de 400 VCD a 3000 VCD o se selecciona de los voltajes de 400 VCD, 450 VCD, 500 VCD, 550 Veo, 600 VCD, 650 VCD, 700 VCD, 750 VCD, 800 VCD, 850 VCD, 900 VCD, 950 VCD, 1000 VCD, 1050 VCD, H00 VCD, 1150 Veo, 1200 VCD, 1250 VCD, 1300 VCD, 1350 VCD, 1400Referring to FIG. 1, the device disclosed in the present invention has a positive voltage transmission line (31) and a negative voltage transmission line (32) whose voltage difference corresponds to the direct source of the device of the present invention, said voltage difference is in the range of 400 V CD to 3000 V CD or is selected from the voltages of 400 V CD , 450 V CD , 500 V CD , 550 Veo, 600 V CD , 650 V CD , 700 V CD , 750 V CD , 800 V CD , 850 V CD , 900 V CD , 950 V CD , 1000 VDC, 1050 V CD , H00 V CD , 1150 Veo, 1200 V CD , 1250 V CD , 1300 V CD , 1350 V CD , 1400
VCD, 1450 VCD, 1500 VCD, 1550 VCD, 1600 VCD, 1650 VCD, 1700 VCD, 1750 VCD, 1800V CD , 1450 V CD , 1500 V CD , 1550 V CD , 1600 V CD , 1650 V CD , 1700 V CD , 1750 V CD , 1800
VCD, 1850 VCD, 1900 VCD, 1950 VCD, 2000 VCD, 2050 VCD, 2100 VCD, 2150 VCD, 2200V CD , 1850 V CD , 1900 V CD , 1950 V CD , 2000 V CD , 2050 V CD , 2100 V CD , 2150 V CD , 2200
VCD, 2250 VCD, 2300 VCD, 2350 VCD, 2400 VCD, 2450 VCD, 2500 VCD, 2550 VCD, 2600V CD , 2250 V CD , 2300 V CD , 2350 V CD , 2400 V CD , 2450 V CD , 2500 V CD , 2550 V CD , 2600
VCD, 2650 VCD, 2700 VCD, 2750 VCD, 2800 VCD, 2850 VCD, 2900 VCD, 2950 VCD o 3000 VCD· Por ejemplo, el valor de la diferencia de tensión entre las líneas de transmisión de tensión positiva (31) y la línea de transmisión de tensión negativa (32) es de 1500VCD y una tensión en vacío de l650VcD· VCD es voltaje en comente directa. V CD , 2650 V CD , 2700 V CD , 2750 V CD , 2800 V CD , 2850 V CD , 2900 V CD , 2950 V CD or 3000 V CD · For example, the value of the voltage difference between the transmission lines positive voltage (31) and the negative voltage transmission line (32) is 1500V DC and a vacuum voltage of l650Vc D · V CD is direct voltage.
Para el entendimiento de la presente invención se entenderá que la tensión en vacío es la diferencia de tensión entre la línea de transmisión de tensión positiva (31) y la línea de transmisión de tensión negativa (32) cuando no hay una carga eléctrica conectada a ellas.  For the understanding of the present invention it will be understood that the idle voltage is the voltage difference between the positive voltage transmission line (31) and the negative voltage transmission line (32) when there is no electric charge connected to them .
También con el ánimo de facilitar la descripción de la presente invención, se entenderá que la tensión de línea es la diferencia de tensión entre la línea de transmisión de tensión positiva (31) y la línea de transmisión de tensión negativa (32).  Also in order to facilitate the description of the present invention, it will be understood that the line voltage is the voltage difference between the positive voltage transmission line (31) and the negative voltage transmission line (32).
Así mismo para referirse a la línea de transmisión de tensión positiva (31) y la línea de transmisión de tensión negativa (32) simplemente se expresará como la línea de transmisión. El dispositivo que divulga la presente invención, en un ejemplo, el dispositivo cuenta con la unidad de protección y control (26) que se encarga de aislar la línea de transmisión del primer elemento de conmutación y del segundo elemento de conmutación y corresponde a la protección primaria del dispositivo. Also to refer to the positive voltage transmission line (31) and the negative voltage transmission line (32) will simply be expressed as the transmission line. The device disclosed by the present invention, in one example, the device has the protection and control unit (26) which is responsible for isolating the transmission line of the first switching element and the second switching element and corresponds to the protection Primary device
Alternativamente en una modalidad de la presente invención, en un ejemplo, la unidad de protección y control (26) se selecciona del grupo de dispositivos de protección en corriente continua, dispositivos de interrupción ultrarrápidos, fusibles ultrarrápidos, interruptores termo-magnéticos, dispositivos de control en corriente continua, detectores de cortocircuitos, relevadores programables y combinaciones de los anteriores.  Alternatively, in one embodiment of the present invention, in one example, the protection and control unit (26) is selected from the group of DC protection devices, ultrafast interruption devices, ultrafast fuses, thermo-magnetic switches, control devices in direct current, short circuit detectors, programmable relays and combinations of the above.
La unidad de protección y control (26) se encarga de aislar la línea de transmisión del primer elemento de conmutación y del segundo elemento de conmutación. En un ejemplo, el dispositivo que divulga la presente invención la unidad de protección y control (26) es un relevador programable.  The protection and control unit (26) is responsible for isolating the transmission line of the first switching element and the second switching element. In one example, the device disclosed by the present invention the protection and control unit (26) is a programmable relay.
La unidad de protección y control (26) es la protección primaria del dispositivo de la presente invención y tiene una velocidad de actuación entre lps y 50ms. Por ejemplo, la velocidad de actuación de la unidad de protección y control es de 40ms.  The protection and control unit (26) is the primary protection of the device of the present invention and has an actuation speed between lps and 50ms. For example, the operating speed of the protection and control unit is 40ms.
Opcionalmente, el dispositivo divulgado en la presente invención cuenta con un dispositivo de arranque suave conformado por un primer contacto (24) y una primera resistencia (25), este entra en funcionamiento como precarga inicial del elemento de alta densidad EDLC (2), el dispositivo de arranque suave previene que un fenómeno transitorio con una corriente superior a la corriente nominal del elemento EDLC (2) afecte el dispositivo de forma negativa. En un ejemplo, la selección del contacto (24) corresponde a una corriente máxima de 180A y un voltaje de aislamiento de 1850V.Optionally, the device disclosed in the present invention has a soft start device consisting of a first contact (24) and a first resistor (25), this comes into operation as an initial preload of the high density element EDLC (2), the Soft start device prevents a transient phenomenon with a current greater than the rated current of the EDLC element (2) from affecting the device negatively. In one example, the selection of the contact (24) corresponds to a maximum current of 180A and an insulation voltage of 1850V.
En una modalidad de la presente invención, por ejemplo, el primer medidor de voltaje conformado por un segundo sensor de efecto hall (12a) dispuesto operativamente sobre un segundo inductor (33a) y una primera señal de voltaje (30) y dispuesto operativamente a la salida de la unidad de protección y control (26) y el segundo medidor de voltaje conformado por un cuarto sensor de efecto hall (12b) dispuesto operativamente sobre un quinto inductor (33b) y una segunda señal de voltaje (27) tienen una velocidad de lectura entre lps y 500ms. En un ejemplo el primer medidor de voltaje y el segundo medidor de voltaje tienen una velocidad de lectura en intervalos entre lps y lOps. Realizar lecturas a esta rata de velocidad permite junto con el primer elemento de conmutación y el segundo elemento de conmutación aumentar la eficiencia del dispositivo de compensación de tensión de la presente invención. La consecuencia natural del efecto de compensación es mejorar la estabilidad de tensión, esto protege equipos de alto costo como los motores, y adicionalmente representa un ahorro de energía debido a que la energía no se disipa en forma de calor en resistencias, sino que es reutilizada para la tracción. In one embodiment of the present invention, for example, the first voltage meter formed by a second hall effect sensor (12a) operatively disposed on a second inductor (33a) and a first voltage signal (30) and operatively arranged at the output of the protection and control unit (26) and the second voltage meter consisting of a fourth hall effect sensor (12b) operatively arranged on a fifth inductor (33b) and a second voltage signal (27) have a speed of reading between lps and 500ms. In one example, the first voltage meter and the second voltage meter have a reading speed in intervals between lps and lOps. Taking readings at this rate allows, together with the first switching element and the second switching element, to increase the efficiency of the voltage compensation device of the present invention. The natural consequence of the compensation effect is to improve the stability of tension, this protects high-cost equipment such as motors, and additionally represents energy savings because the energy does not dissipate in the form of heat in resistors, but is reused for traction.
Para entendimiento de la presente invención, se entenderá que precarga inicial como un estado en el que la comente de carga del elemento de alta densidad EDLC (2) es una porción de la comente máxima de carga del elemento de alta densidad EDLC (2).  For an understanding of the present invention, it will be understood that initial preload as a state in which the load comment of the high density element EDLC (2) is a portion of the maximum load comment of the high density element EDLC (2).
Haciendo referencia a la FIG. 1, en una modalidad de la presente invención el filtro paso-bajo conformado por un primer condensador (22) y una segunda resistencia (23) conectados en serie con la función de mitigar, eliminar y/o filtrar las señales eléctricas contaminantes conducidas, debidas fuentes extemas conectadas a la misma línea de transmisión y también debidas a fuentes intemas del mismo dispositivo de la presente invención para que no interfieran con otros dispositivos conectados a la misma línea de transmisión. En una realización de la presente invención, por ejemplo, el filtro paso- bajo conformado por un primer condensador (22) y una segunda resistencia (23) conectados en serie atenúa las señales armónicas de las frecuencias externas al dispositivo de la presente invención, que por ejemplo son del orden de 250Hz y las señales producidas por las conmutaciones del primer elemento de conmutación y del segundo elemento de conmutación que por ejemplo, tienen frecuencia central del orden de 3kHz, así la frecuencia de corte del filtro paso-bajo se escoge de 3kHz. Referring to FIG. 1, in one embodiment of the present invention, the low-pass filter formed by a first capacitor (22) and a second resistor (23) connected in series with the function of mitigating, eliminating and / or filtering the contaminating electrical signals conducted, due external sources connected to the same transmission line and also due to internal sources of the same device of the present invention so as not to interfere with other devices connected to the same transmission line. In an embodiment of the present invention, for example, the low-pass filter formed by a first capacitor (22) and a second resistor (23) connected in series attenuates the harmonic signals of the frequencies external to the device of the present invention, which for example, they are of the order of 250Hz and the signals produced by the switching of the first switching element and the second switching element which, for example, have a central frequency of the order of 3kHz, thus the cut-off frequency of the low-pass filter is chosen from 3kHz
Opcionalmente el filtro paso-bajo se diseña de acuerdo al tipo de rectificación que utilice la línea de transmisión. Optionally, the low-pass filter is designed according to the type of rectification used by the transmission line.
En una modalidad de la presente invención los tipos de rectificación que se utilizan para la línea de transmisión se selecciona del gmpo de rectificadores no controlados cómo rectificadores de media onda bifásico, rectificadores de media onda trifásico, rectificadores de media onda hexafásico, rectificadores de media onda con elementos reales, rectificadores de media onda con carga RL sin diodo de freewheeling, rectificadores de media onda con diodo freewheeling, rectificadores de onda completa en estrella bifásico, rectificadores de onda completa en estrella trifásico, rectificadores de onda completa en estrella con elementos reales, rectificadores de onda completa en estrella con carga RL, rectificadores de onda completa en estrella con filtro C, rectificadores de onda completa en delta trifásico, rectificadores de onda completa en delta hexafásico, o rectificadores controlados cómo rectificadores controlados media onda trifásico, rectificadores controlados de onda completa bifásico, rectificadores controlados de onda completa trifásicos y combinaciones de estos. In one embodiment of the present invention the types of rectification that are used for the transmission line are selected from the uncontrolled rectifier group as two-phase half-wave rectifiers, three-phase half-wave rectifiers, hexaphase half-wave rectifiers, half-wave rectifiers with real elements, half wave rectifiers with RL load without freewheeling diode, half wave rectifiers with freewheeling diode, full wave rectifiers in two phase star, full wave rectifiers in three phase star, full wave rectifiers in star with real elements, full-wave star rectifiers with RL load, full-wave star rectifiers with C filter, full-wave rectifiers in three-phase delta, full-wave rectifiers in hexaphase delta, or controlled rectifiers as medium controlled rectifiers three-phase wave, two-phase full-wave controlled rectifiers, three-phase full-wave controlled rectifiers and combinations thereof.
Por ejemplo, dispositivo se conecta a línea de transmisión basada en dos rectificadores controlados trifásicos de onda completa o rectificador de 12 pulsos.  For example, the device is connected to a transmission line based on two three-phase controlled full-wave rectifiers or 12-pulse rectifier.
Alternativamente, el dispositivo divulgado en la presente invención tiene un segundo condensador (20) y una tercera resistencia (21) que conectados en paralelo con el filtro paso-bajo conforman un circuito de desacoplo para la conformación del loop de retomo de todas las señales espurias cómo EMI ( Electromagnetic Interference , por sus siglas en inglés EMI) su capacitancia y capacidad para suministrar energía rápidamente en conjunto con una disposición física cercana al primer elemento de conmutación y al segundo elemento de conmutación para garantizar una baja inductancia asociada a los conductores que separan el segundo condensador (20) la tercera resistencia (21) y el primer elemento de conmutación y el segundo elemento de conmutación proporcionando una baja impedancia para las señales de EMI mitigando su efecto sobre el dispositivo divulgado en la presente invención.  Alternatively, the device disclosed in the present invention has a second capacitor (20) and a third resistor (21) that connected in parallel with the low-pass filter form a decoupling circuit for the conformation of the return loop of all spurious signals how EMI (Electromagnetic Interference, for its acronym in English EMI) its capacitance and ability to supply energy quickly in conjunction with a physical arrangement close to the first switching element and the second switching element to ensure a low inductance associated with the separating conductors the second capacitor (20) the third resistor (21) and the first switching element and the second switching element providing a low impedance for EMI signals mitigating their effect on the device disclosed in the present invention.
El segundo condensador (20), en un ejemplo, es de un valor de capacitancia de 602pF @ 2000V con resistencia en serie equivalente (por sus siglas en inglés, Equivalent Series Resistance ESR) de 0.03 Ohmios, sin embargo, es práctico utilizar un valor de capacitancia mayor al calculado, siempre y cuando no se produzca una corriente de pico IPk que sobrepase el nivel de protección que provee la unidad de protección y control (26) ante cambios abruptos de la tensión de entrada V¡n. The second capacitor (20), in one example, has a capacitance value of 602pF @ 2000V with equivalent series resistance (for its acronym in English, Equivalent Series Resistance ESR) of 0.03 Ohms, however, it is practical to use a value higher the capacitance calculated, provided it is not a peak current I Pk exceeding the level of protection provided by the protection and control unit (26) response to sudden changes the input voltage Vj n occur.
En una modalidad del dispositivo de la presente invención, las frecuencias de conmutación del primer elemento de conmutación y del segundo elemento de conmutación van desde 500Hz hasta 100kHz. En un ejemplo, en la presente invención a criterio se selecciona que sea 4 veces la frecuencia natural del tipo de rectificación de la línea de transmisión y es 2880Hz, esto se hace con el objetivo de reducir el valor de la inductancia del tercer inductor (6b).  In one embodiment of the device of the present invention, the switching frequencies of the first switching element and the second switching element range from 500Hz to 100kHz. In one example, in the present invention, at the discretion, it is selected to be 4 times the natural frequency of the type of rectification of the transmission line and is 2880Hz, this is done with the objective of reducing the inductance value of the third inductor (6b ).
En una modalidad de la presente invención, en un ejemplo del dispositivo, el primer elemento de conmutación se utiliza para la operación en modo Buck y el segundo elemento de conmutación se utiliza para la operación en modo Boost.  In one embodiment of the present invention, in an example of the device, the first switching element is used for operation in Buck mode and the second switching element is used for operation in Boost mode.
Para el entendimiento de la presente invención, se entenderá operación en modo Buck cómo el uso de un conversor DC/DC o un elemento de conmutación para la reducción de la tensión en corriente directa, y la operación en modo Boost para la elevación de la tensión en corriente directa. En una modalidad de la presente invención el dispositivo selecciona el modo de operación en modo Buck/Boost y depende de la disponibilidad de energía en relación a la demanda de energía de la línea de transmisión. Por ejemplo, si el estado de disponibilidad de energía de la línea de transmisión es menos frecuente que el estado de demanda, se privilegia el modo de operación en modo Buck, así se almacena la energía disponible; el tercer inductor (6b) entrega su energía al elemento de alta densidad EDLC (2) durante todo el ciclo de apagado del primer transistor IGBT (14a) del primer elemento de conmutación para la operación en modo Buck. For the understanding of the present invention, operation in Buck mode will be understood as the use of a DC / DC converter or a switching element for direct current voltage reduction, and Boost mode operation for voltage elevation. in direct current. In one embodiment of the present invention, the device selects the operating mode in Buck / Boost mode and depends on the availability of energy in relation to the power demand of the transmission line. For example, if the power availability state of the transmission line is less frequent than the demand state, the operating mode in Buck mode is privileged, thus the available energy is stored; The third inductor (6b) delivers its energy to the high density EDLC element (2) during the entire shutdown cycle of the first IGBT transistor (14a) of the first switching element for Buck mode operation.
Alternativamente, en el dispositivo divulgado en la presente invención, la señal de PWM Buck (19) se aplica a través de un primer driver de IGBT (17) a la base del primer transistor IGBT (14a) del primer elemento de conmutación y la señal de PWM Boost (18) se aplica a través de un segundo driver IGBT (16) a la base de un segundo transistor IGBT (14b) del segundo elemento de conmutación, esto se hace para acoplar eléctricamente la señal de PWM Buck (19) y la señal de PWM Boost (18) proveniente de una unidad de cómputo.  Alternatively, in the device disclosed in the present invention, the PWM Buck signal (19) is applied through a first IGBT driver (17) to the base of the first IGBT transistor (14a) of the first switching element and the signal PWM Boost (18) is applied through a second IGBT driver (16) to the base of a second IGBT transistor (14b) of the second switching element, this is done to electrically couple the PWM Buck signal (19) and the PWM Boost signal (18) from a computing unit.
Para el entendimiento de la presente invención una unidad de cómputo se entenderá como un dispositivo que procesa datos, por ejemplo, microcontroladores, micro procesadores, DSCs ( Digital Signal Controller por sus siglas en ingles), FPGAs ( Field Programmable Gate Array por sus siglas en inglés), CPLDs ( Complex Programmable Logic Device por sus siglas en inglés), ASICs ( Application Specific Integrated Circuit por sus siglas en inglés), SoCs ( System on Chip por sus siglas en inglés), PSoCs ( Programmable System on Chip por sus siglas en inglés), computadores, servidores, tabletas, celulares, celulares inteligentes, y unidades de cómputo conocidas por una persona medianamente versada en la materia o combinaciones de estos.  For the understanding of the present invention a computing unit will be understood as a device that processes data, for example, microcontrollers, microprocessors, DSCs (Digital Signal Controller), FPGAs (Field Programmable Gate Array) English), CPLDs (Complex Programmable Logic Device), ASICs (Application Specific Integrated Circuit), SoCs (System on Chip), PSoCs (Programmable System on Chip) in English), computers, servers, tablets, cell phones, smart phones, and computing units known to a person moderately versed in the subject or combinations thereof.
Opcionalmente, la unidad de protección y control (26), la primera señal de voltaje (30), el primer contacto (24), la primera señal de corriente (29), la señal de PWM Boost (18), la señal de PWM Buck (19), el segundo contacto (5), la segunda señal de voltaje (27) y la segunda señal de corriente (28) están conectadas a una unidad de cómputo en la que se implementa el método de la presente invención.  Optionally, the protection and control unit (26), the first voltage signal (30), the first contact (24), the first current signal (29), the PWM Boost signal (18), the PWM signal Buck (19), the second contact (5), the second voltage signal (27) and the second current signal (28) are connected to a computing unit in which the method of the present invention is implemented.
El voltaje sobre el elemento de alta densidad EDLC (2) se rige por el ciclo de trabajo de la señal de PWM Buck (19) en la siguiente fórmula:  The voltage on the high density element EDLC (2) is governed by the duty cycle of the PWM Buck signal (19) in the following formula:
VEDLC = DXVDC VEDLC = DXV DC
D es el ciclo de trabajo de la señal que controla el primer transistor IGBT (14a) del primer elemento de conmutación para la operación en modo Buck. El tercer inductor (6b) al entregar toda su energía almacenada al elemento de alta densidad EDLC (2) garantiza eficiencia en el aprovechamiento de la energía y evita estados de resonancia del dispositivo por tanto baja EMI. D is the duty cycle of the signal that controls the first IGBT transistor (14a) of the first switching element for Buck mode operation. The third inductor (6b) when delivering all its stored energy to the high density element EDLC (2) guarantees efficiency in the use of energy and avoids resonance states of the device therefore low EMI.
Opcionalmente, en el dispositivo de la presente invención el cálculo del tercer inductor (6b) determina la operación en modo Boost que se selecciona de modo Boost en sub modo continuo o modo Boost en sub-modo discontinuidad. En un ejemplo, dicha operación en modo Boost es en sub-modo de discontinuidad.  Optionally, in the device of the present invention the calculation of the third inductor (6b) determines the operation in Boost mode which is selected from Boost mode in continuous sub mode or Boost mode in discontinuous sub-mode. In one example, said operation in Boost mode is in discontinuity sub-mode.
Para el entendimiento de la presente invención, se entenderá que el término modo continuo como un sub-modo de operación de los elementos de conmutación Buck y Boost donde corriente fluye por el elemento de alta densidad EDLC durante todo el ciclo de control, llegando a puntos donde se obtiene una intensidad de corriente máxima o mínima, pero que nunca llega a anularse; en cambio en el sub-modo discontinuo, la magnitud de la corriente de salida del convertidor cae a cero en una porción del ciclo, de manera que el valor de la intensidad de corriente comienza en cero, llega a un valor pico y retoma a cero en cada ciclo.  For the understanding of the present invention, it will be understood that the term continuous mode as a sub-mode of operation of the Buck and Boost switching elements where current flows through the high-density EDLC element throughout the control cycle, reaching points where a maximum or minimum current intensity is obtained, but that never gets canceled; instead in the discontinuous sub-mode, the magnitude of the converter's output current drops to zero in a portion of the cycle, so that the current value starts at zero, reaches a peak value and returns to zero in each cycle
El modo de funcionamiento del primer elemento de conmutación relacionado con la operación en modo Buck y del segundo elemento de conmutación relacionada con la operación en modo Boost tienen un sub-modo de funcionamiento que se selecciona entre sub-modo continuo y sub-modo discontinuo. En un ejemplo, primer elemento de conmutación relacionado con la operación en modo Buck funciona en sub-modo continuo y el segundo elemento de conmutación relacionada con la operación en modo Boost funciona en sub-modo discontinuo y así evitar que ocurra inversión de fase o se supere el criterio de ganancia de ancho de banda en el funcionamiento del dispositivo. The operating mode of the first switching element related to the operation in Buck mode and of the second switching element related to the operation in Boost mode have a sub-mode of operation that is selected between continuous sub-mode and discontinuous sub-mode. In one example, the first switching element related to the operation in Buck mode operates in continuous sub-mode and the second switching element related to the operation in Boost mode operates in discontinuous sub-mode and thus prevents phase inversion from occurring or Exceeds the criteria for bandwidth gain in device operation.
La inductancia del tercer inductor (6b) configura el sub-modo de operación continuo o discontinuo del primer elemento de conmutación asociado a la operación en modo Buck y del segundo elemento de conmutación asociado a la operación en modo Boost. En un ejemplo, un valor de inductancia para el tercer inductor (6b) de 118 mH configura el sub-modo de operación continuo para el primer elemento de conmutación (Buck) y sub- modo discontinuo para el segundo elemento de conmutación (Boost). The inductance of the third inductor (6b) configures the sub-mode of continuous or discontinuous operation of the first switching element associated with the operation in Buck mode and of the second switching element associated with the operation in Boost mode. In one example, an inductance value for the third inductor (6b) of 118 mH configures the continuous operation sub-mode for the first switching element (Buck) and the discontinuous sub-mode for the second switching element (Boost).
Adicionalmente, el tercer inductor (6b) conforma una red snubber con el elemento de alta densidad EDLC (2), la sexta resistencia (4) y el segundo contacto (5) para suprimir los picos de voltaje y amortiguar la oscilación transitoria provocada por la inductancia del circuito cuando se abre el segundo contacto (5). Por lo anterior, es determinante evacuar la energía almacenada el tercer inductor (6b), para asegurar que no ocurra inversión de fase o se supere el criterio de ganancia de ancho de banda en el funcionamiento del dispositivo. Para esto se mantiene el sub modo discontinuo de operación en el modo Boost. Additionally, the third inductor (6b) forms a snubber network with the high density element EDLC (2), the sixth resistor (4) and the second contact (5) to suppress the voltage peaks and dampen the transient oscillation caused by the circuit inductance when the second contact (5) opens. Therefore, it is crucial to evacuate the energy stored in the third inductor (6b), to ensure that no phase inversion occurs or the bandwidth gain criterion is exceeded in the operation of the device. For this, the discontinuous sub mode of operation is maintained in Boost mode.
Haciendo referencia a la FIG. 1 el primer diodo (13a), el segundo diodo (7), la cuarta resistencia (9), el tercer condensador (11) son la red snubber del primer transistor IGBT (14a) para suprimir los picos de voltaje y amortiguar la oscilación transitoria provocada por la inductancia del circuito cuando se abre el transistor IGBT (14a) para la operación en modo Buck.  Referring to FIG. 1 the first diode (13a), the second diode (7), the fourth resistor (9), the third capacitor (11) are the snubber network of the first IGBT transistor (14a) to suppress the voltage peaks and dampen the transient oscillation caused by the inductance of the circuit when the IGBT transistor (14a) is opened for operation in Buck mode.
Alternativamente, el tercer diodo (13b), el cuarto diodo (6a), la quinta resistencia (8), el cuarto condensador (10) son la red snubber del segundo transistor IGBT (14b) para suprimir los picos de voltaje y amortiguar la oscilación transitoria provocada por la inductancia del circuito cuando se abre el segundo transistor IGBT (14b) para la operación en modo Boost.  Alternatively, the third diode (13b), the fourth diode (6a), the fifth resistor (8), the fourth capacitor (10) are the snubber network of the second IGBT transistor (14b) to suppress the voltage peaks and dampen the oscillation transient caused by the inductance of the circuit when the second IGBT transistor (14b) is opened for operation in Boost mode.
El elemento de alta densidad EDCL Electric Double-Layer Capacitor por sus siglas en inglés) hace parte de familia de capacitores electroquímicos conocidos como ultracapacitores o supercapacitores, estos no tienen un dieléctrico sólido en su interior y tienen la capacidad de cargarse y descargarse a una rata muy elevada en comparación a capacitores convencionales, además de soportar más de un millón de ciclos de carga y descarga aunque una baja densidad de almacenamiento de energía que ronda los 30 Wh/kg.  The EDCL Electric Double-Layer Capacitor high density element is part of a family of electrochemical capacitors known as ultracapacitors or supercapacitors, these do not have a solid dielectric inside and have the ability to charge and discharge to a rat very high compared to conventional capacitors, in addition to supporting more than one million cycles of loading and unloading although a low energy storage density of around 30 Wh / kg.
Opcionalmente, en una modalidad divulgada en la presente invención, el dispositivo tiene un elemento de alta densidad EDLC (2) se selecciona del grupo de ultracapacitores electrolíticos, ultracapacitores no electrolíticos, ultracapacitores acuosos de óxido, ultracapacitores de polímeros conductores y combinaciones.  Optionally, in an embodiment disclosed in the present invention, the device has a high density EDLC element (2) selected from the group of electrolytic ultracapacitors, non-electrolytic ultracapacitors, aqueous oxide ultracapacitors, conductive polymer ultracapacitors and combinations.
En una modalidad de la invención el elemento de alta densidad EDLC (2) es un banco de EDLCs que es un arreglo de EDLCs en serie o paralelo o combinaciones. Por ejemplo un banco de EDLCs se compone de ocho EDLCs conectados en serie, cada uno con una capacitancia de 63F y de un voltaje nominal de 125V para obtener una capacitancia de 7,875F con un voltaje nominal de 1000V; este valor de 1000V de voltaje nominal permite que se pueda reducir o elevar el voltaje dentro de un margen de operación; en términos de energía almacenable para ésta configuración, respetando el criterio de la máxima energía almacenada 1.09 kWh. En una de las modalidades de la invención la comente máxima de operación para modo Buck o modo Boost es de 180A si se tiene un margen de seguridad del 25% basado en una corriente máxima de operación del elemento de alta densidad EDLC (2) de 240A. Alternativamente, en una modalidad de la invención el driver IGBT (16), es en un ejemplo, un módulo de administración de corriente nominal de 1500A y voltaje colector-emisor de 3300V. In one embodiment of the invention the high density element EDLC (2) is a bank of EDLCs that is an array of serial or parallel EDLCs or combinations. For example, a bank of EDLCs consists of eight EDLCs connected in series, each with a capacitance of 63F and a nominal voltage of 125V to obtain a capacitance of 7,875F with a nominal voltage of 1000V; This value of 1000V of nominal voltage allows the voltage to be reduced or raised within an operating range; in terms of storable energy for this configuration, respecting the criterion of maximum stored energy 1.09 kWh. In one of the embodiments of the invention, the maximum operating comment for Buck mode or Boost mode is 180A if there is a 25% safety margin based on a maximum operating current of the high density element EDLC (2) of 240A . Alternatively, in one embodiment of the invention, the IGBT driver (16) is, in an example, a nominal current management module of 1500A and collector-emitter voltage of 3300V.
Opcionalmente, en una modalidad de la presente invención la corriente que se inyecta o absorbe de la línea de transmisión está regulada por la tensión de la fuente de manera continua, debido a las velocidades de conmutación del primer elemento de conmutación y del segundo elemento de conmutación. Por ejemplo las velocidades de conmutación del primer elemento de conmutación y del segundo elemento de conmutación son de 3kHz.  Optionally, in one embodiment of the present invention the current that is injected or absorbed from the transmission line is regulated by the source voltage continuously, due to the switching speeds of the first switching element and the second switching element. . For example, the switching speeds of the first switching element and the second switching element are 3kHz.
Haciendo referencia a la FIG. 2, en una modalidad de la presente invención una unidad de cómputo (11A) conecta al circuito conversor DC/DC (7A).  Referring to FIG. 2, in one embodiment of the present invention a computing unit (11A) connects to the DC / DC converter circuit (7A).
Haciendo referencia a la FIG. 2, en un ejemplo el conversor DC/DC (7A) tiene una corriente de conmutación con una frecuencia que va desde 500Hz a 30kHz. Por ejemplo, se selecciona una corriente de conmutación con una frecuencia de 3kHz.  Referring to FIG. 2, in one example the DC / DC converter (7A) has a switching current with a frequency ranging from 500Hz to 30kHz. For example, a switching current with a frequency of 3kHz is selected.
Haciendo referencia a la FIG. 2, el dispositivo divulgado en la presente invención tiene un conversor DC/DC (7A) que se selecciona del grupo de conversores DC/DC magnéticos bidireccionales (v. gr. Step-down (buck), Step-up (boost), SEPIC, Inverting (buck-boost), Cuk, True buck-boost, Split-pi (boost-buck), Forward, Push-pull (half bridge), Full bridge, Flyback), capacitivos bidireccionales y combinaciones. Adicionalmente la topología del conversor DC/DC bidireccional puede ser conmutada, resonante, continua o discontinua. Referring to FIG. 2, the device disclosed in the present invention has a DC / DC converter (7A) that is selected from the group of two-way magnetic DC / DC converters (see step-down (buck), Step-up (boost), SEPIC , Inverting (buck-boost), Cuk, True buck-boost, Split-pi (boost-buck), Forward, Push-pull (half bridge), Full bridge, Flyback), two-way capacitive and combinations. Additionally, the topology of the bidirectional DC / DC converter can be switched, resonant, continuous or discontinuous.
Haciendo referencia a la FIG. 2, en una modalidad de la invención el dispositivo divulgado tiene una unidad de cómputo (11A) que conecta a una unidad de protección y control (26), un primer medidor de voltaje (9A), un primer medidor de corriente (8A), un dispositivo de arranque (3A), un segundo medidor de corriente (8A), un segundo medidor de voltaje (9A), un conversor DC/DC (7A).  Referring to FIG. 2, in one embodiment of the invention, the disclosed device has a computing unit (11A) that connects to a protection and control unit (26), a first voltage meter (9A), a first current meter (8A), a starting device (3A), a second current meter (8A), a second voltage meter (9A), a DC / DC converter (7A).
Con el primer medidor de voltaje (9A) con velocidad de lectura en intervalos entre 1 ps y 10 ps dispuesto operativamente en el EDFC (2) y con el primer medidor de corriente (8A) con velocidad de lectura en intervalos entre \ us y 1 us dispuesto operativamente en el EDFC (2), se toman valores de voltaje del EDFC (2) y con la unidad de cómputo (11A) se controla la señal de PWM del conversor DC/DC para carga y descarga del EDLC (2). With the first voltage meter (9A) with read speed in intervals between 1 ps and 10 ps operatively arranged in the EDFC (2) and with the first current meter (8A) with read speed in intervals between \ us and 1 us operatively arranged in the EDFC (2), voltage values of the EDFC (2) are taken and with the computing unit (11A) the PWM signal of the DC / DC converter is controlled for loading and unloading the EDLC (2).
La unidad de cómputo (11A) con base en las señales del primer medidor de voltaje (9A) y del primer medidor de corriente (8A) controla el conversor DC/DC (7A) para compensar la tensión en corriente directa.  The computing unit (11A) based on the signals of the first voltage meter (9A) and the first current meter (8A) controls the DC / DC converter (7A) to compensate for the direct current voltage.
Haciendo referencia a la FIG. 2, en una modalidad de la invención el dispositivo divulgado el dispositivo de arranque suave (3 A) en un ejemplo, conformado por dos etapas de filtrado de frecuencia, un primer filtro comprende una resistencia en paralelo a un condensador de enlace y la segunda etapa una resistencia conectada en serie con un condensador, la primera etapa conectada en paralelo con la segunda etapa.  Referring to FIG. 2, in one embodiment of the invention the device disclosed the soft start device (3 A) in an example, consisting of two stages of frequency filtering, a first filter comprises a resistance parallel to a link capacitor and the second stage a resistor connected in series with a capacitor, the first stage connected in parallel with the second stage.
En una modalidad de la invención el conversor DC/DC (7A) está conectado a un dispositivo de arranque suave (3 A) y la unidad de cómputo (11 A) conectada al dispositivo de arranque suave (3A).  In one embodiment of the invention, the DC / DC converter (7A) is connected to a soft start device (3 A) and the computing unit (11 A) connected to the soft start device (3A).
Opcionalmente en una modalidad de la presente invención el conversor DC/DC (7A) está conectado a un dispositivo de arranque suave (3A); una unidad de protección y control (26) con una entrada de potencia y una salida de potencia, el dispositivo de arranque suave (3 A) conectado a la salida de la unidad de protección y control (26) y a la unidad de cómputo (11A); la unidad de protección y control (26) conectada a la unidad de cómputo (11A).  Optionally in one embodiment of the present invention the DC / DC converter (7A) is connected to a soft start device (3A); a protection and control unit (26) with a power input and a power output, the soft start device (3 A) connected to the output of the protection and control unit (26) and the computing unit (11A ); the protection and control unit (26) connected to the computing unit (11A).
Haciendo referencia a la FIG. 2, en una modalidad de la presente invención el dispositivo divulgado se conecta a una fuente de tensión de CD (10A) que conecta a una unidad de protección y control (26) a la cual se le mide el voltaje a su salida utilizando un primer medidor de voltaje (9A) y la corriente con un primer medidor de corriente (8A).  Referring to FIG. 2, in one embodiment of the present invention the disclosed device is connected to a DC voltage source (10A) that connects to a protection and control unit (26) to which the voltage at its output is measured using a first voltage meter (9A) and current with a first current meter (8A).
Alternativamente, en una modalidad de la presente invención, la unidad de protección y control (26) está conectada operativamente en su salida de potencia un segundo medidor de voltaje (4A) con velocidad de lectura en intervalos entre l/rs y lO/rs y un segundo medidor de corriente (5 A) con velocidad de lectura en intervalos entre l/rs y 1 Ow.v: la unidad de cómputo ( 11 A) está conectada al segundo medidor de voltaje (4A) y al segundo medidor de corriente (5A).  Alternatively, in one embodiment of the present invention, the protection and control unit (26) is operatively connected at its power output a second voltage meter (4A) with read speed in intervals between l / rs and lO / rs and a second current meter (5 A) with read speed in intervals between l / rs and 1 Ow.v: the computing unit (11 A) is connected to the second voltage meter (4A) and the second current meter ( 5A).
Opcionalmente en otro ejemplo de la presente invención el conversor DC/DC (7A) está conectado a un acondicionador de fuente (6A); un dispositivo de arranque suave (3A) está conectado al acondicionador de fuente (6A) y a la unidad de cómputo (11 A); una unidad de protección y control (26) está conectada al dispositivo de arranque suave (3 A), al acondicionador de fuente (6A) y a la unidad de cómputo (11 A); un segundo medidor de voltaje (4A) dispuesto operativamente en la unidad de protección y control (26) y está conectado a la unidad de cómputo (11 A); un segundo medidor de comente (5A) dispuesto operativamente entre la unidad de protección y control (26) y el acondicionador de fuente (6A) y está conectado a la unidad de cómputo (11A). Optionally in another example of the present invention the DC / DC converter (7A) is connected to a source conditioner (6A); a soft start device (3A) is connected to the source conditioner (6A) and the computing unit (11 A); a protection and control unit (26) is connected to the soft start device (3 A), the source conditioner (6A) and the computing unit (11 A); a second voltage meter (4A) operatively disposed in the protection and control unit (26) and is connected to the computing unit (11 A); a second comment meter (5A) operatively disposed between the protection and control unit (26) and the source conditioner (6A) and is connected to the computing unit (11A).
Haciendo referencia a la FIG. 2, la señal de voltaje del primer medidor de voltaje (4 A) tiene un aislamiento de 6kV y se conecta a la unidad de cómputo (11A). El aislamiento permite que la señal viaje hasta donde está localizada la unidad de cómputo ( 11 A) sin interferencia de señales extemas, que en un ejemplo está a 100 metros de distancia. Haciendo referencia a la FIG. 2, en una modalidad la presente invención tiene un acondicionador de fuente (6A) que comprende filtros de frecuencia activos y filtros de frecuencia pasivos, filtros de frecuencia paso-bajo (LPF), filtros de frecuencia paso-alto (HPF), filtros paso bando y combinaciones de los anteriores.  Referring to FIG. 2, the voltage signal of the first voltage meter (4 A) is 6kV isolated and is connected to the computing unit (11A). The isolation allows the signal to travel to where the computing unit (11 A) is located without interference from external signals, which in one example is 100 meters away. Referring to FIG. 2, in one embodiment the present invention has a source conditioner (6A) comprising active frequency filters and passive frequency filters, low-pass frequency filters (LPF), high-pass frequency filters (HPF), pass filters side and combinations of the above.
En una modalidad de la presente invención el conversor DC/DC (7A) está conectado a un acondicionador de fuente (6A) y el primer medidor de corriente (8A) conectado al acondicionador de fuente (6A).  In one embodiment of the present invention the DC / DC converter (7A) is connected to a source conditioner (6A) and the first current meter (8A) connected to the source conditioner (6A).
Haciendo referencia a la FIG. 1 y FIG. 2, en un ejemplo, la primera señal de voltaje (30) del primer medidor de voltaje tiene un aislamiento dieléctrico de 6 kV, respecto del sistema eléctrico de la línea de transmisión y se conecta a la unidad de cómputo ( 11 A) no ilustrada en la FIG. 1 pero sí en la FIG. 2.  Referring to FIG. 1 and FIG. 2, in one example, the first voltage signal (30) of the first voltage meter has a dielectric isolation of 6 kV, with respect to the electrical system of the transmission line and is connected to the computing unit (11 A) not illustrated in FIG. 1 but yes in FIG. two.
Para el entendimiento del método que se implementa en la presente invención y mostrado en las figuras de la FIG. 3 a la FIG.10 se utiliza la siguiente nomenclatura: For the understanding of the method that is implemented in the present invention and shown in the figures of FIG. 3 to FIG. 10 the following nomenclature is used:
• Vc: Voltaje del almacenamiento • V c : Storage voltage
• Vcmax: Voltaje máximo del sistema de almacenamiento • V cmax : Maximum storage system voltage
• Vop: Voltaje nominal de operación del sistema • V op : Nominal system operating voltage
• Imaxop· corriente máxima de operación • I maxop · maximum operating current
• PWM: Ciclo de encendido y apagado de los sistemas de potencia.  • PWM: On and off cycle of power systems.
• It: variable medida en el instante. Por ejemplo, corriente • I t : variable measured in the instant. For example, current
• It-i : variable medida en el instante anterior. • I ti : variable measured in the previous instant.
• It-N: variable más antigua registrada. • I tN : oldest variable recorded.
• N: Numero de datos en el registro.  • N: Number of data in the register.
• Icargamin: Corriente mínima de carga • I load : Minimum load current
• !ø: corriente instantánea de carga del elemento de alta densidad EDLC El método de la presente invención está implementado en una unidad de cómputo•! Ø: instantaneous load current of the high density element EDLC The method of the present invention is implemented in a computing unit
(HA). (HE HAS).
Haciendo referencia a la FIG. 3, en un ejemplo el método tiene una etapa de standby (34), donde el sistema está en reposo, esperando una señal de inicio la cual proviene de un switch, un pulsador, una unidad de control o estar previamente programada.  Referring to FIG. 3, in one example the method has a standby stage (34), where the system is at rest, waiting for a start signal which comes from a switch, a push button, a control unit or to be previously programmed.
Haciendo referencia a la FIG. 3 y FIG. 5, en una modalidad el método divulgado en la presente invención tiene una etapa de setup (35), donde el sistema cierra las protecciones (50) del circuito al cual se conecta el conversor DC/DC. Fuego de cerrar dichas protecciones (50) el sistema verifica que el voltaje de almacenamiento del elemento de alta densidad EDFC (2) sea mayor que el voltaje mínimo de la línea (51). Si el voltaje de almacenamiento del elemento de alta densidad EDFC es mayor que el voltaje mínimo de la línea (51), se verifica que la corriente de almacenamiento sea menor que 3 amps (52). Si la corriente de almacenamiento es menor que 3 amps (52), se entra en un estado de precarga (36), sino se pasa al estado de standby (34). Si el voltaje de almacenamiento del elemento de alta densidad EDFC no es mayor que el voltaje mínimo de la línea (51), se entra en el estado de standby (34).  Referring to FIG. 3 and FIG. 5, in one embodiment the method disclosed in the present invention has a setup stage (35), where the system closes the protections (50) of the circuit to which the DC / DC converter is connected. When closing said protections (50), the system verifies that the storage voltage of the high-density EDFC element (2) is greater than the minimum line voltage (51). If the storage voltage of the EDFC high density element is greater than the minimum line voltage (51), it is verified that the storage current is less than 3 amps (52). If the storage current is less than 3 amps (52), it enters a preload state (36), but goes to the standby state (34). If the storage voltage of the EDFC high density element is not greater than the minimum line voltage (51), the standby state (34) is entered.
Haciendo referencia a la FIG. 3 y FIG. 6, en una modalidad el método divulgado en la presente invención tiene una etapa de precarga (36), donde el sistema verifica si el voltaje de carga del elemento de alta densidad EDFC es igual al voltaje mínimo de almacenamiento del elemento de alta densidad EDFC (53), donde el voltaje mínimo de almacenamiento del elemento de alta densidad EDFC es igual al 10% del voltaje de operación del EDFC. Si el voltaje de carga del elemento de alta densidad EDFC es igual al voltaje mínimo de almacenamiento del elemento de alta densidad EDFC (53), en una etapa de conexión se conecta una impedancia resistiva para generar una precarga del elemento de alta densidad EDFC (37).  Referring to FIG. 3 and FIG. 6, in one embodiment the method disclosed in the present invention has a preload stage (36), where the system verifies if the charge voltage of the high density element EDFC is equal to the minimum storage voltage of the high density element EDFC ( 53), where the minimum storage voltage of the EDFC high density element is equal to 10% of the EDFC operating voltage. If the load voltage of the high-density EDFC element is equal to the minimum storage voltage of the high-density EDFC element (53), a resistive impedance is connected at a connection stage to generate a pre-load of the high-density EDFC element (37 ).
En una modalidad de la presente invención el método en una etapa de conexión (37) se espera a que el voltaje de almacenamiento del elemento de alta densidad EDFC sea igual al voltaje de operación del elemento de alta densidad EDFC más o menos el 5% (58). Cuando el voltaje de almacenamiento del elemento de alta densidad EDFC es igual al voltaje de operación del elemento de alta densidad EDFC más o menos el 5% (58), se desconecta la impedancia resistiva (59) que se había conectado para generar la precarga y se entra en un estado de idle (39). Al salir del estado de idle (39) se entra en el estado de inicio rápido (60). Si el voltaje de carga del elemento de alta densidad EDLC no es igual al voltaje mínimo de almacenamiento del elemento de alta densidad EDLC (53), el sistema verifica si la corriente de carga del elemento de alta densidad EDLC es menor a la corriente mínima de carga del elemento de alta densidad EDLC (54), donde la corriente mínima de carga del elemento de alta densidad EDLC es igual al 5% de la corriente máxima de operación. Si la corriente de carga del elemento de alta densidad EDLC es menor a la corriente mínima de carga del elemento de alta densidad EDLC (54), la señal de PWM de carga del elemento de alta densidad EDLC aumenta el ancho de pulso (56). In one embodiment of the present invention, the method in a connection stage (37) is expected so that the storage voltage of the high-density element EDFC is equal to the operating voltage of the high-density element EDFC plus or minus 5% ( 58). When the storage voltage of the high density EDFC element is equal to the operating voltage of the high density EDFC element plus or minus 5% (58), the resistive impedance (59) that was connected to generate the preload is disconnected and you enter an idle state (39). Upon exiting the idle state (39), the quick start state (60) is entered. If the charging voltage of the high density element EDLC is not equal to the minimum storage voltage of the high density element EDLC (53), the system checks whether the charging current of the high density element EDLC is less than the minimum current of EDLC high density element load (54), where the minimum load current of the EDLC high density element is equal to 5% of the maximum operating current. If the load current of the high density element EDLC is less than the minimum load current of the high density element EDLC (54), the load PWM signal of the high density element EDLC increases the pulse width (56).
Si la corriente de carga del elemento de alta densidad EDLC no es menor que la corriente mínima de carga del elemento de alta densidad EDLC (54), se aumenta el ancho de pulso del PWM de carga del elemento de alta densidad EDLC (56), se verifica si la corriente de carga del elemento de alta densidad EDLC es mayor que la corriente mínima de carga del elemento de alta densidad EDLC (55).  If the load current of the high density element EDLC is not less than the minimum load current of the high density element EDLC (54), the pulse width of the load PWM of the high density element EDLC (56) is increased, it is checked if the load current of the high density element EDLC is greater than the minimum load current of the high density element EDLC (55).
Si la corriente del elemento de alta densidad EDLC es mayor que la corriente mínima de carga del elemento de alta densidad EDLC (55), se disminuye el ancho de pulso del PWM de carga del elemento de alta densidad EDLC (57).  If the current of the high density element EDLC is greater than the minimum load current of the high density element EDLC (55), the pulse width of the load PWM of the high density element EDLC (57) is decreased.
Si la corriente de carga del elemento de alta densidad EDLC no es mayor que la corriente de carga del elemento de alta densidad EDLC (55) se disminuye el ancho de pulso del elemento de alta densidad EDLC (57), se inicia nuevamente el proceso desde verificar si el voltaje de carga del elemento de alta densidad EDLC es igual al voltaje mínimo de almacenamiento del elemento de alta densidad EDLC (53).  If the load current of the high density element EDLC is not greater than the load current of the high density element EDLC (55) the pulse width of the high density element EDLC (57) is decreased, the process is started again from Check if the charging voltage of the high density element EDLC is equal to the minimum storage voltage of the high density element EDLC (53).
Haciendo referencia a la FIG. 7, el método divulgado en la presente invención tiene una etapa de idle (39) en donde el sistema verifica que el voltaje de almacenamiento del elemento de alta densidad EDLC sea menor que el 95% del voltaje de operación del elemento de alta densidad EDLC (61). Si el voltaje de almacenamiento del elemento de alta densidad EDLC es menor que el 95% al voltaje de operación del elemento de alta densidad EDLC (61), se entra en un estado o etapa de inicio rápido (60).  Referring to FIG. 7, the method disclosed in the present invention has an idle step (39) in which the system verifies that the storage voltage of the high density element EDLC is less than 95% of the operating voltage of the high density element EDLC ( 61). If the storage voltage of the high-density element EDLC is less than 95% to the operating voltage of the high-density element EDLC (61), a state or stage of rapid onset (60) is entered.
Si el voltaje de almacenamiento del elemento de alta densidad EDLC no es menor que el 95% del voltaje de operación del elemento de alta densidad EDLC (61), el sistema verifica si el voltaje de almacenamiento del elemento de alta densidad EDLC es mayor al 105% del voltaje de operación del elemento de alta densidad EDLC (62). Si el voltaje de almacenamiento del elemento de alta densidad EDLC es mayor al 105% voltaje de operación del elemento de alta densidad EDLC (63), se entra en el estado de inicio rápido (60). Si el voltaje de almacenamiento del elemento de alta densidad EDLC no es mayor al 105% del voltaje de operación del elemento de alta densidad EDLC (62), se verifica si hay una condición de detención del sistema de manera local o remota (63). Si hay una condición de detención en el sistema de manera local o remota (63), se entra en el estado de desconexión (41). Si no hay una condición de detención en el sistema de manera local o remota (63), se repite el proceso desde el verificar si el voltaje de almacenamiento del elemento de alta densidad EDLC es menor al 95% del voltaje de operación del elemento de alta densidad EDLC (61). If the storage voltage of the high density element EDLC is not less than 95% of the operating voltage of the high density element EDLC (61), the system checks whether the storage voltage of the high density element EDLC is greater than 105 % of the operating voltage of the high density element EDLC (62). If the storage voltage of the high density element EDLC is greater than 105% operating voltage of the high density element EDLC (63), the quick start state (60) is entered. If the storage voltage of the high density element EDLC is not greater than 105% of the operating voltage of the high density element EDLC (62), it is checked whether there is a system stop condition locally or remotely (63). If there is a stop condition in the system locally or remotely (63), the disconnection state (41) is entered. If there is no stop condition in the system locally or remotely (63), the process is repeated from verifying if the storage voltage of the high density element EDLC is less than 95% of the operating voltage of the high element EDLC density (61).
Haciendo referencia a la FIG. 8, el método divulgado en la presente invención tiene una etapa de inicio rápido (60) donde el sistema verifica si el cambio de la corriente del elemento de alta densidad EDLC es mayor que el máximo cambio del elemento de alta densidad EDLC (64), donde el cambio máximo en la corriente del elemento de alta densidad EDLC es igual al 10% de corriente máxima del elemento de alta densidad EDLC (2). Si el cambio en la corriente del elemento de alta densidad EDLC es mayor al cambio máximo en la corriente del elemento de alta densidad EDLC (64), el sistema entra en una etapa o estado de desconexión (41).  Referring to FIG. 8, the method disclosed in the present invention has a rapid start stage (60) where the system verifies whether the change in the current of the high density element EDLC is greater than the maximum change of the high density element EDLC (64), where the maximum change in the current of the high density element EDLC is equal to 10% of the maximum current of the high density element EDLC (2). If the change in the current of the high density element EDLC is greater than the maximum change in the current of the high density element EDLC (64), the system enters a stage or disconnection state (41).
Si el cambio en la corriente del elemento de alta densidad EDLC no es mayor al cambio máximo en la corriente del elemento de alta densidad EDLC (64), se verifica si el cambio en el voltaje de almacenamiento del elemento de alta densidad EDLC es mayor que el cambio máximo en el voltaje de almacenamiento del elemento de alta densidad EDLC (65), donde el cambio máximo en el voltaje de almacenamiento del elemento de alta densidad EDLC está dado por el 5% del voltaje máximo del elemento de alta densidad EDLC.  If the change in the current of the high density element EDLC is not greater than the maximum change in the current of the high density element EDLC (64), it is verified if the change in the storage voltage of the high density element EDLC is greater than the maximum change in the storage voltage of the high density element EDLC (65), where the maximum change in the storage voltage of the high density element EDLC is given by 5% of the maximum voltage of the high density element EDLC.
Si el cambio en el voltaje de almacenamiento del elemento de alta densidad EDLC es mayor que el cambio máximo en el voltaje de almacenamiento del elemento de alta densidad EDLC (65), se entre en el estado de desconexión (41). Si el cambio en el voltaje de almacenamiento del elemento de alta densidad EDLC no es mayor que el cambio máximo del voltaje de almacenamiento del elemento de alta densidad EDLC (65), se verifica si la corriente de almacenamiento del elemento de alta densidad EDLC es menor que el 90% de la corriente máxima de operación del elemento de alta densidad EDLC (66). Si la corriente de almacenamiento del elemento de alta densidad EDLC es menor que el 90% de la corriente máxima de operación del elemento de alta densidad EDLC (66) el dispositivo pasa a modo Buck o Boost (38). Si la comente de almacenamiento del elemento de alta densidad EDLC no es menor que el 90% de la comente máxima de operación del elemento de alta densidad EDLC (66), se pregunta si el sistema está en forma de Boost (40). Si el sistema está en forma de Boost (40), se verifica que la medida instantánea de la variable, en este caso la comente es menor que 10 (67), donde 10 es aproximadamente igual a cero, durante un tiempo dado por 10 veces más el número de datos en un instante de tiempo, donde el número de datos en un instante de tiempo es menor a la mitad del periodo de la señal de PWM. Esta condición se denomina para la presente invención como“cond”. If the change in the storage voltage of the high-density element EDLC is greater than the maximum change in the storage voltage of the high-density element EDLC (65), the disconnection state (41) is entered. If the change in the storage voltage of the high density element EDLC is not greater than the maximum change in the storage voltage of the high density element EDLC (65), it is checked whether the storage current of the high density element EDLC is smaller than 90% of the maximum operating current of the high density element EDLC (66). If the storage current of the high density element EDLC is less than 90% of the maximum operating current of the high density element EDLC (66) the device goes to Buck or Boost mode (38). If the storage comment of the high density element EDLC is not less than 90% of the maximum operating comment of the high density element EDLC (66), it is asked whether the system is in the form of a Boost (40). If the system is in the form of Boost (40), it is verified that the instantaneous measurement of the variable, in this case the comment is less than 1 0 (67), where 1 0 is approximately equal to zero, during a given time by 10 times the number of data in an instant of time, where the number of data in an instant of time is less than half the period of the PWM signal. This condition is referred to as "cond" for the present invention.
Si durante este tiempo, la medida de la comente no es menor que i© (67) se entra en el estado de desconexión (41). Si durante este tiempo, la medida de la comente es menor que i© (41) o si el sistema no es Boost (40), se repite el proceso desde verificar que el cambio en la corriente del elemento de alta densidad EDLC es mayor al cambio máximo de la comente del elemento de alta densidad EDLC (64). If during this time, the measurement of the comment is not less than i © (67), it enters the disconnection state (41). If during this time, the measurement of the comment is less than i © (41) or if the system is not Boost (40), the process is repeated from verifying that the change in the current of the high density element EDLC is greater than maximum change of the EDLC high density element comment (64).
Haciendo referencia a las FIG. 9, el método divulgado en la presente invención tiene una etapa de desconexión (41), donde el sistema espera que el voltaje de almacenamiento del elemento de alta densidad EDLC sea igual al 10% del voltaje de operación del elemento de alta densidad EDLC (69), cuando el voltaje de almacenamiento del EDLC sea igual al 10% del voltaje de operación del elemento de alta densidad EDLC (69), el sistema entra en el estado de standby (34).  Referring to FIG. 9, the method disclosed in the present invention has a disconnection stage (41), where the system expects the storage voltage of the high density element EDLC to be equal to 10% of the operating voltage of the high density element EDLC (69 ), when the storage voltage of the EDLC is equal to 10% of the operating voltage of the high density element EDLC (69), the system enters the standby state (34).
Alternativamente, el método de la presente invención tiene una etapa de conexión (37) en la que se espera a que la tensión de línea sea igual a un valor de más o menos el 5% del voltaje de operación del elemento de alta densidad EDLC (58) para quitar una resistencia de carga (59) y pasar a un estado de idle (39) Alternatively, the method of the present invention has a connection stage (37) in which the line voltage is expected to be equal to a value of plus or minus 5% of the operating voltage of the high density element EDLC ( 58) to remove a load resistor (59) and enter an idle state (39)
Haciendo referencia a las FIG. 10, el método divulgado en la presente invención tiene un modo de Buck o Boost (38), donde el sistema verifica si está en modo Boost (40). Si el sistema está en modo Boost (40), se verifica si el voltaje de almacenamiento del elemento de alta densidad EDLC es mayor que el 20% del voltaje de operación del elemento de alta densidad EDLC (69). Si el voltaje de almacenamiento del elemento de alta densidad EDLC es mayor que el voltaje de operación del elemento de alta densidad EDLC (69), el sistema verifica que el voltaje de almacenamiento del elemento de alta densidad EDLC sea menor que el 90% del voltaje de operación del elemento de alta densidad EDLC (74).  Referring to FIG. 10, the method disclosed in the present invention has a Buck or Boost mode (38), where the system checks if it is in Boost mode (40). If the system is in Boost mode (40), it is checked whether the storage voltage of the high density element EDLC is greater than 20% of the operating voltage of the high density element EDLC (69). If the storage voltage of the high density element EDLC is greater than the operating voltage of the high density element EDLC (69), the system verifies that the storage voltage of the high density element EDLC is less than 90% of the voltage of operation of the high density element EDLC (74).
Si el voltaje de almacenamiento del elemento de alta densidad EDLC no es mayor a 20% del voltaje de operación del elemento de alta densidad EDLC (69), se regresa el sistema al inicio (79). Cuando se regresa el sistema baja la comente (78) aplicando una rampa con duración inferior a un segundo a un régimen entre 300 V/s y 900 V/s y entra en el estado de idle (39). If the storage voltage of the high density element EDLC is not greater than 20% of the operating voltage of the high density element EDLC (69), the system at startup (79). When the system is returned, lower the comment (78) by applying a ramp that lasts less than one second at a rate between 300 V / s and 900 V / s and enters the idle state (39).
Si el voltaje de almacenamiento del elemento de alta densidad EDLC es menor al 90% del voltaje de operación del elemento de alta densidad EDLC (74), se verifica la condición denominada“cond” (75).  If the storage voltage of the high density element EDLC is less than 90% of the operating voltage of the high density element EDLC (74), the condition called "cond" (75) is verified.
Si el voltaje de almacenamiento del elemento de alta densidad EDLC no es menor a 90% del voltaje de operación del elemento de alta densidad EDLC, se regresa el sistema al inicio (79). Cuando se regresa el sistema baja la corriente (78) aplicando una rampa con duración inferior a un segundo a un régimen entre 300 V/s y 900 V/s y entra en el estado de idle (39).  If the storage voltage of the high density element EDLC is not less than 90% of the operating voltage of the high density element EDLC, the system is returned to the start (79). When the system is returned, it lowers the current (78) by applying a ramp that lasts less than one second at a rate between 300 V / s and 900 V / s and enters the idle state (39).
Si la condición“cond” no se cumple, la señal de PWM se disminuye con una rampa de control (76). Si la condición“cond” se cumple (75) o la señal de PWM disminuye (76), se verifica si la corriente promedio de las mediciones de la corriente del elemento de alta densidad EDLC es menor que la corriente máxima de operación del elemento de alta densidad EDLC (73).  If the “cond” condition is not met, the PWM signal is decreased with a control ramp (76). If the “cond” condition is met (75) or the PWM signal decreases (76), it is checked if the average current of the EDLC high density element current measurements is less than the maximum operating current of the element high density EDLC (73).
Si la corriente promedio de las mediciones de la corriente del elemento de alta densidad EDLC es menor que la corriente máxima de operación del elemento de alta densidad EDLC (73), la señal de PWM se aumenta con una rampa de control (77). Si la corriente promedio de las mediciones de la corriente del elemento de alta densidad EDLC no es menor (73) o la señal de PWM se aumenta con una rampa de control (77), se regresa a verificar si el dispositivo está en modo Boost (40).  If the average current of the EDLC high density element current measurements is less than the maximum operating current of the EDLC high density element (73), the PWM signal is increased with a control ramp (77). If the average current of the EDLC high density element current measurements is not lower (73) or the PWM signal is increased with a control ramp (77), it is checked again if the device is in Boost mode ( 40).
Si el dispositivo no está en modo Boost (40), se verifica si el voltaje de almacenamiento del elemento de alta densidad EDLC es menor que el 90% del voltaje máximo de almacenamiento del elemento de alta densidad EDLC (70). Si el voltaje de almacenamiento del elemento de alta densidad EDLC es menor a 90% del voltaje de operación del elemento de alta densidad EDLC (70), se regresa el sistema al inicio (79). Cuando se regresa el sistema baja la corriente (78) aplicando una rampa con duración inferior a un segundo a un régimen entre 300 V/s y 900 V/s y entra en el estado de idle (39).  If the device is not in Boost mode (40), it is checked whether the storage voltage of the high density element EDLC is less than 90% of the maximum storage voltage of the high density element EDLC (70). If the storage voltage of the high density element EDLC is less than 90% of the operating voltage of the high density element EDLC (70), the system is returned to the start (79). When the system is returned, it lowers the current (78) by applying a ramp that lasts less than one second at a rate between 300 V / s and 900 V / s and enters the idle state (39).
Si el voltaje de almacenamiento del elemento de alta densidad EDLC no es menor que el 90% del voltaje máximo de almacenamiento del elemento de alta densidad EDLC (70), se verifica si el voltaje de almacenamiento del elemento de alta densidad EDLC es mayor que el voltaje de operación del elemento de alta densidad EDLC (71). Si el voltaje de almacenamiento del elemento de alta densidad EDLC no es mayor que el voltaje de operación del elemento de alta densidad EDLC (71), se regresa el sistema al inicio (79). Cuando se regresa el sistema baja la comente (78) aplicando una rampa con duración inferior a un segundo a un régimen entre 300 V/s y 900 V/s y entra en el estado de idle (39). Si el voltaje de almacenamiento del elemento de alta densidad EDLC es mayor que el voltaje de operación del elemento de alta densidad EDLC (71), se verifica si la corriente promedio de las mediciones de la corriente del elemento de alta densidad EDLC es mayor que la corriente máxima de operación del elemento de alta densidad EDLC (72). If the storage voltage of the high density element EDLC is not less than 90% of the maximum storage voltage of the high density element EDLC (70), it is checked whether the storage voltage of the high density element EDLC is greater than the EDLC high density element operating voltage (71). If the storage voltage of the high density element EDLC is not greater than the operating voltage of the high density element EDLC (71), the system is returned to the start (79). When the system is returned, lower the comment (78) by applying a ramp that lasts less than one second at a rate between 300 V / s and 900 V / s and enters the idle state (39). If the storage voltage of the high density element EDLC is greater than the operating voltage of the high density element EDLC (71), it is checked whether the average current of the measurements of the current of the high density element EDLC is greater than the maximum operating current of the high density element EDLC (72).
Si la corriente promedio de las mediciones de corriente del elemento de alta densidad EDLC es mayor que la corriente máxima de operación del elemento de alta densidad EDLC (72), la señal de PWM se disminuye con una rampa de control (76). Si la corriente promedio de las mediciones de corriente del elemento de alta densidad EDLC no es mayor que la corriente de operación (72) o la señal de PWM se disminuye con una rampa de control (76), se verifica si la corriente promedio de medición de corriente del elemento de alta densidad EDLC es menor que la corriente máxima de operación del elemento de alta densidad EDLC (73).  If the average current of the current measurements of the high density element EDLC is greater than the maximum operating current of the high density element EDLC (72), the PWM signal is decreased with a control ramp (76). If the average current of the EDLC high-density element current measurements is not greater than the operating current (72) or the PWM signal is decreased with a control ramp (76), it is checked whether the average measurement current Current of the high density element EDLC is less than the maximum operating current of the high density element EDLC (73).
Si la corriente promedio de las mediciones de la corriente del elemento de alta densidad EDLC es menor que la corriente máxima de operación del elemento de alta densidad EDLC (73), la señal de PWM se aumenta con una rampa de control (77). Si la corriente promedio de las mediciones de la corriente del elemento de alta densidad EDLC no es menor (73) o la señal de PWM se aumenta con una rampa de control (77), se regresa a verificar si el dispositivo está en modo Boost (40).  If the average current of the EDLC high density element current measurements is less than the maximum operating current of the EDLC high density element (73), the PWM signal is increased with a control ramp (77). If the average current of the EDLC high density element current measurements is not lower (73) or the PWM signal is increased with a control ramp (77), it is checked again if the device is in Boost mode ( 40).
El dispositivo de la presente invención toma medidas periódicamente de la siguiente manera como se describe a continuación.  The device of the present invention periodically measures in the following manner as described below.
Haciendo referencia a las FIG. 4, el método divulgado en la presente invención tiene toma una nueva medida de la corriente instantánea (44). Cuando se toma una nueva medida de la corriente instantánea (44), se realiza el cálculo de un delta de la corriente instantánea (45).  Referring to FIG. 4, the method disclosed in the present invention has a new measurement of instantaneous current (44). When a new measurement of the instantaneous current (44) is taken, the calculation of a delta of the instantaneous current (45) is performed.
Para el entendimiento de la presente invención, entiéndase delta como el cambio realizado de una medida a otra. El delta de la corriente instantánea se calcula como la nueva medida de corriente instantánea menos la medida anterior de la corriente instantánea (45). Al calcular el delta de las medidas de comente instantánea (45), se actualiza la comente promedio de la comente del elemento de alta densidad EDLC (46) quitando la medida de comente instantánea más antigua del vector donde se guardan todas la medidas de comente dividido por 2N (46) donde N es el número total de datos. Por ejemplo N es un número natural entre 1 y 1000. For the understanding of the present invention, delta is understood as the change made from one measure to another. The instantaneous current delta is calculated as the new instantaneous current measurement minus the previous instantaneous current measurement (45). When calculating the delta of the instantaneous comment measurements (45), the average comment of the comment of the high density element EDLC (46) is updated by removing the oldest instantaneous comment measure of the vector where all the divided comment measurements are saved by 2 N (46) where N is the total number of data. For example N is a natural number between 1 and 1000.
Cuando se actualiza la comente promedio de la medida de la comente del elemento de alta densidad EDLC (46), se reorganiza el vector donde se guardan las medidas de comente instantánea, quitando la medición más antigua (47). Cuando se reorganiza el vector donde se guardan las medidas (47), se actualiza nuevamente la comente promedio de las medidas de comente del elemento de alta densidad EDLC añadiendo la medida más nueva de la comente instantánea dividido por 2N, donde N es el número total de datos (48). Por ejemplo N es un número natural entre 1 y 1000. When the average comment of the comment of the EDLC high density element (46) is updated, the vector where the instantaneous comment measurements are saved is reorganized, removing the oldest measurement (47). When the vector where the measurements are stored is reorganized (47), the average comment of the comments of the high-density element EDLC is updated again by adding the newest measure of the instantaneous comment divided by 2 N , where N is the number total data (48). For example N is a natural number between 1 and 1000.
Después de actualizar la comente promedio de las medidas de comente del elemento de alta densidad EDLC (48), se regresa (49) al inicio del proceso donde se toma una nueva medida (44).  After updating the average comment of the comments of the high density element EDLC (48), it is returned (49) at the beginning of the process where a new measurement is taken (44).
Este proceso se repite constantemente durante la operación del dispositivo y método de compensación de tensión.  This process is constantly repeated during device operation and voltage compensation method.
Alternativamente, en cada una de las etapas se pasa a una etapa (f) de desconexión si no se cumplen condiciones de seguridad.  Alternatively, in each of the stages a step (f) is switched off if safety conditions are not met.
Para el entendimiento de la presente invención, se entenderá por condiciones de seguridad las condiciones de operación bajo los límites de diseño de cada uno de los elementos del dispositivo de compensación de tensión, por ejemplo, la tensión de línea VL debe estar entre un -5% y +5% del voltaje de operación Vop pre-configurado por un usuario, o límite de comente de operación entre 1 amperio y 200 amperios y los límites establecidos en el método que se describe a continuación. For the understanding of the present invention, safety conditions shall be understood as the operating conditions under the design limits of each of the elements of the voltage compensation device, for example, the line voltage V L must be between a - 5% and + 5% of the operating voltage V op pre-configured by a user, or operating comment limit between 1 ampere and 200 amps and the limits established in the method described below.
A continuación se listan todas las etapas del método de la presente:  Listed below are all stages of the method herein:
• Etapa a. Standby.  • Stage a. Standby
• Etapa b. Setup.  • Stage b. Setup
• Etapa c. Precarga.  • Stage c. Preload
• Etapa d. Conexión.  • Stage d. Connection.
• Etapa e. Idle.  • Stage e. Idle
• Etapa f. Desconexión.  • Stage f. Disconnection
• Etapa g. Inicio rápido.  • Stage g. Quick start.
• Etapa h. Buck/Boost.  • Stage h. Buck / Boost
• Etapa i. Medición. El método para compensación de tensión en comente directa comprende las siguientes etapas: • Stage i. Measurement. The method for direct voltage tension compensation comprises the following steps:
e- verificar que la tensión de línea esté entre un límite inferior de voltaje operación y un límite superior de voltaje de operación pre-configurados por un usuario en un registro de memoria de una unidad de cómputo y pasar a la etapa (g); si la tensión de línea supera dichos límites de voltaje de operación se verifica una condición de detención; e- verify that the line voltage is between a lower operating voltage limit and an upper operating voltage limit pre-configured by a user in a memory register of a computing unit and go to step (g); if the line voltage exceeds these operating voltage limits a stop condition is verified;
g- verificar que la variación de voltaje del EDLC sea inferior a un límite de variación de voltaje del EDLC y que la variación de corriente de carga del EDLC sea inferior a un límite de variación de la corriente de carga del EDLC pre-configurados por un usuario en un registro de memoria de la unidad de cómputo; g- verify that the EDLC voltage variation is less than an EDLC voltage variation limit and that the EDLC load current variation is less than a EDLC load current variation limit pre-configured by a user in a memory register of the computing unit;
si dichas variaciones no superan dichos límites verificar que la corriente de carga del EDLC sea inferior a un límite de corriente de operación del EDLC para controlar conversor DC/DC y verificar modo de funcionamiento del conversor DC/DC, si dichas variaciones superan dichos límites entonces realizar una desconexión; if said variations do not exceed said limits verify that the EDLC load current is lower than an EDLC operating current limit to control DC / DC converter and verify DC / DC converter operation mode, if said variations exceed said limits then make a disconnection;
h- verificar si el modo de funcionamiento del conversor DC/DC es modo Boost; si el modo de funcionamiento del conversor DC/DC es modo Boost, comprobar que el voltaje de carga del EDLC esté en un rango definido por un límite superior de voltaje de operación del EDLC y un límite inferior de voltaje de operación del EDLC pre programados por un usuario en un registro de memoria de la unidad de cómputo y mantener la corriente de carga del EDLC; h- check if the operating mode of the DC / DC converter is Boost mode; If the operating mode of the DC / DC converter is Boost mode, check that the EDLC load voltage is in a range defined by an upper EDLC operating voltage limit and a lower EDLC operating voltage limit preprogrammed by a user in a memory register of the computing unit and maintain the EDLC load current;
i- registrar los cambios de la corriente del EDLC, el voltaje del EDLC y de la línea de tensión, y con base en dichos cambios determinar un diferencial de corriente y voltaje, la unidad de cómputo calcula en cada intervalo un valor promedio de voltaje y corriente con base en valores anteriores y actuales de voltaje y corriente; i- record the changes of the EDLC current, the EDLC voltage and the voltage line, and based on these changes determine a current and voltage differential, the computation unit calculates in each interval an average voltage value and current based on previous and current voltage and current values;
la etapa (i) se ejecuta periódicamente de la etapa (e) a la etapa (h) con un intervalo entre 1 ps y 10 ps independientemente de las otras etapas. stage (i) is periodically executed from stage (e) to stage (h) with an interval between 1 ps and 10 ps regardless of the other stages.
En la etapa (e) el límite inferior de voltaje de operación está definido por un porcentaje desde 90 por ciento al 95 por ciento del voltaje de operación del EDLC y el límite superior de voltaje de operación está definido por un porcentaje desde 90 por ciento al 105 por ciento del voltaje de operación del EDLC.  In step (e) the lower limit of operating voltage is defined by a percentage from 90 percent to 95 percent of the operating voltage of the EDLC and the upper limit of operating voltage is defined by a percentage from 90 percent at 105 percent of the EDLC operating voltage.
En la etapa (g) el límite de variación de voltaje de carga del EDLC está entre 3 por ciento y 7 por ciento, el límite de variación de corriente de carga del EDLC está entre 5 por ciento y 15 por ciento y el límite de comente de operación del EDLC está entre 85 por ciento y 95 por ciento. In step (g) the EDLC charge voltage variation limit is between 3 percent and 7 percent, the EDLC charge current variation limit is between 5 percent and 15 percent and the EDLC operating comment limit is between 85 percent and 95 percent.
En la condición (B) de la etapa (g) el límite de variación de voltaje de carga del EDLC está entre 3 por ciento y 7 por ciento, el límite de variación de corriente de carga del EDLC está entre 5 por ciento y 15 por ciento, el límite de corriente de operación del EDLC está entre 85 por ciento y 95 por ciento.  In condition (B) of step (g) the EDLC charge voltage variation limit is between 3 percent and 7 percent, the EDLC charge current variation limit is between 5 percent and 15 percent percent, the EDLC operating current limit is between 85 percent and 95 percent.
En la condición (D) de la etapa (g) el valor de la corriente del EDLC pre-configurado está en un rango entre 1A y 50A.  In condition (D) of step (g) the pre-configured EDLC current value is in a range between 1A and 50A.
En la condición (A) de la etapa (g) el límite de variación de voltaje del EDLC está entre 3 por ciento y 7 por ciento y el límite de variación de corriente de carga del EDLC está entre 5 por ciento y 15 por ciento.  In condition (A) of step (g) the EDLC voltage variation limit is between 3 percent and 7 percent and the EDLC load current variation limit is between 5 percent and 15 percent.
En la condición (B) de la etapa (g) el valor de la corriente del EDLC pre-configurado está entre 1 A y 50 A.  In condition (B) of step (g) the pre-configured EDLC current value is between 1 A and 50 A.
En la etapa (g) el límite de corriente de operación del EDLC está entre 1 A y 200 A. In step (g) the EDLC operating current limit is between 1 A and 200 A.
En la condición (A) de la etapa (h) el límite superior de voltaje de operación del EDLC está entre 85 por ciento y 95 por ciento y el límite inferior de voltaje de operación del EDLC está entre 15 por ciento y 25 por ciento. In condition (A) of step (h) the upper EDLC operating voltage limit is between 85 percent and 95 percent and the lower EDLC operating voltage limit is between 15 percent and 25 percent.
En la etapa (h) voltaje de carga máximo del EDLC pre-configurado está entre 85 por ciento y 95 por ciento, el voltaje de operación del EDLC está entre 100 V y 1500 V. In step (h) pre-configured EDLC maximum load voltage is between 85 percent and 95 percent, the EDLC operating voltage is between 100 V and 1500 V.
En la etapa (h) el límite inferior es un porcentaje del valor de voltaje de operación del EDLC entre 15 por ciento y 20 por ciento y el límite superior de un porcentaje del valor de voltaje de operación del EDLC entre un 90 por ciento y 95 por ciento. In step (h) the lower limit is a percentage of the EDLC operating voltage value between 15 percent and 20 percent and the upper limit of a percentage of the EDLC operating voltage value between 90 percent and 95 percent.
En la etapa (h) en la condición A, porcentaje pre-configurado del voltaje de carga máximo del EDLC está entre 80 por ciento y 90 por ciento.  In step (h) in condition A, the pre-configured percentage of the maximum charge voltage of the EDLC is between 80 percent and 90 percent.
Opcionalmente después de la etapa (e) se incluye una etapa (f) donde se espera a que el voltaje del EDLC sea igual a un valor pre-configurado por un usuario en un registro de memoria de la unidad de cómputo y pasar a la etapa (a) en la que se espera una señal de inicio de una unidad de cómputo; y en la etapa (e) la verificación de la condición de detención se realiza verificando las siguientes condiciones: condición A- si se presenta un evento de detención pasar a la etapa (f); condición B- si no se presenta un evento de detención repetir la etapa (e);  Optionally after step (e) a stage (f) is included where the EDLC voltage is expected to be equal to a value pre-configured by a user in a memory register of the computing unit and move on to the stage (a) in which a start signal from a computing unit is expected; and in step (e) the verification of the detention condition is carried out by verifying the following conditions: condition A- if an arrest event occurs, go to stage (f); condition B- if a stop event does not occur repeat step (e);
En la etapa (g), dicha verificación se realiza siguiendo estas condiciones:  In step (g), said verification is performed following these conditions:
condición B- si las variaciones de voltaje y corriente del EDLC no superan un límite de variación de voltaje de carga del EDLC ni un límite de variación de corriente de carga del EDLC comparar si la comente de carga del EDLC es inferior a un límite de corriente de operación del EDLC pre -configurados por un usuario en un registro de memoria pasar a la etapa (h); condition B- if the EDLC voltage and current variations do not exceed an EDLC load voltage variation limit or a current variation limit of EDLC load compare if the EDLC load comment is less than an EDLC operating current limit pre-configured by a user in a memory register to go to step (h);
condición C- si la corriente de carga del EDLC es superior al límite de corriente de operación del EDLC pre-configurado por un usuario, comprobar el modo de funcionamiento del conversor DC/DC, si el modo de funcionamiento del conversor DC/DC es modo Boost, y condition C- if the load current of the EDLC is higher than the operating current limit of the EDLC pre-configured by a user, check the operating mode of the DC / DC converter, if the operating mode of the DC / DC converter is mode Boost, and
condición D- si la medida de la corriente de carga del EDLC es menor a un valor de la corriente del EDLC pre-configurado por un usuario en un registro de memoria durante un tiempo dado por un número K veces más un número N de datos en un instante de tiempo Dΐ, donde el número N de datos en un instante Dΐ de tiempo es menor a la mitad del periodo de la señal de PWM; condition D- if the measurement of the EDLC load current is less than a value of the EDLC current pre-configured by a user in a memory register for a given time for a number K times plus a number N of data in an instant of time Dΐ, where the number N of data in an instant Dΐ of time is less than half the period of the PWM signal;
condición F- si el modo de funcionamiento del conversor DC/DC no es modo Boost entonces se repite la etapa (g); condition F- if the operating mode of the DC / DC converter is not Boost mode then step (g) is repeated;
donde la duración del pulso de la señal de PWM está entre 0 ps y 340 ps. where the pulse duration of the PWM signal is between 0 ps and 340 ps.
Alternativamente el método de la presente invención después de la etapa (e) se incluye una etapa (f) donde se espera a que el voltaje del EDLC sea igual a un valor pre- configurado por un usuario en un registro de memoria de la unidad de cómputo y pasar a la etapa (a) en la que se espera una señal de inicio de una unidad de cómputo; antes de la condición B de la etapa (g) se verifica la siguiente condición A- si la variación de voltaje del EDLC supera un límite de variación de voltaje del EDLC o si la variación de corriente del EDLC supera un límite de variación de corriente de carga del EDLC pasar a la etapa (f). Alternatively, the method of the present invention after step (e) includes a step (f) where the EDLC voltage is expected to be equal to a value pre-set by a user in a memory register of the unit of computation and go to step (a) in which a start signal from a computing unit is expected; before condition B of step (g) the following condition A- is verified if the voltage variation of the EDLC exceeds a voltage variation limit of the EDLC or if the current variation of the EDLC exceeds a current variation limit of EDLC load go to step (f).
Opcionalmente el método divulgado en la presente invención después de la condición D de la etapa (g) se verifica la siguiente condición E- si no se cumple la condición D se pasa a la etapa (f), si se cumple la condición D se repite la etapa (g).  Optionally, the method disclosed in the present invention after condition D of step (g) the following condition E- is verified, if condition D is not met, step is passed to step (f), if condition D is met, it is repeated the stage (g).
En otra modalidad de la presente invención en la etapa (h) si el modo de funcionamiento del conversor DC/DC es modo Boost entonces se verifican las siguientes condiciones: In another embodiment of the present invention in step (h) if the operating mode of the DC / DC converter is Boost mode then the following conditions are verified:
B- si la medida de la corriente de carga del EDLC es menor un valor de la corriente del EDLC pre-configurado por un usuario en un registro de memoria durante un tiempo dado por un número K veces más un número N de datos en un instante Dΐ de tiempo, donde el número N de datos en un instante Dΐ de tiempo es menor a la mitad del periodo de la señal de PWM; C- si se cumple la condición B se compara la comente promedio con la comente máxima de operación del EDLC; B- if the measurement of the EDLC load current is less than a value of the EDLC current pre-configured by a user in a memory register for a given time by a number K times plus a number N of data in an instant Dΐ of time, where the number N of data in an instant Dΐ of time is less than half the period of the PWM signal; C- if condition B is met, the average comment is compared with the maximum operating comment of the EDLC;
D- si la comente promedio es menor que la comente máxima de operación del EDLC se incrementa el ciclo útil de la señal PWM del conversor DC/DC y se repite la etapa (h), si la comente promedio es mayor que la comente máxima de operación del EDLC entonces se repite la etapa (h);  D- if the average comment is less than the maximum EDLC operating comment, the useful cycle of the PWM signal of the DC / DC converter is increased and step (h) is repeated, if the average comment is greater than the maximum comment of EDLC operation then step (h) is repeated;
E- si no se cumple de la condición B entonces se disminuye el ciclo útil de la señal de PWM del conversor DC/DC y se compara la comente promedio con la comente máxima de operación del EDLC;  E- if condition B is not fulfilled then the useful cycle of the PWM signal of the DC / DC converter is decreased and the average comment is compared with the maximum operating current of the EDLC;
F- si la comente promedio es menor que la comente máxima de operación del EDLC se incrementa el ciclo útil de la señal PWM del conversor DC/DC y se repite la etapa (h), si la comente promedio es mayor que la comente máxima de operación del EDLC se repite la etapa (h); F- if the average comment is less than the maximum EDLC operating comment, the useful cycle of the PWM signal of the DC / DC converter is increased and step (h) is repeated, if the average comment is greater than the maximum comment of EDLC operation is repeated step (h);
donde la duración del pulso de la señal de PWM está entre 0 ps y 340 ps. where the pulse duration of the PWM signal is between 0 ps and 340 ps.
El valor pre -configurado del voltaje de operación del EDLC en la unidad de cómputo está en el rango de 1 por ciento al 5 por ciento del voltaje de operación del EDLC.The pre-configured value of the operating voltage of the EDLC in the computing unit is in the range of 1 percent to 5 percent of the operating voltage of the EDLC.
El valor pre-configurado de la comente máxima de operación del EDLC en la unidad de cómputo está en el rango de 1 por ciento al 5 por ciento de la comente máxima de operación del EDLC. The pre-configured value of the maximum EDLC operating comment in the computing unit is in the range of 1 percent to 5 percent of the maximum EDLC operating comment.
Alternativamente en un ejemplo de la presente invención antes de la etapa (h) se incluye una etapa (a) en la que se espera una señal de inicio de una unidad de cómputo; en la etapa (h), antes de verificar la condición B se verifica la siguiente condición A- si el voltaje de carga del EDLC no está en el rango definido un límite superior de voltaje de operación del EDLC y un límite inferior de voltaje de operación del EDLC pre- configurados por un usuario en un registro de memoria, se baja la comente aplicando una rampa con duración inferior a un segundo a un régimen entre 300 V/s y 900 V/s y se pasa a la etapa (e); y si el voltaje de carga del EDLC está en del rango definido por dichos límites, entonces se verifica una medida de la comente de carga del EDLC y se verifica la condición B; Alternatively, an example of the present invention prior to step (h) includes a step (a) in which a start signal from a computing unit is expected; in step (h), before checking condition B the following condition A- is verified if the EDLC load voltage is not in the defined range an upper EDLC operating voltage limit and a lower operating voltage limit of the EDLC pre-configured by a user in a memory register, the comment is lowered by applying a ramp lasting less than one second at a rate between 300 V / s and 900 V / s and is passed to step (e); and if the charge voltage of the EDLC is in the range defined by said limits, then a measure of the charge rating of the EDLC is verified and condition B is verified;
Opcionalmente el método de la presente invención en la etapa (h) si el modo de funcionamiento del conversor DC/DC no es modo Boost entonces se realiza la verificación de las siguientes condiciones: Optionally the method of the present invention in step (h) if the operating mode of the DC / DC converter is not Boost mode then the verification of the following conditions is performed:
B- si el voltaje de carga del EDLC no supera un voltaje de carga máximo del EDLC pre-configurado en un registro de memoria entonces se compara si la tensión de línea es mayor que el voltaje de operación del EDLC, si la tensión de línea es mayor que el voltaje de operación del EDLC entonces se compara la comente promedio con la comente máxima de operación del EDLC; y B- if the EDLC load voltage does not exceed a maximum EDLC load voltage pre-configured in a memory register then it is compared if the line voltage is greater than the operating voltage of the EDLC, if the line voltage is greater than the operating voltage of the EDLC then the average comment is compared with the maximum operating comment of the EDLC; Y
C- si la comente promedio es mayor que la comente máxima de operación del EDLC entonces se disminuye el ciclo útil de la señal PWM del conversor DC/DC; y D- si la comente promedio es menor que la comente máxima de operación del EDLC entonces se incrementa el ciclo útil de la señal PWM del conversor DC/DC y se repite la etapa (h);  C- if the average comment is greater than the maximum EDLC operating comment then the useful cycle of the PWM signal of the DC / DC converter is decreased; and D- if the average comment is less than the maximum EDLC operating comment then the useful cycle of the PWM signal of the DC / DC converter is increased and step (h) is repeated;
En una modalidad de la presente invención antes de la etapa (h) se incluye una etapa (a) en la que se espera una señal de inicio de una unidad de cómputo; en la etapa (h) antes de la condición B se incluye la siguiente condición A- comparar el voltaje de carga del EDLC con un voltaje de carga máximo del EDLC pre -configurado por un usuario en un registro de memoria, si el voltaje de carga del EDLC supera dicho límite voltaje entonces se baja la comente aplicando una rampa con duración inferior a un segundo a un régimen entre 300 V/s y 900 V/s y se pasa a la etapa (e);  In one embodiment of the present invention before step (h) a step (a) is included in which a start signal from a computing unit is expected; in step (h) before condition B the following condition is included A- compare the charging voltage of the EDLC with a maximum charging voltage of the EDLC pre-configured by a user in a memory register, if the charging voltage EDLC exceeds this voltage limit, then the comment is lowered by applying a ramp with a duration of less than one second at a rate between 300 V / s and 900 V / s and is passed to step (e);
Alternativamente, en la etapa (h) después de la condición D se incluye la siguiente condición E-si no se cumple la condición B entonces se baja la comente aplicando una rampa con duración inferior a un segundo a un régimen entre 300 V/s y 900 V/s y se pasa a la etapa (e);  Alternatively, in step (h) after condition D the following condition E is included - if condition B is not met then the comment is lowered by applying a ramp lasting less than one second at a rate between 300 V / s and 900 V / s and go to step (e);
Opcionalmente, en el método divulgado en la presente invención, antes de la etapa (e) se incluye una etapa (a) en la que se espera una señal de inicio de una unidad de cómputo para pasar a la etapa (e).  Optionally, in the method disclosed in the present invention, a step (a) is included before step (e) in which a start signal from a computing unit is expected to pass to step (e).
En la etapa (a) la señal de inicio es una señal proveniente de un sensor, un switch táctil, un pulsador, una segunda unidad de cómputo o se encuentra pre-configurada en la unidad de cómputo.  In step (a) the start signal is a signal from a sensor, a touch switch, a push button, a second computing unit or is pre-configured in the computing unit.
Alternativamente en un ejemplo, en el método de la presente invención, antes de la etapa (e) se incluye una etapa (b) para cerrar protecciones en una unidad de protección y control, y verificar que la tensión de línea, la corriente de carga de un EDLC se encuentren en un rango de voltaje y comente pre-configurados por un usuario en un registro de memoria de una unidad de cómputo, si no se encuentran en dicho rango de valores pre-configurados se repite (b), de lo contrario se ejecuta la etapa (e).  Alternatively in one example, in the method of the present invention, a step (b) is included before step (e) to close protections in a protection and control unit, and verify that the line voltage, the load current of an EDLC are in a voltage range and comment pre-configured by a user in a memory register of a computing unit, if they are not in said range of pre-configured values it is repeated (b), otherwise step (e) is executed.
Opcionalmente, la etapa (b) comprende las siguientes sub-etapas: Optionally, step (b) comprises the following sub-stages:
i- cerrar protecciones de la unidad de protección y control; ii- comparar la tensión de línea y el voltaje mínimo de la línea de transmisión pre configurado por un usuario en la unidad de cómputo, si la tensión de línea es menor que el voltaje mínimo de la línea de transmisión repetir la etapa (b), si la tensión de línea es mayor que el voltaje mínimo de la línea de transmisión pasar a la sub etapa (iii); i- close protections of the protection and control unit; ii- compare the line voltage and the minimum voltage of the transmission line pre-configured by a user in the computing unit, if the line voltage is less than the minimum voltage of the transmission line repeat step (b), if the line voltage is greater than the minimum voltage of the transmission line go to the sub stage (iii);
iii- comparar la corriente de almacenamiento del EDLC medida con un medidor de corriente con un valor pre -configurado en la unidad de cómputo, si corriente de almacenamiento del EDLC es mayor que dicho valor pre-configurado repetir la etapa (b) y si corriente de almacenamiento del EDLC es menor que dicho valor pre configurado pasar a la etapa (c); iii- compare the measured EDLC storage current with a current meter with a pre-configured value in the computing unit, if EDLC storage current is greater than said pre-configured value repeat step (b) and if current EDLC storage is less than said pre-configured value move to step (c);
En la sub etapa (ii) de la etapa (b) el valor del voltaje mínimo de la línea de transmisión pre-configurado en la unidad de cómputo está en el rango entre 10 V y 500 V.  In the sub stage (ii) of stage (b) the minimum voltage value of the pre-configured transmission line in the computing unit is in the range between 10 V and 500 V.
En la sub etapa (iii) de la etapa (b) el valor de la corriente de almacenamiento del EDLC pre-configurado en la unidad de cómputo está en el rango entre 1 A y 50 A.  In sub-stage (iii) of stage (b) the value of the pre-configured EDLC storage current in the computing unit is in the range between 1 A and 50 A.
Alternativamente por ejemplo, en el método de la presente invención, antes de la etapa (e) se incluye una etapa (c) para verificar si voltaje del EDLC es igual a un límite inferior de voltaje de operación del EDLC pre-configurado en un registro de memoria y verificar que la corriente de carga sea igual a la corriente de carga mínima, estas verificaciones se hacen siguiendo las siguientes condiciones: Alternatively, for example, in the method of the present invention, a step (c) is included before step (e) to verify if EDLC voltage is equal to a lower EDLC operating voltage limit pre-configured in a register of memory and verify that the load current is equal to the minimum load current, these verifications are made following the following conditions:
condición B- si el voltaje del EDLC es diferente a dicho límite inferior de voltaje de operación del EDLC pre-configurado entonces verificar que la corriente de carga del EDLC se mantenga en un valor de un porcentaje de la corriente máxima de operación del EDLC pre-configurado en un registro de memoria; condition B- if the EDLC voltage is different from said lower EDLC operating voltage limit pre-configured then verify that the EDLC load current is maintained at a value of a percentage of the maximum EDLC operating current pre configured in a memory register;
condición C- si la corriente de carga del EDLC es menor que dicho valor de la corriente máxima de operación del EDLC entonces se incrementa el ciclo útil de una señal PWM para controlar el conversor DC/DC; y condition C- if the load current of the EDLC is less than said value of the maximum operating current of the EDLC then the useful cycle of a PWM signal to control the DC / DC converter is increased; Y
condición D- si la corriente de carga del EDLC es mayor que dicho valor de la corriente máxima de operación del EDLC entonces se disminuye el ciclo útil de la señal PWM para controlar el conversor DC/DC y se repite la etapa (c). condition D- if the load current of the EDLC is greater than said value of the maximum operating current of the EDLC then the useful cycle of the PWM signal to control the DC / DC converter is decreased and step (c) is repeated.
Opcionalmente, por ejemplo, en el método de la presente invención, antes de la etapa (e) se incluye una etapa (d) para accionar un dispositivo de arranque suave con base en un valor dado por la resta entre la tensión de línea y el voltaje de operación del EDLC empleando la unidad de cómputo.  Optionally, for example, in the method of the present invention, a step (d) is included before step (e) to operate a soft start device based on a value given by the subtraction between the line voltage and the EDLC operating voltage using the computing unit.
Alternativamente, en un ejemplo del método de la presente invención en la etapa (c) antes de la condición B se verifica la siguiente condición A- si el voltaje del EDLC es igual a dicho límite inferior de voltaje de operación del EDLC pre-configurado entonces pasar a la etapa (d). Alternatively, in an example of the method of the present invention in step (c) before condition B the following condition A- is verified if the EDLC voltage is equal to said lower operating voltage limit of the pre-configured EDLC then go to step (d).
Opcionalmente, en un ejemplo del método implementado en la presente invención, la etapa (d) comprende las siguientes sub etapas:  Optionally, in an example of the method implemented in the present invention, step (d) comprises the following sub stages:
i- esperar a que la tensión de línea sea igual a un valor de un porcentaje definido del voltaje de operación del EDLC por un usuario; i- wait for the line voltage to be equal to a value of a defined percentage of the EDLC operating voltage by a user;
ii- quitar la resistencia de carga y pasar a la etapa (e). ii- remove the load resistance and go to step (e).
En la sub etapa (i) de la etapa (d), el porcentaje del valor de operación del EDLC está en el rango de 1 por ciento a 5 por ciento.  In sub stage (i) of stage (d), the percentage of the EDLC's operating value is in the range of 1 percent to 5 percent.
En la sub etapa (ii) de la etapa (d), la acción de quitar una resistencia de carga y corresponde a accionar un contacto eléctrico conectado en paralelo a una resistencia de carga.  In the sub stage (ii) of stage (d), the action of removing a load resistor corresponds to activating an electrical contact connected in parallel to a load resistor.
Alternativamente, por ejemplo, en el método de la presente invención la etapa (i) comprende las siguientes sub etapas:  Alternatively, for example, in the method of the present invention step (i) comprises the following sub stages:
i- registrar valor de la medida de corriente instantánea del EDLC con el segundo medidor de corriente; i- record value of the EDLC instantaneous current measurement with the second current meter;
ii- calcular el cambio de la corriente instantánea del EDLC (DI) con la diferencia entre el valor de la sub etapa anterior (h) (it) y el valor anterior de la medida de corriente instantánea del EDLC (i(t-i)), con la siguiente ecuación implementada en la unidad de cómputo: ii- calculate the change in the instantaneous current of the EDLC (DI) with the difference between the value of the previous sub-stage (h) (i t ) and the previous value of the instantaneous current measurement of the EDLC (i (t -i ) ), with the following equation implemented in the computing unit:
DI = it— it-i DI = i t - i ti
iii- calcular la corriente promedio del EDLC I restando el valor de la medida de corriente instantánea del EDLC más antiguo ¿t-w, con la siguiente ecuación implementada en la unidad de cómputo:
Figure imgf000034_0001
iii- calculate the average current of the EDLC I by subtracting the value of the instantaneous current measurement of the oldest EDLC ¿ tw , with the following equation implemented in the computation unit:
Figure imgf000034_0001
iv- reorganizar vector de valores de medidas de corriente instantánea con la siguiente ecuación implementada en la unidad de cómputo:
Figure imgf000034_0002
iv- reorganize vector values of instantaneous current measurements with the following equation implemented in the computation unit:
Figure imgf000034_0002
v- recalcular la corriente promedio del EDLC I sumando el valor de la medida de corriente instantánea del EDLC actual it-1, , con la siguiente ecuación implementada en la unidad de cómputo:
Figure imgf000034_0003
vi- volver a la sub etapa (i). v- recalculate the average current of EDLC I by adding the value of the instantaneous current measurement of the current EDLC i t-1 , with the following equation implemented in the computing unit:
Figure imgf000034_0003
live back to the sub stage (i).
En la etapa (i) del método que implementa la presente invención (K), (t) y (N) son números naturales del 1 al 1000.  In step (i) of the method that implements the present invention (K), (t) and (N) are natural numbers from 1 to 1000.
Ejemplo. Dispositivo y método de compensación de tensión.  Example. Device and method of voltage compensation.
Se diseñó y construyó un dispositivo y se implementó un método que se ejecuta en el dispositivo de compensación de tensión. El dispositivo tiene las siguientes características: A device was designed and built and a method implemented in the voltage compensation device was implemented. The device has the following characteristics:
Parámetros:  Parameters:
Energía máxima almacenada: E(max) = l,09kWh; Maximum stored energy: E (max) = l, 09kWh;
Corriente máxima en operación en modo Buck/Boost I(max): 180 A;Maximum current in operation in Buck / Boost I mode (max) : 180 A;
Voltaje nominal de línea: Vin(nom) 1500V; Nominal line voltage: Vi n (nom) 1500V;
Voltaje en vacío de línea: Vin(Set) = 1650V; Line empty voltage: Vi n (Set) = 1650V;
Voltaje máximo de línea: Vin(max) : 2000V; Maximum line voltage: Vi n (max) : 2000V;
Voltaje máximo en el EDLC: VC(max) = 1000V; Maximum voltage in the EDLC: V C (max) = 1000V;
Voltaje mínimo en el EDLC: VC(min) = 150V (voltaje hasta el que se llegará en los EDLCs en operación en modo Boost, que mantendrá una comente de mínimo el 10% de I(max)); Minimum voltage in the EDLC: V C (min) = 150V (voltage that will be reached in the EDLCs in operation in Boost mode, which will keep a comment of at least 10% of I (max) );
Voltaje inicial en el EDLC: VC(ini): 150V (voltaje límite de la precarga y corresponde al 10% del voltaje nominal del sistema de catenaria); Initial voltage in the EDLC: V C (ini) : 150V (preload limit voltage and corresponds to 10% of the nominal voltage of the catenary system);
Energía intercambiable: E(int): 0.787kWh (energía disponible entre Vc(max) y Vc(min) en el EDLC); Exchangeable energy: E (int) : 0.787kWh (available energy between V c (max) and V c (min) in the EDLC);
• Corriente de arranque suave: 7.33 A (corriente de precarga del • Soft start current: 7.33 A (preload current of the
EDLC hasta lograr un voltaje de 150 V); EDLC until a voltage of 150 V is achieved);
• Ciclo de trabajo máximo en operación en modo Boost D^-boost): 65% (ciclo de trabajo que garantiza que el sistema se mantenga en modo de operación discontinua y (teóricamente su valor está entre 0.33 y 0.75)).• Maximum duty cycle in operation in Boost D ^ - boost mode ) : 65% (duty cycle that ensures that the system is maintained in discontinuous operation mode and (theoretically its value is between 0.33 and 0.75)).
El dispositivo de protección y control (26) es un equipo de referencia SITRAS PRO como la protección primaria del dispositivo de la presente invención con velocidad de actuación de 40ms. The protection and control device (26) is a reference device SITRAS PRO as the primary protection of the device of the present invention with an actuation speed of 40ms.
El primer medidor de voltaje entrega una primera señal de voltaje (30), y el cable conductor de esta señal tiene un aislamiento eléctrico de 6kV respecto de la línea de transmisión. El criterio para la selección del primer contacto (24) es: The first voltage meter delivers a first voltage signal (30), and the conductor cable of this signal has an electrical isolation of 6kV from the transmission line. The criteria for selecting the first contact (24) is:
Ijiom Imax 180A  Ijiom Imax 180A
aislamiento ^ ín(max ) lc(mí)  isolation ^ ín (max) lc (me)
V aislamiento = 2000 - 150 = 1850E  V insulation = 2000 - 150 = 1850E
El dispositivo de compensación de tensión inicia su ciclo asegurando un régimen de corriente bajo en la carga del elemento EDLC (2), hasta alcanzar una tensión de !50VCD. The voltage compensation device starts its cycle ensuring a low current regime in the load of the EDLC element (2), until reaching a voltage of! 50V CD .
La primera resistencia (25) es de 75W @ 1 lkW el primer contacto (24) es normalmente abierto. La segunda resistencia (23) es de 3,45W @ 300W.  The first resistance (25) is 75W @ 1 lkW the first contact (24) is normally open. The second resistance (23) is 3.45W @ 300W.
El proceso de carga es exponencial decreciente para la corriente y el dispositivo compensador de tensión de la presente invención inicia su ciclo con régimen de corriente pico máxima IPk de 11A, esto en un ejemplo se logra con una primera resistencia (25) conformada por la serie de cinco resistencias de 30 W @ 220 V @ 1600 W cuya resistencia equivalente es 150 W y permite una corriente máxima de 7,33A. La corriente inicial pico del dispositivo si se considera un Vm(Set) de 1650V sobre un valor de primera resistencia (25) de 150 W es IPk = 11A, calculada con la siguiente fórmula: The charging process is exponentially decreasing for the current and the voltage compensating device of the present invention begins its cycle with maximum peak current regime I Pk of 11A, this in an example is achieved with a first resistance (25) formed by the series of five resistors of 30 W @ 220 V @ 1600 W whose equivalent resistance is 150 W and allows a maximum current of 7.33A. The initial peak current of the device if a V m (Set) of 1650V is considered on a first resistance value (25) of 150 W is I Pk = 11A, calculated with the following formula:
V, i.nfset ) 1650  V, i.nfset) 1650
Ipk = 11 A  Ipk = 11 A
R2 s 150 R 2 s 150
En un ejemplo de la invención el tiempo en el que se alcanza la corriente nominal de precarga es de 343 microsegundos. Se calcula utilizando la siguiente fórmula:
Figure imgf000036_0001
In an example of the invention, the time at which the nominal preload current is reached is 343 microseconds. It is calculated using the following formula:
Figure imgf000036_0001
• Iprc es la corriente de precarga; • I prc is the preload current;
• V0 es el voltaje de la línea de transmisión o tensión de línea; • V 0 is the transmission line voltage or line voltage;
• R25 es el valor óhmico de la resistencia (25); • R 25 is the ohmic value of the resistance (25);
t es el tiempo de en el que se alcanza la corriente nominal de precarga;  t is the time in which the nominal preload current is reached;
t es el tiempo de carga del elemento de alta densidad EDLC (2).
Figure imgf000036_0002
t is the loading time of the high density element EDLC (2).
Figure imgf000036_0002
La máxima potencia promedio P25 es la que debe ser disipada por las cinco resistencias en serie cada una con 1600 W, para un total de 8000 W, se calcula de la siguiente forma: The maximum average power P 25 is that which must be dissipated by the five series resistors each with 1600 W, for a total of 8000 W, it is calculated as follows:
P25 = Ipre 2xR25 = 7.332xl50 = 8060VK El filtro paso-bajo se diseña de acuerdo al tipo de rectificación que utilice la línea de transmisión, si se tiene una rectificación de 12 pulsos, que produce un riso de frecuencia P/6 de una señal de frecuencia de 60Hz, la frecuencia natural el tipo de rectificación de la línea de transmisión es de 720Hz, sin embargo, esta frecuencia natural supone una disipación elevada de potencia sobre la primera resistencia (25). P 25 = I pre 2 xR 25 = 7.33 2 xl50 = 8060VK The low-pass filter is designed according to the type of rectification used by the transmission line, if there is a 12-pulse rectification, which produces a P / 6 frequency lag of a 60Hz frequency signal, the natural frequency The type of rectification of the transmission line is 720Hz, however, this natural frequency means a high power dissipation on the first resistance (25).
Se establece la frecuencia de operación del dispositivo de compensación Fsw a criterio se selecciona de ser 4 veces la frecuencia natural del tipo de rectificación de la línea de transmisión Fsw = 720 Hz x 4 = 2880 Hz. The operating frequency of the compensation device F sw is determined at the discretion selected to be 4 times the natural frequency of the type of rectification of the transmission line F sw = 720 Hz x 4 = 2880 Hz.
Se asume una capacitancia de 16pF @ 2200V para el primer condensador (22) y se calcula la segunda resistencia (23) así:
Figure imgf000037_0001
A capacitance of 16pF @ 2200V is assumed for the first capacitor (22) and the second resistor (23) is calculated as follows:
Figure imgf000037_0001
¾3 = 3,45W ¾ 3 = 3.45W
La potencia en la segunda resistencia (23) se calcula sumando las contribuciones del tipo de rectificador de la línea de transmisión Pi = 3,l2W, más la contribución de los fenómenos de conmutación extemos al dispositivo de la presente invención conectados a la línea de transmisión P2 = 130W, más las contribuciones del dispositivo de compensación de tensión de la presente invención P3 = 6,53W. Con estos valores la potencia en la segunda resistencia (23) P23 = 140W. The power at the second resistor (23) is calculated by adding the contributions of the type of rectifier of the transmission line Pi = 3, l2W, plus the contribution of the external switching phenomena to the device of the present invention connected to the transmission line P 2 = 130W, plus the contributions of the voltage compensation device of the present invention P 3 = 6.53W. With these values the power at the second resistance (23) P 23 = 140W.
Para la selección del primer transistor IGBT (14a) y el segundo transistor IGBT (14b) se seleccionan los valores de los siguientes parámetros:  For the selection of the first IGBT transistor (14a) and the second IGBT transistor (14b), the values of the following parameters are selected:
• VCE ³ 2000V (Tensión colector emisor en corte. Se configura teniendo como base la tensión máxima de la línea de transmisión); • V CE ³ 2000V (Transmitter collector voltage in cut. It is configured based on the maximum transmission line voltage);
• Ic(nom) ³ 180A. (corriente nominal de colector. La corriente máxima nominal de este prototipo se establece a % de la corriente calculada); • Ic (nom) ³ 180A. (nominal collector current. The maximum nominal current of this prototype is set to% of the calculated current);
• ICRM = 300A @ lms (corriente máxima repetitiva de colector en inverso. Este parámetro se estima como el doble de la corriente Ic(nom)); • I CRM = 300A @ lms (maximum repetitive collector current in reverse. This parameter is estimated as double the current Ic (nom) );
• Isc = 800 A @ 10 ps. (corriente de corto circuito no repetitiva);  • Isc = 800 A @ 10 ps. (non-repetitive short circuit current);
• td(on>: 33.3 ps (retardo en el encendido. 10 veces más rápido (criterio de Nyquist) que la frecuencia de conmutación); • t d (on >: 33.3 ps (ignition delay. 10 times faster (Nyquist criterion) than the switching frequency);
Con base a estos parámetros se seleccionan con un nivel de seguridad muy por encima un par de transistores IGBTs de referencia DS-FZ1500R33HE3 para el primer transistor IGBT (14a) y el segundo transistor IGBT (14b) de la compañía Infineon y su módulo driver ISD536F2- FZ1500R33HE3 para el primer driver IGBT (17) y el segundo driver IGBT (16). Para el cálculo de los valores de capacitancia para el cuarto capacitor (10) del segundo elemento de conmutación y el tercer condensador (11) del primer elemento de conmutación se aplica la siguiente fórmula:
Figure imgf000038_0001
Based on these parameters, a pair of IGBT transistors of reference DS-FZ1500R33HE3 for the first IGBT transistor (14a) and the second IGBT transistor (14b) of the company Infineon and its driver module ISD536F2 are selected with a safety level - FZ1500R33HE3 for the first IGBT driver (17) and the second IGBT driver (16). For the calculation of the capacitance values for the fourth capacitor (10) of the second switching element and the third capacitor (11) of the first switching element the following formula is applied:
Figure imgf000038_0001
Cio = 0,013 pF y Cn = 0,013 pF.  Cio = 0.013 pF and Cn = 0.013 pF.
Los valores de resistencia y potencia para la quinta resistencia (8) del segundo elemento de conmutación y la cuarta resistencia (9) del primer elemento de conmutación son R(x) = 4273W @ 69Wy R j = 4273W @ 69W. The resistance and power values for the fifth resistance (8) of the second switching element and the fourth resistance (9) of the first switching element are R ( x ) = 4273W @ 69W and R j = 4273W @ 69W.
Para la selección de los diodos de la red snubber del primer elemento de conmutación el segundo diodo (7) y para el segundo elemento de conmutación el cuarto diodo (6a) se seleccionan con tipo diodo de recuperación ultra rápida con VRRM = 2500V y Ip = 180A. Más específicamente la referencia SD303C25S20C-ND. For the selection of the diodes of the snubber network of the first switching element the second diode (7) and for the second switching element the fourth diode (6a) is selected with ultra-fast recovery diode type with V RRM = 2500V and Ip = 180A. More specifically the reference SD303C25S20C-ND.
La disposición física del segundo condensador (20) y de los elementos de conmutación se encuentran conectados físicamente cerca para garantizar un camino de baja impedancia para las señales de EMI, por ejemplo una distancia de 2 metros, el valor de la capacitancia mínima se calcula con la siguiente fórmula:
Figure imgf000038_0002
The physical arrangement of the second capacitor (20) and the switching elements are physically connected nearby to ensure a low impedance path for EMI signals, for example a distance of 2 meters, the minimum capacitance value is calculated with The following formula:
Figure imgf000038_0002
C20(min) = 602pF @ 2000V. C 20 (min) = 602pF @ 2000V.
C20 se selecciona 4 veces mayor a C20(min) con un valor 2000pF @ 2250V. C 20 is selected 4 times higher than C 20 (min) with a value of 2000pF @ 2250V.
Para el cálculo de la inductancia mínima del tercer inductor (6b) para garantizar modo de operación continuo en operación en modo Buck se utiliza la siguiente fórmula:
Figure imgf000038_0003
The following formula is used to calculate the minimum inductance of the third inductor (6b) to guarantee continuous operation mode in Buck mode operation:
Figure imgf000038_0003
• L6b es la inductancia del tercer inductor (6b); • L 6b is the inductance of the third inductor (6b);
• Dmin es el ciclo de trabajo mínimo sobre el elemento de conmutación IGBT (14a); • D min is the minimum duty cycle on the IGBT switching element (14a);
• V in(set) es el voltaje de entrada de la línea de transmisión; • V i n (set) is the input voltage of the transmission line;
• VC(max) es el voltaje máximo soportado por el elemento de alta densidad EDLC (2); • V C (max) is the maximum voltage supported by the high density element EDLC (2);
• Ibuck(nom) es la corriente nominal en operación en modo Buck.• I buck (nom) is the nominal current in operation in Buck mode.
L6min(buck)— 118mH. L6min (buck) - 118mH.
La siguiente ecuación determina la inductancia mínima del tercer inductor (6b) mínima para asegurar la operación en modo Boost, desde una tensión de VC(min) = 300V hasta una tensión de Vm(Set) = 1650V y considerando una Iboost(nzo) que equivale a I(max/2:
Figure imgf000039_0001
The following equation determines the minimum inductance of the third minimum inductor (6b) to ensure operation in Boost mode, from a voltage of V C (min) = 300V to a voltage of V m (Set) = 1650V and considering an I boost ( nzo) which equals I (max / 2:
Figure imgf000039_0001
L6min(boost) 0,959mH. L 6min (boost) 0.959mH.
Se opta por el valor de L6min(buck) para satisfacer las exigencias de operación de modo Buck en modo continuo para el primer elemento de conmutación y de la operación de modo Boost en modo discontinuo para el segundo elemento de conmutación. The value of L 6min (buck) is chosen to meet the operating requirements of Buck mode in continuous mode for the first switching element and of the operation of Boost mode in discontinuous mode for the second switching element.
La sexta resistencia (4) del elemento de descarga del elemento de alta densidad EDLC (2) se calcula con un régimen inicial de 20A para 1000V. Esto resulta en un valor resistivo para la sexta resistencia del elemento de descarga del elemento de alta densidad EDLC (2) de 50 W cuya a potencia máxima instantánea soportada es de 20 kW.  The sixth resistance (4) of the discharge element of the high density element EDLC (2) is calculated with an initial rate of 20A for 1000V. This results in a resistive value for the sixth resistance of the discharge element of the high-density EDLC element (2) of 50 W whose maximum instantaneous power supported is 20 kW.
El valor de la capacitancia de para el elemento de alta densidad EDLC (2) es de 7.875 F  The capacitance value of for the high density element EDLC (2) is 7,875 F
Se selecciona un primer fusible (3a) y un segundo fusible (3b) de operación rápida con una velocidad de respuesta con base en la corriente de 20ms. A first fuse (3a) and a second fuse (3b) of fast operation are selected with a response speed based on the current of 20ms.
Se debe entender que la presente invención no se halla limitada a las modalidades descritas e ilustradas, pues como será evidente para una persona versada en el arte, existen variaciones y modificaciones posibles que no se apartan del espíritu de la invención, el cual solo se encuentra definido por las siguientes reivindicaciones.  It should be understood that the present invention is not limited to the modalities described and illustrated, since as will be evident to a person versed in art, there are possible variations and modifications that do not depart from the spirit of the invention, which is only found defined by the following claims.

Claims

REIVINDICACIONES
1. Un dispositivo para compensación de tensión en comente directa que comprende:  1. A device for direct current voltage compensation comprising:
- un EDLC (2) con un terminal positivo y un terminal negativo;  - an EDLC (2) with a positive terminal and a negative terminal;
- un primer medidor de voltaje (9A) con velocidad de lectura en intervalos entre l/rs y IOm,ϊ y dispuesto operativamente en el EDLC (2);  - a first voltage meter (9A) with read speed in intervals between l / rs and IOm, ϊ and operatively arranged in the EDLC (2);
- un primer medidor de corriente (8A) con velocidad de lectura en intervalos entre l/rs y 10/^ y dispuesto operativamente en el EDLC (2);  - a first current meter (8A) with read speed in intervals between l / rs and 10 / ^ and operatively arranged in the EDLC (2);
- un conversor DC/DC (7A) con corriente de conmutación de 3KHz, conectado al EDLC (2) y al primer medidor de corriente (8A);  - a DC / DC converter (7A) with 3KHz switching current, connected to the EDLC (2) and the first current meter (8A);
- una unidad de cómputo (11 A) conectada al conversor DC/DC (7A), al primer medidor de voltaje (9A) y al primer medidor de corriente (8A);  - a computing unit (11 A) connected to the DC / DC converter (7A), the first voltage meter (9A) and the first current meter (8A);
donde la unidad de cómputo (11A) con base en las señales del primer medidor de voltaje (9A) y del primer medidor de corriente (8A) controla el conversor DC/DC (7A) para compensar la tensión en corriente directa. where the computing unit (11A) based on the signals of the first voltage meter (9A) and the first current meter (8A) controls the DC / DC converter (7A) to compensate for the direct current voltage.
2. El dispositivo de la Reivindicación 1, donde el conversor DC/DC (7A) está conectado a un acondicionador de fuente (6A) y el primer medidor de corriente (8A) conectado al acondicionador de fuente (6A).  2. The device of Claim 1, wherein the DC / DC converter (7A) is connected to a source conditioner (6A) and the first current meter (8A) connected to the source conditioner (6A).
3. El dispositivo de la Reivindicación 1, donde el conversor DC/DC (7A) está conectado a una unidad de protección y control (26) que tiene una entrada de potencia y una salida de potencia y el primer medidor de corriente (8A) conectado a la salida de la unidad de protección y control (26); la unidad de cómputo (11A) conectada a la unidad de protección y control (26).  3. The device of Claim 1, wherein the DC / DC converter (7A) is connected to a protection and control unit (26) having a power input and a power output and the first current meter (8A) connected to the output of the protection and control unit (26); the computing unit (11A) connected to the protection and control unit (26).
donde el conversor DC/DC (7A) está conectado a la salida de potencia de la unidad de protección y control (26) where the DC / DC converter (7A) is connected to the power output of the protection and control unit (26)
4. El dispositivo de la Reivindicación 1, donde el conversor DC/DC (7A) está conectado a un dispositivo de arranque suave (3A) y la unidad de cómputo (11 A) conectada al dispositivo de arranque suave (3A).  4. The device of Claim 1, wherein the DC / DC converter (7A) is connected to a soft start device (3A) and the computing unit (11 A) connected to the soft start device (3A).
5. El dispositivo de la Reivindicación 1, donde el conversor DC/DC (7A) está conectado a un dispositivo de arranque suave (3A); una unidad de protección y control (26) con una entrada de potencia y una salida de potencia, el dispositivo de arranque suave (3 A) conectado a la salida de la unidad de protección y control (26) y a la unidad de cómputo (11A); la unidad de protección y control (26) conectada a la unidad de cómputo (11 A). 5. The device of Claim 1, wherein the DC / DC converter (7A) is connected to a soft start device (3A); a protection and control unit (26) with a power input and a power output, the soft start device (3 A) connected to the output of the protection and control unit (26) and the unit of computation (11A); the protection and control unit (26) connected to the computing unit (11 A).
6. El dispositivo de la Reivindicación 3, donde la unidad de protección y control (26) está conectado operativamente en su salida de potencia un segundo medidor de voltaje (4A) con velocidad de lectura en intervalos entre l/rs y 10/^ y un segundo medidor de comente (5 A) con velocidad de lectura en intervalos entre l/rs y 1 Ow.v: la unidad de cómputo (11A) está conectada al segundo medidor de voltaje (4A) y al segundo medidor de comente (5A).  6. The device of Claim 3, wherein the protection and control unit (26) is operatively connected at its power output a second voltage meter (4A) with read speed in intervals between l / rs and 10 / ^ and a second comment meter (5 A) with read speed in intervals between l / rs and 1 Ow.v: the computation unit (11A) is connected to the second voltage meter (4A) and the second comment meter (5A ).
7. El dispositivo de la Reivindicación 1, donde el conversor DC/DC (7A) está conectado a un acondicionador de fuente (6A); un dispositivo de arranque suave (3A) está conectado al acondicionador de fuente (6A) y a la unidad de cómputo (11 A); una unidad de protección y control (26) está conectada al dispositivo de arranque suave (3 A), al acondicionador de fuente (6A) y a la unidad de cómputo (11A);  7. The device of Claim 1, wherein the DC / DC converter (7A) is connected to a source conditioner (6A); a soft start device (3A) is connected to the source conditioner (6A) and the computing unit (11 A); a protection and control unit (26) is connected to the soft start device (3 A), the source conditioner (6A) and the computing unit (11A);
un segundo medidor de voltaje (4A) dispuesto operativamente en la unidad de protección y control (26) y está conectado a la unidad de cómputo (11A); un segundo medidor de comente (5A) dispuesto operativamente entre la unidad de protección y control (26) y el acondicionador de fuente (6A) y está conectado a la unidad de cómputo (HA). a second voltage meter (4A) operatively disposed in the protection and control unit (26) and is connected to the computing unit (11A); a second current meter (5A) operatively arranged between the protection and control unit (26) and the source conditioner (6A) and is connected to the computing unit (HA).
8. Un método para compensación de tensión en comente directa que comprende las siguientes etapas:  8. A method for direct current voltage compensation comprising the following stages:
e- verificar que la tensión de línea esté entre un límite inferior de voltaje operación y un límite superior de voltaje de operación pre-configurados por un usuario en un registro de memoria de una unidad de cómputo y pasar a la etapa (g); si la tensión de línea supera dichos límites de voltaje de operación se verifica una condición de detención;  e- verify that the line voltage is between a lower operating voltage limit and an upper operating voltage limit pre-configured by a user in a memory register of a computing unit and go to step (g); if the line voltage exceeds these operating voltage limits a stop condition is verified;
g- verificar que la variación de voltaje del EDLC sea inferior a un límite de variación de voltaje del EDLC y que la variación de comente de carga del EDLC sea inferior a un límite de variación de la comente de carga del EDLC pre-configurados por un usuario en un registro de memoria de la unidad de cómputo;  g- verify that the EDLC voltage variation is less than an EDLC voltage variation limit and that the EDLC load comment variation is less than a variation limit of the EDLC load comment pre-configured by a user in a memory register of the computing unit;
si dichas variaciones no superan dichos límites verificar que la comente de carga del EDLC sea inferior a un límite de comente de operación del EDLC para controlar el conversor DC/DC y verificar modo de funcionamiento del conversor DC/DC, si dichas variaciones superan dichos límites entonces realizar una desconexión; if said variations do not exceed said limits, verify that the EDLC load comment is lower than an EDLC operating comment limit to control the DC / DC converter and verify the mode of DC / DC converter operation, if these variations exceed said limits then make a disconnection;
h- verificar si el modo de funcionamiento del conversor DC/DC es modo Boost ; si el modo de funcionamiento del conversor DC/DC es modo Boost, comprobar que el voltaje de carga del EDLC esté en un rango definido por un límite superior de voltaje de operación del EDLC y un límite inferior de voltaje de operación del EDLC pre-programados por un usuario en un registro de memoria de la unidad de cómputo y mantener la corriente de carga del EDLC;  h- check if the operating mode of the DC / DC converter is Boost mode; If the operating mode of the DC / DC converter is Boost mode, check that the EDLC load voltage is in a range defined by an upper EDLC operating voltage limit and a pre-programmed EDLC operating voltage lower limit by a user in a memory register of the computing unit and maintain the EDLC charge current;
i- registrar los cambios de la corriente del EDLC, el voltaje del EDLC y de la línea de tensión, y con base en dichos cambios determinar un diferencial de corriente y voltaje, la unidad de cómputo calcula en cada intervalo un valor promedio de voltaje y corriente con base en valores anteriores y actuales de voltaje y corriente;  i- record the changes of the EDLC current, the EDLC voltage and the voltage line, and based on these changes determine a current and voltage differential, the computation unit calculates in each interval an average voltage value and current based on previous and current voltage and current values;
donde la etapa (i) se ejecuta periódicamente de la etapa (e) a la etapa (h) con un intervalo entre 1 ps y 10 ps independientemente de las otras etapas. where stage (i) is periodically executed from stage (e) to stage (h) with an interval between 1 ps and 10 ps regardless of the other stages.
9. El método de la Reivindicación 8, donde después de la etapa (e) se incluye una etapa (f) donde se espera a que el voltaje del EDLC sea igual a un valor pre -configurado por un usuario en un registro de memoria de la unidad de cómputo y pasar a la etapa (a) en la que se espera una señal de inicio de una unidad de cómputo; y en la etapa (e) la verificación de la condición de detención se realiza verificando las siguientes condiciones:  9. The method of Claim 8, wherein after step (e) a stage (f) is included where the EDLC voltage is expected to be equal to a value pre-configured by a user in a memory register of the computing unit and going to step (a) in which a start signal from a computing unit is expected; and in step (e) the verification of the detention condition is carried out by verifying the following conditions:
A- si se presenta un evento de detención pasar a la etapa (f);  A- if a detention event occurs, go to stage (f);
B- si no se presenta un evento de detención repetir la etapa (e);  B- if a detention event does not occur repeat step (e);
10. El método de la Reivindicación 8, donde en la etapa (g), dicha verificación se realiza siguiendo estas condiciones:  10. The method of Claim 8, wherein in step (g), said verification is performed following these conditions:
B- si las variaciones de voltaje y corriente del EDLC no superan un límite de variación de voltaje de carga del EDLC ni un límite de variación de corriente de carga del EDLC comparar si la corriente de carga del EDLC es inferior a un límite de corriente de operación del EDLC pre-configurados por un usuario en un registro de memoria pasar a la etapa (h);  B- If the EDLC voltage and current variations do not exceed an EDLC charge voltage variation limit or an EDLC charge current variation limit, compare if the EDLC load current is less than a current limit of EDLC operation pre-configured by a user in a memory register go to step (h);
C- si la corriente de carga del EDLC es superior al límite de corriente de operación del EDLC pre -configurado por un usuario, comprobar el modo de funcionamiento del conversor DC/DC, si el modo de funcionamiento del conversor DC/DC es modo Boost, y C- if the EDLC load current is higher than the EDLC operating current limit pre-configured by a user, check the mode of DC / DC converter operation, if the operating mode of the DC / DC converter is Boost mode, and
D- si la medida de la comente de carga del EDLC es menor a un valor de la comente del EDLC pre -configurado por un usuario en un registro de memoria durante un tiempo dado por un número K veces más un número N de datos en un instante de tiempo Dΐ, donde el número N de datos en un instante Dΐ de tiempo es menor a la mitad del periodo de la señal de PWM;  D- if the measurement of the EDLC load comment is less than an EDLC comment value pre-configured by a user in a memory register for a given time by a number K times plus a number N of data in a time instant Dΐ, where the number N of data in an instant Dΐ of time is less than half the period of the PWM signal;
F- si el modo de funcionamiento del conversor DC/DC no es modo Boost entonces se repite la etapa (g);  F- if the operating mode of the DC / DC converter is not Boost mode then step (g) is repeated;
donde la duración del pulso de la señal de PWM está entre 0 ps y 340 ps. where the pulse duration of the PWM signal is between 0 ps and 340 ps.
11. El método de la Reivindicación 10, donde en después de la etapa (e) se incluye una etapa (f) donde se espera a que el voltaje del EDLC sea igual a un valor pre- configurado por un usuario en un registro de memoria de la unidad de cómputo y pasar a la etapa (a) en la que se espera una señal de inicio de una unidad de cómputo; antes de la condición B de la etapa (g) se verifica la siguiente condición A:  11. The method of Claim 10, wherein after stage (e) a stage (f) is included where the EDLC voltage is expected to be equal to a value pre-configured by a user in a memory register from the computation unit and go to step (a) in which a start signal from a computation unit is expected; before condition B of step (g) the following condition A is verified:
A- si la variación de voltaje del EDLC supera un límite de variación de voltaje del EDLC o si la variación de comente del EDLC supera un límite de variación de comente de carga del EDLC pasar a la etapa (f).  A- if the EDLC voltage variation exceeds an EDLC voltage variation limit or if the EDLC comment variation exceeds an EDLC load comment variation limit go to step (f).
12. El método de la Reivindicación 11, donde después de la condición D de la etapa (g) se verifica la siguiente condición E:  12. The method of Claim 11, wherein after condition D of step (g) the following condition E is verified:
E- si no se cumple la condición D se pasa a la etapa (f), si se cumple la condición D se repite la etapa (g).  E- if condition D is not met, step (f) is passed, if condition D is met, step (g) is repeated.
13. El método de la Reivindicación 8, donde en la etapa (h) si el modo de funcionamiento del conversor DC/DC es modo Boost entonces se verifican las siguientes condiciones:  13. The method of Claim 8, wherein in step (h) if the operating mode of the DC / DC converter is Boost mode then the following conditions are verified:
B- si la medida de la comente de carga del EDLC es menor un valor de la comente del EDLC pre -configurado por un usuario en un registro de memoria durante un tiempo dado por un número K veces más un número N de datos en un instante Dΐ de tiempo, donde el número N de datos en un instante Dΐ de tiempo es menor a la mitad del periodo de la señal de PWM;  B- if the measurement of the EDLC load comment is less than an EDLC comment value pre-configured by a user in a memory register for a given time for a number K times plus a number N of data in an instant Dΐ of time, where the number N of data in an instant Dΐ of time is less than half the period of the PWM signal;
C- si se cumple la condición B se compara la comente promedio con la comente máxima de operación del EDLC;  C- if condition B is met, the average comment is compared with the maximum operating comment of the EDLC;
D- si la comente promedio es menor que la comente máxima de operación del EDLC se incrementa el ciclo útil de la señal PWM del conversor DC/DC y se repite la etapa (h), si la comente promedio es mayor que la corriente máxima de operación del EDLC entonces se repite la etapa (h); D- if the average comment is less than the maximum EDLC operating comment, the useful cycle of the PWM signal of the DC / DC converter is increased and stage (h) is repeated, if the average comment is greater than the maximum EDLC operating current then stage (h) is repeated;
E- si no se cumple de la condición B entonces se disminuye el ciclo útil de la señal de PWM del conversor DC/DC y se compara la comente promedio con la comente máxima de operación del EDLC;  E- if condition B is not fulfilled then the useful cycle of the PWM signal of the DC / DC converter is decreased and the average comment is compared with the maximum operating current of the EDLC;
F- si la comente promedio es menor que la comente máxima de operación del EDLC se incrementa el ciclo útil de la señal PWM del conversor DC/DC y se repite la etapa (h), si la comente promedio es mayor que la comente máxima de operación del EDLC se repite la etapa (h);  F- if the average comment is less than the maximum EDLC operating comment, the useful cycle of the PWM signal of the DC / DC converter is increased and step (h) is repeated, if the average comment is greater than the maximum comment of EDLC operation is repeated step (h);
donde la duración del pulso de la señal de PWM está entre 0 ps y 340 ps. where the pulse duration of the PWM signal is between 0 ps and 340 ps.
14. El método de la Reivindicación 13, donde antes de la etapa (h) se incluye una etapa (a) en la que se espera una señal de inicio de una unidad de cómputo; en la etapa (h), antes de verificar la condición B se verifica la siguiente condición A:  14. The method of Claim 13, wherein before step (h) a stage (a) is included in which a start signal from a computing unit is expected; in step (h), before checking condition B the following condition A is verified:
A- si el voltaje de carga del EDLC no está en el rango definido un límite superior de voltaje de operación del EDLC y un límite inferior de voltaje de operación del EDLC pre-configurados por un usuario en un registro de memoria, se baja la comente aplicando una rampa con duración inferior a un segundo a un régimen entre 300 V/s y 900 V/s y se pasa a la etapa (e); y si el voltaje de carga del EDLC está en del rango definido por dichos límites, entonces se verifica una medida de la comente de carga del EDLC y se verifica la condición B;  A- if the EDLC load voltage is not in the defined range an upper EDLC operating voltage limit and a lower EDLC operating voltage limit pre-configured by a user in a memory register, the comment is lowered applying a ramp that lasts less than one second at a rate between 300 V / s and 900 V / s and goes to stage (e); and if the charge voltage of the EDLC is in the range defined by said limits, then a measure of the charge rating of the EDLC is verified and condition B is verified;
15. El método de la Reivindicación 8, donde en la etapa (h) si el modo de funcionamiento del conversor DC/DC no es modo Boost entonces se realiza la verificación de las siguientes condiciones:  15. The method of Claim 8, wherein in step (h) if the operating mode of the DC / DC converter is not Boost mode then the verification of the following conditions is performed:
B- si el voltaje de carga del EDLC no supera un voltaje de carga máximo del EDLC pre -configurado en un registro de memoria entonces se compara si la tensión de línea es mayor que el voltaje de operación del EDLC, si la tensión de línea es mayor que el voltaje de operación del EDLC entonces se compara la comente promedio con la comente máxima de operación del EDLC; y  B- if the EDLC load voltage does not exceed a maximum EDLC load voltage pre-configured in a memory register then it is compared if the line voltage is greater than the EDLC operating voltage, if the line voltage is higher than the EDLC operating voltage then the average comment is compared with the maximum EDLC operating comment; Y
C- si la comente promedio es mayor que la comente máxima de operación del EDLC entonces se disminuye el ciclo útil de la señal PWM del conversor DC/DC; y  C- if the average comment is greater than the maximum EDLC operating comment then the useful cycle of the PWM signal of the DC / DC converter is decreased; Y
D- si la comente promedio es menor que la comente máxima de operación del EDLC entonces se incrementa el ciclo útil de la señal PWM del conversor DC/DC y se repite la etapa (h); D- if the average comment is less than the maximum EDLC operating comment then the useful cycle of the PWM signal of the DC / DC converter is increased and step (h) is repeated;
16. El método de la Reivindicación 15, donde antes de la etapa (h) se incluye una etapa (a) en la que se espera una señal de inicio de una unidad de cómputo; en la etapa (h) antes de la condición B se incluye la siguiente condición A: 16. The method of Claim 15, wherein prior to step (h) a step (a) is included in which a start signal from a computing unit is expected; in step (h) before condition B the following condition A is included:
A- comparar el voltaje de carga del EDLC con un voltaje de carga máximo del EDLC pre-configurado por un usuario en un registro de memoria, si el voltaje de carga del EDLC supera dicho límite voltaje entonces se baja la corriente aplicando una rampa con duración inferior a un segundo a un régimen entre 300 V/s y 900 V/s y se pasa a la etapa (e);  A- compare the charge voltage of the EDLC with a maximum charge voltage of the EDLC pre-configured by a user in a memory register, if the charge voltage of the EDLC exceeds said voltage limit then the current is lowered by applying a ramp with duration less than one second at a rate between 300 V / s and 900 V / s and go to step (e);
17. El método de la Reivindicación 16, donde en la etapa (h) después de la condición D se incluye la siguiente condición E:  17. The method of Claim 16, wherein the following condition E is included in step (h) after condition D:
E- si no se cumple la condición B entonces se baja la corriente aplicando una rampa con duración inferior a un segundo a un régimen entre 300 V/s y 900 V/s y se pasa a la etapa (e);  E- if condition B is not fulfilled then the current is lowered by applying a ramp with a duration of less than one second at a rate between 300 V / s and 900 V / s and is passed to step (e);
18. El método de la Reivindicación 8, donde antes de la etapa (e) se incluye una etapa (a) en la que se espera una señal de inicio de una unidad de cómputo para pasar a la etapa (e).  18. The method of Claim 8, wherein before step (e) a step (a) is included in which a start signal from a computing unit is expected to pass to step (e).
19. El método de la Reivindicación 8, donde antes de la etapa (e) se incluye una etapa (b) para cerrar protecciones en una unidad de protección y control, y verificar que la tensión de línea, la corriente de carga de un EDLC se encuentren en un rango de voltaje y corriente pre -configurados por un usuario en un registro de memoria de una unidad de cómputo, si no se encuentran en dicho rango de valores pre -configurados se repite (b), de lo contrario se ejecuta la etapa (e).  19. The method of Claim 8, wherein before step (e) a step (b) is included to close protections in a protection and control unit, and verify that the line voltage, the load current of an EDLC they are in a range of voltage and current pre-configured by a user in a memory register of a computing unit, if they are not in said range of pre-configured values it is repeated (b), otherwise the stage (e).
20. El método de la Reivindicación 19, caracterizado porque la etapa (b) comprende las siguientes sub-etapas:  20. The method of Claim 19, characterized in that step (b) comprises the following sub-stages:
i- cerrar protecciones de la unidad de protección y control;  i- close protections of the protection and control unit;
ii- comparar la tensión de línea y el voltaje mínimo de la línea de transmisión pre-configurado por un usuario en la unidad de cómputo, si la tensión de línea es menor que el voltaje mínimo de la línea de transmisión repetir la etapa (b), si la tensión de línea es mayor que el voltaje mínimo de la línea de transmisión pasar a la sub etapa (iii);  ii- compare the line voltage and the minimum voltage of the transmission line pre-configured by a user in the computing unit, if the line voltage is less than the minimum voltage of the transmission line repeat step (b) , if the line voltage is greater than the minimum transmission line voltage, go to the sub stage (iii);
iii- comparar la corriente de almacenamiento del EDLC medida con un medidor de corriente con un valor pre-configurado en la unidad de cómputo, si corriente de almacenamiento del EDLC es mayor que dicho valor pre-configurado repetir la etapa (b) y si corriente de almacenamiento del EDLC es menor que dicho valor pre-configurado pasar a la etapa (c); iii- compare the measured EDLC storage current with a current meter with a pre-configured value in the computation unit, if EDLC storage current is greater than said pre-configured value repeat step (b) and if current of EDLC storage is less than said pre-configured value move to step (c);
21. El método de la Reivindicación 11, donde antes de la etapa (e) se incluye una etapa (c) para verificar si voltaje del EDLC es igual a un límite inferior de voltaje de operación del EDLC pre-configurado en un registro de memoria y verificar que la corriente de carga sea igual a la corriente de carga mínima, estas verificaciones se hacen siguiendo las siguientes condiciones:  21. The method of Claim 11, wherein a step (c) is included before step (e) to verify whether EDLC voltage is equal to a lower EDLC operating voltage limit pre-configured in a memory register and verify that the load current is equal to the minimum load current, these verifications are made following the following conditions:
B- si el voltaje del EDLC es diferente a dicho límite inferior de voltaje de operación del EDLC pre-configurado entonces verificar que la corriente de carga del EDLC se mantenga en un valor de un porcentaje de la corriente máxima de operación del EDLC pre-configurado en un registro de memoria;  B- if the EDLC voltage is different from said lower limit of operating voltage of the pre-configured EDLC then verify that the EDLC load current is maintained at a value of a percentage of the maximum operating current of the pre-configured EDLC in a memory register;
C- si la corriente de carga del EDLC es menor que dicho valor de la corriente máxima de operación del EDLC entonces se incrementa el ciclo útil de una señal PWM para controlar el conversor DC/DC; y  C- if the load current of the EDLC is less than said value of the maximum operating current of the EDLC then the useful cycle of a PWM signal to control the DC / DC converter is increased; Y
D- si la corriente de carga del EDLC es mayor que dicho valor de la corriente máxima de operación del EDLC entonces se disminuye el ciclo útil de la señal PWM para controlar el conversor DC/DC y se repite la etapa (c).  D- if the load current of the EDLC is greater than said value of the maximum operating current of the EDLC then the useful cycle of the PWM signal to control the DC / DC converter is decreased and step (c) is repeated.
22. El método de la Reivindicación 21, donde antes de la etapa (e) se incluye una etapa (d) para accionar un dispositivo de arranque suave con base en un valor dado por la resta entre la tensión de línea y el voltaje de operación del EDLC empleando la unidad de cómputo.  22. The method of Claim 21, wherein prior to step (e) a step (d) is included for operating a soft start device based on a value given by the subtraction between the line voltage and the operating voltage EDLC using the computing unit.
23. El método de la Reivindicación 22, donde en la etapa (c) antes de la condición B se verifica la siguiente condición A:  23. The method of Claim 22, wherein in step (c) before condition B the following condition A is verified:
A- si el voltaje del EDLC es igual a dicho límite inferior de voltaje de operación del EDLC pre-configurado entonces pasar a la etapa (d);  A- if the EDLC voltage is equal to said lower operating voltage limit of the pre-configured EDLC then go to step (d);
24. El método de la Reivindicación 22, caracterizado porque la etapa (d) comprende las siguientes sub etapas:  24. The method of Claim 22, characterized in that step (d) comprises the following sub stages:
i- esperar a que la tensión de línea sea igual a un valor de un porcentaje definido del voltaje de operación del EDLC por un usuario;  i- wait for the line voltage to be equal to a value of a defined percentage of the EDLC operating voltage by a user;
ii- quitar la resistencia de carga y pasar a la etapa (e).  ii- remove the load resistance and go to step (e).
25. El método de la Reivindicación 8, donde la etapa (i) comprende las siguientes sub etapas:  25. The method of Claim 8, wherein step (i) comprises the following sub stages:
i- registrar valor de la medida de corriente instantánea del EDLC con el segundo medidor de corriente; ii- calcular el cambio de la comente instantánea del EDLC (DI) con la diferencia entre el valor de la sub etapa anterior (h) (it) y el valor anterior de la medida de corriente instantánea del EDLC (i(t-i)), con la siguiente ecuación implementada en la unidad de cómputo: i- record value of the EDLC instantaneous current measurement with the second current meter; ii- calculate the change of the EDLC instantaneous comment (DI) with the difference between the value of the previous sub stage (h) (i t ) and the previous value of the EDLC instantaneous current measurement (i (ti) ) , with the following equation implemented in the computing unit:
DI = it ¿t— i DI = i t ¿ t— i
iii- calcular la comente promedio del EDLC I restando el valor de la medida de comente instantánea del EDLC más antiguo
Figure imgf000047_0001
con la siguiente ecuación implementada en la unidad de cómputo: iii- calculate the average EDLC I comment by subtracting the value of the oldest EDLC instantaneous comment measurement
Figure imgf000047_0001
with the following equation implemented in the computing unit:
lt-N  lt-N
= - = -
2N 2 N
iv- reorganizar vector de valores de medidas de comente instantánea con la siguiente ecuación implementada en la unidad de cómputo: iv- reorganize vector values of instantaneous comment measurements with the following equation implemented in the computation unit:
ll -N = lt-N*l lt- 1 = lt ll -N = l tN * l l t- 1 = l t
v- recalcular la comente promedio del EDLC I sumando el valor de la medida de comente instantánea del EDLC actual ® , con la siguiente ecuación implementada en la unidad de cómputo:
Figure imgf000047_0002
v- recalculate the average EDLC I comment by adding the value of the current EDLC ® instant comment measurement, with the following equation implemented in the computation unit:
Figure imgf000047_0002
vi- volver a la sub etapa (i). live back to the sub stage (i).
PCT/IB2019/050535 2018-01-22 2019-01-22 Voltage compensation device and method WO2019142173A1 (en)

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KR101122598B1 (en) * 2009-02-15 2012-03-19 김래영 Apparatus for uniform charging battery
CN104648165B (en) * 2015-03-14 2017-03-08 浙江大学 A kind of automotive braking energy recovering device and its Discrete control method
US20170155274A1 (en) * 2014-03-03 2017-06-01 Robert Bosch Gmbh Topology and control strategy for hybrid storage systems

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101122598B1 (en) * 2009-02-15 2012-03-19 김래영 Apparatus for uniform charging battery
US20170155274A1 (en) * 2014-03-03 2017-06-01 Robert Bosch Gmbh Topology and control strategy for hybrid storage systems
CN104648165B (en) * 2015-03-14 2017-03-08 浙江大学 A kind of automotive braking energy recovering device and its Discrete control method

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