WO2019132874A1

WO2019132874A1 - High temperature wafers bonded to low temperature wafers

Info

Publication number: WO2019132874A1
Application number: PCT/US2017/068488
Authority: WO
Inventors: Abhishek A. Sharma; Ravi Pillarisetty; Willy Rachmady; Gilbert Dewey
Original assignee: Intel Corporation
Priority date: 2017-12-27
Filing date: 2017-12-27
Publication date: 2019-07-04

Abstract

Disclosed is an integrated circuit device. The integrated circuit device includes at least a portion of a first wafer including one or more first devices formed therein or thereon. The one or more first devices are susceptible to damage responsive to exposure to temperatures above a predetermined threshold temperature. The integrated circuit device also includes at least a portion of a second wafer including one or more second devices formed therein or thereon. The at least the portion of the second wafer is bonded to and electrically connected to the at least the portion of the first wafer. The one or more second devices were formed at least by heating the second wafer above the predetermined threshold temperature.

Description

HIGH TEMPERATURE WAFERS BONDED TO LOW TEMPERATURE WAFERS

Background

[0001] Some devices formed on or in semiconductor substrates are more sensitive to heat than others. In fact, some of these device may be damaged or destroyed if exposed to heat resulting from processes used to form other devices.

Brief Description of the Drawings

[0002] FIG. 1 is a simplified cross-sectional view of an integrated circuit device, according to some embodiments.

[0003] FIG. 2 is a simplified cross-sectional view of a memory device, according to some embodiments.

[0004] FIG. 3 is a simplified flowchart illustrating a method of manufacturing a semiconductor device.

[0005] FIG. 4 illustrates an interposer that includes one or more embodiments of the disclosure.

[0006] FIG. 5 illustrates a computing device in accordance with one embodiment of the disclosure.

Detailed Description

[0007] Described herein are systems and methods of bonding together semiconductor wafers that have non-compatible temperature characteristics. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the disclosure may be practiced without the specific details. In other instances, well- known features are omitted or simplified in order not to obscure the illustrative implementations.

[0008] Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the disclosure. The order of the description, however, should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

[0009] The terms“over,”“under,”“between,” and“on,” as used herein, refer to a relative position of one material (e.g., region, structure, layer, etc.) or component with respect to other materials (e.g., regions, structures, layers, etc.) or components. For example, one material disposed over, on, or under another material may be directly in contact with the other material or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two materials or may have one or more intervening materials. Moreover, to the extent that the terms“over,”“under,” and“on” imply a vertical orientation of materials, components, or combinations thereof, it is contemplated within the scope of the disclosure that these materials, components, or combinations thereof may also be oriented horizontally, at some non-vertical and non-horizontal orientation, some non-linear orientation, or at some angular orientation without departing from the scope of the disclosure.

[0010] Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the

semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In other implementations, the

semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the disclosure.

[0011] Cross-point phase-change memory has a low temperature budget. For example, a typical backend phase-change material has lower temperature

parameters (e.g., selector of about 300° C, memory of about 380° C). In contrast, complementary metal oxide semiconductor (CMOS) may be manufactured using four hundred degrees Celsius (400° C) forming gas anneal (FGA) processing. As a result, manufacturing such CMOS device structures on a wafer that includes phase- change materials would damage the phase-change materials. As a result, it is difficult to integrate phase-change materials with scaled CMOS devices.

[0012] Older technologies that do not use high temperature processes may be used to form CMOS devices on the same wafer as phase-change materials. For example, where a back end interlayer dielectric is relaxed, CMOS devices may be used. This, however, compromises the use of phase-change memory technology as embedded non-volatile memory (eNVM) because such CMOS devices are not compact enough for use in eNVM. Also, such CMOS devices may not be used in enhanced dynamic random access memory (eDRAM). As a result, phase-change memory may be limited to use as a storage class memory because more modern, scaled CMOS devices are manufactured using temperatures that would damage phase-change materials.

[0013] Disclosed herein are integrated circuit devices, memory devices, and computing devices including low temperature wafers bonded to and electrically connected to high temperature wafers, and related methods. One use case for this technology would be bonding and electrically connecting a first wafer including one or more phase-change memory elements (e.g., an array of phase-change memory elements, a three-dimensional cross-point array of phase-change memory elements, a two-dimensional cross-point array of phase-change memory elements, a non- cross-point memory array, etc.) to a second wafer including modern, scaled CMOS devices formed using temperatures that would damage the phase-change memory elements if formed on the same wafer. As a result, phase-change memory according to some embodiments of the disclosure may be used for eNVM and/or eDRAM, not just storage class memory. Also, this enables hybrid integration of heterogeneous systems for fast storage-class memory.

[0014] Moreover, disclosed herein are integrated circuit devices, memory devices, and computing devices including wafers having different pitches bonded together and electrically connected together. As a result, disclosed herein are devices that include wafers bonded and electrically connected together, wherein the wafers are not temperature compatible, are not pitch compatible, or combinations thereof.

[0015] In some embodiments, disclosed herein are low-temperature processed memory wafers bonded to scaled CMOS wafers, which support R/W periphery. In some embodiments, electrical connection between the low-temperature processed memory wafers may be made only at the array periphery. Accordingly, strong alignment may not be used (e.g., 90-180 nanometer pitch alignment may be used).

[0016] FIG. 1 is a simplified cross-sectional view of an integrated circuit device 100, according to some embodiments. The integrated circuit device 100 includes a first wafer 110 including one or more first devices 112 (sometimes referred to herein simply as“first devices” 112 or“devices” 112) formed therein or thereon. The first devices 112 are susceptible to damage responsive to exposure to temperatures above a predetermined threshold temperature. For example, a maximum

non-operating temperature threshold of the first devices 112 may be the

predetermined threshold temperature. As a result, the first wafer 110 may include a low temperature processed wafer (e.g., a low-temperature processed memory wafer). The integrated circuit device 100 also includes a second wafer 120 including one or more second devices 122 (sometimes referred to herein simply as“second devices” 122 or“devices” 122) formed therein or thereon. The second devices 122 were formed at least by heating the second wafer 120 above the predetermined threshold temperature over which the first devices 112 are susceptible to damage. For example, a maximum manufacturing temperature of the second devices 122 is higher than the predetermined threshold temperature. The second wafer 120 is bonded to and electrically connected to the first wafer 110. Although illustrated herein as the second wafer 120 being bonded on top of the first wafer 110, it is contemplated herein that the first wafer 110 may be bonded on top of the second wafer 120 without departing from the scope of the disclosure.

[0017] In some embodiments, the first devices 112 of the first wafer 110 include one or more memory cells. By way of non-limiting example, the first devices 112 may include phase-change memory cells (P-RAM), resistive random access memory (RRAM) cells, ferroelectric RAM (FRAM) cells, magneto-resistive RAM (MRAM), Flash memory cells, capacitive memory cells, programmable read only memory (PROM such as electrically erasable programmable read only memory (EEPROM)) cells, other memory cells, or combinations thereof. In some embodiments, the first devices 112 may include a three-dimensional cross-point memory array of any of the above-mentioned memory technologies. In some embodiments, the first devices 112 may include a two-dimensional cross-point memory array of any of the above-mentioned memory technologies. In some embodiments, the first devices 112 may include a non-cross-point memory array of any of the above-mentioned memory technologies. In some embodiments, the first wafer 110 is electrically connected to the second wafer 120 via structures comprising electrically conductive material at a periphery of the memory array.

[0018] The predetermined threshold temperature over which the first devices 112 are susceptible to damage may depend on materials that the first devices 112 include. For example, the first devices 112 may include phase-change memory materials (e.g., chalcogenide glass) that may be damaged if heated above 150° C to 350° C (e.g., 300° C), depending on the phase-change materials. Also, the first devices 112 may include a ferroelectric capacitor that may be damaged if heated above 400° C. Furthermore, the first devices 112 may include a metal oxide or chalcogenide based select device that may be damaged if heated above 100° C to 200° C.

[0019] In some embodiments, the second devices 122 include a complementary metal oxide semiconductor (CMOS) device. By way of non-limiting example, the second devices 122 may include a memory controller, memory access circuitry, processing circuitry, other CMOS circuitry, or combinations thereof. In some embodiments, the second devices 122 may include circuitry configured to control access to the one or more memory cells of the first wafer 110. In some

embodiments, the second devices 122 may be formed using at least one heating (e.g., annealing) process that heats the second devices 122 to at or above four hundred degrees Celsius (400° C). By way of non-limiting example, the second devices 122 may be formed using a 400° C forming gas anneal (FGA). Also by way of non-limiting example, the second devices 122 may be formed using a 400° C etchstop layer deposition process. As a further non-limiting example, the second devices 122 may be formed using a 400° C etchstop interlayer dielectric layer deposition.

[0020] In some embodiments, the first devices 112 of the first wafer 110 include memory cells, and the second devices 122 of the second wafer 120 include selection switches (e.g., transistors) configured to select the memory cells during a memory access operation. By way of non-limiting example, individual ones of the memory cells may have individual ones of the selection switches connected thereto. The selection switches that correspond to the memory cells may be located in a position vertically offset (e.g., under or over, with or without intervening metal layers of back end structures) from the memory cells that correspond thereto. [0021] In some embodiments, the second devices 122 of the second wafer 120 include memory devices that have a higher temperature tolerance than memory devices of the first devices 112 of the first wafer 110. By way of non-limiting example, the first wafer 110 may be a phase-change memory wafer and the second wafer 120 may include a dynamic RAM (DRAM) wafer.

[0022] In some embodiments, the first wafer 110 may be bonded to the second wafer 120 using pins (not shown). In some embodiments, the first wafer 110 may be bonded to the second wafer 120 using an intervening bond material that is annealed to the first wafer 110 and the second wafer 120. In some embodiments, conductive pads on a top of the second wafer 120 may be lined up with conductive pads on a bottom of the first wafer 110, and pressure and heat may be applied to bond the conductive pads together. Regardless, to the extend an anneal or heat process is applied in bonding the first wafer 110 to the second wafer 120, the integrated circuit device 100 may not be heated above the predetermined threshold temperature.

[0023] FIG. 2 is a simplified cross-sectional view of a memory device 200, according to some embodiments. The memory device 200 includes a high

temperature wafer 220 bonded to a low temperature wafer 210. The high

temperature wafer 220 includes one or more complementary metal oxide

semiconductor (CMOS) devices 222 (sometimes referred to herein simply as“CMOS devices” 222) therein or thereon. The low temperature wafer 210 includes one or more memory cells 212 (sometimes referred to herein simply as“memory cells” 212) therein or thereon. An annealing temperature that was used to form the CMOS devices 222 of the high temperature wafer 220 would damage the memory cells 212 of the low temperature wafer 210.

[0024] In some embodiments, the memory cells 212 include a three-dimensional cross-point memory array, a two-dimensional cross point memory array, or a non-cross-point memory array. The embodiment illustrated in FIG. 2 illustrates a cross-point memory array. For example, the memory cells 212 include memory elements 214 that are connected between an access line 217 (e.g., a bit line extending left to right in FIG. 2) and individual access lines 216 (e.g., word lines extending into and out of the page). The memory cells 212 may also include an electrically insulating material 218.

[0025] In some embodiments, the memory cells 212 of the low temperature wafer 210 include phase-change memory cells. In such embodiments, the memory elements 214 may include one or more phase-change materials. In some

embodiments, the memory cells 212 may include phase-change memory cells (P- RAM), resistive random access memory (RRAM) cells, ferroelectric RAM (FRAM) cells, magneto-resistive RAM (MRAM), Flash memory cells, capacitive memory cells, programmable read only memory (PROM such as electrically erasable

programmable read only memory (EEPROM)) cells, spin torque transfer (STT) memory cells, other memory cells, or combinations thereof.

[0026] In some embodiments, the low temperature wafer 210 includes at least one structure 219 comprising electrically conductive material at a peripheral edge of the array of memory cells 212. The structure 219 is configured to electrically connect the low temperature wafer 210 to the high temperature wafer 220.

[0027] In some embodiments, the CMOS devices 222 of the high temperature wafer 220 include circuitry configured to control access to the memory cells 212 of the low temperature wafer 210. By way of non-limiting example, the CMOS devices 222 may include access transistors. In some embodiments, individual ones of the memory elements 214 may correspond to individual ones of the access transistors.

In some embodiments, these access transistors may be vertically offset from the corresponding ones of the memory elements 214. These access transistors may be connected to the memory cells 212 using vertical conductive structures that extend from the access transistors to the memory elements 214. In some embodiments, the CMOS devices 222 may include other access circuitry, such as sense amplifiers, decoders (e.g., column decoders, row decoders, etc.), a memory controller, a processor, other circuitry, or combinations thereof.

[0028] In some embodiments, the memory device 200 includes an interconnect structure 230 including metal layers 232, 234, and 236 and interlayer dielectric 238. The interconnect structure 230 is configured to electrically connect the low

temperature wafer 210 to the high temperature wafer 220.

[0029] FIG. 3 is a simplified flowchart illustrating a method 300 of manufacturing a semiconductor device (e.g., the integrated circuit device 100 of FIG. 1 , the memory device 200 of FIG. 2, etc.), according to some embodiments. The method 300 includes forming 310 one or more first devices on or in a first wafer according to a first process that does not subject the first wafer to a temperature greater than a predetermined threshold temperature. The one or more first devices may be susceptible to damage if exposed to temperatures that exceed the predetermined threshold temperature. In some embodiments, forming 310 includes forming, on or in the first wafer, one or more memory elements selected from the group consisting of phase-change memory (P RAM) elements, resistive random access memory (RRAM) elements, ferroelectric RAM (FRAM) elements, magneto-resistive RAM (MRAM) elements, transistor-based memory elements, capacitive memory elements, and electrically erasable programmable read only memory (EEPROM) elements, spin torque transfer (STT) memory elements, or combinations thereof.

[0030] The method 300 also includes forming 320 one or more second devices on or in a second wafer according to a second process that subjects the second wafer to temperatures greater than the predetermined threshold temperature. In some embodiments, forming 320 one or more second devices on or in a second wafer according to a second process comprises forming the one or more second devices using a four hundred degrees Celsius (400° C) process (e.g., a 400° C forming gas anneal (FGA), a 400° C etchstop layer deposition process, a 400° C etchstop interlayer dielectric layer deposition, etc.). In some embodiments, forming 320 one or more second devices on or in a second wafer comprises forming a complementary metal oxide semiconductor (CMOS) device on or in the second wafer.

[0031] The method 300 further includes bonding 330 the first wafer to the second wafer. In some embodiments, bonding 330 the first wafer to the second wafer includes electrically connecting the first wafer to the second wafer. In some embodiments, electrically connecting the first wafer to the second wafer comprises aligning conductive pads of the first wafer with conductive pads of the second wafer, and applying the first wafer to the second wafer (e.g., in an inverted or a

non-inverted orientation, depending on whether the conductive pads of the first wafer are on the top or bottom of the first wafer). Pressure and/or heat may then be applied to bond the first wafer to the second wafer. In some embodiments where the first wafer includes a memory array, bonding 330 the first wafer to the second wafer includes electrically connecting the first wafer to the second wafer using structures including electrically conductive materials at a periphery of the memory array. In some embodiments, bonding 330 the first wafer to the second wafer includes bonding a memory array wafer to a CMOS wafer (e.g., a COMS memory control circuitry wafer). [0032] In some embodiments, a CMOS wafer may include a plurality of

transistors. The plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the disclosure, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.

Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as

nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the disclosure may also be carried out using nonplanar transistors.

[0033] Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.

[0034] The gate electrode is formed on the gate dielectric and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some

implementations, the gate electrode may consist of a stack of two or more metals, where one or more metals are workfunction metals and at least one metal is a fill metal. Further metals may be included for other purposes, such as a barrier material.

[0035] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[0036] In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially

perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may include a

combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metals formed atop one or more planar, non-U-shaped materials.

[0037] In some implementations of the disclosure, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0038] As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. In further embodiments, one or more metals and/or metal alloys may be used to form the source and drain regions.

[0039] One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials.

Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si0₂), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

[0040] FIG. 4 illustrates an interposer 1000 that includes one or more

embodiments of the disclosure. The interposer 1000 is an intervening substrate used to bridge a first substrate 1002 to a second substrate 1004. The first substrate 1002 may be, for instance, an integrated circuit die. The second substrate 1004 may be, for instance, a memory module (e.g., the integrated circuit device 100 of FIG. 1 or the memory device 200 of FIG. 2), a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1000 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006 that can subsequently be coupled to the second substrate 1004. In some

embodiments, the first and second substrates 1002/1004 are attached to opposing sides of the interposer 1000. In other embodiments, the first and second substrates 1002/1004 are attached to the same side of the interposer 1000. And in further embodiments, three or more substrates are interconnected by way of the interposer 1000. [0041] The interposer 1000 may be formed of an epoxy resin, a

fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.

[0042] The interposer may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012. The interposer 1000 may further include embedded devices 1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and

electrostatic discharge (ESD) devices. More complex devices such as

radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1000.

[0043] In accordance with embodiments of the disclosure, the first substrate 1002, the second substrate 1004, or the interposer 1000 may include the integrated circuit device 100 of FIG. 1 or the memory device 200 of FIG. 2.

[0044] FIG. 5 illustrates a computing device 1200 in accordance with one embodiment of the disclosure. The computing device 1200 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices. The components in the computing device 1200 include, but are not limited to, an integrated circuit die 1202 and at least one communications chip 1208 (also referred to herein as“communications logic unit” 1208). In some implementations the communications chip 1208 is fabricated within the integrated circuit die 1202 while in other implementations the communications logic unit 1208 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1202. The integrated circuit die 1202 may include a processor 1204 (e.g., a CPU) as well as on- die memory 1206, often used as cache memory, which can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT-MRAM). [0045] Computing device 1200 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1210 (e.g., DRAM), non-volatile memory 1212 (e.g., ROM or flash memory), a graphics processing unit (GPU) 1214, a digital signal processor (DSP) 1216, a crypto processor 1242 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 1220, at least one antenna 1222 (in some

implementations two or more antennas may be used), a display or a touchscreen display 1224, a touchscreen display controller 1226, a battery 1229 or other power source (not shown), a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1228, a compass (not shown), one or more motion sensors 1232 (e.g., a motion coprocessor such as an accelerometer, a gyroscope, a compass, etc.), a microphone (not shown), a speaker 1234, a camera 1236, user input devices 1238 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 1240 (such as a hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 1200 may

incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device 1200 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 1200 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.

[0046] The communications chip 1208 may include a communications logic unit configured to transfer data to and from the computing device 1200. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communications logic unit 1208 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM,

GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1200 may include a plurality of communications chips 1208. For instance, a first communications chip 1208 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth, and a second communications chip 1208 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0047] The processor 1204 of the computing device 1200 includes one or more devices, such as the integrated circuit device 100 of Fig. 1 or the memory device 200 of FIG. 2 (e.g., on-board memory). The term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0048] The communications logic unit 1208 may also include one or more devices, such as the integrated circuit device 100 of FIG. 1 or the memory device 200 of FIG. 2, that are formed in accordance with embodiments of the disclosure.

[0049] In further embodiments, another component housed within the computing device 1200 may contain one or more devices, such as the integrated circuit device 100 of FIG. 1 or the memory device 200 of FIG. 2, that are formed in accordance with implementations of the disclosure.

[0050] In various embodiments, the computing device 1200 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further

implementations, the computing device 1200 may be any other electronic device that processes data.

[0051] In some embodiments, a computing device includes an integrated circuit structure. The integrated circuit structure includes a low temperature wafer and a high temperature wafer. The low temperature wafer is bonded to and electrically connected to the high temperature wafer. The low temperature wafer includes one or more low temperature electronic devices that would be damaged if exposed to temperatures above a predetermined threshold temperature. The high temperature wafer includes one or more high temperature electronics that were formed using temperatures above the predetermined threshold temperature. The computing device further includes a processor mounted on a substrate, a memory unit capable of storing data, a graphics processing unit, an antenna within the computing device, a display on the computing device, a battery within the computing device, a power amplifier within the processor, and a voltage regulator within the processor. At least one of the processor, the memory unit, the graphics processing unit, the antenna, the display, the battery, the power amplifier, or the voltage regulator includes the semiconductor device structure.

Examples

[0052] The following is a non-exhaustive list of example embodiments that fall within the scope of the disclosure. In order to avoid complexity in providing the disclosure, not all of the examples listed below are separately and explicitly disclosed as having been contemplated herein as combinable with all of the others of the examples listed below and other embodiments disclosed hereinabove. Unless one of ordinary skill in the art would understand that these examples listed below, and the above disclosed embodiments, are not combinable, it is contemplated within the scope of the disclosure that such examples and embodiments are combinable.

[0053] Example 1 : An integrated circuit device, comprising: at least a portion of a first wafer including one or more first devices formed therein or thereon, the one or more first devices having a maximum non-operating temperature threshold of a predetermined threshold temperature; and at least a portion of a second wafer including one or more second devices formed therein or thereon, the at least the portion of the second wafer bonded to and electrically connected to the at least the portion of the first wafer, the one or more second devices having a maximum manufacturing temperature above the predetermined threshold temperature.

[0054] Example 2: The integrated circuit device of Example 1 , wherein the one or more first devices of the first wafer include one or more memory cells.

[0055] Example 3: The integrated circuit device according to any one of

Examples 1 and 2, wherein the one or more first devices of the first wafer include one or more phase-change memory cells.

[0056] Example 4: The integrated circuit device according to any one of

Examples 1 -3, wherein the first wafer comprises a low temperature processed wafer. [0057] Example 5: The integrated circuit device according to any one of

Examples 1 -4, wherein the first wafer comprises a low temperature processed memory wafer.

[0058] Example 6: The integrated circuit device according to any one of

Examples 1 -5, wherein the first wafer comprises a three-dimensional cross-point memory array.

[0059] Example 7: The integrated circuit device according to any one of

Examples 1 -6, wherein the first wafer comprises a three-dimensional cross-point phase-change memory array.

[0060] Example 8: The integrated circuit device of Example 7, wherein the first wafer is electrically connected to the second wafer via structures comprising electrically conductive material at a periphery of the three-dimensional cross-point phase-change memory array.

[0061] Example 9: The integrated circuit device according to any one of

Examples 1 -8, wherein the one or more second devices comprise a complementary metal oxide semiconductor (CMOS) device.

[0062] Example 10: The integrated circuit device according to any one of

Examples 1 -9, wherein the predetermined threshold temperature is about three hundred degrees Celsius (300° C).

[0063] Example 11 : The integrated circuit device according to any one of

Examples 1 -10, wherein the one or more second devices are formed using a four hundred degrees Celsius (400° C) process.

[0064] Example 12: A memory device, comprising: at least a portion of a high temperature wafer including one or more complementary metal oxide semiconductor (CMOS) devices therein or thereon; and at least a portion of a low temperature wafer including one or more memory cells therein or thereon, the at least the portion of the low temperature wafer bonded to the at least the portion of the high temperature wafer, wherein an annealing temperature of the one or more CMOS devices of the at least the portion of the high temperature wafer is greater than a maximum non- operating temperature threshold of the one or more memory cells of the at least the portion of the low temperature wafer.

[0065] Example 13: The memory device of Example 12, wherein the one or more memory cells of the low temperature wafer include an array of phase-change memory cells. [0066] Example 14: The memory device according to any one of Examples 12 and 13, wherein the one or more memory cells include a three-dimensional cross- point memory array, a two-dimensional cross point memory array, or a non-cross- point memory array.

[0067] Example 15: The memory device according to any one of Examples 12-14, wherein the one or more memory cells include a three-dimensional cross-point memory array, a two-dimensional cross-point memory array, or a non-cross-point array of phase-change memory cells.

[0068] Example 16: The memory device according to any one of Examples 12-15, wherein the one or more CMOS devices of the high temperature wafer comprise circuitry configured to control access to the one or more memory cells of the low temperature wafer.

[0069] Example 17: The memory device according to any one of Examples 12-16, wherein the at least the portion of the low temperature wafer includes at least one structure comprising electrically conductive material at a peripheral edge of an array of the one or more memory cells, the at least one structure configured to electrically connect the at least the portion of the low temperature wafer to the at least the portion of the high temperature wafer.

[0070] Example 18: The memory device according to any one of Examples 12-17, wherein the at least the portion of the low temperature wafer includes structures comprising electrically conductive material for individual ones of the one or more memory cells that extend from the individual ones of the one or more memory cells to individual switch devices of the at least the portion of the high temperature wafer and electrically connect the individual ones of the one or more memory cells to the individual switch devices, wherein the individual switch devices are vertically offset from the individual memory cells.

[0071] Example 19: A method of manufacturing a semiconductor device, the method comprising: forming one or more first devices on or in a first wafer according to a first process that does not subject the first wafer to a temperature greater than a predetermined threshold temperature; forming one or more second devices on a second wafer according to a second process that subjects the second wafer to temperatures greater than the predetermined threshold temperature; and bonding the first wafer to the second wafer. [0072] Example 20: The method of Example 19, further comprising electrically connecting the first wafer to the second wafer.

[0073] Example 21 : The method according to any one of Examples 19 and 20, wherein forming one or more first devices on or in a first wafer comprises forming, on or in the first wafer, one or more memory elements selected from the group consisting of phase-change memory (P RAM) elements, resistive random access memory (RRAM) elements, ferroelectric RAM (FRAM) elements, magneto-resistive RAM (MRAM) elements, transistor-based memory elements, capacitive memory elements, and electrically erasable programmable read only memory (EEPROM) elements.

[0074] Example 22: The method according to any one of Examples 19-21 , wherein forming one or more second devices on or in a second wafer according to a second process comprises forming the one or more second devices using a four hundred degrees Celsius (400° C) process.

[0075] Example 23: The method according to any one of Examples 19-22, wherein forming one or more second devices on or in a second wafer comprises forming a complementary metal oxide semiconductor (CMOS) device on or in the second wafer.

[0076] Example 24: A computing device comprising: an integrated circuit structure, comprising: at least a portion of a low temperature wafer including one or more low temperature electronic devices having a maximum non-operating temperature threshold equal to a predetermined threshold temperature; and at least a portion of a high temperature wafer including one or more high temperature electronics having a maximum manufacturing temperature above the predetermined threshold temperature, the at least the portion of the low temperature wafer bonded to and electrically connected to the at least the portion of the high temperature wafer.

[0077] Example 25: The computing device of Example 24, further comprising: a processor mounted on a substrate; a memory unit capable of storing data; a graphics processing unit; an antenna within the computing device; a display on the computing device; a battery within the computing device; a power amplifier within the processor; and a voltage regulator within the processor; wherein at least one of the processor, the memory unit, the graphics processing unit, the antenna, the display, the battery, the power amplifier, or the voltage regulator comprises the integrated circuit structure. [0078] Example 26: A method of forming an integrated circuit device, the method comprising: forming one or more first devices on or in a first wafer, the one or more first devices having a maximum non-operating temperature threshold of a

predetermined threshold temperature; forming one or more second devices on or in a second wafer at least by heating the second wafer above the predetermined threshold temperature; and bonding and electrically connecting the second wafer to the first wafer.

[0079] Example 27: The method of Example 26, wherein forming one or more first devices on or in the first wafer includes forming one or more memory cells.

[0080] Example 28: The method according to any one of Examples 26 and 27, wherein forming one or more first devices on or in the first wafer includes forming one or more phase-change memory cells.

[0081] Example 29: The method according to any one of Examples 26-28, wherein forming one or more first device on or in the first wafer comprises

performing a low temperature process on the first wafer.

[0082] Example 30: The method according to any one of Examples 26-29, wherein forming one or more first device on or in the first wafer comprises

performing a low temperature process on the first wafer to form memory on or in the first wafer.

[0083] Example 31 : The method according to any one of Examples 26-30, wherein forming one or more first device on or in the first wafer comprises forming a three-dimensional cross-point memory array.

[0084] Example 32: The method according to any one of Examples 26-31 , wherein forming one or more first device on or in the first wafer comprises forming a three-dimensional cross-point phase change memory array.

[0085] Example 33: The method of Example 32, wherein electrically connecting the first wafer to the second wafer comprises electrically connecting the first wafer to the second wafer via structures comprising electrically conductive material at a periphery of the three-dimensional cross-point phase-change memory array.

[0086] Example 34: The method according to any one of Examples 26-33, wherein forming one or more second devices on or in a second wafer comprises forming a complementary metal oxide semiconductor (CMOS) device. [0087] Example 35: The method according to any one of Examples 26-34, wherein the predetermined threshold temperature is about three hundred degrees Celsius (300° C).

[0088] Example 36: The method according to any one of Examples 26-35, wherein forming one or more second devices on or in a second wafer comprises forming the one or more second devices using a four hundred degrees Celsius (400° C) process.

[0089] Example 37: A method of forming a memory device, the method

comprising: forming one or more complementary metal oxide semiconductor

(CMOS) devices on or in a high temperature wafer using an annealing temperature; forming one or more memory cells on or in a low temperature wafer; and bonding the low temperature wafer to the high temperature wafer, wherein the annealing temperature that was used to form the one or more CMOS devices of the high temperature wafer is greater than a maximum non-operating temperature threshold of the one or more memory cells of the low temperature wafer.

[0090] Example 38: The method of Example 37, wherein forming one or more memory cells on or in the low temperature wafer includes forming an array of phase-change memory cells.

[0091] Example 39: The method according to any one of Examples 37 and 38, wherein forming one or more memory cells on or in the low temperature wafer includes forming a three-dimensional cross point memory array, a two-dimensional cross point memory array, or a non cross point memory array.

[0092] Example 40: The method according to any one of Examples 37-39, wherein forming one or more memory cells on or in the low temperature wafer includes forming a three-dimensional cross-point memory array, a two-dimensional cross-point memory array, or a non-cross-point array of phase change memory cells.

[0093] Example 41 : The method according to any one of Examples 37-40, wherein forming one or more CMOS devices on or in a high temperature wafer comprises forming circuitry configured to control access to the one or more memory cells of the low temperature wafer.

[0094] Example 42: The method according to any one of Examples 37-41 , further comprising forming at least one structure comprising electrically conductive material at a peripheral edge of an array of the one or more memory cells, the at least one structure configured to electrically connect the low temperature wafer to the high temperature wafer.

[0095] Example 43: The method according to any one of Examples 37-42, further comprising forming structures comprising electrically conductive material for individual ones of the one or more memory cells, the structures extending from the individual memory cells to individual switch devices of the high temperature wafer and electrically connecting the individual ones of the one or more memory cells to the individual switch devices.

[0096] Example 44: A semiconductor device, comprising: one or more first devices formed on or in at least a portion of a first wafer, a maximum manufacturing temperature of the one or more first devices less than a predetermined threshold temperature; and one or more second devices formed on or in at least a portion of a second wafer, a maximum manufacturing temperature of the one or more second devices greater than the predetermined threshold temperature; wherein the first wafer is bonded to the second wafer.

[0097] Example 45: The semiconductor device of Example 44, wherein the at least the portion of the first wafer is electrically connected to the at least the portion of the second wafer.

[0098] Example 46: The semiconductor device according to any one of Examples 44 and 45, wherein the one or more first devices comprise one or more memory elements selected from the group consisting of phase-change memory (P RAM) elements, resistive random access memory (RRAM) elements, ferroelectric RAM (FRAM) elements, magneto-resistive RAM (MRAM) elements, transistor-based memory elements, capacitive memory elements, and electrically erasable

programmable read only memory (EEPROM) elements.

[0099] Example 47: The semiconductor device according to any one of Examples 44-46, wherein the one or more second devices were formed using a four hundred degrees Celsius (400° C) process.

[0100] Example 48: The semiconductor device according to any one of Examples 44-47, wherein the one or more second devices comprise a complementary metal oxide semiconductor (CMOS) device.

[0101] Example 49: A method of operating a computing device, the method comprising: operating an integrated circuit structure comprising: at least a portion of a low temperature wafer including one or more low temperature electronic devices having a maximum non-operating temperature threshold equal to a predetermined threshold temperature; and at least a portion of a high temperature wafer including one or more high temperature electronics having a maximum manufacturing temperature above the predetermined threshold temperature, the at least the portion of the low temperature wafer bonded to and electrically connected to the at least the portion of the high temperature wafer.

[0102] Example 50: The method of Example 49, further comprising: operating a processor mounted on a substrate; operating a memory unit capable of storing data; operating a graphics processing unit; operating an antenna within the computing device; operating a display on the computing device; operating a battery within the computing device; operating a power amplifier within the processor; and operating a voltage regulator within the processor; wherein at least one of the processor, the memory unit, the graphics processing unit, the antenna, the display, the battery, the power amplifier, or the voltage regulator comprises the integrated circuit structure.

[0103] Example 51 : A computer-readable storage medium having computer- readable instructions stored thereon, the computer-readable instructions configured to instruct on or more processors to perform at least a portion of the method according to any one of Examples 19-23, 26-43, 49, and 50.

[0104] Example 52: A means for performing at least a portion of the method according to any one of Examples 19-23, 26-43, 49, and 50.

Conclusion

[0105] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

Claims

1. An integrated circuit device, comprising:

at least a portion of a first wafer including one or more first devices formed therein or thereon, the one or more first devices having a maximum non-operating temperature threshold of a predetermined threshold temperature; and

at least a portion of a second wafer including one or more second devices formed therein or thereon, the at least the portion of the second wafer bonded to and electrically connected to the at least the portion of the first wafer, the one or more second devices having a maximum manufacturing temperature above the

predetermined threshold temperature.

2. The integrated circuit device of claim 1 , wherein the one or more first devices of the first wafer include one or more memory cells.

3. The integrated circuit device of claim 1 , wherein the one or more first devices of the first wafer include one or more phase-change memory cells.

4. The integrated circuit device of claim 1 , wherein the first wafer comprises a low temperature processed wafer.

5. The integrated circuit device of claim 1 , wherein the first wafer comprises a low temperature processed memory wafer.

6. The integrated circuit device of claim 1 , wherein the first wafer comprises a three-dimensional cross-point memory array.

7. The integrated circuit device of claim 1 , wherein the first wafer comprises a three-dimensional cross-point phase-change memory array.

8. The integrated circuit device of claim 7, wherein the first wafer is electrically connected to the second wafer via structures comprising electrically conductive material at a periphery of the three-dimensional cross-point phase- change memory array.

9. The integrated circuit device according to any one of claims 1-8, wherein the one or more second devices comprise a complementary metal oxide semiconductor (CMOS) device.

10. The integrated circuit device according to any one of claims 1-8, wherein the predetermined threshold temperature is about three hundred degrees Celsius (300° C).

11. The integrated circuit device according to any one of claims 1-8, wherein the one or more second devices are formed using a four hundred degrees Celsius (400° C) process.

12. A memory device, comprising:

at least a portion of a high temperature wafer including one or more complementary metal oxide semiconductor (CMOS) devices therein or thereon; and at least a portion of a low temperature wafer including one or more memory cells therein or thereon, the at least the portion of the low temperature wafer bonded to the at least the portion of the high temperature wafer, wherein an annealing temperature of the one or more CMOS devices of the high temperature wafer is greater than a maximum non-operating temperature threshold of the one or more memory cells of the at least the portion of the low temperature wafer.

13. The memory device of claim 12, wherein the one or more memory cells of the low temperature wafer include an array of phase-change memory cells.

14. The memory device of claim 12, wherein the one or more memory cells include a three-dimensional cross-point memory array, a two-dimensional cross-point memory array, or a non-cross-point memory array.

15. The memory device of claim 12, wherein the one or more memory cells include a three-dimensional cross-point memory array, a two-dimensional cross- point memory array, or a non-cross-point array of phase-change memory cells.

16. The memory device according to any one of claims 12-15, wherein the one or more CMOS devices of the high temperature wafer comprise circuitry configured to control access to the one or more memory cells of the low temperature wafer.

17. The memory device according to any one of claims 12-15, wherein the at least the portion of the low temperature wafer includes at least one structure comprising electrically conductive material at a peripheral edge of an array of the one or more memory cells, the at least one structure configured to electrically connect the at least the portion of the low temperature wafer to the at least the portion of the high temperature wafer.

18. The memory device according to any one of claims 12-15, wherein the at least the portion of the low temperature wafer includes structures comprising electrically conductive material for individual ones of the one or more memory cells that extend from the individual ones of the one or more memory cells to individual switch devices of the at least the portion of the high temperature wafer and electrically connect the individual ones of the one or more memory cells to the individual switch devices, wherein the individual switch devices are vertically offset from the individual memory cells.

19. A method of manufacturing a semiconductor device, the method comprising:

forming one or more first devices on or in a first wafer according to a first process that does not subject the first wafer to a temperature greater than a predetermined threshold temperature;

forming one or more second devices on a second wafer according to a second process that subjects the second wafer to temperatures greater than the predetermined threshold temperature; and

bonding the first wafer to the second wafer.

20. The method of claim 19, further comprising electrically connecting the first wafer to the second wafer.

21. The method of claim 19, wherein forming one or more first devices on or in a first wafer comprises forming, on or in the first wafer, one or more memory elements selected from the group consisting of phase-change memory (P-RAM) elements, resistive random access memory (RRAM) elements, ferroelectric RAM (FRAM) elements, magneto-resistive RAM (MRAM) elements, transistor-based memory elements, capacitive memory elements, and electrically erasable

programmable read only memory (EEPROM) elements.

22. The method according to any one of claims 19-21 , wherein forming one or more second devices on or in a second wafer according to a second process comprises forming the one or more second devices using a four hundred degrees Celsius (400° C) process.

23. The method according to any one of claims 19-21 , wherein forming one or more second devices on or in a second wafer comprises forming a

complementary metal oxide semiconductor (CMOS) device on or in the second wafer.

24. A computing device comprising:

an integrated circuit structure, comprising: at least a portion of a low temperature wafer including one or more low temperature electronic devices having a maximum non-operating temperature threshold equal to a predetermined threshold temperature; and

at least a portion of a high temperature wafer including one or more high temperature electronics having a maximum manufacturing temperature above the predetermined threshold temperature, the at least the portion of the low temperature wafer bonded to and electrically connected to the at least the portion of the high temperature wafer.

25. The computing device of claim 24, further comprising:

a processor mounted on a substrate;

a memory unit capable of storing data;

a graphics processing unit;

an antenna within the computing device;

a display on the computing device;

a battery within the computing device;

a power amplifier within the processor; and

a voltage regulator within the processor;

wherein at least one of the processor, the memory unit, the graphics processing unit, the antenna, the display, the battery, the power amplifier, or the voltage regulator comprises the integrated circuit structure.