WO2019128845A1 - 栅极驱动单元电路、栅极驱动电路和显示装置 - Google Patents

栅极驱动单元电路、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2019128845A1
WO2019128845A1 PCT/CN2018/122431 CN2018122431W WO2019128845A1 WO 2019128845 A1 WO2019128845 A1 WO 2019128845A1 CN 2018122431 W CN2018122431 W CN 2018122431W WO 2019128845 A1 WO2019128845 A1 WO 2019128845A1
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Prior art keywords
thin film
film transistor
control node
stage
pull
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PCT/CN2018/122431
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English (en)
French (fr)
Inventor
黄洪涛
戴超
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南京中电熊猫平板显示科技有限公司
南京中电熊猫液晶显示科技有限公司
南京华东电子信息科技股份有限公司
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Priority to US16/957,960 priority Critical patent/US20200372873A1/en
Publication of WO2019128845A1 publication Critical patent/WO2019128845A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular, to a gate driving unit circuit, a gate driving circuit, and a display device.
  • the integrated gate scan driver (Gate Driver Monolithic, GDM) is a technology that utilizes the existing thin film transistor array substrate manufacturing process to directly build the gate scan drive circuit on the array substrate, which reduces cost and reduces process flow. Reduce the width of the panel border.
  • GDM Gate Driver Monolithic
  • FIG. 1 is a circuit diagram of a gate drive unit circuit having a positive and negative sweep function, the gate drive unit circuit including a pull-up control module for controlling positive and negative sweeps, a pull-up module 2, and a control node generating module. 4.
  • Pull-up control node maintenance module 5 output node maintenance module 6, emptying module 7, auxiliary maintenance module 8, and bootstrap capacitor C1.
  • the pull-up control module 1 and the maintenance control node generating module 4 are both controlled by the signals in the pre-stage and post-stage gate drive unit circuits, and have symmetry.
  • the thin film transistors M1 and M9 in the pull-up control module 1 are symmetric and maintained.
  • the thin film transistors M5 and M7 in the control node generating module 4 are symmetrical.
  • the scanning direction of the gate driving unit circuit controls the pair of mutually inverted constant voltage signals by the forward scanning control signal U2D and the reverse scanning control signal D2U, and U2D takes a high level, and D2U takes a low level to perform a forward direction. Scan, and vice versa.
  • U2D and D2U make the two thin film transistors M5 and M7 in the control node generating module 4 suffer from the opposite sign bias stress for a long time, resulting in a threshold voltage drift in the opposite direction, which is lowered after switching the scanning direction.
  • the pull control node maintains the maintenance capability of the module 5, which reduces the reliability of the circuit and increases the complexity of the circuit.
  • the present invention provides a gate driving unit circuit, a gate driving circuit, and a display device, which can avoid the problem that the thin film transistor in the control node generating module is subjected to a bias voltage to generate a threshold voltage, and at any time The pull-up control node can be maintained to improve the reliability of the circuit.
  • a gate driving unit circuit which is adapted to perform multi-level connection to form a gate driving circuit, including a pull-up control module, a pull-up module, a pull-down module, a maintenance control node generating module, and an upper
  • the pull control node maintenance module and the output node maintenance module; the pull-up control module, the pull-up module, the maintenance control node generation module, and the pull-up control node maintenance module are connected to the pull-up control node of the current level; the pull-up module and the output node maintenance module Connected to the scanning signal line of this stage;
  • the pull-up control node maintains the module connected to the front-stage gate driving unit circuit and maintains the control node generating module's pre-maintaining control node and
  • the maintenance control node of the rear-stage gate drive unit circuit generates a control node for the subsequent stage of the module, and maintains the pull-up control node of the current stage under the control of the previous-stage maintenance control node and the subsequent-stage maintenance control node;
  • the pull-up control node maintains the module connection last clock signal and the rear-stage maintenance control node of the maintenance control node generating module of the rear-stage gate driving unit circuit, Maintaining the pull-up control node of the current level under the control of the last clock signal and the subsequent maintenance control node;
  • the pull-up control node maintains the module connecting the first bit clock signal and the pre-stage sustaining control node of the pre-stage gate driving unit circuit to maintain the control node generating module,
  • the first-stage pull-up control node is maintained under the control of the first-level clock signal and the pre-stage maintenance control node.
  • the maintenance control node generating module includes a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor;
  • the fifth thin film transistor is used for charging the maintenance control node of the current stage, the first path end is connected to the current level maintaining control node, and the control end and the second path end are inputting the first clock signal;
  • the sixth thin film transistor is used to prohibit the current stage from maintaining the output of the control node during the operation of the gate driving unit circuit of the current stage, and the control end is connected to the pull-up control node of the current stage, the first path end is connected to the low level, and the second path end is connected to the current Level maintenance control node;
  • the seventh thin film transistor is used to discharge the control node of the current stage, and the control terminal inputs the second clock signal, the first path end is connected to the low level, and the second path end is connected to the current level maintaining control node.
  • the maintenance control node generating module includes a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor;
  • the fifth thin film transistor is used for charging the maintenance control node of the current stage, and the control terminal inputs the first clock signal, the first path end is connected to the current level maintaining control node, and the second path end is connected to the high level;
  • the sixth thin film transistor is used to prohibit the current stage from maintaining the output of the control node during the operation of the gate driving unit circuit of the current stage, and the control end is connected to the pull-up control node of the current stage, the first path end is connected to the low level, and the second path end is connected to the current Level maintenance control node;
  • the seventh thin film transistor is used to discharge the control node of the current stage, and the control terminal inputs the second clock signal, the first path end is connected to the low level, and the second path end is connected to the current level maintaining control node.
  • the pull-up control node maintaining module includes an eighth thin film transistor and an eighteenth thin film transistor;
  • the control terminal of the eighth thin film transistor is connected to the front stage sustaining control node, the first path end is connected to the low level, and the second path end is connected to the pull-up control node of the current stage; wherein the eighth film of the first stage gate driving unit circuit
  • the control terminal of the transistor inputs the last clock signal
  • the control terminal of the eighteenth thin film transistor is connected to the rear stage sustaining control node, the first path end is connected to a low level, and the second path end is connected to the first stage pull-up control node; wherein, the first stage gate driving unit circuit is The control terminal of the eighteen thin film transistor inputs the first clock signal.
  • the pull-up control module includes a first thin film transistor and a sixteenth thin film transistor
  • the first thin film transistor is configured to precharge the pull-up control node of the current stage during forward scanning, and the control end is connected to the scan signal line of the front-stage gate drive unit circuit, and the first path end is connected to the pull-up control node of the first stage, The second path end is connected to a high level; wherein, the control end of the first thin film transistor of the first stage gate driving unit circuit inputs a positive sweep start signal;
  • the sixteenth thin film transistor is used for precharging the pull-up control node of the current stage in the reverse scan, and the control end is connected to the scan signal line of the gate drive unit circuit of the rear stage, and the first path end is connected to the pull-up control node of the current stage, The second path end is connected to a high level; wherein the control end of the sixteenth thin film transistor of the tail stage driving unit circuit inputs a back sweep enable signal.
  • the circuit further includes a level transfer node generating module;
  • the level transfer node generating module includes a thirteenth thin film transistor and a fourteenth thin film transistor; and the control end of the thirteenth thin film transistor is connected to the first stage pull-up a control node, the first path end and the second path end are respectively connected to the current level transmitting node and the first clock signal; the control end of the fourteenth thin film transistor is connected to the current level maintaining control node, and the first path end and the second path end respectively Connect a low level and a level pass node;
  • the pull-up control module includes a first thin film transistor and a sixteenth thin film transistor; a control end of the first thin film transistor is connected to a pre-stage pass node of the pre-gate drive unit circuit, and the first pass end is connected to the pull-up control of the first stage a node, the second path end is connected to a high level; a control end of the sixteenth thin film transistor is connected to a subsequent stage pass node in the rear stage gate drive unit circuit, and the first path end is connected to the first stage pull-up control node, and the second path is The terminal is connected to a high level.
  • the output node maintenance module includes an eleventh thin film transistor, the eleventh thin film transistor is used for maintaining the scan signal of the current stage, and the control end is connected to the second clock signal, the first path end and the first The two path ends are respectively connected to the low level and the scanning signal lines of the current level.
  • the output node maintenance module includes an eleventh thin film transistor, and the eleventh thin film transistor is used for maintaining the scanning signal of the current stage, and the control end is connected to the current level maintaining control node, and the first path end is The second path ends are respectively connected to the low level and the scanning signal lines of the current level.
  • the output node maintenance module includes an eleventh thin film transistor and a nineteenth thin film transistor, wherein the eleventh thin film transistor is used for maintaining the scanning signal of the current stage, and the control end is connected to the second clock signal.
  • the first path end and the second path end are respectively connected to the low level and the scanning signal line of the current stage; the control end of the nineteenth thin film transistor is connected to the current maintaining control node, and the first path end and the second path end are respectively connected to the low level and the present Level scan signal line.
  • the output node maintenance module includes an eleventh thin film transistor and a nineteenth thin film transistor;
  • a control terminal of the eleventh thin film transistor is connected to the front stage sustaining control node, and the first path end and the second path end are respectively connected to the low level and the current scanning signal line; and the control end of the nineteenth thin film transistor is connected to the rear stage The control node is maintained, and the first path end and the second path end are respectively connected to the low level and the scanning signal lines of the current level.
  • the circuit further includes a touch maintaining module;
  • the touch maintaining module includes a twelfth thin film transistor; the control end of the twelfth thin film transistor inputs a touch control signal, the first path end and the The two path ends are respectively connected to the low level and the scanning signal lines of the current level.
  • the pull-up module includes a tenth thin film transistor; the control end of the tenth thin film transistor is connected to the pull-up control node of the first stage, and the first path end and the second path end are respectively connected to the scan signal line of the current level And the first clock signal.
  • the pull-down module includes a ninth thin film transistor; a control terminal of the ninth thin film transistor inputs a second clock signal, and the first path end and the second path end are respectively connected to a low level and the first stage pull-up control node.
  • the circuit further includes an auxiliary sustaining module;
  • the auxiliary maintaining module includes a fourth thin film transistor and a seventeenth thin film transistor;
  • the control terminal of the fourth thin film transistor inputs a positive sweep start signal, and the first path end and the second path end are respectively connected to the low level and the first stage pull-up control node; wherein, the fourth thin film transistor of the first three stages of the gate drive unit circuit The control terminal inputs a low level;
  • the control terminal of the seventeenth thin film transistor inputs a reverse sweep enable signal, and the first path end and the second path end are respectively connected to a low level and a pull-up control node of the current stage; wherein, the seventeenth film of the last three stages of the gate drive unit circuit The control terminal of the transistor inputs a low level.
  • the circuit further includes a clearing module;
  • the emptying module includes a second thin film transistor, a third thin film transistor, and a twelfth thin film transistor;
  • the control terminal of the second thin film transistor inputs a clear signal, and the first path end and the second path end are respectively connected to the low level and the first stage pull-up control node;
  • the control terminal of the third thin film transistor inputs a clear signal, and the first path end and the second path end are respectively connected to the low level and the current level maintaining control node;
  • the control terminal of the twelfth thin film transistor inputs a clear signal, and the first path end and the second path end are respectively connected to the low level and the scanning signal lines of the current level.
  • the circuit further includes a clearing module;
  • the emptying module includes a second thin film transistor, a third thin film transistor, a twelfth thin film transistor, and a fifteenth thin film transistor;
  • the control terminal of the second thin film transistor inputs a clear signal, and the first path end and the second path end are respectively connected to the low level and the first stage pull-up control node;
  • the control terminal of the third thin film transistor inputs a clear signal, and the first path end and the second path end are respectively connected to the low level and the current level maintaining control node;
  • the control terminal of the twelfth thin film transistor inputs a clear signal, and the first path end and the second path end are respectively connected to the low level and the scanning signal lines of the current level;
  • the control terminal of the fifteenth thin film transistor inputs a clear signal, and the first path end and the second path end are respectively connected to the low level and the level pass node.
  • the circuit further includes a clearing module;
  • the emptying module includes a second thin film transistor and a third thin film transistor;
  • the control terminal of the second thin film transistor inputs a clear signal, and the first path end and the second path end are respectively connected to the low level and the first stage pull-up control node;
  • the control terminal of the third thin film transistor inputs a clear signal, and the first path end and the second path end are respectively connected to the low level and the current level maintaining control node.
  • a gate driving circuit comprising: the gate driving unit circuit of any one of the N stages described above, wherein N is an integer greater than 3;
  • the pull-up control node maintaining module of the nth-level gate driving unit circuit is respectively connected to the sustain control node generating module of the n-1th-level gate driving unit circuit and the n+1th-level gate a maintenance control node generating module of the driving unit circuit;
  • the pull-up control node of the n-th gate driving unit circuit maintains the module input last-bit clock signal, and is connected to the maintenance control node generating module of the n+1th-level gate driving unit circuit;
  • the pull-up control node of the nth-level gate driving unit circuit maintains the module input first-level clock signal, and connects the maintenance control node generating module of the n-1th-level gate driving unit circuit.
  • a display device comprising the gate drive circuit of any of the preceding embodiments.
  • the sustain control node generating module of each stage in the gate driving circuit of the embodiment of the present invention is responsible for controlling the pull-up control node maintaining module of the upper and lower stages, and the pull-up control node maintaining module of the same level is
  • the upper-level maintenance control node generating module and the next-level maintenance control node generating module perform control, and the pull-up control node maintaining module and the maintenance control node generating module have the same working state in the forward scanning and reverse scanning processes, It is possible to avoid the problem that the circuit function is disabled due to the threshold voltage drift caused by the bias voltage of the thin film transistor after switching the scanning direction, thereby improving the reliability of the circuit.
  • 1 is a circuit diagram of a gate drive unit circuit having a positive and negative sweep function
  • FIG. 2 is a circuit diagram of a gate driving unit circuit and a gate driving circuit formed according to an embodiment of the present invention
  • FIG. 3 is a circuit diagram of a gate driving unit circuit according to a first embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a gate driving unit circuit according to a second embodiment of the present invention.
  • FIG. 5 is a circuit diagram of a gate driving unit circuit according to a third embodiment of the present invention.
  • FIG. 6 is a schematic diagram of driving waveforms of the gate driving unit circuit shown in FIG. 5 during forward scanning;
  • FIG. 7 is a schematic diagram of driving waveforms of the gate driving unit circuit shown in FIG. 5 in reverse scanning;
  • FIG. 8 is a circuit diagram of a gate driving unit circuit according to a fourth embodiment of the present invention.
  • FIG. 9 is a circuit diagram of a gate driving unit circuit according to Embodiment 5 of the present invention.
  • FIG. 10 is a circuit diagram of a gate driving unit circuit according to Embodiment 6 of the present invention.
  • FIG. 11 is a circuit diagram of a gate driving unit circuit according to Embodiment 7 of the present invention.
  • FIG. 12 is a circuit diagram of a gate driving unit circuit according to an eighth embodiment of the present invention.
  • FIG. 13 is a schematic diagram showing driving waveforms of the gate driving unit circuit shown in FIG. 12 in forward scanning;
  • FIG. 14 is a schematic diagram showing driving waveforms of the gate driving unit circuit shown in FIG. 12 in reverse scanning;
  • Fig. 15 is a view showing an example of a liquid crystal display device employing a gate driving circuit of an embodiment of the present invention.
  • Gn scan signal of the nth gate drive unit circuit, netAn, pull-up control node, netBn, sustain control node, VGH, high level, VSS, low level, CKm, first clock signal, CKm+2 Second clock signal, CK1, first bit clock signal, CKM, last bit clock signal, Gn-1, scanning signal of the n-1th stage gate driving unit circuit, Gn+1, n+1th stage gate driving unit circuit Scan signal, CLR, clear reset signal, GSP1, positive sweep enable signal, GSP2, reverse sweep enable signal, Tn, stage pass node of the nth gate drive unit circuit, Tn-1, n-1th gate The level transfer node of the pole drive unit circuit, the pass node of the Tn+1, the n+1th stage gate drive unit circuit, the TC, the touch control signal.
  • CK1 is the first clock signal
  • CKM is recorded. It is the last clock signal, and takes CKm as the first clock signal and CKm+2 as the second clock signal.
  • the second clock signal is not limited to CKm+2, and the second clock signal may be CKm+3, CKm+4, and the like.
  • the equivalent of CK-1 is CK(M-1), the equivalent of CK0 is CKM, the equivalent of CK1 is CKM+1, and so on.
  • the first-stage gate driving unit circuit in the following embodiments refers to the first-stage gate driving unit circuit
  • the tail-level gate driving unit circuit is Refers to the Nth stage gate drive unit circuit
  • the nth stage gate drive unit circuit may be referred to as the present stage gate drive unit circuit
  • the n-1th stage gate drive unit The circuit may be referred to as a pre-gate drive unit circuit
  • the n+1th stage gate drive unit circuit may be referred to as a post-stage gate drive unit circuit.
  • the thin film transistors in the following embodiments each include a control terminal, a first path end and a second path end, wherein the control end is a gate, the first pass end is a source, and the second pass end is a drain, in an optional implementation In the mode, the first path end may also be a drain, and the second path end is a source.
  • the control terminal is at a high level, the first via end and the second via end are connected through the semiconductor layer, and the thin film transistor is turned on at this time.
  • the gate driving unit circuit is adapted to perform multi-stage connection to form a gate driving circuit, including a pull-up control module 1, a pull-up module 2, a pull-down module 3, a maintenance control node generating module 4, and a pull-up control.
  • the pull-up control module 1, the pull-up module 2, the maintenance control node generating module 4, and the pull-up control node maintaining module 5 are connected to the pull-up control node netAn; the pull-up module 2 and the output node maintaining module 6 are connected to the current-level scanning Signal line.
  • the pull-up control node maintaining module 5 is connected to the pre-stage gate driving unit circuit to maintain the control node generating module 4 of the preceding stage maintaining the control node and
  • the maintenance control node of the rear-stage gate drive unit circuit generates a control node for the subsequent stage of the module 4, and maintains the pull-up control node of the current stage under the control of the previous-stage maintenance control node and the subsequent-stage maintenance control node;
  • the pull-up control node maintaining module 5 is connected to the last-level clock signal and the subsequent-stage maintenance control node of the maintenance control node generating module 4 of the rear-stage gate driving unit circuit, Maintaining the pull-up control node of the current level under the control of the last clock signal and the subsequent maintenance control node;
  • the pull-up control node maintaining module 5 is connected to the first-level clock signal and the front-stage maintenance control node of the maintenance control node generating module 4 of the pre-stage gate driving unit circuit.
  • the pull-up control node of the current stage is maintained under the control of the first clock signal and the pre-stage maintenance control node.
  • the first-stage pull-up control node maintaining module 5 of the gate driving unit circuit of the embodiment of the present invention is controlled by the maintaining control node generating module of the front stage and the rear stage, and the maintaining control node generating module 4 and the pull-up controlling node maintaining module 5 are
  • the same working state in the forward scanning and reverse scanning processes can avoid the problem that the circuit function fails due to the threshold voltage drift caused by the bias voltage of the thin film transistor after switching the scanning direction, thereby improving the reliability of the circuit.
  • the N-stage gate drive unit circuit can implement the gate drive circuit of the present invention by cascading.
  • N can be a positive integer greater than 3.
  • the pull-up control node maintaining module 5 of the nth-level gate driving unit circuit is respectively connected to the sustain control node of the n-1th-level gate driving unit circuit
  • the maintenance control node generating module 4 of the generating module 4 and the n+1th stage gate driving unit circuit is respectively connected to the sustain control node of the n-1th-level gate driving unit circuit.
  • the pull-up control node of the n-th gate driving unit circuit maintains the module 5 inputting the last bit clock signal CKM, and is connected to the sustain control node generating module 4 of the n+1th stage gate driving unit circuit.
  • the pull-up control node of the n-th gate driving unit circuit maintains the module 5 to input the first bit clock signal CK1, and connects the sustain control node generating module 4 of the n-1th stage gate driving unit circuit.
  • the gate driving unit circuit of the embodiment of the present invention has various specific embodiments.
  • the circuit structure of each stage of the gate driving unit circuit is the same, except that the signals input by some thin film transistors are different, and the following will be based on the nth stage gate driving unit.
  • the circuit describes a specific embodiment of the gate drive unit circuit, 1 ⁇ n ⁇ N, and n is a positive integer.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the gate driving unit circuit includes a pull-up control module 1, a pull-up module 2, a pull-down module 3, a maintenance control node generating module 4, a pull-up control node maintaining module 5, and an output node maintaining module 6.
  • the maintenance control node generation module 4 is responsible for generating a maintenance control signal for controlling the maintenance control node netBn, which is connected to the pull-up control node maintenance module 5 of the gate drive unit circuit of the preceding and succeeding stages, and is responsible for the pull-up control of the front and rear stages.
  • the node performs maintenance control.
  • the sustain control node generating module 4 includes a fifth thin film transistor M5, a sixth thin film transistor M6, and a seventh thin film transistor M7.
  • the first path end of the fifth thin film transistor M5 is connected to the current level maintaining control node netBn, the control end and the second path end are input with the first clock signal CKm, and the fifth thin film transistor M5 is used for charging the current level maintaining control node netBn.
  • the control terminal of the sixth thin film transistor M6 is connected to the pull-up control node netAn of the current stage, the first path terminal is connected to the low level VSS, the second path end is connected to the sustain control node netBn, and the sixth thin film transistor M6 is used for driving at the gate of the current stage.
  • the unit is prohibited from maintaining the output of the control node netBn during the operation of the unit circuit.
  • the control terminal of the seventh thin film transistor M7 inputs the second clock signal CKm+2, the first path terminal is connected to the low level VSS, the second path terminal is connected to the current level maintaining control node netBn, and the seventh thin film transistor M7 is used for maintaining the level.
  • the control node netBn is discharged.
  • the pull-up control node maintaining module 5 is connected to the front-stage maintenance control node netBn-1 of the maintenance control node generating module 4 of the front-stage gate driving unit circuit and the subsequent-stage maintenance of the maintenance control node generating module 4 of the rear-stage gate driving unit circuit.
  • the control node netBn+1 is used to maintain the level pull-up control node netAn, so that the pull-up control node netAn of the current stage is maintained at a stable low potential without interference from other signals to ensure high reliability of the circuit.
  • the pull-up control node maintaining module 5 includes an eighth thin film transistor M8A and an eighteenth thin film transistor M8B.
  • the control terminal of the eighth thin film transistor M8A is connected to the previous stage sustain control node netBn-1 of the pre-stage gate driving unit circuit, the first path terminal is connected to the low level VSS, and the second path end is connected to the local pull-up control node netAn.
  • the control terminal of the eighth thin film transistor M8A of the first stage gate driving unit circuit inputs the last bit clock signal CKM.
  • the control end of the eighteenth thin film transistor M8B is connected to the subsequent stage of the rear stage gate drive unit circuit to maintain the control node netBn+1, the first path end is connected to the low level VSS, and the second path end is connected to the upper stage pull control node netAn .
  • the control terminal of the eighteenth thin film transistor M8B of the tail gate driving unit circuit inputs the first bit clock signal CK1.
  • the eighth thin film transistor M8A and the eighteenth thin film transistor M8B are respectively controlled by the sustain control nodes of the front stage gate driving unit circuit and the rear stage gate driving unit circuit, and alternately maintain the level pull-up control node netAn.
  • the pull-up control module 1 is used for charging the level pull-up control node netAn, and the pull-down module 3 and the timing control can implement the forward-backward scanning function.
  • the pull-up module 2 is controlled by the pull-up control node netAn, and the first clock signal CKm is input to generate the local-level scan signal Gn.
  • the pull-down module 3 is responsible for receiving the second clock signal CKm+2 and performing an empty reset on the pull-up control node netAn.
  • the output node maintenance module 6 is responsible for maintaining the current level scan signal Gn.
  • the gate driving unit circuit of the embodiment of the present invention may further include an emptying module 7 and an auxiliary maintaining module 8.
  • the clearing module 7 is responsible for performing an empty reset operation on the pull-up control node netAn, the current-level maintenance control node netBn, and the local-level scan signal Gn, respectively, after the end of each frame picture and when the machine is turned on and off.
  • the auxiliary maintenance module 8 is responsible for maintaining the level pull-up control node netAn during the startup phase during the forward scan and the reverse scan.
  • the emptying module 7 and the auxiliary maintaining module 8 are functional modules that need to be added according to actual use. Whether or not the above-mentioned modules are included in the circuit is not limited, and other functional modules may be added in order to meet actual needs. Conventional functional improvements are intended to fall within the scope of the present invention.
  • the gate driving unit circuit of the embodiment of the present invention is controlled by the maintenance control node generating module 4 of the upper and lower stages, and the maintenance control node generating module 4 and the pull-up control node maintaining module 5 are scanned in the forward direction. It has the same working state as the reverse scanning process, and can avoid the problem that the circuit function fails due to the threshold voltage drift caused by the bias voltage of the thin film transistor after switching the scanning direction.
  • the pull-up control node maintenance module 5 includes two thin film transistors, which can alternately maintain the pull-up control node netAn, and one of them maintains the pull-up control node at any time, thereby improving circuit reliability.
  • U2D and D2U control signals are not required, the layout space is saved, which is advantageous for narrowing the frame of the display panel.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • FIG. 4 is a circuit diagram of a gate driving unit circuit according to a second embodiment of the present invention.
  • the difference between the gate driving unit circuit and the first embodiment shown in FIG. 3 is that the control terminal of the fifth thin film transistor M5 included in the maintenance control node generating module 4 inputs the first clock signal CKm, the first path.
  • the terminal is connected to the maintenance control node netBn, and the second path is connected to the high level VGH.
  • the implementation of the other circuit portions is the same as that of the first embodiment shown in FIG.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • FIG. 5 is a circuit diagram of a gate driving unit circuit according to a third embodiment of the present invention.
  • the gate driving unit circuit includes a pull-up control module 1, a pull-up module 2, a pull-down module 3, a maintenance control node generating module 4, a pull-up control node maintaining module 5, and an output node maintaining module 6.
  • the circuit configuration of the maintenance control node generating module 4 and the pull-up control node maintaining module 5 is the same as that of the first embodiment shown in FIG.
  • the pull-up control module 1 includes a first thin film transistor M1A and a sixteenth thin film transistor M1B.
  • the control end of the first thin film transistor M1A is connected to the scanning signal line Gn-1 of the front stage gate driving unit circuit, the first path end is connected to the local pull-up control node netAn, and the second path end is connected to the high level VGH.
  • the control terminal of the first thin film transistor M1A of the first stage gate driving unit circuit inputs the positive sweep enable signal GSP1.
  • the first thin film transistor M1A is used to precharge the local pull-up control node netAn during forward scanning.
  • the control terminal of the sixteenth thin film transistor M1B is connected to the scanning signal line Gn+1 of the rear stage gate driving unit circuit, the first path end is connected to the local pull-up control node netAn, and the second path end is connected to the high level VGH.
  • the control terminal of the sixteenth thin film transistor M1B of the tail gate drive unit circuit inputs the flyback enable signal GSP2.
  • the sixteenth thin film transistor M1B is used to precharge the stage pull-up control node netAn in the reverse scan.
  • the pull-up control module 1 pre-charges the pull-up control node of the current stage when the high-level VGH is connected to the second path end to control the forward-backward scanning, thereby reducing the bias stress and the threshold voltage drift of the thin film transistor.
  • the pull-up module 2 includes a tenth thin film transistor M10.
  • the control terminal of the tenth thin film transistor M10 is connected to the pull-up control node netAn of the first stage, the first path end is connected to the scanning signal line Gn of the current stage, and the second path end is connected to the first clock signal CKm.
  • the tenth thin film transistor M10 is configured to perform pull-up output and pull-down clearing of the scan signal Gn of the current stage.
  • the pull-down module 3 includes a ninth thin film transistor M9.
  • the control terminal of the ninth thin film transistor M9 is connected to the second clock signal CKm+2, the first path end is connected to the low level VSS, and the second path end is connected to the pull-up control node netAn of the current stage.
  • the ninth thin film transistor M9 is used to discharge the stage pull-up control node netAn.
  • the output node maintenance module 6 includes an eleventh thin film transistor M11A.
  • the control terminal of the eleventh thin film transistor M11A is connected to the second clock signal CKm+2, the first path terminal is connected to the low level VSS, and the second path end is connected to the current scanning signal line Gn.
  • the eleventh thin film transistor M11A is used to maintain the scanning signal Gn of the present stage.
  • the gate driving unit circuit of the embodiment of the present invention may further include an emptying module 7 and an auxiliary maintaining module 8.
  • the emptying module 7 includes a second thin film transistor M2, a third thin film transistor M3, and a twelfth thin film transistor M12.
  • the control terminal of the second thin film transistor M2 inputs the clear signal CLR, and the first path end and the second path end are respectively connected to the low level VSS and the current stage pull-up control node netAn, and the second thin film transistor M2 is used to end at each frame. After the switch and the switch, the reset control operation of the pull-up control node netAn is performed.
  • the control terminal of the third thin film transistor M3 inputs the clear signal CLR, and the first path end and the second path end are respectively connected to the low level VSS and the current level maintaining control node netBn, and the third thin film transistor M3 is used after the end of each frame picture.
  • the reset control node netBn is reset and reset.
  • the control terminal of the twelfth thin film transistor M12 inputs the clear signal CLR, and the first path end and the second path end are respectively connected to the low level VSS and the current scanning signal line, and the twelfth thin film transistor M12 is used to end each frame. After the switch is turned on and off, the scan signal Gn of the current stage is cleared and reset.
  • the auxiliary sustaining module 8 includes a fourth thin film transistor M4A and a seventeenth thin film transistor M4B.
  • the control terminal of the fourth thin film transistor M4A inputs the positive sweep enable signal GSP1, and the first path end and the second path end are respectively connected to the low level VSS and the current stage pull-up control node netAn.
  • the control terminal of the fourth thin film transistor M4A of the first three stages of gate drive unit circuits inputs a low level VSS.
  • the fourth thin film transistor M4A is used to maintain the level pull-up control node netAn in the startup phase during the startup mode.
  • the control terminal of the seventeenth thin film transistor M4B inputs the anti-sweep enable signal GSP2, and the first path end and the second path end are respectively connected to the low level VSS and the current stage pull-up control node netAn.
  • the control terminal of the seventeenth thin film transistor M4B of the last three stages of gate drive unit circuits inputs a low level VSS.
  • the seventeenth thin film transistor M4B is used to maintain the stage pull-up control node netAn in the startup phase in the reverse scan mode.
  • the gate driving unit circuit of the embodiment of the present invention may further include a bootstrap capacitor C1 connected between the pull-up control node netAn of the current stage and the scanning signal line of the current stage, through capacitive coupling. During the output process, the potential of the pull-up control node netAn is raised, and the charging speed of the scanning signal line of the current level is increased.
  • FIG. 6 is a schematic diagram showing driving waveforms of the gate driving unit circuit shown in FIG. 5 in forward scanning. among them,
  • GSP1 is the positive sweep start signal and is responsible for starting during forward scan
  • GSP2 is the anti-sweep start signal and is responsible for starting during reverse scan
  • CK1, CK2, CK3, and CK4 are clock signals, which are sequentially output during forward scanning
  • the CLR is a clear reset signal, and is mainly responsible for performing charge emptying on the internal nodes of the circuit at the end of each frame and when the machine is turned on and off;
  • VGH is a high level VGH, which is mainly responsible for the input of the pull-up control module 1;
  • VSS is a low level VSS, which is mainly responsible for providing a low potential of the scan signal Gn;
  • waveforms such as netA1, netA2, netAlast-1, and netAlast are the output waveforms of the internal nodes of the circuit, and G1, G2, and Glast are the waveforms of the scan signals output by the gate drive unit circuits of each stage.
  • FIG. 7 is a schematic diagram showing driving waveforms of the gate driving unit circuit shown in FIG. 5 in reverse scanning. among them,
  • GSP1 is the positive sweep start signal and is responsible for starting during forward scan
  • GSP2 is the anti-sweep start signal and is responsible for starting during reverse scan
  • CK1, CK2, CK3, and CK4 are clock signals, and are output in reverse order during reverse scanning
  • the CLR is a clear reset signal, and is mainly responsible for performing charge emptying on the internal nodes of the circuit at the end of each frame and when the machine is turned on and off;
  • VGH is a high level VGH, which is mainly responsible for the input of the pull-up control module 1;
  • VSS is a low level VSS, which is mainly responsible for providing a low potential of the scan signal Gn;
  • waveforms such as netA1, netA2, netAlast-1, and netAlast are the output waveforms of the internal nodes of the circuit, and G1, G2, and Glast are the waveforms of the scan signals output by the gate drive unit circuits of each stage.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • FIG. 8 is a circuit diagram of a gate driving unit circuit according to a fourth embodiment of the present invention. As shown in FIG. 8, the difference between the gate driving unit circuit and the third embodiment shown in FIG. 5 is:
  • the gate of the eleventh thin film transistor M11A in the output node maintaining module 6 is connected to the current level maintaining control node netBn, the first path end is connected to the low level VSS, and the second path end is connected to the local level scanning signal line Gn.
  • the implementation of the other circuit portions is the same as that of the third embodiment shown in FIG.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • FIG. 9 is a circuit diagram of a gate driving unit circuit according to a fifth embodiment of the present invention.
  • the gate driving unit circuit is based on the third embodiment shown in FIG. 7, the output node maintaining module 6 further includes a nineteenth thin film transistor M11B, and the control end of the nineteenth thin film transistor M11B is connected to the current level.
  • the control node netBn is maintained, the first path end is connected to the low level VSS, and the second path end is connected to the current scanning signal line Gn.
  • the eleventh thin film transistor M11A and the nineteenth thin film transistor M11B collectively maintain the scanning signal Gn of the present stage to enhance the sustaining capability.
  • FIG. 10 is a circuit diagram of a gate driving unit circuit according to Embodiment 6 of the present invention. As shown in FIG. 10, the difference between the gate driving unit circuit and the fifth embodiment shown in FIG. 9 is:
  • the control terminal of the eleventh thin film transistor M11A in the output node maintenance module 6 is connected to the sustain control node netBn-1 of the front gate drive unit circuit, and the first path end and the second path end are respectively connected to the low level VSS and the current stage. Scanning signal line;
  • the control terminal of the nineteenth thin film transistor M11B is connected to the sustain control node netBn+1 of the rear gate drive unit circuit, and the first path end and the second path end are respectively connected to the low level VSS and the current scanning signal line.
  • FIG. 11 is a circuit diagram of a gate driving unit circuit according to a seventh embodiment of the present invention. As shown in FIG. 11, the difference between the gate driving unit circuit and the fourth embodiment shown in FIG. 8 is as follows:
  • the gate driving unit circuit further includes a level transfer node generating module 9, and the level transmitting node generating module 9 includes a thirteenth thin film crystal M13 and a fourteenth thin film crystal M14.
  • the control end of the thirteenth thin film crystal M13 is connected to the pull-up control node netAn of the first stage, the first pass end is connected to the local pass node Tn, the second pass end is connected to the first clock signal CKm; the control end of the fourteenth thin film crystal M14 Connect the local maintenance control node netBn, the second path end is connected to the local level transfer node Tn, and the first path end is connected to the low level VSS.
  • the control terminal of the first thin film transistor M1A in the pull-up control module 1 is connected to the level transfer node Tn-1 in the front gate drive unit circuit, and the control terminal of the sixteenth thin film transistor M1B is connected to the rear gate drive unit circuit.
  • the emptying module 7 further includes a fifteenth thin film transistor M15.
  • the control terminal of the fifteenth thin film transistor M15 inputs a clear signal CLR, the first path terminal is connected to the low level VSS, and the second path end is connected to the current level transmitting node Tn.
  • the fifteenth thin film transistor M15 is used to clear the level transfer node Tn after the end of one frame display and when the machine is turned off.
  • the level transmitting node generating module 9 is responsible for generating a level transmitting signal to control the level transmitting node Tn, and the step transmitting node Tn is connected to the pull-up control module 1 in the front-end stage gate driving unit circuit to make the gate driving circuit Implement forward and reverse scanning.
  • FIG. 12 is a circuit diagram of a gate drive unit circuit in accordance with an eighth embodiment of the present invention. As shown in FIG. 12, the gate driving unit circuit is improved on the basis of the third embodiment shown in FIG. 5, and can be used for an in-cell touch display screen. The specific improvement is as follows:
  • a touch-maintaining module 10 is added.
  • the touch-maintaining module 10 includes a twelfth thin film transistor M12.
  • the control terminal of the twelfth thin film transistor M12 inputs a touch control signal TC, and the first path end and the second path end are respectively connected to the low voltage.
  • the touch-maintaining module 10 is configured to maintain control of the scan signal Gn of the gate driving unit circuit of the current stage during the touch control, so that the gate driving circuit supports the pause during any time during the display, and can be used for the 120 Hz in-cell touch display.
  • the emptying module 7 includes a second thin film transistor M2 and a third thin film transistor M3; the control terminal of the second thin film transistor M2 inputs a clear signal CLR, and the first path end and the second path end are respectively connected to the low level VSS and the current level
  • the pull-up control node netAn, the second thin film transistor M2 is used to perform a clear reset operation on the level pull-up control node netAn after the end of each frame picture and when the machine is turned on and off.
  • the control terminal of the third thin film transistor M3 inputs the clear signal CLR, and the first path end and the second path end are respectively connected to the low level VSS and the current level maintaining control node netBn, and the third thin film transistor M3 is used after the end of each frame picture.
  • the reset control node netBn is reset and reset.
  • FIG. 13 is a schematic diagram showing driving waveforms of the gate driving unit circuit shown in FIG. 12 in forward scanning. among them,
  • GSP1 is the positive sweep start signal and is responsible for starting during forward scan
  • GSP2 is the anti-sweep start signal and is responsible for starting during reverse scan
  • CK1, CK2, CK3, and CK4 are clock signals, which are sequentially output during forward scanning
  • the CLR is a clear reset signal, and is mainly responsible for performing charge emptying on the internal nodes of the circuit at the end of each frame and when the machine is turned on and off;
  • the TC is a touch control signal during touch, and is responsible for maintaining the scanning signal of the current level during the touch period;
  • VGH is a high level VGH, which is mainly responsible for the input of the pull-up control module 1;
  • VSS is a low level VSS, which is mainly responsible for providing a low potential of the scan signal Gn;
  • waveforms such as netA1, netA2, netAlast-1, and netAlast are the output waveforms of the internal nodes of the circuit, and G1, G2, and Glast are the waveforms of the scan signals output by the gate drive unit circuits of each stage.
  • FIG. 14 is a schematic diagram showing driving waveforms of the gate driving unit circuit shown in FIG. 12 in reverse scanning. among them,
  • GSP1 is the positive sweep start signal and is responsible for starting during forward scan
  • GSP2 is the anti-sweep start signal and is responsible for starting during reverse scan
  • CK1, CK2, CK3, and CK4 are clock signals, and are output in reverse order during reverse scanning
  • the CLR is a clear reset signal, and is mainly responsible for performing charge emptying on the internal nodes of the circuit at the end of each frame and when the machine is turned on and off;
  • the TC is a touch control signal during touch, and is responsible for maintaining the scanning signal of the current level during the touch period;
  • VGH is a high level VGH, which is mainly responsible for the input of the pull-up control module 1;
  • VSS is a low level VSS, which is mainly responsible for providing a low potential of the scan signal Gn;
  • waveforms such as netA1, netA2, netAlast-1, and netAlast are the output waveforms of the internal nodes of the circuit, and G1, G2, and Glast are the waveforms of the scan signals output by the gate drive unit circuits of each stage.
  • the fifth thin film transistor M5 included in the maintenance control node generating module 4 can also be implemented according to the second embodiment shown in FIG. 4, that is, the gate of the fifth thin film transistor M5.
  • the first clock signal CKm is input, the first path end is connected to the current stage maintaining control node netBn, and the second path end is connected to the high level VGH.
  • the embodiment of the invention further provides a liquid crystal display device, which comprises the above-mentioned gate driving circuit, and the gate driving circuit can be a single-side driving method or a bilateral driving method.
  • Fig. 15 is a view showing an example of a liquid crystal display device employing a gate driving circuit of an embodiment of the present invention.
  • the AA area in the figure represents a display area
  • the liquid crystal display device adopts a left and right interleaved driving structure, including a left gate driving circuit, a right gate driving circuit, and other driving circuits. .

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Abstract

一种栅极驱动单元电路、栅极驱动电路和显示装置，栅极驱动单元电路包括上拉控制模块（1）、上拉模块（2）、下拉模块（3）、维持控制节点产生模块（4）、上拉控制节点维持模块（5）以及输出节点维持模块（6）；当栅极驱动单元电路不是首级和尾级栅极驱动单元电路时，上拉控制节点维持模块（5）连接前级栅极驱动单元电路的维持控制节点产生模块（4）的前级维持控制节点和后级栅极驱动单元电路的维持控制节点产生模块（4）的后级维持控制节点，在前级维持控制节点和后级维持控制节点的控制下，对本级上拉控制节点进行维持。能够避免切换扫描方向后由于薄膜晶体管受到偏压应力产生阈值电压漂移而造成电路功能失效的问题，提高了电路的可靠性。

Description

栅极驱动单元电路、栅极驱动电路和显示装置 技术领域
本发明涉及液晶显示领域，尤其涉及一种栅极驱动单元电路、栅极驱动电路和显示装置。
背景技术
集成的栅极扫描驱动电路(Gate Driver Monolithic，GDM)是一种利用现有的薄膜晶体管阵列基板制造工艺，将栅极扫描驱动电路直接构建在阵列基板上的技术，具有降低成本、减少工艺流程、减小面板边框宽度的作用。随着产品和技术的发展，平板显示器对栅极扫描驱动电路的要求越来越高，其中之一就是要求同时具有正向扫描和反向扫描的功能。
图1所示是一种具有正反扫功能的栅极驱动单元电路的电路示意图，该栅极驱动单元电路包括控制正反扫的上拉控制模块1、上拉模块2、维持控制节点产生模块4、上拉控制节点维持模块5、输出节点维持模块6、清空模块7、辅助维持模块8以及自举电容C1。其中上拉控制模块1和维持控制节点产生模块4均同时被前级和后级栅极驱动单元电路中信号所控制，具有对称性，上拉控制模块1中的薄膜晶体管M1与M9对称，维持控制节点产生模块4中的薄膜晶体管M5与M7对称。
该栅极驱动单元电路的扫描方向通过正向扫描控制信号U2D和反向扫描控制信号D2U这一对相互反相的恒压信号进行控制，U2D取高电平、D2U取低电平时进行正向扫描，反之进行反向扫描。但是，U2D和D2U相互反相的特性使得维持控制节点产生模块4中M5和M7两颗薄膜晶体管长期受到符号相反的偏压应力，产生方向相反的阈值电压漂移，在切换扫描方向之后会降低上拉控制节点维持模块5的维持能力，降低了电路的可靠性，也增加了电路的复杂性。
发明内容
为解决上述技术问题，本发明提供一种栅极驱动单元电路、栅极驱动电路和显示装置，能够避免维持控制节点产生模块中的薄膜晶体管受到偏压应力产 生阈值电压的问题，并且任何时候都可以对上拉控制节点进行维持，提高了电路的可靠性。
根据本发明的第一方面，提供一种栅极驱动单元电路，适于进行多级连接以形成栅极驱动电路，包括上拉控制模块、上拉模块、下拉模块、维持控制节点产生模块、上拉控制节点维持模块以及输出节点维持模块；上拉控制模块、上拉模块、维持控制节点产生模块以及上拉控制节点维持模块相连接于本级上拉控制节点；上拉模块和输出节点维持模块相连接于本级扫描信号线；
其中，当所述栅极驱动单元电路不是首级和尾级栅极驱动单元电路时，上拉控制节点维持模块连接前级栅极驱动单元电路的维持控制节点产生模块的前级维持控制节点和后级栅极驱动单元电路的维持控制节点产生模块的后级维持控制节点，在所述前级维持控制节点和后级维持控制节点的控制下，对本级上拉控制节点进行维持；
当所述栅极驱动单元电路是首级栅极驱动单元电路时，上拉控制节点维持模块连接末位时钟信号和后级栅极驱动单元电路的维持控制节点产生模块的后级维持控制节点，在所述末位时钟信号和后级维持控制节点的控制下，对本级上拉控制节点进行维持；
当所述栅极驱动单元电路是尾级栅极驱动单元电路时，上拉控制节点维持模块连接首位时钟信号和前级栅极驱动单元电路的维持控制节点产生模块的前级维持控制节点，在所述首位时钟信号和前级维持控制节点的控制下，对本级上拉控制节点进行维持。
根据本发明的优选实施方式，所述维持控制节点产生模块包括第五薄膜晶体管、第六薄膜晶体管和第七薄膜晶体管；
第五薄膜晶体管用于给本级维持控制节点充电，其第一通路端连接本级维持控制节点，控制端和第二通路端输入第一时钟信号；
第六薄膜晶体管用于在本级栅极驱动单元电路工作期间禁止本级维持控制节点输出，其控制端连接本级上拉控制节点，第一通路端连接低电平，第二通路端连接本级维持控制节点；
第七薄膜晶体管用于给本级维持控制节点放电，其控制端输入第二时钟信 号，第一通路端连接低电平,第二通路端连接本级维持控制节点。
根据本发明的优选实施方式，所述维持控制节点产生模块包括第五薄膜晶体管、第六薄膜晶体管和第七薄膜晶体管；
第五薄膜晶体管用于给本级维持控制节点充电，其控制端输入第一时钟信号，第一通路端连接本级维持控制节点，第二通路端连接高电平；
第六薄膜晶体管用于在本级栅极驱动单元电路工作期间禁止本级维持控制节点输出，其控制端连接本级上拉控制节点，第一通路端连接低电平，第二通路端连接本级维持控制节点；
第七薄膜晶体管用于给本级维持控制节点放电，其控制端输入第二时钟信号，第一通路端连接低电平,第二通路端连接本级维持控制节点。
根据本发明的优选实施方式，所述上拉控制节点维持模块包括第八薄膜晶体管和第十八薄膜晶体管；
第八薄膜晶体管的控制端连接所述前级维持控制节点，第一通路端连接低电平，第二通路端连接本级上拉控制节点；其中，首级栅极驱动单元电路的第八薄膜晶体管的控制端输入末位时钟信号；
第十八薄膜晶体管的控制端连接到所述后级维持控制节点，第一通路端连接低电平，第二通路端连接本级上拉控制节点；其中，首级栅极驱动单元电路的第十八薄膜晶体管的控制端输入首位时钟信号。
根据本发明的优选实施方式，所述上拉控制模块包括第一薄膜晶体管和第十六薄膜晶体管；
第一薄膜晶体管用于在正向扫描时对本级上拉控制节点进行预充，其控制端连接前级栅极驱动单元电路的扫描信号线，第一通路端连接本级上拉控制节点，第二通路端连接高电平；其中，首级栅极驱动单元电路的第一薄膜晶体管的控制端输入正扫启动信号；
第十六薄膜晶体管用于在反向扫描时对本级上拉控制节点进行预充，其控制端连接后级栅极驱动单元电路的扫描信号线，第一通路端连接本级上拉控制节点，第二通路端连接高电平；其中，尾级栅极驱动单元电路的第十六薄膜晶体管的控制端输入反扫启动信号。
根据本发明的优选实施方式，所述电路还包括级传节点产生模块；级传节点产生模块包括第十三薄膜晶体管和第十四薄膜晶体管；第十三薄膜晶体管的控制端连接本级上拉控制节点，第一通路端和第二通路端分别连接本级级传节点和第一时钟信号；第十四薄膜晶体管的控制端连接本级维持控制节点，第一通路端和第二通路端分别连接低电平和本级级传节点；
所述上拉控制模块包括第一薄膜晶体管和第十六薄膜晶体管；第一薄膜晶体管的控制端连接前级栅极驱动单元电路的前级级传节点，第一通路端连接本级上拉控制节点，第二通路端连接高电平；第十六薄膜晶体管的控制端连接后级栅极驱动单元电路中的后级级传节点，第一通路端连接本级上拉控制节点，第二通路端连接高电平。
根据本发明的优选实施方式，所述输出节点维持模块包括第十一薄膜晶体管，第十一薄膜晶体管用于对本级扫描信号进行维持，其控制端连接第二时钟信号，第一通路端和第二通路端分别连接低电平和本级扫描信号线。
根据本发明的优选实施方式，所述输出节点维持模块包括第十一薄膜晶体管,第十一薄膜晶体管用于对本级扫描信号进行维持，其控制端连接本级维持控制节点，第一通路端和第二通路端分别连接低电平和本级扫描信号线。
根据本发明的优选实施方式，所述输出节点维持模块包括第十一薄膜晶体管和第十九薄膜晶体管，第十一薄膜晶体管用于对本级扫描信号进行维持，其控制端连接第二时钟信号，第一通路端和第二通路端分别连接低电平和本级扫描信号线；第十九薄膜晶体管的控制端连接本级维持控制节点，第一通路端和第二通路端分别连接低电平和本级扫描信号线。
根据本发明的优选实施方式，所述输出节点维持模块包括第十一薄膜晶体管和第十九薄膜晶体管；
第十一薄膜晶体管的控制端连接所述前级维持控制节点，第一通路端和第二通路端分别连接低电平和本级扫描信号线；第十九薄膜晶体管的控制端连接所述后级维持控制节点，第一通路端和第二通路端分别连接低电平和本级扫描信号线。
根据本发明的优选实施方式，所述电路还包括触控维持模块；所述触控维 持模块包括第十二薄膜晶体管；第十二薄膜晶体管的控制端输入触摸控制信号，第一通路端和第二通路端分别连接低电平和本级扫描信号线。
根据本发明的优选实施方式，所述上拉模块包括第十薄膜晶体管；第十薄膜晶体管的控制端连接本级上拉控制节点，第一通路端和第二通路端分别连接本级扫描信号线和第一时钟信号。
根据本发明的优选实施方式，所述下拉模块包括第九薄膜晶体管；第九薄膜晶体管的控制端输入第二时钟信号，第一通路端和第二通路端分别连接低电平和本级上拉控制节点。
根据本发明的优选实施方式，所述电路还包括辅助维持模块；所述辅助维持模块包括第四薄膜晶体管和第十七薄膜晶体管；
第四薄膜晶体管的控制端输入正扫启动信号，第一通路端和第二通路端分别连接低电平和本级上拉控制节点；其中，前三级栅极驱动单元电路的第四薄膜晶体管的控制端输入低电平；
第十七薄膜晶体管的控制端输入反扫启动信号，第一通路端和第二通路端分别连接低电平和本级上拉控制节点；其中，后三级栅极驱动单元电路的第十七薄膜晶体管的控制端输入低电平。
根据本发明的优选实施方式，所述电路还包括清空模块；所述清空模块包括第二薄膜晶体管、第三薄膜晶体管和第十二薄膜晶体管；
第二薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级上拉控制节点；
第三薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级维持控制节点；
第十二薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级扫描信号线。
根据本发明的优选实施方式，所述电路还包括清空模块；所述清空模块包括第二薄膜晶体管、第三薄膜晶体管、第十二薄膜晶体管以及第十五薄膜晶体管；
第二薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连 接低电平和本级上拉控制节点；
第三薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级维持控制节点；
第十二薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级扫描信号线；
第十五薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级级传节点。
根据本发明的优选实施方式，所述电路还包括清空模块；所述清空模块包括第二薄膜晶体管和第三薄膜晶体管；
第二薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级上拉控制节点；
第三薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级维持控制节点。
根据本发明的第二方面，提供一种栅极驱动电路，包括N级前述任一实施方式所述的栅极驱动单元电路，N为大于3的整数；其中，
当2≦n≦N-1，第n级栅极驱动单元电路的上拉控制节点维持模块分别连接第n-1级栅极驱动单元电路的维持控制节点产生模块和第n+1级栅极驱动单元电路的维持控制节点产生模块；
当n＝1，第n级栅极驱动单元电路的上拉控制节点维持模块输入末位时钟信号，并连接第n+1级栅极驱动单元电路的维持控制节点产生模块；
当n＝N，第n级栅极驱动单元电路的上拉控制节点维持模块输入首位时钟信号，并连接第n-1级栅极驱动单元电路的维持控制节点产生模块。
根据本发明的第三方面，提供一种显示装置，包括前述任一实施方式所述的栅极驱动电路。
与现有技术相比，本发明实施例的栅极驱动电路中每一级的维持控制节点产生模块负责控制上下两级的上拉控制节点维持模块，同样本级的上拉控制节点维持模块由上一级的维持控制节点产生模块和下一级的维持控制节点产生模块进行控制，上拉控制节点维持模块和维持控制节点产生模块在正向扫描和 反向扫描过程中具有相同的工作状态，能够避免切换扫描方向后由于薄膜晶体管受到偏压应力产生阈值电压漂移而造成电路功能失效的问题，从而提高了电路的可靠性。
附图说明
下面将以明确易懂的方式，结合附图说明优选实施方式，对本发明予以进一步说明。
图1为一种具有正反扫功能的栅极驱动单元电路的电路示意图；
图2为根据本发明实施例的栅极驱动单元电路和所构成的栅极驱动电路的电路示意图；
图3为根据本发明实施例一的栅极驱动单元电路的电路示意图；
图4为根据本发明实施例二的栅极驱动单元电路的电路示意图；
图5为根据本发明实施例三的栅极驱动单元电路的电路示意图；
图6为图5所示的栅极驱动单元电路在正向扫描时的驱动波形示意图；
图7为图5所示的栅极驱动单元电路在反向扫描时的驱动波形示意图；
图8为根据本发明实施例四的栅极驱动单元电路的电路示意图；
图9为根据本发明实施例五的栅极驱动单元电路的电路示意图；
图10为根据本发明实施例六的栅极驱动单元电路的电路示意图；
图11为根据本发明实施例七的栅极驱动单元电路的电路示意图；
图12为根据本发明实施例八的栅极驱动单元电路的电路示意图；
图13为图12所示的栅极驱动单元电路在正向扫描时的驱动波形示意图；
图14为图12所示的栅极驱动单元电路在反向扫描时的驱动波形示意图；
图15为采用本发明实施例的栅极驱动电路的液晶显示装置的示例图。
附图标号说明：
1、上拉控制模块，2、上拉模块，3、下拉模块、4、维持控制节点产生模块，5、上拉控制节点维持模块，6、输出节点维持模块，7、清空模块，8、辅助维持模块，9、级传节点产生模块、10、触控维持模块；
M1A、第一薄膜晶体管，M1B、第十六薄膜晶体管，M2、第二薄膜晶体管，M3、第三薄膜晶体管，M4A、第四薄膜晶体管，M4B、第十七薄膜晶体 管，M5、第五薄膜晶体管，M6、第六薄膜晶体管，M7、第七薄膜晶体管，M8A、第八薄膜晶体管，M8B、第十八薄膜晶体管，M9、第九薄膜晶体管，M10、第十薄膜晶体管，M11、第十一薄膜晶体管，M11B、第十九薄膜晶体管，M12、第十二薄膜晶体管，M13、第十三薄膜晶体管，M14、第十四薄膜晶体管，M15、第十五薄膜晶体管，C1、自举电容；
Gn、第n级栅极驱动单元电路的扫描信号，netAn、上拉控制节点，netBn、维持控制节点，VGH、高电平，VSS、低电平，CKm、第一时钟信号，CKm+2、第二时钟信号，CK1、首位时钟信号，CKM、末位时钟信号，Gn-1、第n-1级栅极驱动单元电路的扫描信号，Gn+1、第n+1级栅极驱动单元电路的扫描信号，CLR、清空重置信号，GSP1、正扫启动信号，GSP2、反扫启动信号，Tn、第n级栅极驱动单元电路的级传节点，Tn-1、第n-1级栅极驱动单元电路的级传节点，Tn+1、第n+1级栅极驱动单元电路的级传节点，TC、触摸控制信号。
具体实施方式
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对照附图说明本发明的具体实施方式。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，并获得其他的实施方式。
为使图面简洁，各图中只示意性地表示出了与本发明相关的部分，它们并不代表其作为产品的实际结构。另外，以使图面简洁便于理解，在有些图中具有相同结构或功能的部件，仅示意性地绘示了其中的一个，或仅标出了其中的一个。在本文中，“一个”不仅表示“仅此一个”，也可以表示“多于一个”的情形。
本发明的栅极驱动电路使用M(M>1且M为整数)个时钟信号CKm(m＝1、2、…、M)，在以下的实施例中，记CK1为首位时钟信号，记CKM为末位时钟信号，并取CKm作为第一时钟信号，取CKm+2作为第二时钟信号。应当说明的是，第二时钟信号并不限定为CKm+2，第二时钟信号可为CKm+3、CKm+4等。其中CK-1等价为CK(M-1)，CK0等价为CKM，CK1等价为CKM+1，并依次类推。
需要说明的是，对于N级栅极驱动单元电路组成的栅极驱动电路，以下实施例中首级栅极驱动单元电路是指第1级栅极驱动单元电路，尾级栅极驱动单元电路是指第N级栅极驱动单元电路；对于第n级栅极驱动单元电路而言，第n 级栅极驱动单元电路可以称为本级栅极驱动单元电路，第n-1级栅极驱动单元电路可以称为前级栅极驱动单元电路，第n+1级栅极驱动单元电路可以称为后级栅极驱动单元电路。
以下实施例中薄膜晶体管均包括控制端、第一通路端和第二通路端，其中，控制端为栅极，第一通路端为源极，第二通路端为漏极，在可选的实施方式中，第一通路端也可以为漏极，第二通路端为源极。当给控制端高电平时，第一通路端和第二通路端通过半导体层连接，此时薄膜晶体管处于开启状态。
图2为根据本发明实施例的栅极驱动单元电路和所构成的栅极驱动电路的电路示意图。如图2所示，栅极驱动单元电路适于进行多级连接以形成栅极驱动电路，包括上拉控制模块1、上拉模块2、下拉模块3、维持控制节点产生模块4、上拉控制节点维持模块5以及输出节点维持模块6。
上拉控制模块1、上拉模块2、维持控制节点产生模块4以及上拉控制节点维持模块5相连接于上拉控制节点netAn；上拉模块2和输出节点维持模块6相连接于本级扫描信号线。
其中，当栅极驱动单元电路不是首级和尾级栅极驱动单元电路时，上拉控制节点维持模块5连接前级栅极驱动单元电路的维持控制节点产生模块4的前级维持控制节点和后级栅极驱动单元电路的维持控制节点产生模块4的后级维持控制节点，在所述前级维持控制节点和后级维持控制节点的控制下，对本级上拉控制节点进行维持；
当栅极驱动单元电路是首级栅极驱动单元电路时，上拉控制节点维持模块5连接末位时钟信号和后级栅极驱动单元电路的维持控制节点产生模块4的后级维持控制节点，在所述末位时钟信号和后级维持控制节点的控制下，对本级上拉控制节点进行维持；
当所述栅极驱动单元电路是尾级栅极驱动单元电路时，上拉控制节点维持模块5连接首位时钟信号和前级栅极驱动单元电路的维持控制节点产生模块4的前级维持控制节点，在所述首位时钟信号和前级维持控制节点的控制下，对本级上拉控制节点进行维持。
本发明实施例的栅极驱动单元电路的本级上拉控制节点维持模块5由前级 和后级的维持控制节点产生模块负责控制，维持控制节点产生模块4和上拉控制节点维持模块5在正向扫描和反向扫描过程中具有相同的工作状态，能够避免切换扫描方向后由于薄膜晶体管受到偏压应力产生阈值电压漂移而造成电路功能失效的问题，提高了电路的可靠性。
如图2所示，N级栅极驱动单元电路通过级联可以实现本发明的栅极驱动电路，根据本发明的优选实施方式，N可以是大于3的正整数。
本发明的栅极驱动电路中，当2≦n≦N-1，第n级栅极驱动单元电路的上拉控制节点维持模块5分别连接第n-1级栅极驱动单元电路的维持控制节点产生模块4和第n+1级栅极驱动单元电路的维持控制节点产生模块4。
当n＝1，第n级栅极驱动单元电路的上拉控制节点维持模块5输入末位时钟信号CKM，并连接第n+1级栅极驱动单元电路的维持控制节点产生模块4。
当n＝N，第n级栅极驱动单元电路的上拉控制节点维持模块5输入首位时钟信号CK1，并连接第n-1级栅极驱动单元电路的维持控制节点产生模块4。
本发明实施例的栅极驱动单元电路具有多种具体实施例，每级栅极驱动单元电路的电路结构相同，区别仅在于部分薄膜晶体管输入的信号不同,以下将基于第n级栅极驱动单元电路对栅极驱动单元电路的具体实施例进行描述，1≦n≦N，且n为正整数。
实施例一：
图3为根据本发明实施例一的栅极驱动单元电路的电路示意图。如图3所示，该栅极驱动单元电路包括上拉控制模块1、上拉模块2、下拉模块3、维持控制节点产生模块4、上拉控制节点维持模块5以及输出节点维持模块6。
维持控制节点产生模块4负责产生维持控制信号来控制维持控制节点netBn，该维持控制节点netBn连接至前后级的栅极驱动单元电路的上拉控制节点维持模块5，负责对前后级的上拉控制节点进行维持控制。
维持控制节点产生模块4包括第五薄膜晶体管M5、第六薄膜晶体管M6以及第七薄膜晶体管M7。
第五薄膜晶体管M5的第一通路端连接本级维持控制节点netBn，控制端和第二通路端输入第一时钟信号CKm，第五薄膜晶体管M5用于给本级维持控制 节点netBn充电。
第六薄膜晶体管M6的控制端连接本级上拉控制节点netAn，第一通路端连接低电平VSS，第二通路端连接维持控制节点netBn，第六薄膜晶体管M6用于在本级栅极驱动单元电路工作期间禁止本级维持控制节点netBn输出。
第七薄膜晶体管M7的控制端输入第二时钟信号CKm+2,第一通路端连接低电平VSS，第二通路端连接本级维持控制节点netBn，第七薄膜晶体管M7用于给本级维持控制节点netBn放电。
上拉控制节点维持模块5连接前级栅极驱动单元电路的维持控制节点产生模块4的前级维持控制节点netBn-1和后级栅极驱动单元电路的维持控制节点产生模块4的后级维持控制节点netBn+1，用于维持本级上拉控制节点netAn，使本级上拉控制节点netAn维持在稳定的低电位而不受到其他信号的干扰，以确保电路具有较高的可靠性。
上拉控制节点维持模块5包括第八薄膜晶体管M8A和第十八薄膜晶体管M8B。
第八薄膜晶体管M8A的控制端连接到前级栅极驱动单元电路的前级维持控制节点netBn-1，第一通路端连接低电平VSS，第二通路端连接本级上拉控制节点netAn。在可选的实施方式中，首级栅极驱动单元电路的第八薄膜晶体管M8A的控制端输入末位时钟信号CKM。
第十八薄膜晶体管M8B的控制端连接到后级栅极驱动单元电路的后级维持控制节点netBn+1,第一通路端连接低电平VSS，第二通路端连接本级上拉控制节点netAn。在可选的实施方式中，尾级栅极驱动单元电路的第十八薄膜晶体管M8B的控制端输入首位时钟信号CK1。
第八薄膜晶体管M8A与第十八薄膜晶体管M8B分别受前级栅极驱动单元电路和后级栅极驱动单元电路的维持控制节点所控制，交替对本级上拉控制节点netAn进行维持。
上拉控制模块1用于对本级上拉控制节点netAn进行充电，搭配下拉模块3和时序控制可以实现正反向扫描功能。
上拉模块2由上拉控制节点netAn进行控制，输入第一时钟信号CKm产生本 级扫描信号Gn。
下拉模块3负责接收第二时钟信号CKm+2，对上拉控制节点netAn进行清空重置。
输出节点维持模块6负责对本级扫描信号Gn进行维持。
在一些实施方式中，本发明实施例的栅极驱动单元电路还可以包括清空模块7、辅助维持模块8。
清空模块7负责在每一帧画面结束后和开关机时，分别对本级上拉控制节点netAn、本级维持控制节点netBn和本级扫描信号Gn进行清空重置操作。
辅助维持模块8负责在正向扫描和反向扫描过程中，在启动阶段对本级上拉控制节点netAn进行维持。
需要说明的是，本发明中清空模块7、辅助维持模块8是根据实际使用需要增设的功能模块，电路中是否包含上述模块不作限定，同时为了满足实际需要还可以增加其他功能模块，在此基础上的常规功能改进均应落入本发明的保护范围。
本发明实施例的栅极驱动单元电路本级上拉控制节点维持模块5由上下级的维持控制节点产生模块4负责控制，维持控制节点产生模块4和上拉控制节点维持模块5在正向扫描和反向扫描过程中具有相同的工作状态，能够避免切换扫描方向后由于薄膜晶体管受到偏压应力产生阈值电压漂移而造成电路功能失效的问题。上拉控制节点维持模块5包含两颗薄膜晶体管，可交替对上拉控制节点netAn进行维持，任何时候都有其中一颗对上拉控制节点进行维持，提高了电路可靠性。此外，由于无需采用U2D和D2U控制信号，节省了版图空间，有利于缩窄显示面板的边框。
实施例二：
图4为根据本发明实施例二的栅极驱动单元电路的电路示意图。如图4所示，该栅极驱动单元电路与图3所示实施例一的区别在于，维持控制节点产生模块4包含的第五薄膜晶体管M5的控制端输入第一时钟信号CKm，第一通路端连接本级维持控制节点netBn，第二通路端改为连接高电平VGH。其他电路部分的实施方式与图3所示实施例一相同。
实施例三：
图5为根据本发明实施例三的栅极驱动单元电路的电路示意图。如图5所示，该栅极驱动单元电路包括上拉控制模块1、上拉模块2、下拉模块3、维持控制节点产生模块4、上拉控制节点维持模块5以及输出节点维持模块6。维持控制节点产生模块4、上拉控制节点维持模块5的电路结构与图3所示实施例一相同。
上拉控制模块1包括第一薄膜晶体管M1A和第十六薄膜晶体管M1B。
第一薄膜晶体管M1A的控制端连接前级栅极驱动单元电路的扫描信号线Gn-1，第一通路端连接本级上拉控制节点netAn，第二通路端连接高电平VGH。在可选的实施方式中，首级栅极驱动单元电路的第一薄膜晶体管M1A的控制端输入正扫启动信号GSP1。第一薄膜晶体管M1A用于在正向扫描时对本级上拉控制节点netAn进行预充。
第十六薄膜晶体管M1B的控制端连接后级栅极驱动单元电路的扫描信号线Gn+1，第一通路端连接本级上拉控制节点netAn，第二通路端连接高电平VGH。在可选的实施方式中，尾级栅极驱动单元电路的第十六薄膜晶体管M1B的控制端输入反扫启动信号GSP2。第十六薄膜晶体管M1B用于在反向扫描时对本级上拉控制节点netAn进行预充。
本发明实施例中，上拉控制模块1采用高电平VGH接第二通路端控制正反向扫描时对本级上拉控制节点预充，减轻了薄膜晶体管的偏压应力和阈值电压漂移。
上拉模块2包括第十薄膜晶体管M10。第十薄膜晶体管M10的控制端连接本级上拉控制节点netAn，第一通路端连接本级扫描信号线Gn，第二通路端连接第一时钟信号CKm。第十薄膜晶体管M10用于对本级扫描信号Gn进行上拉输出以及下拉清空。
下拉模块3包括第九薄膜晶体管M9。第九薄膜晶体管M9的控制端连接第二时钟信号CKm+2，第一通路端连接低电平VSS，第二通路端连接本级上拉控制节点netAn。第九薄膜晶体管M9用于对本级上拉控制节点netAn进行放电。
输出节点维持模块6包括第十一薄膜晶体管M11A。第十一薄膜晶体管 M11A的控制端连接第二时钟信号CKm+2，第一通路端连接低电平VSS，第二通路端连接本级扫描信号线Gn。第十一薄膜晶体管M11A用于对本级扫描信号Gn进行维持。
在一些实施方式中，本发明实施例的栅极驱动单元电路还可以包括清空模块7、辅助维持模块8。
清空模块7包括第二薄膜晶体管M2、第三薄膜晶体管M3以及第十二薄膜晶体管M12。
第二薄膜晶体管M2的控制端输入清空信号CLR，第一通路端和第二通路端分别连接低电平VSS和本级上拉控制节点netAn，第二薄膜晶体管M2用于在每一帧画面结束后和开关机时，对本级上拉控制节点netAn进行清空重置操作。
第三薄膜晶体管M3的控制端输入清空信号CLR，第一通路端和第二通路端分别连接低电平VSS和本级维持控制节点netBn，第三薄膜晶体管M3用于在每一帧画面结束后和开关机时，对本级维持控制节点netBn进行清空重置操作。
第十二薄膜晶体管M12的控制端输入清空信号CLR，第一通路端和第二通路端分别连接低电平VSS和本级扫描信号线，第十二薄膜晶体管M12用于在每一帧画面结束后和开关机时，对本级扫描信号Gn进行清空重置操作。
辅助维持模块8包括第四薄膜晶体管M4A和第十七薄膜晶体管M4B。
第四薄膜晶体管M4A的控制端输入正扫启动信号GSP1，第一通路端和第二通路端分别连接低电平VSS和本级上拉控制节点netAn。在可选的实施方式中，前三级栅极驱动单元电路的第四薄膜晶体管M4A的控制端输入低电平VSS。第四薄膜晶体管M4A用于在正扫画面中，在启动阶段对本级上拉控制节点netAn进行维持。
第十七薄膜晶体管M4B的控制端输入反扫启动信号GSP2，第一通路端和第二通路端分别连接低电平VSS和本级上拉控制节点netAn。在可选的实施方式中，后三级栅极驱动单元电路的第十七薄膜晶体管M4B的控制端输入低电平VSS。第十七薄膜晶体管M4B用于在反扫画面中，在启动阶段对本级上拉控制节点netAn进行维持。
在一些实施方式中，本发明实施例的栅极驱动单元电路还可以包括自举电 容C1，自举电容C1连接于本级上拉控制节点netAn和本级扫描信号线之间，通过电容耦合作用在输出过程中抬升本级上拉控制节点netAn的电位，提高本级扫描信号线的充电速度。
图6为图5所示的栅极驱动单元电路在正向扫描时的驱动波形示意图。其中，
GSP1是正扫启动信号，同时负责在正向扫描时进行启动；
GSP2是反扫启动信号，同时负责在反向扫描时进行启动；
CK1、CK2、CK3、CK4是时钟信号，正向扫描时依序输出；
CLR是清空重置信号，主要负责在每帧结束以及开关机时对电路内部节点进行电荷清空；
VGH是高电平VGH，主要负责上拉控制模块1的输入；
VSS是低电平VSS，主要负责提供扫描信号Gn的低电位；
其他所示波形如netA1、netA2、netAlast-1、netAlast是电路内部节点的输出波形，G1、G2以及Glast分别为各级栅极驱动单元电路输出的扫描信号的波形。
图7为图5所示的栅极驱动单元电路在反向扫描时的驱动波形示意图。其中，
GSP1是正扫启动信号，同时负责在正向扫描时进行启动；
GSP2是反扫启动信号，同时负责在反向扫描时进行启动；
CK1、CK2、CK3、CK4是时钟信号，反向扫描时倒序输出；
CLR是清空重置信号，主要负责在每帧结束以及开关机时对电路内部节点进行电荷清空；
VGH是高电平VGH，主要负责上拉控制模块1的输入；
VSS是低电平VSS，主要负责提供扫描信号Gn的低电位；
其他所示波形如netA1、netA2、netAlast-1、netAlast是电路内部节点的输出波形，G1、G2以及Glast分别为各级栅极驱动单元电路输出的扫描信号的波形。
实施例四：
图8为根据本发明实施例四的栅极驱动单元电路的电路示意图。如图8所示，该栅极驱动单元电路与图5所示实施例三的区别在于：
输出节点维持模块6中的第十一薄膜晶体管M11A的栅极连接本级维持控制节点netBn，第一通路端连接低电平VSS，第二通路端连接本级扫描信号线Gn。其他电路部分的实施方式与图5所示实施例三相同。
实施例五：
图9为根据本发明实施例五的栅极驱动单元电路的电路示意图。如图9所示，该栅极驱动单元电路在图7所示实施例三的基础上，输出节点维持模块6还包括第十九薄膜晶体管M11B，第十九薄膜晶体管M11B的控制端连接本级维持控制节点netBn，第一通路端连接低电平VSS，第二通路端连接本级扫描信号线Gn。第十一薄膜晶体管M11A和第十九薄膜晶体管M11B共同对本级扫描信号Gn进行维持，增强维持能力。
实施例六：
图10为根据本发明实施例六的栅极驱动单元电路的电路示意图。如图10所示，该栅极驱动单元电路与图9所示实施例五的区别在于：
输出节点维持模块6中的第十一薄膜晶体管M11A的控制端连接前级栅极驱动单元电路的维持控制节点netBn-1,第一通路端和第二通路端分别连接低电平VSS和本级扫描信号线；
第十九薄膜晶体管M11B的控制端连接后级栅极驱动单元电路的维持控制节点netBn+1,第一通路端和第二通路端分别连接低电平VSS和本级扫描信号线。
实施例七：
图11为根据本发明实施例七的栅极驱动单元电路的电路示意图。如图11所示，该栅极驱动单元电路与图8所示实施例四的区别在于：
该栅极驱动单元电路还包括级传节点产生模块9，级传节点产生模块9包括第十三薄膜晶体M13和第十四薄膜晶体M14。
第十三薄膜晶体M13的控制端连接本级上拉控制节点netAn，第一通路端连接本级级传节点Tn，第二通路端连接第一时钟信号CKm；第十四薄膜晶体M14的控制端连接本级维持控制节点netBn，第二通路端连接本级级传节点Tn，第一通路端连接低电平VSS。
上拉控制模块1中的第一薄膜晶体管M1A的控制端连接前级栅极驱动单元电路中的级传节点Tn-1，第十六薄膜晶体管M1B的控制端连接后级栅极驱动单元电路中的级传节点Tn+1。
清空模块7还包括第十五薄膜晶体管M15，第十五薄膜晶体管M15的控制端输入清空信号CLR，第一通路端连接低电平VSS，第二通路端连接级本级传节点Tn。第十五薄膜晶体管M15用于一帧显示结束后和开关机时清空本级级传节点Tn。
级传节点产生模块9负责产生级传信号来控制本级级传节点Tn，同时该本级级传节点Tn连接至前后级栅极驱动单元电路中的上拉控制模块1，使栅极驱动电路实现正反向扫描功能。
实施例八：
图12为根据本发明实施例八的栅极驱动单元电路的电路示意图。如图12所示，该栅极驱动单元电路在图5所示实施例三的基础上进行改进，可用于内嵌式触控显示屏，具体改进点在于：
增加了外部输入的触摸控制信号TC；
增加了触控维持模块10，该触控维持模块10包括第十二薄膜晶体管M12，第十二薄膜晶体管M12的控制端输入触摸控制信号TC，第一通路端和第二通路端分别连接低电平VSS和本级扫描信号线。触控维持模块10用于在触控期间对本级栅极驱动单元电路的扫描信号Gn进行维持控制，使得栅极驱动电路支持显示期间任意时间暂停，可用于120Hz的内嵌式触控显示屏。
相应地，清空模块7包括第二薄膜晶体管M2和第三薄膜晶体管M3；第二薄膜晶体管M2的控制端输入清空信号CLR，第一通路端和第二通路端分别连接低电平VSS和本级上拉控制节点netAn，第二薄膜晶体管M2用于在每一帧画面结束后和开关机时，对本级上拉控制节点netAn进行清空重置操作。第三薄膜晶体管M3的控制端输入清空信号CLR，第一通路端和第二通路端分别连接低电平VSS和本级维持控制节点netBn，第三薄膜晶体管M3用于在每一帧画面结束后和开关机时，对本级维持控制节点netBn进行清空重置操作。
图13为图12所示的栅极驱动单元电路在正向扫描时的驱动波形示意图。其 中，
GSP1是正扫启动信号，同时负责在正向扫描时进行启动；
GSP2是反扫启动信号，同时负责在反向扫描时进行启动；
CK1、CK2、CK3、CK4是时钟信号，正向扫描时依序输出；
CLR是清空重置信号，主要负责在每帧结束以及开关机时对电路内部节点进行电荷清空；
TC是触控期间的触摸控制信号，负责在触控期间维持本级扫描信号；
VGH是高电平VGH，主要负责上拉控制模块1的输入；
VSS是低电平VSS，主要负责提供扫描信号Gn的低电位；
其他所示波形如netA1、netA2、netAlast-1、netAlast是电路内部节点的输出波形，G1、G2以及Glast分别为各级栅极驱动单元电路输出的扫描信号的波形。
图14为图12所示的栅极驱动单元电路在反向扫描时的驱动波形示意图。其中，
GSP1是正扫启动信号，同时负责在正向扫描时进行启动；
GSP2是反扫启动信号，同时负责在反向扫描时进行启动；
CK1、CK2、CK3、CK4是时钟信号，反向扫描时倒序输出；
CLR是清空重置信号，主要负责在每帧结束以及开关机时对电路内部节点进行电荷清空；
TC是触控期间的触摸控制信号，负责在触控期间维持本级扫描信号；
VGH是高电平VGH，主要负责上拉控制模块1的输入；
VSS是低电平VSS，主要负责提供扫描信号Gn的低电位；
其他所示波形如netA1、netA2、netAlast-1、netAlast是电路内部节点的输出波形，G1、G2以及Glast分别为各级栅极驱动单元电路输出的扫描信号的波形。
需要说明的是，以上实施例三至实施例八中，维持控制节点产生模块4包含的第五薄膜晶体管M5还可以按照图4所示实施例二进行实施，即第五薄膜晶体管M5的栅极输入第一时钟信号CKm，第一通路端连接本级维持控制节点netBn，第二通路端改为连接高电平VGH。
本发明实施例还提供一种液晶显示装置，该液晶显示装置包括上述栅极驱 动电路，该栅极驱动电路可以是单边驱动方式，也可以是双边驱动方式。
图15为采用本发明实施例的栅极驱动电路的液晶显示装置的示例图。作为本发明实施例的一种可选实施方式，图中AA区表示显示区域，该液晶显示装置采用左右交错式驱动架构，包括左侧栅极驱动电路、右侧栅极驱动电路以及其他驱动电路。
应当说明的是，上述实施例均可根据需要自由组合。以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (19)

  1. 一种栅极驱动单元电路，适于进行多级连接以形成栅极驱动电路，其特征在于，包括上拉控制模块、上拉模块、下拉模块、维持控制节点产生模块、上拉控制节点维持模块以及输出节点维持模块；上拉控制模块、上拉模块、维持控制节点产生模块以及上拉控制节点维持模块相连接于本级上拉控制节点；上拉模块和输出节点维持模块相连接于本级扫描信号线；
    其中，当所述栅极驱动单元电路不是首级和尾级栅极驱动单元电路时，上拉控制节点维持模块连接前级栅极驱动单元电路的维持控制节点产生模块的前级维持控制节点和后级栅极驱动单元电路的维持控制节点产生模块的后级维持控制节点，在所述前级维持控制节点和后级维持控制节点的控制下，对本级上拉控制节点进行维持；
    当所述栅极驱动单元电路是首级栅极驱动单元电路时，上拉控制节点维持模块连接末位时钟信号和后级栅极驱动单元电路的维持控制节点产生模块的后级维持控制节点，在所述末位时钟信号和后级维持控制节点的控制下，对本级上拉控制节点进行维持；
    当所述栅极驱动单元电路是尾级栅极驱动单元电路时，上拉控制节点维持模块连接首位时钟信号和前级栅极驱动单元电路的维持控制节点产生模块的前级维持控制节点，在所述首位时钟信号和前级维持控制节点的控制下，对本级上拉控制节点进行维持。
  2. 根据权利要求1所述的栅极驱动单元电路，其特征在于，所述维持控制节点产生模块包括第五薄膜晶体管、第六薄膜晶体管和第七薄膜晶体管；
    第五薄膜晶体管用于给本级维持控制节点充电，其第一通路端连接本级维持控制节点，控制端和第二通路端输入第一时钟信号；
    第六薄膜晶体管用于在本级栅极驱动单元电路工作期间禁止本级维持控制节点输出，其控制端连接本级上拉控制节点，第一通路端连接低电平，第二通路端连接本级维持控制节点；
    第七薄膜晶体管用于给本级维持控制节点放电，其控制端输入第二时钟信号，第一通路端连接低电平,第二通路端连接本级维持控制节点。
  3. 根据权利要求1所述的栅极驱动单元电路，其特征在于，所述维持控 制节点产生模块包括第五薄膜晶体管、第六薄膜晶体管和第七薄膜晶体管；
    第五薄膜晶体管用于给本级维持控制节点充电，其控制端输入第一时钟信号，第一通路端连接本级维持控制节点，第二通路端连接高电平；
    第六薄膜晶体管用于在本级栅极驱动单元电路工作期间禁止本级维持控制节点输出，其控制端连接本级上拉控制节点，第一通路端连接低电平，第二通路端连接本级维持控制节点；
    第七薄膜晶体管用于给本级维持控制节点放电，其控制端输入第二时钟信号，第一通路端连接低电平,第二通路端连接本级维持控制节点。
  4. 根据权利要求2或3所述的栅极驱动单元电路，其特征在于，所述上拉控制节点维持模块包括第八薄膜晶体管和第十八薄膜晶体管；
    第八薄膜晶体管的控制端连接所述前级维持控制节点，第一通路端连接低电平，第二通路端连接本级上拉控制节点；其中，首级栅极驱动单元电路的第八薄膜晶体管的控制端输入末位时钟信号；
    第十八薄膜晶体管的控制端连接到所述后级维持控制节点，第一通路端连接低电平，第二通路端连接本级上拉控制节点；其中，首级栅极驱动单元电路的第十八薄膜晶体管的控制端输入首位时钟信号。
  5. 根据权利要求2或3所述的栅极驱动单元电路，其特征在于，所述上拉控制模块包括第一薄膜晶体管和第十六薄膜晶体管；
    第一薄膜晶体管用于在正向扫描时对本级上拉控制节点进行预充，其控制端连接前级栅极驱动单元电路的扫描信号线，第一通路端连接本级上拉控制节点，第二通路端连接高电平；其中，首级栅极驱动单元电路的第一薄膜晶体管的控制端输入正扫启动信号；
    第十六薄膜晶体管用于在反向扫描时对本级上拉控制节点进行预充，其控制端连接后级栅极驱动单元电路的扫描信号线，第一通路端连接本级上拉控制节点，第二通路端连接高电平；其中，尾级栅极驱动单元电路的第十六薄膜晶体管的控制端输入反扫启动信号。
  6. 根据权利要求4所述的栅极驱动单元电路，其特征在于，所述电路还包括级传节点产生模块；级传节点产生模块包括第十三薄膜晶体管和第十四 薄膜晶体管；第十三薄膜晶体管的控制端连接本级上拉控制节点，第一通路端和第二通路端分别连接本级级传节点和第一时钟信号；第十四薄膜晶体管的控制端连接本级维持控制节点，第一通路端和第二通路端分别连接低电平和本级级传节点；
    所述上拉控制模块包括第一薄膜晶体管和第十六薄膜晶体管；第一薄膜晶体管的控制端连接前级栅极驱动单元电路的前级级传节点，第一通路端连接本级上拉控制节点，第二通路端连接高电平；第十六薄膜晶体管的控制端连接后级栅极驱动单元电路中的后级级传节点，第一通路端连接本级上拉控制节点，第二通路端连接高电平。
  7. 根据权利要求2或3所述的栅极驱动单元电路，其特征在于，所述输出节点维持模块包括第十一薄膜晶体管，第十一薄膜晶体管用于对本级扫描信号进行维持，其控制端连接第二时钟信号，第一通路端和第二通路端分别连接低电平和本级扫描信号线。
  8. 根据权利要求2或3所述的栅极驱动单元电路，其特征在于，所述输出节点维持模块包括第十一薄膜晶体管,第十一薄膜晶体管用于对本级扫描信号进行维持，其控制端连接本级维持控制节点，第一通路端和第二通路端分别连接低电平和本级扫描信号线。
  9. 根据权利要求7所述的栅极驱动单元电路，其特征在于，所述输出节点维持模块还包括第十九薄膜晶体管；第十九薄膜晶体管的控制端连接本级维持控制节点，第一通路端和第二通路端分别连接低电平和本级扫描信号线。
  10. 根据权利要求2或3所述的栅极驱动单元电路，其特征在于，所述输出节点维持模块包括第十一薄膜晶体管和第十九薄膜晶体管；
    第十一薄膜晶体管的控制端连接所述前级维持控制节点，第一通路端和第二通路端分别连接低电平和本级扫描信号线；第十九薄膜晶体管的控制端连接所述后级维持控制节点，第一通路端和第二通路端分别连接低电平和本级扫描信号线。
  11. 根据权利要求2或3所述的栅极驱动单元电路，其特征在于，所述电路还包括触控维持模块；所述触控维持模块包括第十二薄膜晶体管；第十 二薄膜晶体管的控制端输入触摸控制信号，第一通路端和第二通路端分别连接低电平和本级扫描信号线。
  12. 根据权利要求2或3所述的栅极驱动单元电路，其特征在于，所述上拉模块包括第十薄膜晶体管；第十薄膜晶体管的控制端连接本级上拉控制节点，第一通路端和第二通路端分别连接本级扫描信号线和第一时钟信号。
  13. 根据权利要求2或3所述的栅极驱动单元电路，其特征在于，所述下拉模块包括第九薄膜晶体管；第九薄膜晶体管的控制端输入第二时钟信号，第一通路端和第二通路端分别连接低电平和本级上拉控制节点。
  14. 根据权利要求2或3所述的栅极驱动单元电路，其特征在于，所述电路还包括辅助维持模块；所述辅助维持模块包括第四薄膜晶体管和第十七薄膜晶体管；
    第四薄膜晶体管的控制端输入正扫启动信号，第一通路端和第二通路端分别连接低电平和本级上拉控制节点；其中，前三级栅极驱动单元电路的第四薄膜晶体管的控制端输入低电平；
    第十七薄膜晶体管的控制端输入反扫启动信号，第一通路端和第二通路端分别连接低电平和本级上拉控制节点；其中，后三级栅极驱动单元电路的第十七薄膜晶体管的控制端输入低电平。
  15. 根据权利要求2或3所述的栅极驱动单元电路，其特征在于，所述电路还包括清空模块；所述清空模块包括第二薄膜晶体管、第三薄膜晶体管和第十二薄膜晶体管；
    第二薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级上拉控制节点；
    第三薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级维持控制节点；
    第十二薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级扫描信号线。
  16. 根据权利要求6所述的栅极驱动单元电路，其特征在于，所述电路还包括清空模块；所述清空模块包括第二薄膜晶体管、第三薄膜晶体管、第 十二薄膜晶体管以及第十五薄膜晶体管；
    第二薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级上拉控制节点；
    第三薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级维持控制节点；
    第十二薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级扫描信号线；
    第十五薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级级传节点。
  17. 根据权利要求11所述的栅极驱动单元电路，其特征在于，所述电路还包括清空模块；所述清空模块包括第二薄膜晶体管和第三薄膜晶体管；
    第二薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级上拉控制节点；
    第三薄膜晶体管的控制端输入清空信号，第一通路端和第二通路端分别连接低电平和本级维持控制节点。
  18. 一种栅极驱动电路，其特征在于，包括N级如权利要求1-17任一项所述的栅极驱动单元电路，N为大于3的整数；其中，
    当2≦n≦N-1，第n级栅极驱动单元电路的上拉控制节点维持模块分别连接第n-1级栅极驱动单元电路的维持控制节点产生模块和第n+1级栅极驱动单元电路的维持控制节点产生模块；
    当n＝1，第n级栅极驱动单元电路的上拉控制节点维持模块输入末位时钟信号，并连接第n+1级栅极驱动单元电路的维持控制节点产生模块；
    当n＝N，第n级栅极驱动单元电路的上拉控制节点维持模块输入首位时钟信号，并连接第n-1级栅极驱动单元电路的维持控制节点产生模块。
  19. 一种显示装置，其特征在于，包括如权利要求18所述的栅极驱动电路。
PCT/CN2018/122431 2017-12-27 2018-12-20 栅极驱动单元电路、栅极驱动电路和显示装置 WO2019128845A1 (zh)

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