WO2019125392A1

WO2019125392A1 - Integrated circuit structures, selector devices, and methods

Info

Publication number: WO2019125392A1
Application number: PCT/US2017/067127
Authority: WO
Inventors: Roza Kotlyar; Ravi Pillarisetty; Elijah Karpov; Brian Doyle; Abhishek Sharma
Original assignee: Intel Corporation
Priority date: 2017-12-18
Filing date: 2017-12-18
Publication date: 2019-06-27

Abstract

Integrated circuit structures are provided that may include a first insulating-to-metallic transition material, a second insulating-to-metallic transition material, and a third layer. The third layer may have an electron affinity that is greater than the electron affinity of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material. Selectors that include integrated circuit structures also are provided.

Description

INTEGRATED CIRCUIT STRUCTURES, SELECTOR DEVICES, AND METHODS

Technical Field

Embodiments described herein generally relate to integrated circuit structures and selector devices that may have a reduced off-state current, and methods of making integrated circuit structures and selector devices.

Background

Selector devices are found in many different forms. For example, selector devices may replace transistors in non-volatile memory arrays. Selector devices may also be used in phase change memory (PCM) arrays. Such devices may use various materials, such as chalcogenide glass, that exhibit volatile transition from a non-conductive state to a conductive state based on how the devices are biased. Selector devices, however, often have unacceptable leakage current which can lead to power inefficiency and overall poor product performance.

Selector devices can include three terminal selector devices and two terminal selector devices, and some two terminal selector devices can include an insulating-to-metallic transition (IMT) material instead of an insulator.

An IMT material can switch from an insulating state to a metallic state, and when in the insulating state, most, if not all, common IMT materials have unacceptable leakage current. Therefore, attempts have been made to address this disadvantage by inserting barrier layers between an active layer and each of the electrodes of certain selectors to increase the Schottky barrier.

There remains a need, however, for integrated circuit structures and selector devices that overcome the foregoing disadvantage by reducing or eliminating leakage current.

Brief Description of the Drawings

FIG. 1 depicts one embodiment of an integrated circuit structure.

FIG. 2 depicts one embodiment of a selector device.

FIG. 3 depicts one embodiment of a memory array including selector devices.

FIG. 4 depicts one embodiment of a system that may include embodiments of selector devices herein. FIG. 5 depicts one embodiment of a system that may include embodiments of selector devices herein.

FIG. 6 depicts one embodiment of a system that may include embodiments of selector devices herein.

Description of Embodiments

Provided herein are embodiments of integrated circuit structures that may be part of a selector, and, in some embodiments, the integrated circuit structures have a configuration that reduces or eliminates leakage current when one or more IMT materials of the integrated circuit structure are in an insulating state.

The leakage current may be reduced or eliminated by including a third layer, as described herein, in an integrated circuit structure. Due at least in part to the reduction or elimination of leakage, embodiments of the integrated circuit structures provided herein have a lower off- current than comparable integrated circuit structures that lack a third layer.

In embodiments, the integrated circuit structures that include a third layer are capable of maintaining the threshold voltage and ON current at about (i.e., ± 5 %) the same level as comparable integrated circuit structures that lack a third layer, but have substantially the same (i) thickness and (ii) IMT material(s).

In embodiments, the integrated circuit structures provided herein include [1] a first layer comprising a first insulating-to-metallic transition material; [2] a second layer comprising a second insulating-to-metallic transition material; and [3] a third layer arranged between the first layer and the second layer.

The third layer may include a dielectric material having an electron affinity that is greater than the electron affinity of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material. In embodiments, the electron affinity of the dielectric material is greater than the electron affinity of the first insulating-to-metallic transition material and the second insulating-to-metallic transition material.

The third layer may include a dielectric material having a dielectric constant that is greater than the dielectric constant of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material. In some embodiments, the dielectric constant of the dielectric material is greater than the dielectric constant of the first insulating-to-metallic transition material and the second insulating-to-metallic transition material.

The third layer may include a dielectric material having (1) an electron affinity that is greater than the electron affinity of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material, and (2) a dielectric constant that is greater than the dielectric constant of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material. The third layer may include a dielectric material having (1) an electron affinity that is greater than the electron affinity of the first insulating-to-metallic transition material and the second insulating-to-metallic transition material, and (2) a dielectric constant that is greater than the dielectric constant of the first insulating-to-metallic transition material and the second insulating-to-metallic transition material.

An embodiment of an integrated circuit structure is depicted at FIG. 1. The integrated circuit structure 100 of FIG. 1 includes a first layer 110 that includes a first insulating-to- metallic transition material, and a second layer 130 that includes a second insulating-to-metallic transition material. Arranged between the first layer 110 and the second layer 130 is a third layer 120 of a dielectric material.

In embodiments, the third layer includes a dielectric material having at electron affinity of at least 3 eV. In embodiments, the third layer includes a dielectric material having at electron affinity of at least 4 eV. In embodiments, the third layer includes a dielectric material having at electron affinity of at least 5 eV. In embodiments, the third layer includes a dielectric material having at electron affinity of at least 6 eV. In embodiments, the third layer includes a dielectric material having at electron affinity of at least 7 eV.

In embodiments, the third layer includes a dielectric material having an electron affinity that is at least 1 eV greater than the electron affinity of (1) the first insulating-to-metallic transition material, (2) the second insulating-to-metallic transition material, or (3) each of the first insulating-to-metallic transition material and the second insulting-to-metallic transition material. In embodiments, the third layer includes a dielectric material having an electron affinity that is at least 1.5 eV greater than the electron affinity of (1) the first insulating-to- metallic transition material, (2) the second insulating-to-metallic transition material, or (3) each of the first insulating-to-metallic transition material and the second insulting-to-metallic transition material. In embodiments, the third layer includes a dielectric material having an electron affinity that is at least 2 eV greater than the electron affinity of (1) the first insulating-to- metallic transition material, (2) the second insulating-to-metallic transition material, or (3) each of the first insulating-to-metallic transition material and the second insulting-to-metallic transition material. In embodiments, the third layer includes a dielectric material having an electron affinity that is at least 2.5 eV greater than the electron affinity of (1) the first insulating- to-metallic transition material, (2) the second insulating-to-metallic transition material, or (3) each of the first insulating-to-metallic transition material and the second insulting-to-metallic transition material. In embodiments, the third layer includes a dielectric material having an electron affinity that is at least 3 eV greater than the electron affinity of (1) the first insulating-to- metallic transition material, (2) the second insulating-to-metallic transition material, or (3) each of the first insulating-to-metallic transition material and the second insulting-to-metallic transition material.

In embodiments, the third layer includes a dielectric material having a dielectric constant of at least 30. In embodiments, the third layer includes a dielectric material having a dielectric constant of at least 35. In embodiments, the third layer includes a dielectric material having a dielectric constant of at least 40. In embodiments, the third layer includes a dielectric material having a dielectric constant of at least 45. In embodiments, the third layer includes a dielectric material having a dielectric constant of at least 50.

In embodiments, the third layer includes a dielectric material having a dielectric constant that is at least 10 % greater than the dielectric constant of (1) the first insulating-to-metallic transition material, (2) the second insulating-to-metallic transition material, or (3) each of the first insulating-to-metallic transition material and the second insulating-to-metallic transition material. In embodiments, the third layer includes a dielectric material having a dielectric constant that is at least 15 % greater than the dielectric constant of (1) the first insulating-to- metallic transition material, (2) the second insulating-to-metallic transition material, or (3) each of the first insulating-to-metallic transition material and the second insulating-to-metallic transition material. In embodiments, the third layer includes a dielectric material having a dielectric constant that is at least 20 % greater than the dielectric constant of (1) the first insulating-to-metallic transition material, (2) the second insulating-to-metallic transition material, or (3) each of the first insulating-to-metallic transition material and the second insulating-to- metallic transition material. In embodiments, the third layer includes a dielectric material having a dielectric constant that is at least 25 % greater than the dielectric constant of (1) the first insulating-to-metallic transition material, (2) the second insulating-to-metallic transition material, or (3) each of the first insulating-to-metallic transition material and the second insulating-to- metallic transition material. In embodiments, the third layer includes a dielectric material having a dielectric constant that is at least 30 % greater than the dielectric constant of (1) the first insulating-to-metallic transition material, (2) the second insulating-to-metallic transition material, or (3) each of the first insulating-to-metallic transition material and the second insulating-to- metallic transition material.

Generally, the integrated circuit structures provided herein may have any thickness, including a thickness that does not substantially undermine the function of the integrated circuit structure. In embodiments, the integrated circuit structures provided herein have a thickness of about 3 nm to about 50 nm. In embodiments, the integrated circuit structures provided herein have a thickness of about 5 nm to about 50 nm. In embodiments, the integrated circuit structures provided herein have a thickness of about 10 nm to about 40 nm. In embodiments, the integrated circuit structures provided herein have a thickness of about 10 nm to about 30 nm. In

embodiments, the integrated circuit structures provided herein have a thickness of about 15 nm to about 25 nm. In embodiments, the integrated circuit structures provided herein have a thickness of about 20 nm. The thickness of the integrated circuit structure includes the sum of the thickness of each layer in an integrated circuit structure, which may include a third layer, a first insulating-to-metallic transition material, and a second insulating-to-metallic transition material.

Generally, the third layer may have any thickness, including a thickness that does not substantially undermine a third layer’s ability to achieve one or more of the advantages provided herein. In embodiments, the third layer has a thickness of about 0.2 nm to about 5 nm. In embodiments, the third layer has a thickness of about 0.5 nm to about 5 nm. In embodiments, the third layer has a thickness of about 0.5 nm to about 4 nm. In embodiments, the third layer has a thickness of about 0.5 nm to about 3 nm. In embodiments, the third layer has a thickness of about 0.5 nm to about 2 nm. In embodiments, the third layer has a thickness of about 0.5 nm to about 1.5 nm. In embodiments, the third layer has a thickness of about 1 nm. Generally, the first insulating-to-metallic transition material and the second insulating-to- metallic transition material may, independently, have any thickness, including any thickness that does not substantially undermine the function of the integrated circuit structure. The thickness of the first insulating-to-metallic transition material and the thickness of the second insulating-to- metallic transition material may be the same or different. In embodiments, the first insulating-to- metallic transition material and the second insulating-to-metallic transition material,

independently, have a thickness of about 5 nm to about 20 nm. In embodiments, the first insulating-to-metallic transition material and the second insulating-to-metallic transition material, independently, have a thickness of about 5 nm to about 15 nm. In embodiments, the first insulating-to-metallic transition material and the second insulating-to-metallic transition material, independently, have a thickness of about 7 nm to about 13 nm. In embodiments, the first insulating-to-metallic transition material and the second insulating-to-metallic transition material, independently, have a thickness of about 8 nm to about 10.5 nm. In embodiments, the first insulating-to-metallic transition material and the second insulating-to-metallic transition material, independently, have a thickness of about 9.5 nm.

In embodiments, the selectors provided herein include a first electrode, a second electrode, and an integrated circuit structure arranged between the first electrode and the second electrode, wherein the integrated circuit structure includes a first layer comprising a first insulating-to-metallic transition material, a second layer comprising a second insulating-to- metallic transition material, and a third layer, as described herein, arranged between the first layer and the second layer.

An embodiment of a selector is depicted at FIG. 2. The selector 200 of FIG. 2 includes an integrated circuit structure of three layers: a first layer 210 that includes a first insulating-to- metallic transition material, a second layer 230 that includes a second insulating-to-metallic transition material, and a third layer 220 of a dielectric material arranged between the first layer 210 and the second layer 230. The integrated circuit structure is arranged between a first electrode 240 and a second electrode 250.

The selectors provided herein may also include at least one of a third electrode arranged between the first insulating-to-metallic transition material and the third layer, or a fourth electrode arranged between the second insulating-to-metallic transition material and the third layer. The electrodes of the selectors provided herein can include one or more conductive materials, including conductive materials having high work function, for example, to minimize the leakage current to the dielectric layer at low voltages. The electrode materials can have work function greater than about 3 eV, or greater than 4 eV, such as 4.5 or 5 eV. The electrode materials can include TiN, TaN, Ni, Pt, Ru, or any mixture or alloy thereof. Example materials for the electrodes may include one or more conducting materials, such as Pt, Ta, Hf, Zr, Al, Co, Ni, Fe, Nb, Mo, W, Cu, Ti, TiN, TaN, Ta₂N, WN₂, NbN, MoN, TiSi₂, TiSi, TisSis, TaSi₂, WSi₂, NbSi₂, V3S1, electrically doped Si polycrystalline, or electrically doped Ge polycrystalline.

The third layers provided herein may include a metal, such as a transition metal, and oxygen. For example, the third layers may include a metal oxide, such as a transition metal oxide. In some embodiments, the third layers provided herein include oxygen and at least one element selected from the group consisting of Ti, Hf, Ta, and Zr. In some embodiments, the third layers provided herein include a compound selected from the group consisting of Ti0₂, Hf0₂, TaOx, and Zr0₂. In some embodiments, the third layers provided herein include a compound selected from the group consisting of Ti0₂, Hf0₂, Ta₂Os, and Zr0₂. Non-limiting examples of metal oxides include oxides that include at least one of niobium (Nb), tantalum (Ta), vanadium (V), titanium (Ti), chromium (Cr), yttrium (Y), aluminum (Al), or silicon (Si).

The integrated circuit structures and the selectors provided herein may be made by any methods known in the art. For example, the integrated circuit structure and the selector devices may be made by one or more methods that include atomic layer deposition, physical vapor deposition, such as RF sputtering of an oxide target or reactive sputtering of metal target in the oxygen atmosphere.

Also provided herein are memory arrays, including transistor-less non-volatile memory arrays, that include one or more of the selector devices provided herein. In some embodiments, the memory arrays have a structure as depicted at FIG. 3. FIG. 3 depicts a transistor-less non volatile memory array 300. More specifically, FIG. 3 depicts a perspective view of one embodiment of a portion of a chalcogenide-based phase-change cross point memory array 300.

Cross-point memory 300 can be, but is not limited to, part of a solid-state memory array or a solid-state drive. Cross point memory 300 comprises a plurality of memory cells 301 that are each arranged in a column (or pillar), of which only a few are indicated. Additionally, it should be understood that a dielectric material that is normally between memory cells 301 is not shown in FIG. 3 for clarity.

Each memory cell 301 comprises a selector device as described herein that includes a first electrode 304 formed on a word line metallization 302. A first layer comprising a first insulating-to-metallic transition material 305 is formed on electrode 304. A third layer 306 is formed on the first insulating-to-metallic transition material 305. A second layer comprising a second insulating-to-metallic transition material 307 is formed on the third layer 306. A second electrode 308 is formed on second insulating-to-metallic transition material 307.

An embodiment forms an electrode-chalcogenide interface layer 309 on electrode 308. Layer 309 may include tungsten and/or molybdenum carbide and/or boride interface layers. The interface layer formed between an electrode layer 308 and chalcogenide layer 310 provides a reduced resistance in comparison to an electrode-chalcogenide interface without a carbide- and/or boride-based interface layer. Interface layers such as layers (309, 311) are described more fully in U.S. Patent Application Publication Number 20150123066, assigned to Intel Corp. of Santa Clara, CA, USA and are included in some but not all memory related embodiments described herein. A chalcogenide memory cell (MC) 310 is formed on interface layer 309. An electrode-chalcogenide interface layer 311 is formed on MC 310. An electrode 312 is formed on interface layer 311. A bit line metallization layer 313 is formed on electrode 312.

The memory cell (layers 309, 310, 311, 312) is not limited to PCM. Other memory element options are, for example, programmable metallization cell (PMC) memory cells (also sometimes referred to as conductive bridge random access memory (CBRAM)) based on Ag or Cu filaments. Other memory element options are, for example, HfOx or TaOx based resistive RAM (RRAM) based on oxygen vacancy based filaments, or other resistive switching memories.

In embodiments of the subject matter disclosed herein, word line metallization layer 302 and bit line metallization layer 313 are formed from, for example, tungsten, copper and/or aluminum. In one exemplary embodiment, electrode layers 304, 308 and 312 are composite electrodes that are formed from, for example, carbon (C) and/or titanium nitride (TiN). In one exemplary embodiment, switching device layer 306 is formed from, for example, an OTS (Ovonic Threshold Switch) comprising a glassy mixture of the chalcogenides, such as, but not limited to, Te and Se, and glass forming additives such as, but not limited to, arsenic (As), germanium (Ge) and silicon (Si). Note that this is not an exhaustive list of either chalcogenides or glass forming additives. In other embodiments, layer 306 may include MIT or Mott materials formed of one of: Mott Oxides such as Nb02, metal doped Nb02, VO2, metal-doped V2O3,

Fe30₄, FeS, Ta20s, T1₃O5, T12O₃, LaCo0₃, or SmNi0_3. In one exemplary embodiment, chalcogenide memory cell 310 is formed from, for example, but is not limited to,

Ge₂Sb2Te₅(GST) and In₃SbTe2(IST).

In one exemplary embodiment, electrode-chalcogenide interface layers 309 and 311 are formed from carbides and/or borides of tungsten (W) and/or molybdenum (Mo). In one exemplary embodiment, interface layers 309 and 311 are formed by using, for example, a reactive physical vapor deposition (PVD) (e.g., reactive sputtering) from W/Mo targets using unsaturated organic carbon compounds, such as benzene and acetylene. In another exemplary embodiment, interface layers 309 and 311 are formed non-reactively by being sputtered from W/Mo carbide and boride targets. Although interface layers 309 and 311 are depicted in FIG. 3, it should be understood that alternative exemplary embodiments may have fewer (e.g., 0 or 1) or more interface layers (e.g., 2 or more).

FIG. 3 depicts a schematic diagram of an exemplary embodiment of a cross-point memory array 300 comprising a plurality of memory cells 301. Memory cells 301 are located at intersections of column signal lines 302 (e.g., word lines) and row signal lines 313 (e.g., bit lines). Individual column and/or row signal lines are electrically connected in a well-known manner to a memory controller (not shown) to selectively operate memory cells 301 in a well- known manner. It should be understood that memory array 300 can comprise part of a solid-state memory array or a solid-state drive that is coupled in a well-known manner to a computer system or an information-processing system (not shown).

FIG. 4, FIG. 5, and FIG. 6 each include a system that may include any of the above described embodiments. FIG. 4, FIG. 5, and FIG. 6 include block diagrams of systems 900, 1000, 1300 in accordance with embodiments. Each of those systems may include hundreds or thousands of the above described selector devices (e.g., FIG. 2) and be critical to functions (e.g., memory functions of memories that include such selector devices) in those systems. The selector devices may be included in, for example, elements 910, 930, 1070, 1032, 1090, 1310, 1340,

1380, and the like. Systems 900, 1000, 1300 may be included in, for example, a mobile computing node such as a cellular phone, smartphone, tablet, Ultrabook®, notebook, laptop, personal digital assistant, and mobile processor based platform. The size savings and power efficiency of such devices accumulates when, for example, the selector switch based memories are deployed in mass and provides significant performance advantages to such computing nodes.

Referring now to FIG. 4, shown is a block diagram of an example system with which embodiments can be used. As seen, system 900 may be a smartphone or other wireless communicator or any other IoT device. A baseband processor 905 is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system. In turn, baseband processor 905 is coupled to an application processor 910, which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps.

Application processor 910 may further be configured to perform a variety of other computing operations for the device.

In turn, application processor 910 can couple to a user interface/display 920, e.g., a touch screen display. In addition, application processor 910 may couple to a memory system including a non-volatile memory, namely a flash memory 930 and a system memory, namely a DRAM 935. In some embodiments, flash memory 930 may include a secure portion 932 in which secrets and other sensitive information may be stored. As further seen, application processor 910 also couples to a capture device 945 such as one or more image capture devices that can record video and/or still images.

A universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure storage 942 to store secure user information. System 900 may further include a security processor 950 that may couple to application processor 910. A plurality of sensors 925, including one or more multi-axis accelerometers may couple to application processor 910 to enable input of a variety of sensed information such as motion and other environmental information. In addition, one or more authentication devices 995 may be used to receive, e.g., user biometric input for use in authentication operations.

As further illustrated, a near field communication (NFC) contactless interface 960 is provided that communicates in a NFC near field via an NFC antenna 965. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities. A power management integrated circuit (PMIC) 915 couples to application processor 910 to perform platform level power management. To this end, PMIC 915 may issue power management requests to application processor 910 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 915 may also control the power level of other components of system 900.

To enable communications to be transmitted and received such as in one or more IoT networks, various circuitries may be coupled between baseband processor 905 and an antenna 990. Specifically, a radio frequency (RF) transceiver 970 and a wireless local area network (WLAN) transceiver 975 may be present. In general, RF transceiver 970 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition, a GPS sensor 980 may be present, with location information being provided to security processor 950 for use as described herein when context information is to be used in a pairing process. Other wireless communications such as receipt or transmission of radio signals, e.g., AM/FM and other signals may also be provided. In addition, via WLAN transceiver 975, local wireless communications, such as according to a Bluetooth™ or IEEE 802.1 1 standard can also be realized.

Referring now to FIG. 5, shown is a block diagram of a system in accordance with another embodiment. Multiprocessor system 1000 is a point-to-point interconnect system such as a server system, and includes a first processor 1070 and a second processor 1080 coupled via a point-to- point interconnect 1050. Each of processors 1070 and 1080 may be multicore processors such as SoCs, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b), although potentially many more cores may be present in the processors. In addition, processors 1070 and 1080 each may include a secure engine 1075 and 1085 to perform security operations such as key management, attestations, loT network onboarding or so forth.

First processor 1070 further includes a memory controller hub (MCH) 1072 and point-to- point (P-P) interfaces 1076 and 1078. Similarly, second processor 1080 includes a MCH 1082 and P-P interfaces 1086 and 1088. MCH's 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors. First processor 1070 and second processor 1080 may be coupled to a chipset 1090 via P-P interconnects 1052 and 1054,

respectively. As shown in FIG. 5, chipset 1090 includes P-P interfaces 1094 and 1098.

Furthermore, chipset 1090 includes an interface 1092 to couple chipset 1090 with a high performance graphics engine 1038, by a P-P interconnect 1039. In turn, chipset 1090 may be coupled to a first bus 1016 via an interface 1096. Various input/output (I/O) devices 1014 may be coupled to first bus 1016, along with a bus bridge 1018 which couples first bus 1016 to a second bus 1020. Various devices may be coupled to second bus 1020 including, for example, a keyboard/mouse 1022, communication devices 1026 and a data storage unit 1028 such as a nonvolatile storage or other mass storage device. As seen, data storage unit 1028 may include code 1030, in one embodiment. As further seen, data storage unit 1028 also includes a trusted storage 1029 to store sensitive information to be protected. Further, an audio I/O 1024 may be coupled to second bus 1020.

Embodiments may be used in environments where Internet of Things (loT) devices may include wearable devices or other small form factor loT devices.

Referring now to FIG. 6, shown is a block diagram of a wearable module 1300 in accordance with another embodiment. In one particular implementation, module 1300 may be an Intel® Curie™ module that includes multiple components adapted within a single small module that can be implemented as all or part of a wearable device. As seen, module 1300 includes a core 1310 (of course in other embodiments more than one core may be present). Such core may be a relatively low complexity in-order core, such as based on an Intel Architecture® Quark™ design. In some embodiments, core 1310 may implement a TEE as described herein. Core 1310 couples to various components including a sensor hub 1320, which may be configured to interact with a plurality of sensors 1380, such as one or more biometric, motion environmental or other sensors. A power delivery circuit 1330 is present, along with a non-volatile storage 1340. In an embodiment, this circuit may include a rechargeable battery and a recharging circuit, which may in one embodiment receive charging power wirelessly. One or more input/output (IO) interfaces 1350, such as one or more interfaces compatible with one or more of ETSB/SPI/I2C/GPIO protocols, may be present. In addition, a wireless transceiver 1390, which may be a Bluetooth™ low energy or other short-range wireless transceiver is present to enable wireless

communications as described herein. Understand that in different implementations a wearable module can take many other forms. Wearable and/or loT devices have, in comparison with a typical general purpose CPU or a GPU, a small form factor, low power requirements, limited instruction sets, relatively slow computation throughput, or any of the above.

Various embodiments include a semiconductive substrate. Such a substrate may be a bulk semiconductive material this is part of a wafer. In an embodiment, the semiconductive substrate is a bulk semiconductive material as part of a chip that has been singulated from a wafer. In an embodiment, the semiconductive substrate is a semiconductive material that is formed above an insulator such as a semiconductor on insulator (SOI) substrate. In an embodiment, the

semiconductive substrate is a prominent structure such as a fin that extends above a bulk semiconductive material.

Examples

The following examples pertain to further embodiments. Various optional features of the apparatuses and methods described herein are provided by the Examples, and all optional features of the apparatuses may also be implemented with respect to the methods described herein. Specifics in the following examples may be used anywhere in one or more embodiments.

Example 1 is an integrated circuit structure including a first layer comprising a first insulating-to-metallic transition material; a second layer comprising a second insulating-to- metallic transition material; and a third layer arranged between the first layer and the second layer; wherein the third layer includes a dielectric material having an electron affinity that is greater than the electron affinity of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material.

In example 2, the subject matter of example 1 can optionally include the dielectric material, wherein the dielectric material has an electron affinity that is greater than the electron affinity of the first insulating-to-metallic transition material and the second insulating-to-metallic transition material.

In example 3, the subject matter of examples 1 or 2 can optionally include the dielectric material, wherein the dielectric material has a dielectric constant that is greater than the dielectric constant of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material. In example 4, the subject matter of examples 1, 2, or 3 can optionally include the dielectric material, wherein the dielectric constant of the dielectric material is greater than the dielectric constant of the first insulating-to-metallic transition material and the second insulating- to-metallic transition material.

In example 5, the subject matter of example 3 or 4 can optionally include a dielectric constant of the dielectric material of at least 30.

In example 6, the subject matter of example 3 or 4 can optionally include a dielectric constant of the dielectric material of at least 35.

In example 7, the subject matter of example 3 or 4 can optionally include a dielectric constant of the dielectric material of at least 40.

In example 8, the subject matter of example 3 or 4 can optionally include a dielectric constant of the dielectric material of at least 45.

In example 9, the subject matter of example 3 or 4 can optionally include a dielectric constant of the dielectric material of at least 50.

In example 10, the subject matter of any one of examples 1-9 can optionally include a dielectric constant of the dielectric material that is at least 10 % greater than the dielectric constant of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material.

In example 11, the subject matter of any one of examples 1-9 can optionally include a dielectric constant of the dielectric material that is at least 10 % greater than the dielectric constant of the first insulating-to-metallic transition material and the second insulating-to- metallic transition material.

In example 12, the subject matter of any one of examples 1-9 can optionally include a dielectric constant of the dielectric material that is at least 15 % greater than the dielectric constant of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material.

In example 13, the subject matter of any one of examples 1-9 can optionally include a dielectric constant of the dielectric material that is at least 15 % greater than the dielectric constant of the first insulating-to-metallic transition material and the second insulating-to- metallic transition material. In example 14, the subject matter of any one of examples 1-9 can optionally include a dielectric constant of the dielectric material that is at least 20 % greater than the dielectric constant of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material.

In example 15, the subject matter of any one of examples 1-9 can optionally include a dielectric constant of the dielectric material that is at least 20 % greater than the dielectric constant of the first insulating-to-metallic transition material and the second insulating-to- metallic transition material.

In example 16, the subject matter of any one of examples 1-9 can optionally include a dielectric constant of the dielectric material that is at least 25 % greater than the dielectric constant of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material.

In example 17, the subject matter of any one of examples 1-9 can optionally include a dielectric constant of the dielectric material that is at least 25 % greater than the dielectric constant of the first insulating-to-metallic transition material and the second insulating-to- metallic transition material.

In example 18, the subject matter of any one of examples 1-9 can optionally include a dielectric constant of the dielectric material that is at least 30 % greater than the dielectric constant of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material.

In example 19, the subject matter of any one of examples 1-9 can optionally include a dielectric constant of the dielectric material that is at least 30 % greater than the dielectric constant of the first insulating-to-metallic transition material and the second insulating-to- metallic transition material.

In example 20, the subject matter of any one of examples 1-19 can optionally include a dielectric constant of the dielectric material that is at least 10 % greater than the dielectric constant of the first insulating-to-metallic transition material.

In example 21, the subject matter of any one of examples 1-19 can optionally include a dielectric constant of the dielectric material that is at least 15 % greater than the dielectric constant of the first insulating-to-metallic transition material. In example 22, the subject matter of any one of examples 1-19 can optionally include a dielectric constant of the dielectric material that is at least 20 % greater than the dielectric constant of the first insulating-to-metallic transition material.

In example 23, the subject matter of any one of examples 1-19 can optionally include a dielectric constant of the dielectric material that is at least 25 % greater than the dielectric constant of the first insulating-to-metallic transition material.

In example 24, the subject matter of any one of examples 1-19 can optionally include a dielectric constant of the dielectric material that is at least 30 % greater than the dielectric constant of the first insulating-to-metallic transition material.

In example 25, the subject matter of any one of examples 1-19 can optionally include a dielectric constant of the dielectric material that is at least 10 % greater than the dielectric constant of the second insulating-to-metallic transition material.

In example 26, the subject matter of any one of examples 1-24 can optionally include a dielectric constant of the dielectric material that is at least 15 % greater than the dielectric constant of the second insulating-to-metallic transition material.

In example 27, the subject matter of any one of examples 1-24 can optionally include a dielectric constant of the dielectric material that is at least 20 % greater than the dielectric constant of the second insulating-to-metallic transition material.

In example 28, the subject matter of any one of examples 1-24 can optionally include a dielectric constant of the dielectric material that is at least 25 % greater than the dielectric constant of the second insulating-to-metallic transition material.

In example 29, the subject matter of any one of examples 1-24 can optionally include a dielectric constant of the dielectric material that is at least 30 % greater than the dielectric constant of the second insulating-to-metallic transition material.

In example 30, the subject matter of any one of claims 1-29 can optionally include the dielectric material having an electron affinity of at least 3 eV.

In example 31, the subject matter of any one of claims 1-29 can optionally include the dielectric material having an electron affinity of at least 4 eV.

In example 32, the subject matter of any one of claims 1-29 can optionally include the dielectric material having an electron affinity of at least 5 eV. In example 33, the subject matter of any one of claims 1-29 can optionally include the dielectric material having an electron affinity of at least 6 eV.

In example 34, the subject matter of any one of claims 1-29 can optionally include the dielectric material having an electron affinity of at least 7 eV.

In example 35, the subject matter of any one of claims 1-34 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 1 eV greater than the electron affinity of the first insulating-to-metallic transition material.

In example 36, the subject matter of any one of claims 1-34 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 1.5 eV greater than the electron affinity of the first insulating-to-metallic transition material.

In example 37, the subject matter of any one of claims 1-34 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 2 eV greater than the electron affinity of the first insulating-to-metallic transition material.

In example 38, the subject matter of any one of claims 1-34 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 2.5 eV greater than the electron affinity of the first insulating-to-metallic transition material.

In example 39, the subject matter of any one of claims 1-34 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 3 eV greater than the electron affinity of the first insulating-to-metallic transition material.

In example 40, the subject matter of any one of claims 1-39 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 1 eV greater than the electron affinity of the second insulating-to-metallic transition material.

In example 41, the subject matter of any one of claims 1-39 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 1.5 eV greater than the electron affinity of the second insulating-to-metallic transition material.

In example 42, the subject matter of any one of claims 1-39 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 2 eV greater than the electron affinity of the second insulating-to-metallic transition material.

In example 43, the subject matter of any one of claims 1-39 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 2.5 eV greater than the electron affinity of the second insulating-to-metallic transition material. In example 44, the subject matter of any one of claims 1-39 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 3 eV greater than the electron affinity of the second insulating-to-metallic transition material.

In example 45, the subject matter of any one of claims 1-44 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 1 eV greater than the electron affinity of each of the first insulating-to-metallic transition material and the second insulating-metallic-transition material.

In example 46, the subject matter of any one of claims 1-44 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 1.5 eV greater than the electron affinity of each of the first insulating-to-metallic transition material and the second insulating-metallic-transition material.

In example 47, the subject matter of any one of claims 1-44 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 2 eV greater than the electron affinity of each of the first insulating-to-metallic transition material and the second insulating-metallic-transition material.

In example 48, the subject matter of any one of claims 1-44 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 2.5 eV greater than the electron affinity of each of the first insulating-to-metallic transition material and the second insulating-metallic-transition material.

In example 49, the subject matter of any one of claims 1-44 can optionally include the dielectric material, wherein the electron affinity of the dielectric material is at least 3 eV greater than the electron affinity of each of the first insulating-to-metallic transition material and the second insulating-metallic-transition material.

In example 50, the subject matter of any one of examples 1-49 can optionally include the first insulating-to-metallic transition material and the second insulating-to-metallic transition material, wherein the first insulating-to-metallic transition material and the second insulating-to- metallic transition material are identical.

In example 51, the subject matter of any one of examples 1-50 can optionally include the first insulating-to-metallic transition material, wherein the first insulating-to-metallic transition material is selected from the group consisting of an oxide-based insulating-to-metallic transition material and a chalcogenide-based insulating-to-metallic transition material. In example 52, the subject matter of any one of examples 1-51 can optionally include the first insulating-to-metallic transition material, wherein the first insulating-to-metallic material comprises [1] oxygen and at least one element selected from the group consisting of vanadium, titanium, lanthanum, cobalt, niobium, samarium, and nickel, or [2] at least one element selected from the group consisting of silicon, tellurium, arsenic, and germanium; or the first insulating-to- metallic material is selected from the group consisting of VO2, TbOs, TriCb, LaCoCb, NbCb, SmNiCb, and a silicon-tellurium-arsenic-germanium alloy.

In example 53, the subject matter of any one of examples 1-52 can optionally include the second insulating-to-metallic transition material, wherein the second insulating-to-metallic transition material is selected from the group consisting of an oxide-based insulating-to-metallic transition material and a chalcogenide-based insulating-to-metallic transition material.

In example 54, the subject matter of any one of claims 1-54 can optionally include the second insulating-to-metallic transition material, wherein the second insulating-to-metallic material comprises [1] oxygen and at least one element selected from the group consisting of vanadium, titanium, lanthanum, cobalt, niobium, samarium, and nickel, or [2] at least one element selected from the group consisting of silicon, tellurium, arsenic, and germanium; or the second insulating-to-metallic material is selected from the group consisting of VO2, TbCb,

T12O3, LaCoCb, NbCh, SmNiCb, and a silicon-tellurium-arsenic-germanium alloy.

In example 55, the subject matter of any one of claims 1-54 can optionally include the dielectric material, wherein the dielectric material includes a transition metal oxide.

In example 56, the subject matter of any one of claims 1-55 can optionally include the dielectric material, wherein the dielectric material [1] comprising oxygen and at least one element selected from the group consisting of Ta, Ti, Hf, and Zr, or [1] is selected from the group consisting of TaOx, ZrCh, TiCb and HfCh.

Example 57 is a selector that includes a first electrode; a second electrode; and an integrated circuit structure of any one of examples 1-56, wherein the integrated circuit structure is arranged between the first electrode and the second electrode.

In example 58, the subject matter of example 57 can optionally include a third electrode, wherein the third electrode is arranged between the first insulating-to-metallic transition material and the third layer. In example 59, the subject matter of examples 57 or 58 can optionally include a fourth electrode, wherein the fourth electrode is arranged between the second insulating-to-metallic transition material and the third layer.

In example 60, the subject matter of any one of examples 57-59 can optionally include the first electrode and the second electrode, wherein the first electrode and the second electrode independently include one or more materials selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride.

In example 61, the subject matter of any one of examples 57-60 can optionally include the third electrode, the fourth electrode, or both the third electrode and the fourth electrode, wherein the third electrode and the fourth electrode independently include one or more materials selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride.

In example 62, the subject matter of any one of examples 1-61 can optionally include the integrated circuit structure having a thickness of about 3 nm to about 50 nm.

In example 63, the subject matter of any one of examples 1-61 can optionally include the integrated circuit structure having a thickness of 5 nm to about 50 nm.

In example 64, the subject matter of any one of examples 1-61 can optionally include the integrated circuit structure having a thickness of about 10 nm to about 40 nm.

In example 65, the subject matter of any one of examples 1-61 can optionally include the integrated circuit structure having a thickness of about 10 nm to about 30 nm.

In example 66, the subject matter of any one of examples 1-61 can optionally include the integrated circuit structure having a thickness of about 15 nm to about 25 nm.

In example 67, the subject matter of any one of examples 1-61 can optionally include the integrated circuit structure having a thickness of about 20 nm.

In example 68, the subject matter of any one of examples 1-61 can optionally include the third layer having a thickness of about 0.2 nm to about 5 nm.

In example 69, the subject matter of any one of examples 1-67 can optionally include the third layer having a thickness of about 0.5 nm to about 5 nm.

In example 70, the subject matter of any one of examples 1-67 can optionally include the third layer having a thickness of about 0.5 nm to about 4 nm.

In example 71, the subject matter of any one of examples 1-67 can optionally include the third layer having a thickness of about 0.5 nm to about 3 nm. In example 72, the subject matter of any one of examples 1-67 can optionally include the third layer having a thickness of about 0.5 nm to about 2 nm.

In example 73, the subject matter of any one of examples 1-67 can optionally include the third layer having a thickness of about 0.5 nm to about 1.5 nm.

In example 74, the subject matter of any one of examples 1-67 can optionally include the third layer having a thickness of about 1 nm.

In example 75, the subject matter of any one of claims 1-74 can optionally include the first insulating-to-metallic transition material having a thickness of about 5 nm to about 20 nm.

In example 76, the subject matter of any one of claims 1-74 can optionally include the first insulating-to-metallic transition material having a thickness of about 5 nm to about 15 nm.

In example 77, the subject matter of any one of claims 1-74 can optionally include the first insulating-to-metallic transition material having a thickness of about 7 nm to about 13 nm.

In example 78, the subject matter of any one of claims 1-74 can optionally include the first insulating-to-metallic transition material having a thickness of about 8 nm to about 10.5 nm.

In example 79, the subject matter of any one of claims 1-74 can optionally include the first insulating-to-metallic transition material having a thickness of about 9.5 nm.

In example 80, the subject matter of any one of claims 1-79 can optionally include the second insulating-to-metallic transition material having a thickness of about 5 nm to about 20 nm.

In example 81, the subject matter of any one of claims 1-79 can optionally include the second insulating-to-metallic transition material having a thickness of about 5 nm to about 15 nm.

In example 82, the subject matter of any one of claims 1-79 can optionally include the second insulating-to-metallic transition material having a thickness of about 7 nm to about 13 nm.

In example 83, the subject matter of any one of claims 1-79 can optionally include the second insulating-to-metallic transition material having a thickness of about 8 nm to about 10.5 nm.

In example 84, the subject matter of any one of claims 1-79 can optionally include the second insulating-to-metallic transition material having a thickness of about 9.5 nm. Example 85 is a memory array that includes a plurality of memory cells, wherein the memory cells comprise the integrated circuit structure or selector device of examples 1-84.

Example 86 is a system that includes a memory and a processor coupled to the memory, wherein at least one of the processor and the memory includes a dielectric material or a selector device of any one of examples 1-84.

The optional features of the foregoing examples may be used anywhere in one or more embodiments, and all optional features of the apparatuses described herein may also be implemented with respect to the methods or processes described herein.

In the descriptions provided herein, the terms“includes,”“is,”“containing,”“having,” and“comprises” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to.” When integrated circuit structures, selectors, or methods are claimed or described in terms of“comprising” various components or processing features, the composite materials and methods can also“consist essentially of’ or“consist of’ the various components or processing features, unless stated otherwise.

The terms“a,”“an,” and“the” are intended to include plural alternatives, e.g ., at least one. For instance, the disclosure of“a third layer,”“a metal oxide,” and the like, is meant to encompass one, or mixtures or combinations of more than one third layer, metal oxide, and the like, unless otherwise specified.

Various numerical ranges may be disclosed herein. When Applicant discloses or claims a range of any type, Applicant’s intent is to disclose or claim individually each possible number that such a range could reasonably encompass, including end points of the range as well as any sub-ranges and combinations of sub-ranges encompassed therein, unless otherwise specified. Moreover, all numerical end points of ranges disclosed herein are approximate. As a

representative example, Applicant discloses, in one embodiment, that“the first insulating-to- metallic transition material and the second insulating-to-metallic transition material,

independently, have a thickness of about 7 nm to about 13 nm.” This range should be interpreted as encompassing values in a range of about 7 nm to about 13 nm, and further encompasses “about” each of 8 nm, 8.5 nm, 9 nm, 9.5 nm, 10 nm, 10.5 nm, 11 nm, 11.5 nm, 12 nm, and 12.5 nm, including any ranges and sub-ranges between any of these values.

The processes described herein may be carried out or performed in any suitable order as desired in various implementations. Additionally, in certain implementations, at least a portion of the processes may be carried out in parallel. Furthermore, in certain implementations, less than or more than the processes described may be performed.

Many modifications and other implementations of the disclosure set forth herein will be apparent having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the disclosure is not to be limited to the specific implementations disclosed and that modifications and other implementations are intended to be included within the scope of the appended claims.

Claims

Claims:

1. An integrated circuit structure comprising:

a first layer comprising a first insulating-to-metallic transition material;

a second layer comprising a second insulating-to-metallic transition material; and a third layer arranged between the first layer and the second layer; wherein the third layer comprises a dielectric material having an electron affinity that is greater than the electron affinity of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material.

2. The integrated circuit structure of claim 1, wherein the dielectric material has a dielectric constant that is greater than the dielectric constant of at least one of the first insulating-to- metallic transition material or the second insulating-to-metallic transition material.

3. The integrated circuit structure of claim 2, wherein the dielectric constant of the dielectric material is greater than the dielectric constant of the first insulating-to-metallic transition material and the second insulating-to-metallic transition material.

4. The integrated circuit structure of claim 2 or 3, wherein the dielectric constant of the dielectric material is at least 30.

5. The integrated circuit structure of claim 2 or 3, wherein the dielectric constant of the dielectric material is at least 10 % greater than the dielectric constant of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material.

6. The integrated circuit structure of claim 1, wherein the electron affinity of the dielectric material is greater than the electron affinity of the first insulating-to-metallic transition material and the second insulating-to-metallic transition material.

7. The integrated circuit structure of claim 1 or 6, wherein the electron affinity of the dielectric material is at least 3 eV.

8. The integrated circuit structure of claim 1 or 6, wherein the electron affinity of the

dielectric material is at least 1 eV greater than the electron affinity of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material.

9. The integrated circuit structure of claim 1, wherein the first insulating-to-metallic

transition material and the second insulating-to-metallic transition material are identical.

10. The integrated circuit structure of claim 1, wherein the first insulating-to-metallic

transition material comprises a material selected from the group consisting of an oxide- based insulating-to-metallic transition material and a chalcogenide-based insulating-to- metallic transition material.

11. The integrated circuit structure of claim 1, wherein the first insulating-to-metallic

transition material comprises [1] oxygen and at least one element selected from the group consisting of vanadium, titanium, lanthanum, cobalt, niobium, samarium, tantalum, and nickel, or [2] at least one element selected from the group consisting of silicon, tellurium, arsenic, and germanium.

12. The integrated circuit structure of any one of claims 1, 10, and 11, wherein the second insulating-to-metallic transition material comprises a material selected from the group consisting of an oxide-based insulating-to-metallic transition material and a

chalcogenide-based insulating-to-metallic transition material.

13. The integrated circuit structure of any one of claims 1, 10, and 11, wherein the second insulating-to-metallic transition material comprises [1] oxygen and at least one element selected from the group consisting of vanadium, titanium, lanthanum, cobalt, niobium, samarium, and nickel, or [2] at least one element selected from the group consisting of silicon, tellurium, arsenic, and germanium.

14. The integrated circuit structure of claim 1, wherein the dielectric material comprises a transition metal and oxygen.

15. The integrated circuit structure of claim 1, wherein the dielectric material comprising oxygen and at least one element selected from the group consisting of Ta, Ti, Hf, and Zr.

16. A selector device comprising:

a first electrode;

a second electrode; and

the integrated circuit structure of any one of claims 1-3 arranged between the first electrode and the second electrode.

17. The selector device of claim 16, further comprising a third electrode, wherein the third electrode is arranged between the first insulating-to-metallic transition material and the third layer.

18. The selector device of claim 18, further comprising a fourth electrode, wherein the fourth electrode is arranged between the second insulating-to-metallic transition material and the third layer.

19. A memory array comprising a plurality of memory cells, wherein the memory cells

comprise the selector device of any one of claims 16-18.

20. A system comprising:

a memory; and

a processor coupled to the memory,

wherein at least one of the processor and the memory include a selector device of any one of claims 16-18.