WO2019125361A1 - Switching device with pocket having high mobility carriers - Google Patents

Switching device with pocket having high mobility carriers Download PDF

Info

Publication number
WO2019125361A1
WO2019125361A1 PCT/US2017/066992 US2017066992W WO2019125361A1 WO 2019125361 A1 WO2019125361 A1 WO 2019125361A1 US 2017066992 W US2017066992 W US 2017066992W WO 2019125361 A1 WO2019125361 A1 WO 2019125361A1
Authority
WO
WIPO (PCT)
Prior art keywords
fin
channel
axis
source
package
Prior art date
Application number
PCT/US2017/066992
Other languages
French (fr)
Inventor
Roza Kotlyar
Rishabh Mehandru
Stephen M. Cea
Willy Rachmady
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/066992 priority Critical patent/WO2019125361A1/en
Publication of WO2019125361A1 publication Critical patent/WO2019125361A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • Embodiments of the invention are in the field of semiconductor devices and, in particular, non-planar transistors.
  • a FinFET is a transistor built around a thin strip of semiconductor material (referred to as the “fin”).
  • the transistor includes the standard field effect transistor (FET) nodes/components: a gate, a gate dielectric, a source region, and a drain region.
  • the conductive channel of the device resides on the outer sides of the fin beneath the gate dielectric. Specifically, current runs along both“sidewalls” of the fin as well as along the top side of the fin. Because the conductive channel essentially resides along the three different outer, planar regions of the fin, such a FinFET is typically referred to as a“tri-gate” FinFET.
  • Other types of FinFETs exist (such as“double-gate” FinFETs in which the conductive channel principally resides only along both sidewalls of the fin and not along the top side of the fin).
  • Figure 1 includes an embodiment of a switching device with a high carrier mobility pocket.
  • Figure 2 includes an embodiment of a switching device with a high carrier mobility pocket.
  • Figure 3 includes an embodiment of a package with a switching device with a high carrier mobility pocket.
  • Figures 4, 5, and 6 include systems that further include embodiments. Detailed Description
  • high mobility materials e.g., Ge and InGaAs
  • homojunction FinFETs where the same high mobility material in used in the source, channel, and drain.
  • These materials have relatively lighter transport mass (as compared to silicon) and give relatively higher ON current (as compared to silicon) in the ballistic limit of short gate length (e.g., less than 20 nm) scaled devices.
  • Applicant determined these materials have lower bandgaps and therefore gives rise to higher OFF-state leakage current (as compared to silicon). This limits their suitability for low power applications, such as mobile computing nodes (e.g., Smartphones) and devices on the Internet of Things.
  • an embodiment uses low bandgap, high mobility, low transport mass material in a pocket (between the source and channel) to boost injection velocity at the source.
  • a pocket between the source and channel
  • the materials in the pocket are stressed (tensile for PMOS or compression for NMOS).
  • the channel and drain use wide bandgap materials.
  • the use of different materials in the pocket and channel creates a heterostructure.
  • the conduction band for the pocket material matches or is higher than the channel materials for NMOS devices.
  • the valence band for the pocket material matches or is lower than the channel materials for PMOS devices. This transport band (conduction or valence) matching minimizes heterointerface resistance.
  • embodiments include MOSFETs with low bandgap, high mobility, low transport mass materials in a pocket (that may or may not be stressed) coupled to a wide bandgap material in the channel and drain.
  • An embodiment includes an NMOS heterostructure.
  • the pocket material has a conduction band matching or higher than that of the channel and/or drain materials to minimize heterointerface resistance.
  • the channel is on a wafer with (100) orientation.
  • the channel has a ⁇ H0> channel transport direction.
  • An embodiment includes a PMOS heterostructure.
  • the pocket material has a valence band that matches or is lower than that of the channel and/or drain materials. This minimizes heterointerface resistance (e.g., resistance where material of pocket interfaces different material of the channel).
  • the pocket includes germanium and the channel includes Sii_ x Sn x (where x is between .3 and .4).
  • the channel is on a wafer with (100) orientation.
  • the channel has a ⁇ 110> channel transport direction.
  • Embodiments have various elements that improve ON/OFF current ratio and ON current.
  • a heterostructure device uses: (1) low bandgap, high mobility, low transport mass material in the pocket between the source and channel; (2) wide bandgap material in the channel region; (3) conduction band in the pocket matches or is higher than the conduction band for the channel materials for NMOS devices to minimize heterointerface resistance, and/or (4) valence band for the pocket materials match or are lower than the valence band for the channel materials for PMOS devices to minimize heterointerface resistance.
  • channel and wafer orientation and/or stress are selected to accomplish any or all of elements (l)-(4) in the immediately preceding paragraph.
  • the stress has a tensile strain component along ⁇ HO> channel direction for NMOS FinFETs (with a compressive source pocket) on a wafer with a (100) orientation.
  • the stress has a compressive strain component along ⁇ H0> channel direction for PMOS FinFETs (with a tensile source pocket) on a wafer with a (100) orientation.
  • Heterostructure embodiments addressed herein provide higher ON current than conventional homojunction devices while still maintaining OFF current at or near the low level of homojunction devices.
  • Figure 1 includes FinFET 100.
  • Device 100 includes a fin 101 including a channel 102 that includes a first material. The channel is included in the fin.
  • the device further includes a source 103 and a drain 104 corresponding to the channel 102.
  • Device 100 includes a gate 105, source contact 106, and drain contact 107 corresponding to the channel, the source, and the drain.
  • a fin portion 108 includes a second material.
  • a first axis 109 which is orthogonal to a long axis 112 of the channel, intersects a middle portion of the source contact 106 and the fin 101.
  • a second axis 110 parallel to the first axis, intersects a middle portion of the gate contact 105 and the fin 101.
  • the fin portion 108 is located entirely between the first and second axes 109, 110.
  • Figure 1 may include layers that are not labeled and which may or may not be found in varying embodiments.
  • seed layers and various dielectric layers may be seen in Figure 1 but not necessarily found in all embodiments.
  • interfacial oxide and gate dielectric are shown in Figure 1 but not labeled to maintain focus on elements such as pocket 108 and the like.
  • the first material of the channel 102 includes silicon.
  • the second material of region 108 includes germanium. Region 108 is sometimes referred to herein as a “pocket”.
  • the first material includes germanium and silicon.
  • the first material of channel 102 includes Sii_ x Ge x and x is between .6 and .8.
  • x is between (a) .7 and .8, (b) .6 and .7, (c) .5 and .8, (d) .6 and .9, and (e) .4 and .9.
  • Embodiments that include silicon and germanium as the first material may be included in a NMOS switching device, such as a FinFET.
  • the first material of the channel includes silicon.
  • the second material of region 108 includes germanium.
  • the first material includes silicon and tin.
  • the first material of channel 102 includes Sii_ x Sn x and x is between .25 and .45.
  • x is between (a) .2 and .5, (b) .2 and .4, (c) .2 and .3, (d) .3 and .6, and (e) .3 and .4.
  • Embodiments that include silicon and tin as the first material may be included in a PMOS switching device, such as a FinFET.
  • the second material of pocket 108 has a conduction band greater than or equal to a conduction band of the first material of channel 102.
  • Such an embodiment may include a NMOS transistor.
  • Such an embodiment may have the second material of region 108 tensile stressed.
  • the second material of pocket 108 has a conduction band greater than or equal to a conduction band of the first material of channel 102.
  • Such an embodiment may include a substrate portion 113 (which may or may not be monolithic with region 108 and/or the fin).
  • the fin 101 is on the substrate portion 113.
  • the substrate portion 113 has a (100) crystal orientation.
  • the channel is oriented to conduct current in a [110] direction.
  • the second material of region 108 is tensile stressed along the [110] direction. Further, in an embodiment the second material of region 108 is compressive stressed orthogonal to the [110] direction.
  • the second material of region 108 has a valence band less than or equal to a valence band of the first material of channel 102.
  • Such an embodiment may include a PMOS transistor.
  • the second material of region 108 has a valence band less than or equal to a valence band of the first material of channel 102.
  • Such an embodiment may include a substrate portion 113.
  • the fin 101 is on the substrate portion 113.
  • the substrate portion 113 has a (100) crystal orientation.
  • the channel 102 is oriented to conduct current in a [110] direction.
  • the second material of region 108 is compressive stressed along the [110] direction. Further, in an embodiment the second material of region 108 is tensile stressed orthogonal to the [110] direction.
  • a spacer 114 is between the source and drain contacts 106, 107. In an embodiment a spacer 114 is between the source and gate contacts 106, 105.
  • a material including nitrogen 114 is between the source and drain contacts 106, 107.
  • a material including nitrogen 114 is between the source and gate contacts 106, 105.
  • fin 101 includes a fin height 119, measured parallel to the first axis 106, extending from a top of the fin to a bottom of the fin.
  • the second material of region 108 includes second material height, measured parallel to the first axis, which is at least 75% of the fin height.
  • the second material of region 108 includes second material height, measured parallel to the first axis, that is at least 80%, 90%, or 100% of the fin height
  • the channel 102 has a length 115, measured along the long axis 112 of the channel, which is between 5 and 20 nm, however in other embodiments the gate length is between (a) 10 and 20 nm, (b) 15 and 20 nm, or (c) generally less than 20 nm.
  • Figure 2 includes FinFET 200.
  • Figure 2 is an abstracted view of what images of a fin-based device may look like after experiencing real world semiconductor manufacturing. Actual images may not include every layer or boundary shown in Figure 2. Focus should instead be placed on general areas, such as pocket 208, and the like.
  • Device 200 includes a fin 201 including a channel 202 that includes a first material. The channel is included in the fin.
  • the device further includes a source 203 and a drain 204 corresponding to the channel 202.
  • Device 200 includes a gate 205, source contact 206, and drain contact 207 corresponding to the channel, the source, and the drain.
  • a fin portion 208 includes a second material.
  • a first axis 209 which is orthogonal to a long axis 212 of the channel, intersects a middle portion of the source contact 206 and the fin 201.
  • a second axis 210 parallel to the first axis, intersects a middle portion of the gate contact 205 and the fin 201.
  • the fin portion 208 is located entirely between the first and second axes 209, 210.
  • Other gates are shown at 205’ and other contacts 207’ are shown to illustrate fin 201 may include several devices such as device 200.
  • Other spacers 214’ are shown as well.
  • the first material of the channel 202 includes silicon.
  • the second material of region 208 includes germanium.
  • the first material includes germanium and silicon.
  • the first material of channel 202 includes Sii_ x Ge x and x is between .6 and .8. However, in other embodiments x is between .6 and .8.
  • Embodiments that include silicon and germanium as the first material may be included in a NMOS switching device, such as a FinFET.
  • the first material of the channel includes silicon.
  • the second material of region 208 includes germanium.
  • the first material includes silicon and tin.
  • the first material of channel 202 includes Sii_ x Sn x and x is between .25 and .45. However, in other embodiments x is between (a) .2 and .5,
  • Embodiments that include silicon and tin as the first material may be included in a PMOS switching device, such as a FinFET.
  • the second material of pocket 208 has a conduction band greater than or equal to a conduction band of the first material of channel 202.
  • Such an embodiment may include a NMOS transistor.
  • Such an embodiment may have the second material of region 208 tensile stressed.
  • the second material of pocket 208 has a conduction band greater than or equal to a conduction band of the first material of channel 202.
  • the channel is oriented to conduct current in a [110] direction.
  • the second material of region 208 is tensile stressed along the [110] direction. Further, in an embodiment the second material of region 208 is compressive stressed orthogonal to the [110] direction. Thus, the second material is biaxial stressed.
  • the second material of region 208 has a valence band less than or equal to a valence band of the first material of channel 202.
  • Such an embodiment may include a PMOS transistor.
  • the second material of region 208 has a valence band less than or equal to a valence band of the first material of channel 202.
  • the channel 202 is oriented to conduct current in a [110] direction.
  • the second material of region 208 is compressive stressed along the [110] direction. Further, in an embodiment the second material of region 208 is tensile stressed orthogonal to the [110] direction. Thus, the second material is biaxial stressed.
  • a spacer 214 is between the source and drain contacts 206, 207. In an embodiment a spacer 214 is between the source and gate contacts 206, 205. A third axis 211, parallel to the first axis 209, intersects the spacer 214 and the second material of region 208. In an embodiment a material including nitrogen 214 is between the source and drain contacts 206, 207. In an embodiment a material including nitrogen 214 is between the source and gate contacts 206, 205. A third axis 211, parallel to the first axis 209, intersects the material including nitrogen 214 and the second material of region 208.
  • IC integrated circuits
  • PCB printed circuit board
  • the package has conductive leads or pins that are soldered to the PCB and further coupled to the IC.
  • a ball grid array is an IC package which has a plurality of solder balls that interconnect the package to a PCB.
  • a package on package is an integrated circuit packaging method to combine vertically discrete logic and memory BGA packages. Two or more packages are installed atop each other (i.e., stacked) with a standard interface to route signals between them. This allows higher component density in devices, such as mobile phones and the like.
  • Figure 3 includes a package system in an embodiment.
  • the system includes a processor die 301 (a first package) on a package substrate 303.
  • a memory die (a second package) 302 couples to the substrate 303 by way of interposer system 307.
  • Underfill material 305 exists between die 301 and substrate 303.
  • Substrate 303 may include controlled collapse chip connection (C4) interconnects 306.
  • C4 controlled collapse chip connection
  • die 301 may couple to a metal stiffener 304.
  • Die 301 may include a die stack (e.g., multiple dies which may have the same function or differing functions) that may be molded as one unit that functions as a single die. For example, one die of the stack may have a first logic function while another die of the stack has another logic function that differs from the first logic function.
  • die 301 includes a device such as the device of Figure 1.
  • die 302 includes a device such as the device of Figure 1.
  • die 301 includes a device such as the device of Figure 1 and die 302 includes a device such as the device of Figure 1.
  • element 304 is not a stiffener but instead is a heat spreader (or is both a stiffener and a heat spreader).
  • a heat spreader is a heat exchanger that moves heat between a heat source and a secondary heat exchanger whose surface area and geometry are more favorable than the source.
  • Such a spreader may be a plate made of copper, which has a high thermal conductivity. By definition, heat is "spread out" over this geometry, so that the secondary heat exchanger may be more fully utilized. This has the potential to increase the heat capacity of the total assembly.
  • system 900 may be a smartphone or other wireless communicator or any other Internet of Things (IoT) device.
  • a baseband processor 905 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system.
  • baseband processor 905 is coupled to an application processor 910 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1), which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps.
  • Application processor 910 may further be configured to perform a variety of other computing operations for the device.
  • application processor 910 can couple to a user interface/display 920 (e.g., touch screen display).
  • application processor 910 may couple to a memory system including a non-volatile memory, namely a flash memory 930 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) and a system memory, namely a DRAM 935 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1).
  • flash memory 930 may include a secure portion 932 in which secrets and other sensitive information may be stored.
  • application processor 910 also couples to a capture device 945 such as one or more image capture devices that can record video and/or still images.
  • a universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure storage 942 to store secure user information.
  • System 900 may further include a security processor 950 (e.g., Trusted Platform Module (TPM)) (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) that may couple to application processor 910.
  • TPM Trusted Platform Module
  • a plurality of sensors 925, including one or more multi-axis accelerometers may couple to application processor 910 to enable input of a variety of sensed information such as motion and other environmental information.
  • one or more authentication devices 995 may be used to receive, for example, user biometric input for use in authentication operations.
  • a near field communication (NFC) contactless interface 960 is provided that communicates in a NFC near field via an NFC antenna 965. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities.
  • NFC near field communication
  • a power management integrated circuit (PMIC) 915 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) couples to application processor 910 to perform platform level power management. To this end, PMIC 915 may issue power management requests to application processor 910 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 915 may also control the power level of other components of system 900.
  • PMIC power management integrated circuit
  • RF transceiver 970 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol.
  • CDMA code division multiple access
  • GSM global system for mobile communication
  • LTE long term evolution
  • a GPS sensor 980 may be present, with location information being provided to security processor 950 for use as described herein when context information is to be used in a pairing process.
  • Other wireless communications such as receipt or transmission of radio signals (e.g., AM/FM) and other signals may also be provided.
  • radio signals e.g., AM/FM
  • WLAN transceiver 975 local wireless communications, such as according to a BluetoothTM or IEEE 802.11 standard can also be realized.
  • Multiprocessor system 1000 is a point-to-point interconnect system such as a server system, and includes a first processor 1070 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) and a second processor 1080 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) coupled via a point-to-point interconnect 1050.
  • processors 1070 and 1080 may be multicore processors such as SoCs, including first and second processor cores (i.e., processor cores l074a and l074b and processor cores l084a and l084b), although potentially many more cores may be present in the processors.
  • processors 1070 and 1080 each may include a secure engine 1075 and 1085 to perform security operations such as attestations, IoT network onboarding or so forth.
  • First processor 1070 further includes a memory controller hub (MCH) 1072 and point-to-point (P-P) interfaces 1076 and 1078.
  • second processor 1080 includes a MCH 1082 and P-P interfaces 1086 and 1088.
  • MCH’s 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors.
  • First processor 1070 and second processor 1080 may be coupled to a chipset 1090 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) via P-P interconnects 1052 and 1054, respectively.
  • Chipset 1090 includes P-P interfaces 1094 and 1098.
  • chipset 1090 includes an interface 1092 to couple chipset 1090 with a high performance graphics engine 1038, by a P-P interconnect 1039.
  • chipset 1090 may be coupled to a first bus 1016 via an interface 1096.
  • Various input/output (I/O) devices 1014 may be coupled to first bus 1016, along with a bus bridge 1018 which couples first bus 1016 to a second bus 1020.
  • Various devices may be coupled to second bus 1020 including, for example, a keyboard/mouse 1022, communication devices 1026 and a data storage unit 1028 such as a non-volatile storage or other mass storage device.
  • data storage unit 1028 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) may include code 1030, in one embodiment. As further seen, data storage unit 1028 also includes a trusted storage 1029 to store sensitive information to be protected. Further, an audio I/O 1024 may be coupled to second bus 1020.
  • Embodiments may be used in environments where IoT devices may include wearable devices or other small form factor Internet of Things (IoT) devices.
  • IoT Internet of Things
  • FIG 6 shown is a block diagram of a wearable module 1300 in accordance with another embodiment.
  • module 1300 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) may be an Intel® CurieTM module that includes multiple components adapted within a single small module that can be implemented as all or part of a wearable device.
  • module 1300 includes a core 1310 (of course in other embodiments more than one core may be present).
  • core 1310 may be a relatively low complexity in-order core, such as based on an Intel Architecture® QuarkTM design.
  • core 1310 may implement a Trusted Execution Environment (TEE).
  • TEE Trusted Execution Environment
  • Core 1310 couples to various components including a sensor hub 1320, which may be configured to interact with a plurality of sensors 1380, such as one or more biometric, motion environmental or other sensors.
  • a power delivery circuit 1330 is present, along with a non-volatile storage 1340.
  • this circuit may include a rechargeable battery and a recharging circuit, which may in one embodiment receive charging power wirelessly.
  • One or more input/output (IO) interfaces 1350 may be present.
  • IO input/output
  • a wireless transceiver 1390 which may be a BluetoothTM low energy or other short-range wireless transceiver is present to enable wireless communications as described herein. Understand that in different implementations a wearable module can take many other forms. Wearable and/or IoT devices have, in comparison with a typical general purpose CPU or a GPU, a small form factor, low power requirements, limited instruction sets, relatively slow computation throughput, or any of the above.
  • Example 1 includes a device comprising: a fin including a first material; a channel including the first material and included in the fin; a source and a drain corresponding to the channel; gate, source, and drain contacts corresponding to the channel, the source, and the drain; a fin portion that includes a second material, wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects a middle portion of the source contact and the fin, (b) a second axis, parallel to the first axis, intersects a middle portion of the gate contact and the fin, (c) the fin portion is located between the first and second axes.
  • Example 2 includes the device of example 1 wherein the first material includes silicon and the second material includes germanium.
  • Example 3 includes the device of example 2 wherein the first material includes germanium.
  • Example 4 includes the device of example 3 wherein the first material includes Sii_ x Ge x and x is between .6 and .8.
  • Example 5 includes the device of example 2 wherein the first material includes tin.
  • Example 6 includes the device of example 4 wherein the first material includes Sii_ x Sn x and x is between .25 and .45.
  • Example 7 includes the device of example 1 wherein the second material includes a conduction band greater than or equal to a conduction band of the first material.
  • Example 8 includes the device of example 7 wherein the device includes a NMOS transistor.
  • Example 9 includes the device of example 7 wherein the second material is tensile stressed.
  • Example 10 includes the device of example 7 comprising a substrate portion, wherein (a) the fin is on the substrate portion, (a) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is tensile stressed along the [110] direction.
  • Example 11 includes the device of example 10 wherein the second material is compressive stressed orthogonal to the [110] direction.
  • germanium in the pocket has -1.3% biaxial compressive strain in-plane normal to transport, and 0.97 % tensile strain along the channel direction. This improves electron transport mass.
  • Example 12 includes the device of example 1 wherein the second material includes a valence band less than or equal to a valence band of the first material.
  • Example 13 includes the device of example 12 wherein the device includes a PMOS transistor.
  • Example 14 includes the device of example 12 comprising a substrate portion, wherein (a) the fin is on the substrate portion, (b) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is compressive stressed along the [110] direction.
  • Example 15 includes the device of example 14 wherein the second material is tensile stressed orthogonal to the [110] direction.
  • germanium in the pocket has 3.3% tensile strain in plane normal to transport, and compressive strain along the transport direction lowering the hole mass and boosting the injection velocity.
  • the pocket width is between 2 to 5 nm (measured parallel to axis 112) to prevent defects due to stress relaxation in the germanium pocket.
  • Example 16 includes the device of example 1 comprising: a spacer between the source and drain contacts; wherein a third axis, parallel to the first axis, intersects the spacer and the second material.
  • Example 17 includes the device of example 1 comprising a substrate, wherein: the fin includes a fin height, measured parallel to the first axis, extending from a top of the fin to a bottom of the fin; the second material includes second material height, measured parallel to the first axis, that is at least 75% of the fin height.
  • Example 18 includes the device of example 1 wherein the channel has a length, measured along the long axis of the channel, which is between 5 and 20 nm.
  • Example 19 includes a package comprising: a package substrate; a first die on the package substrate; a second die on the package substrate; wherein the first die includes (a)(i) a fin including a first material; (a)(ii) a channel including the first material and included in the fin; (a)(iii) a source and a drain corresponding to the channel; (a)(iv) gate, source, and drain contacts corresponding to the channel, the source, and the drain; (a)(v) a fin portion that includes a second material, wherein (b)(i) a first axis, which is orthogonal to a long axis of the channel, intersects a middle portion of the source contact and the fin, (b)(ii) a second axis, parallel to the first axis, intersects a middle portion of the gate contact and the fin, and (b)(iii) the fin portion is located entirely between the first and second axes.
  • Example 20 includes the package of example 19 wherein: the first material includes silicon and at least one of germanium and tin; the second material includes germanium.
  • Example 21 includes the package of example 19 wherein: the second material includes a conduction band greater than or equal to a conduction band of the first material; and the second material is tensile stressed.
  • Example 22 includes the package of example 19 wherein: the second material includes a valence band less than or equal to a valence band of the first material; the second material is compressive stressed.
  • Example 23 includes the package according to example 19 comprising at least one of (a) a stiffener coupled to the first die, and (b) a heat spreader coupled to the first die.
  • Example 24 includes a system comprising: a memory; and a processor coupled to the memory, wherein at least one of the processor and the memory include the device according to any one of example 1.
  • Example 25 includes the package of claim 19 wherein the first material includes silicon and the second material includes germanium.
  • Example 26 includes the package of claim 25 wherein the first material includes germanium.
  • Example 27 includes the package of claim 26 wherein the first material includes Sil-xGex and x is between .6 and .8.
  • Example 28 includes the package of claim 25 wherein the first material includes tin.
  • Example 29 The package of claim 28 wherein the first material includes Sil-xSnx and x is between .25 and .45.
  • Example 30 includes the package of claim 19 wherein the second material includes a conduction band greater than or equal to a conduction band of the first material.
  • Example 31 includes the package of claim 30 wherein the package includes a NMOS transistor.
  • Example 32 includes the package of claim 30 wherein the second material is tensile stressed.
  • Example 33 includes the package of claim 30 comprising a substrate portion, wherein (a) the fin is on the substrate portion, (a) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is tensile stressed along the [110] direction.
  • Example 34 includes the package of claim 33 wherein the second material is compressive stressed orthogonal to the [110] direction.
  • Example 35 includes the package of claim 19 wherein the second material includes a valence band less than or equal to a valence band of the first material.
  • Example 36 includes the package of claim 35 wherein the package includes a PMOS transistor.
  • Example 37 includes the package of claim 35 comprising a substrate portion, wherein (a) the fin is on the substrate portion, (b) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is compressive stressed along the [110] direction.
  • Example 38 includes the package of claim 37 wherein the second material is tensile stressed orthogonal to the [110] direction.
  • Example 39 includes the package of claim 19 comprising: a spacer between the source and drain contacts; wherein a third axis, parallel to the first axis, intersects the spacer and the second material.
  • Example 40 includes the package of claim 19 comprising a substrate, wherein: the fin includes a fin height, measured parallel to the first axis, extending from a top of the fin to a bottom of the fin; the second material includes second material height, measured parallel to the first axis, that is at least 75% of the fin height.
  • Example 41 includes the package of claim 19 wherein the channel has a length, measured along the long axis of the channel, which is between 5 and 20 nm.
  • Example la includes a device comprising: a fin including a first material; a channel including the first material and included in the fin; a source and a drain corresponding to the channel; gate, source, and drain contacts corresponding to the channel, the source, and the drain; a fin portion that includes a second material, wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects a middle portion of the source contact and the fin, (b) a second axis, parallel to the first axis, intersects a middle portion of the gate contact and the fin, (c) the fin portion is located entirely between the first and second axes.
  • Example la In another version of Example la at least a subportion of the fin portion is located entirely between the first and second axes.
  • a“material” is different from an“element.”
  • SiGe is a different material from Ge even though both have a Ge element.
  • Example la includes a device comprising: a fin including a first material, the first material comprising a first material composition; a channel including the first material and included in the fin; a source and a drain corresponding to the channel; gate, source, and drain contacts corresponding to the channel, the source, and the drain; a fin portion that includes a second material, the second material including a second material composition that differs from the first material composition; wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects a middle portion of the source contact and the fin, (b) a second axis, parallel to the first axis, intersects a middle portion of the gate contact and the fin, (c) the fin portion is located entirely between the first and second axes.
  • Example la includes a device comprising: a fin including a first material; a channel including the first material, the channel being included in the fin; a source and a drain both corresponding to the channel; gate, source, and drain contacts corresponding to the channel, the source, and the drain; a fin portion that includes a second material; wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects the fin and a middle portion of the source contact, (b) a second axis, parallel to the first axis, intersects the fin and a middle portion of the gate contact, (c) the fin portion is located between the first and second axes, (d) the first material has a first material composition and the second material has a second material composition, and (e) the second material composition differs from the first material composition.
  • a channel located in a nanoribbon or nanowire is still a channel included in a fin if the ribbon or wire is formed from a fin.
  • Example la includes a device comprising: a fin including a first material; a channel including the first material; a source and a drain both corresponding to the channel; gate, source, and drain contacts corresponding to the channel, the source, and the drain; a fin portion that includes a second material; wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects the fin and a middle portion of the source contact, (b) a second axis, parallel to the first axis, intersects the fin and a middle portion of the gate contact, (c) the fin portion is located between the first and second axes, (d) the first material has a first material composition and the second material has a second material composition, and (e) the second material composition differs from the first material composition.
  • Example la includes a device comprising: a semiconductor layer including a first material; a channel including the first material; a source and a drain both corresponding to the channel; gate, source, and drain contacts corresponding to the channel, the source, and the drain; a semiconductor layer portion that includes a second material; wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects the semiconductor layer and a middle portion of the source contact, (b) a second axis, parallel to the first axis, intersects the semiconductor layer and a middle portion of the gate contact, (c) the semiconductor layer portion is located between the first and second axes, (d) the first material has a first material composition and the second material has a second material composition, and (e) the second material composition differs from the first material composition.
  • planar transistors can benefit from this technology.
  • Example 2a includes the device of example la wherein the first material includes silicon and the second material includes germanium.
  • Example 3a includes the device of example 2a wherein the first material includes germanium.
  • Example 4a includes the device of example 3 a wherein the first material includes Sil-xGex and x is between .6 and .8.
  • Example 5a includes the device of example 2a wherein the first material includes tin.
  • Example 6a includes the device of example 4a wherein the first material includes Sil-xSnx and x is between .25 and .45.
  • Example 7a includes the device according to any of examples la-4a wherein the second material includes a conduction band greater than or equal to a conduction band of the first material.
  • Example 8a includes the device according to any of examples la-4a and 7a wherein the device includes a NMOS transistor.
  • Example 9a includes the device according to any of examples la-4 and 7-8 wherein the second material is tensile stressed.
  • Example lOain includes the device according to any of examples la-4a and 7-9a comprising a substrate portion, wherein (a) the fin is on the substrate portion, (a) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is tensile stressed along the [110] direction.
  • the fin may be (a) formed from the substrate (i.e., monolithic with substrate), or (b) coupled to the substrate but not monolithic with the substrate.
  • Example lla includes the device according to any of examples la-4a and 7a-l0a wherein the second material is compressive stressed orthogonal to the [110] direction.
  • an embodiment includes the subject matter of examples la, 2a, 3a, 7a, lOa, and lla.
  • Example l2a includes the device according to any of examples la-2a and 5a-6a wherein the second material includes a valence band less than or equal to a valence band of the first material.
  • Example l3a includes the device according to any of examples la-2a, 5a-6a, and l2a wherein the device includes a PMOS transistor.
  • Example l4a includes the device according to any of examples la-2a, 5a-6a, and l2a-l3a comprising a substrate portion, wherein (a) the fin is on the substrate portion, (b) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is compressive stressed along the [110] direction.
  • Example l5a includes the device according to any of examples la-2a, 5a-6a, and l2a-l4a wherein the second material is tensile stressed orthogonal to the [110] direction.
  • Example l6a includes the device according to any of examples la-l5a comprising: a spacer between the source and drain contacts; wherein a third axis, parallel to the first axis, intersects the spacer and the second material.
  • Example l7a includes the device according to any of examples la-l6a comprising a substrate, wherein: the fin includes a fin height, measured parallel to the first axis, extending from a top of the fin to a bottom of the fin; the second material includes second material height, measured parallel to the first axis, that is at least 75% of the fin height.
  • Example l8a includes the device according to any of examples la-l7a wherein the channel has a length, measured along the long axis of the channel, which is between 5 and 20 nm.
  • Example l9a includes a system comprising: a memory; and a processor coupled to the memory, wherein at least one of the processor and the memory include the device according to any one of examples la to l8a.
  • Example 20a includes a package comprising: a package substrate; a first die on the package substrate; a second die on the package substrate; wherein the first die includes (a)(i) a fin including a first material; (a)(ii) a channel including the first material and included in the fin; (a)(iii) a source and a drain corresponding to the channel; (a)(iv) gate, source, and drain contacts corresponding to the channel, the source, and the drain; (a)(v) a fin portion that includes a second material, wherein (b)(i) a first axis, which is orthogonal to a long axis of the channel, intersects a middle portion of the source contact and the fin, (b)(ii) a second axis, parallel to the first axis, intersects a middle portion of the gate contact and the fin, and (b)(iii) the fin portion is located entirely between the first and second axes.
  • Example 2la includes the package of example 20a wherein: the first material includes silicon and at least one of germanium and tin; the second material includes germanium.
  • Example 22a includes the package according to any of examples 20a-2la wherein: the second material includes a conduction band greater than or equal to a conduction band of the first material; and the second material is tensile stressed.
  • Example 23a includes the package according to any of examples 20a-2la wherein: the second material includes a valence band less than or equal to a valence band of the first material; the second material is compressive stressed.
  • Example 24a includes the package according to any of examples 20a-23a comprising at least one of (a) a stiffener coupled to the first die, and (b) a heat spreader coupled to the first die.
  • Various embodiments include a semiconductive substrate.
  • a semiconductive substrate may be a bulk semiconductive material this is part of a wafer.
  • the semiconductive substrate is a bulk semiconductive material as part of a chip that has been singulated from a wafer.
  • the semiconductive substrate is a semiconductive material that is formed above an insulator such as a semiconductor on insulator (SOI) substrate.
  • SOI semiconductor on insulator
  • the semiconductive substrate is a prominent structure such as a fin that extends above a bulk semiconductive material.
  • terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top” surface of that substrate; the substrate may actually be in any orientation so that a "top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.”
  • the term “on” as used herein does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer.
  • the embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations.

Abstract

An embodiment includes a device comprising: a fin including a first material; a channel including the first material and included in the fin; a source and a drain corresponding to the channel; gate, source, and drain contacts corresponding to the channel, the source, and the drain; a fin portion that includes a second material, wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects a middle portion of the source contact and the fin, (b) a second axis, parallel to the first axis, intersects a middle portion of the gate contact and the fin, (c) the fin portion is located entirely between the first and second axes. Other embodiments are described herein.

Description

SWITCHING DEVICE WITH POCKET HAVING HIGH MOBILITY CARRIERS Technical Field
[0001] Embodiments of the invention are in the field of semiconductor devices and, in particular, non-planar transistors.
Background
[0002] A FinFET is a transistor built around a thin strip of semiconductor material (referred to as the “fin”). The transistor includes the standard field effect transistor (FET) nodes/components: a gate, a gate dielectric, a source region, and a drain region. The conductive channel of the device resides on the outer sides of the fin beneath the gate dielectric. Specifically, current runs along both“sidewalls” of the fin as well as along the top side of the fin. Because the conductive channel essentially resides along the three different outer, planar regions of the fin, such a FinFET is typically referred to as a“tri-gate” FinFET. Other types of FinFETs exist (such as“double-gate” FinFETs in which the conductive channel principally resides only along both sidewalls of the fin and not along the top side of the fin).
Brief Description of the Drawings
[0003] Features and advantages of embodiments of the present invention will become apparent from the appended claims, the following detailed description of one or more example embodiments, and the corresponding figures. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
[0004] Figure 1 includes an embodiment of a switching device with a high carrier mobility pocket.
[0005] Figure 2 includes an embodiment of a switching device with a high carrier mobility pocket.
[0006] Figure 3 includes an embodiment of a package with a switching device with a high carrier mobility pocket.
[0007] Figures 4, 5, and 6 include systems that further include embodiments. Detailed Description
[0008] Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments more clearly, the drawings included herein are diagrammatic representations of semiconductor/circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures useful to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. For example, not every layer (e.g., barrier layer, seed layer, etch stop layer) of a semiconductor device is necessarily shown.“An embodiment”,“various embodiments” and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments.“First”,“second”,“third” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. “Connected” may indicate elements are in direct physical or electrical contact with each other and“coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact.
[0009] To improve performance in scaled devices, such as small node FinFETs, high mobility materials (e.g., Ge and InGaAs) are sometimes used in homojunction FinFETs where the same high mobility material in used in the source, channel, and drain. These materials have relatively lighter transport mass (as compared to silicon) and give relatively higher ON current (as compared to silicon) in the ballistic limit of short gate length (e.g., less than 20 nm) scaled devices. However, Applicant determined these materials have lower bandgaps and therefore gives rise to higher OFF-state leakage current (as compared to silicon). This limits their suitability for low power applications, such as mobile computing nodes (e.g., Smartphones) and devices on the Internet of Things.
[0010] Embodiments addressed herein address this problem. For example, an embodiment uses low bandgap, high mobility, low transport mass material in a pocket (between the source and channel) to boost injection velocity at the source. This is described below with regard to, for example, Figure 1. In some embodiments the materials in the pocket are stressed (tensile for PMOS or compression for NMOS). In contrast with the pocket materials, the channel and drain use wide bandgap materials. Thus, the use of different materials in the pocket and channel creates a heterostructure.
[0011] The conduction band for the pocket material matches or is higher than the channel materials for NMOS devices. The valence band for the pocket material matches or is lower than the channel materials for PMOS devices. This transport band (conduction or valence) matching minimizes heterointerface resistance.
[0012] Thus, embodiments include MOSFETs with low bandgap, high mobility, low transport mass materials in a pocket (that may or may not be stressed) coupled to a wide bandgap material in the channel and drain.
[0013] An embodiment includes an NMOS heterostructure. The pocket material has a conduction band matching or higher than that of the channel and/or drain materials to minimize heterointerface resistance. The embodiment includes germanium in the pocket and the channel includes Sii_xGex (where x=.7). The channel is on a wafer with (100) orientation. The channel has a <H0> channel transport direction.
[0014] An embodiment includes a PMOS heterostructure. The pocket material has a valence band that matches or is lower than that of the channel and/or drain materials. This minimizes heterointerface resistance (e.g., resistance where material of pocket interfaces different material of the channel). The pocket includes germanium and the channel includes Sii_xSnx (where x is between .3 and .4). The channel is on a wafer with (100) orientation. The channel has a <110> channel transport direction.
[0015] Embodiments have various elements that improve ON/OFF current ratio and ON current. For example, a heterostructure device uses: (1) low bandgap, high mobility, low transport mass material in the pocket between the source and channel; (2) wide bandgap material in the channel region; (3) conduction band in the pocket matches or is higher than the conduction band for the channel materials for NMOS devices to minimize heterointerface resistance, and/or (4) valence band for the pocket materials match or are lower than the valence band for the channel materials for PMOS devices to minimize heterointerface resistance.
[0016] In various embodiments channel and wafer orientation and/or stress are selected to accomplish any or all of elements (l)-(4) in the immediately preceding paragraph. For example, the stress has a tensile strain component along <HO> channel direction for NMOS FinFETs (with a compressive source pocket) on a wafer with a (100) orientation. As another example, the stress has a compressive strain component along <H0> channel direction for PMOS FinFETs (with a tensile source pocket) on a wafer with a (100) orientation.
[0017] Heterostructure embodiments addressed herein provide higher ON current than conventional homojunction devices while still maintaining OFF current at or near the low level of homojunction devices.
[0018] Figure 1 includes FinFET 100. Device 100 includes a fin 101 including a channel 102 that includes a first material. The channel is included in the fin. The device further includes a source 103 and a drain 104 corresponding to the channel 102. Device 100 includes a gate 105, source contact 106, and drain contact 107 corresponding to the channel, the source, and the drain. A fin portion 108 includes a second material. A first axis 109, which is orthogonal to a long axis 112 of the channel, intersects a middle portion of the source contact 106 and the fin 101. A second axis 110, parallel to the first axis, intersects a middle portion of the gate contact 105 and the fin 101. The fin portion 108 is located entirely between the first and second axes 109, 110.
[0019] Figure 1 may include layers that are not labeled and which may or may not be found in varying embodiments. For example, seed layers and various dielectric layers may be seen in Figure 1 but not necessarily found in all embodiments. For example, interfacial oxide and gate dielectric are shown in Figure 1 but not labeled to maintain focus on elements such as pocket 108 and the like.
[0020] In an embodiment the first material of the channel 102 includes silicon. The second material of region 108 includes germanium. Region 108 is sometimes referred to herein as a “pocket”. In an embodiment the first material includes germanium and silicon. For example, in an embodiment the first material of channel 102 includes Sii_xGex and x is between .6 and .8. However, in other embodiments x is between (a) .7 and .8, (b) .6 and .7, (c) .5 and .8, (d) .6 and .9, and (e) .4 and .9. Embodiments that include silicon and germanium as the first material may be included in a NMOS switching device, such as a FinFET.
[0021] In an embodiment the first material of the channel includes silicon. The second material of region 108 includes germanium. In an embodiment the first material includes silicon and tin. For example, in an embodiment the first material of channel 102 includes Sii_ xSnx and x is between .25 and .45. However, in other embodiments x is between (a) .2 and .5, (b) .2 and .4, (c) .2 and .3, (d) .3 and .6, and (e) .3 and .4. Embodiments that include silicon and tin as the first material may be included in a PMOS switching device, such as a FinFET.
[0022] In an embodiment the second material of pocket 108 has a conduction band greater than or equal to a conduction band of the first material of channel 102. Such an embodiment may include a NMOS transistor. Such an embodiment may have the second material of region 108 tensile stressed.
[0023] In an embodiment the second material of pocket 108 has a conduction band greater than or equal to a conduction band of the first material of channel 102. Such an embodiment may include a substrate portion 113 (which may or may not be monolithic with region 108 and/or the fin). The fin 101 is on the substrate portion 113. The substrate portion 113 has a (100) crystal orientation. The channel is oriented to conduct current in a [110] direction. The second material of region 108 is tensile stressed along the [110] direction. Further, in an embodiment the second material of region 108 is compressive stressed orthogonal to the [110] direction.
[0024] In an embodiment the second material of region 108 has a valence band less than or equal to a valence band of the first material of channel 102. Such an embodiment may include a PMOS transistor.
[0025] In an embodiment the second material of region 108 has a valence band less than or equal to a valence band of the first material of channel 102. Such an embodiment may include a substrate portion 113. The fin 101 is on the substrate portion 113. The substrate portion 113 has a (100) crystal orientation. The channel 102 is oriented to conduct current in a [110] direction. The second material of region 108 is compressive stressed along the [110] direction. Further, in an embodiment the second material of region 108 is tensile stressed orthogonal to the [110] direction. [0026] In an embodiment a spacer 114 is between the source and drain contacts 106, 107. In an embodiment a spacer 114 is between the source and gate contacts 106, 105. A third axis 111, parallel to the first axis 109, intersects the spacer 114 and the second material of region 108. In an embodiment a material including nitrogen 114 is between the source and drain contacts 106, 107. In an embodiment a material including nitrogen 114 is between the source and gate contacts 106, 105. A third axis 111, parallel to the first axis 109, intersects the material including nitrogen 114 and the second material of region 108.
[0027] In an embodiment fin 101 includes a fin height 119, measured parallel to the first axis 106, extending from a top of the fin to a bottom of the fin. The second material of region 108 includes second material height, measured parallel to the first axis, which is at least 75% of the fin height. However, in other embodiments the second material of region 108 includes second material height, measured parallel to the first axis, that is at least 80%, 90%, or 100% of the fin height
[0028] In an embodiment the channel 102 has a length 115, measured along the long axis 112 of the channel, which is between 5 and 20 nm, however in other embodiments the gate length is between (a) 10 and 20 nm, (b) 15 and 20 nm, or (c) generally less than 20 nm.
[0029] Figure 2 includes FinFET 200. Figure 2 is an abstracted view of what images of a fin-based device may look like after experiencing real world semiconductor manufacturing. Actual images may not include every layer or boundary shown in Figure 2. Focus should instead be placed on general areas, such as pocket 208, and the like.
[0030] Device 200 includes a fin 201 including a channel 202 that includes a first material. The channel is included in the fin. The device further includes a source 203 and a drain 204 corresponding to the channel 202. Device 200 includes a gate 205, source contact 206, and drain contact 207 corresponding to the channel, the source, and the drain. A fin portion 208 includes a second material. A first axis 209, which is orthogonal to a long axis 212 of the channel, intersects a middle portion of the source contact 206 and the fin 201. A second axis 210, parallel to the first axis, intersects a middle portion of the gate contact 205 and the fin 201. The fin portion 208 is located entirely between the first and second axes 209, 210. [0031] Other gates (dummy gates and/or active gates) are shown at 205’ and other contacts 207’ are shown to illustrate fin 201 may include several devices such as device 200. Other spacers 214’ are shown as well.
[0032] In an embodiment the first material of the channel 202 includes silicon. The second material of region 208 includes germanium. In an embodiment the first material includes germanium and silicon. For example, in an embodiment the first material of channel 202 includes Sii_xGex and x is between .6 and .8. However, in other embodiments x is between
(a) .7 and .8, (b) .6 and .7, (c) .5 and .8, (d) .6 and .9, and (e) .4 and .9. Embodiments that include silicon and germanium as the first material may be included in a NMOS switching device, such as a FinFET.
[0033] In an embodiment the first material of the channel includes silicon. The second material of region 208 includes germanium. In an embodiment the first material includes silicon and tin. For example, in an embodiment the first material of channel 202 includes Sii_ xSnx and x is between .25 and .45. However, in other embodiments x is between (a) .2 and .5,
(b) .2 and .4, (c) .2 and .3, (d) .3 and .6, and (e) .3 and .4. Embodiments that include silicon and tin as the first material may be included in a PMOS switching device, such as a FinFET.
[0034] In an embodiment the second material of pocket 208 has a conduction band greater than or equal to a conduction band of the first material of channel 202. Such an embodiment may include a NMOS transistor. Such an embodiment may have the second material of region 208 tensile stressed.
[0035] In an embodiment the second material of pocket 208 has a conduction band greater than or equal to a conduction band of the first material of channel 202. The channel is oriented to conduct current in a [110] direction. The second material of region 208 is tensile stressed along the [110] direction. Further, in an embodiment the second material of region 208 is compressive stressed orthogonal to the [110] direction. Thus, the second material is biaxial stressed.
[0036] In an embodiment the second material of region 208 has a valence band less than or equal to a valence band of the first material of channel 202. Such an embodiment may include a PMOS transistor. [0037] In an embodiment the second material of region 208 has a valence band less than or equal to a valence band of the first material of channel 202. The channel 202 is oriented to conduct current in a [110] direction. The second material of region 208 is compressive stressed along the [110] direction. Further, in an embodiment the second material of region 208 is tensile stressed orthogonal to the [110] direction. Thus, the second material is biaxial stressed.
[0038] In an embodiment a spacer 214 is between the source and drain contacts 206, 207. In an embodiment a spacer 214 is between the source and gate contacts 206, 205. A third axis 211, parallel to the first axis 209, intersects the spacer 214 and the second material of region 208. In an embodiment a material including nitrogen 214 is between the source and drain contacts 206, 207. In an embodiment a material including nitrogen 214 is between the source and gate contacts 206, 205. A third axis 211, parallel to the first axis 209, intersects the material including nitrogen 214 and the second material of region 208.
[0039] As noted in U.S. Patent 7,170,188, assigned to Intel Corp. of Santa Clara, CA, USA, integrated circuits (IC) are typically housed within a package that is mounted to a printed circuit board (PCB). The package has conductive leads or pins that are soldered to the PCB and further coupled to the IC. One kind of package commonly referred to as a ball grid array (BGA) is an IC package which has a plurality of solder balls that interconnect the package to a PCB.
[0040] A package on package (PoP) is an integrated circuit packaging method to combine vertically discrete logic and memory BGA packages. Two or more packages are installed atop each other (i.e., stacked) with a standard interface to route signals between them. This allows higher component density in devices, such as mobile phones and the like.
[0041] Figure 3 includes a package system in an embodiment. The system includes a processor die 301 (a first package) on a package substrate 303. A memory die (a second package) 302 couples to the substrate 303 by way of interposer system 307. Underfill material 305 exists between die 301 and substrate 303. Substrate 303 may include controlled collapse chip connection (C4) interconnects 306. Further, to prevent warping of die 301, die 301 may couple to a metal stiffener 304. Die 301 may include a die stack (e.g., multiple dies which may have the same function or differing functions) that may be molded as one unit that functions as a single die. For example, one die of the stack may have a first logic function while another die of the stack has another logic function that differs from the first logic function.
[0042] In the embodiment of Figure 3, die 301 includes a device such as the device of Figure 1. In another embodiment die 302 includes a device such as the device of Figure 1. In an embodiment die 301 includes a device such as the device of Figure 1 and die 302 includes a device such as the device of Figure 1.
[0043] In an embodiment element 304 is not a stiffener but instead is a heat spreader (or is both a stiffener and a heat spreader). A heat spreader is a heat exchanger that moves heat between a heat source and a secondary heat exchanger whose surface area and geometry are more favorable than the source. Such a spreader may be a plate made of copper, which has a high thermal conductivity. By definition, heat is "spread out" over this geometry, so that the secondary heat exchanger may be more fully utilized. This has the potential to increase the heat capacity of the total assembly.
[0044] Referring now to Figure 4, shown is a block diagram of an example system with which embodiments can be used. As seen, system 900 may be a smartphone or other wireless communicator or any other Internet of Things (IoT) device. A baseband processor 905 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system. In turn, baseband processor 905 is coupled to an application processor 910 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1), which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps. Application processor 910 may further be configured to perform a variety of other computing operations for the device.
[0045] In turn, application processor 910 can couple to a user interface/display 920 (e.g., touch screen display). In addition, application processor 910 may couple to a memory system including a non-volatile memory, namely a flash memory 930 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) and a system memory, namely a DRAM 935 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1). In some embodiments, flash memory 930 may include a secure portion 932 in which secrets and other sensitive information may be stored. As further seen, application processor 910 also couples to a capture device 945 such as one or more image capture devices that can record video and/or still images.
[0046] A universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure storage 942 to store secure user information. System 900 may further include a security processor 950 (e.g., Trusted Platform Module (TPM)) (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) that may couple to application processor 910. A plurality of sensors 925, including one or more multi-axis accelerometers may couple to application processor 910 to enable input of a variety of sensed information such as motion and other environmental information. In addition, one or more authentication devices 995 may be used to receive, for example, user biometric input for use in authentication operations.
[0047] As further illustrated, a near field communication (NFC) contactless interface 960 is provided that communicates in a NFC near field via an NFC antenna 965. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities.
[0048] A power management integrated circuit (PMIC) 915 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) couples to application processor 910 to perform platform level power management. To this end, PMIC 915 may issue power management requests to application processor 910 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 915 may also control the power level of other components of system 900.
[0049] To enable communications to be transmitted and received such as in one or more IoT networks, various circuitry may be coupled between baseband processor 905 and an antenna 990. Specifically, a radio frequency (RF) transceiver 970 and a wireless local area network (WLAN) transceiver 975 may be present. In general, RF transceiver 970 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor 980 may be present, with location information being provided to security processor 950 for use as described herein when context information is to be used in a pairing process. Other wireless communications such as receipt or transmission of radio signals (e.g., AM/FM) and other signals may also be provided. In addition, via WLAN transceiver 975, local wireless communications, such as according to a Bluetooth™ or IEEE 802.11 standard can also be realized.
[0050] Referring now to Figure 5, shown is a block diagram of a system in accordance with another embodiment of the present invention. Multiprocessor system 1000 is a point-to-point interconnect system such as a server system, and includes a first processor 1070 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) and a second processor 1080 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) coupled via a point-to-point interconnect 1050. Each of processors 1070 and 1080 may be multicore processors such as SoCs, including first and second processor cores (i.e., processor cores l074a and l074b and processor cores l084a and l084b), although potentially many more cores may be present in the processors. In addition, processors 1070 and 1080 each may include a secure engine 1075 and 1085 to perform security operations such as attestations, IoT network onboarding or so forth.
[0051] First processor 1070 further includes a memory controller hub (MCH) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, second processor 1080 includes a MCH 1082 and P-P interfaces 1086 and 1088. MCH’s 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors. First processor 1070 and second processor 1080 may be coupled to a chipset 1090 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) via P-P interconnects 1052 and 1054, respectively. Chipset 1090 includes P-P interfaces 1094 and 1098. [0052] Furthermore, chipset 1090 includes an interface 1092 to couple chipset 1090 with a high performance graphics engine 1038, by a P-P interconnect 1039. In turn, chipset 1090 may be coupled to a first bus 1016 via an interface 1096. Various input/output (I/O) devices 1014 may be coupled to first bus 1016, along with a bus bridge 1018 which couples first bus 1016 to a second bus 1020. Various devices may be coupled to second bus 1020 including, for example, a keyboard/mouse 1022, communication devices 1026 and a data storage unit 1028 such as a non-volatile storage or other mass storage device. As seen, data storage unit 1028 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) may include code 1030, in one embodiment. As further seen, data storage unit 1028 also includes a trusted storage 1029 to store sensitive information to be protected. Further, an audio I/O 1024 may be coupled to second bus 1020.
[0053] Embodiments may be used in environments where IoT devices may include wearable devices or other small form factor Internet of Things (IoT) devices. Referring now to Figure 6, shown is a block diagram of a wearable module 1300 in accordance with another embodiment. In one particular implementation, module 1300 (which may be included in a package such as the package of Figure 3 and/or may include devices such as the device 100 of Figure 1) may be an Intel® Curie™ module that includes multiple components adapted within a single small module that can be implemented as all or part of a wearable device. As seen, module 1300 includes a core 1310 (of course in other embodiments more than one core may be present). Such core may be a relatively low complexity in-order core, such as based on an Intel Architecture® Quark™ design. In some embodiments, core 1310 may implement a Trusted Execution Environment (TEE). Core 1310 couples to various components including a sensor hub 1320, which may be configured to interact with a plurality of sensors 1380, such as one or more biometric, motion environmental or other sensors. A power delivery circuit 1330 is present, along with a non-volatile storage 1340. In an embodiment, this circuit may include a rechargeable battery and a recharging circuit, which may in one embodiment receive charging power wirelessly. One or more input/output (IO) interfaces 1350, such as one or more interfaces compatible with one or more of U SB/S PI/ 12C7G P I O protocols, may be present. In addition, a wireless transceiver 1390, which may be a Bluetooth™ low energy or other short-range wireless transceiver is present to enable wireless communications as described herein. Understand that in different implementations a wearable module can take many other forms. Wearable and/or IoT devices have, in comparison with a typical general purpose CPU or a GPU, a small form factor, low power requirements, limited instruction sets, relatively slow computation throughput, or any of the above.
[0054] The following examples pertain to further embodiments.
[0055] Example 1 includes a device comprising: a fin including a first material; a channel including the first material and included in the fin; a source and a drain corresponding to the channel; gate, source, and drain contacts corresponding to the channel, the source, and the drain; a fin portion that includes a second material, wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects a middle portion of the source contact and the fin, (b) a second axis, parallel to the first axis, intersects a middle portion of the gate contact and the fin, (c) the fin portion is located between the first and second axes.
[0056] Example 2 includes the device of example 1 wherein the first material includes silicon and the second material includes germanium.
[0057] Example 3 includes the device of example 2 wherein the first material includes germanium.
[0058] Example 4 includes the device of example 3 wherein the first material includes Sii_ xGex and x is between .6 and .8.
[0059] Example 5 includes the device of example 2 wherein the first material includes tin.
[0060] Example 6 includes the device of example 4 wherein the first material includes Sii_ xSnx and x is between .25 and .45.
[0061] Example 7 includes the device of example 1 wherein the second material includes a conduction band greater than or equal to a conduction band of the first material.
[0062] This helps limit leakage current.
[0063] Example 8 includes the device of example 7 wherein the device includes a NMOS transistor.
[0064] Example 9 includes the device of example 7 wherein the second material is tensile stressed. [0065] Example 10 includes the device of example 7 comprising a substrate portion, wherein (a) the fin is on the substrate portion, (a) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is tensile stressed along the [110] direction.
[0066] Example 11 includes the device of example 10 wherein the second material is compressive stressed orthogonal to the [110] direction.
[0067] For instance, in a NMOS embodiment germanium in the pocket has -1.3% biaxial compressive strain in-plane normal to transport, and 0.97 % tensile strain along the channel direction. This improves electron transport mass.
[0068] Example 12 includes the device of example 1 wherein the second material includes a valence band less than or equal to a valence band of the first material.
[0069] This helps limit leakage current.
[0070] Example 13 includes the device of example 12 wherein the device includes a PMOS transistor.
[0071] Example 14 includes the device of example 12 comprising a substrate portion, wherein (a) the fin is on the substrate portion, (b) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is compressive stressed along the [110] direction.
[0072] Example 15 includes the device of example 14 wherein the second material is tensile stressed orthogonal to the [110] direction.
[0073] For instance, in an embodiment germanium in the pocket has 3.3% tensile strain in plane normal to transport, and compressive strain along the transport direction lowering the hole mass and boosting the injection velocity.
[0074] In an embodiment the pocket width is between 2 to 5 nm (measured parallel to axis 112) to prevent defects due to stress relaxation in the germanium pocket.
[0075] Example 16 includes the device of example 1 comprising: a spacer between the source and drain contacts; wherein a third axis, parallel to the first axis, intersects the spacer and the second material. [0076] Example 17 includes the device of example 1 comprising a substrate, wherein: the fin includes a fin height, measured parallel to the first axis, extending from a top of the fin to a bottom of the fin; the second material includes second material height, measured parallel to the first axis, that is at least 75% of the fin height.
[0077] Example 18 includes the device of example 1 wherein the channel has a length, measured along the long axis of the channel, which is between 5 and 20 nm.
[0078] Example 19 includes a package comprising: a package substrate; a first die on the package substrate; a second die on the package substrate; wherein the first die includes (a)(i) a fin including a first material; (a)(ii) a channel including the first material and included in the fin; (a)(iii) a source and a drain corresponding to the channel; (a)(iv) gate, source, and drain contacts corresponding to the channel, the source, and the drain; (a)(v) a fin portion that includes a second material, wherein (b)(i) a first axis, which is orthogonal to a long axis of the channel, intersects a middle portion of the source contact and the fin, (b)(ii) a second axis, parallel to the first axis, intersects a middle portion of the gate contact and the fin, and (b)(iii) the fin portion is located entirely between the first and second axes.
[0079] Example 20 includes the package of example 19 wherein: the first material includes silicon and at least one of germanium and tin; the second material includes germanium.
[0080] Example 21 includes the package of example 19 wherein: the second material includes a conduction band greater than or equal to a conduction band of the first material; and the second material is tensile stressed.
[0081] Example 22 includes the package of example 19 wherein: the second material includes a valence band less than or equal to a valence band of the first material; the second material is compressive stressed.
[0082] Example 23 includes the package according to example 19 comprising at least one of (a) a stiffener coupled to the first die, and (b) a heat spreader coupled to the first die.
[0083] Example 24 includes a system comprising: a memory; and a processor coupled to the memory, wherein at least one of the processor and the memory include the device according to any one of example 1. [0084] Example 25 includes the package of claim 19 wherein the first material includes silicon and the second material includes germanium.
[0085] Example 26 includes the package of claim 25 wherein the first material includes germanium.
[0086] Example 27 includes the package of claim 26 wherein the first material includes Sil-xGex and x is between .6 and .8.
[0087] Example 28 includes the package of claim 25 wherein the first material includes tin.
[0088] Example 29. The package of claim 28 wherein the first material includes Sil-xSnx and x is between .25 and .45.
[0089] Example 30 includes the package of claim 19 wherein the second material includes a conduction band greater than or equal to a conduction band of the first material.
[0090] Example 31 includes the package of claim 30 wherein the package includes a NMOS transistor.
[0091] Example 32 includes the package of claim 30 wherein the second material is tensile stressed.
[0092] Example 33 includes the package of claim 30 comprising a substrate portion, wherein (a) the fin is on the substrate portion, (a) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is tensile stressed along the [110] direction.
[0093] Example 34 includes the package of claim 33 wherein the second material is compressive stressed orthogonal to the [110] direction.
[0094] Example 35 includes the package of claim 19 wherein the second material includes a valence band less than or equal to a valence band of the first material.
[0095] Example 36 includes the package of claim 35 wherein the package includes a PMOS transistor. [0096] Example 37 includes the package of claim 35 comprising a substrate portion, wherein (a) the fin is on the substrate portion, (b) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is compressive stressed along the [110] direction.
[0097] Example 38 includes the package of claim 37 wherein the second material is tensile stressed orthogonal to the [110] direction.
[0098] Example 39 includes the package of claim 19 comprising: a spacer between the source and drain contacts; wherein a third axis, parallel to the first axis, intersects the spacer and the second material.
[0099] Example 40 includes the package of claim 19 comprising a substrate, wherein: the fin includes a fin height, measured parallel to the first axis, extending from a top of the fin to a bottom of the fin; the second material includes second material height, measured parallel to the first axis, that is at least 75% of the fin height.
[0100] Example 41 includes the package of claim 19 wherein the channel has a length, measured along the long axis of the channel, which is between 5 and 20 nm.
[0101] Example la includes a device comprising: a fin including a first material; a channel including the first material and included in the fin; a source and a drain corresponding to the channel; gate, source, and drain contacts corresponding to the channel, the source, and the drain; a fin portion that includes a second material, wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects a middle portion of the source contact and the fin, (b) a second axis, parallel to the first axis, intersects a middle portion of the gate contact and the fin, (c) the fin portion is located entirely between the first and second axes.
[0102] In another version of Example la at least a subportion of the fin portion is located entirely between the first and second axes.
[0103] As used herein, a“material” is different from an“element.” For example, SiGe is a different material from Ge even though both have a Ge element.
[0104] Embodiments with pockets are applicable to FinFETs as well as planar transistors. [0105] Another version of Example la includes a device comprising: a fin including a first material, the first material comprising a first material composition; a channel including the first material and included in the fin; a source and a drain corresponding to the channel; gate, source, and drain contacts corresponding to the channel, the source, and the drain; a fin portion that includes a second material, the second material including a second material composition that differs from the first material composition; wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects a middle portion of the source contact and the fin, (b) a second axis, parallel to the first axis, intersects a middle portion of the gate contact and the fin, (c) the fin portion is located entirely between the first and second axes.
[0106] Another version of Example la includes a device comprising: a fin including a first material; a channel including the first material, the channel being included in the fin; a source and a drain both corresponding to the channel; gate, source, and drain contacts corresponding to the channel, the source, and the drain; a fin portion that includes a second material; wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects the fin and a middle portion of the source contact, (b) a second axis, parallel to the first axis, intersects the fin and a middle portion of the gate contact, (c) the fin portion is located between the first and second axes, (d) the first material has a first material composition and the second material has a second material composition, and (e) the second material composition differs from the first material composition.
[0107] For example, a channel located in a nanoribbon or nanowire is still a channel included in a fin if the ribbon or wire is formed from a fin.
[0108] Another version of Example la includes a device comprising: a fin including a first material; a channel including the first material; a source and a drain both corresponding to the channel; gate, source, and drain contacts corresponding to the channel, the source, and the drain; a fin portion that includes a second material; wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects the fin and a middle portion of the source contact, (b) a second axis, parallel to the first axis, intersects the fin and a middle portion of the gate contact, (c) the fin portion is located between the first and second axes, (d) the first material has a first material composition and the second material has a second material composition, and (e) the second material composition differs from the first material composition. [0109] Another version of Example la includes a device comprising: a semiconductor layer including a first material; a channel including the first material; a source and a drain both corresponding to the channel; gate, source, and drain contacts corresponding to the channel, the source, and the drain; a semiconductor layer portion that includes a second material; wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects the semiconductor layer and a middle portion of the source contact, (b) a second axis, parallel to the first axis, intersects the semiconductor layer and a middle portion of the gate contact, (c) the semiconductor layer portion is located between the first and second axes, (d) the first material has a first material composition and the second material has a second material composition, and (e) the second material composition differs from the first material composition.
[0110] Thus, not all embodiments require fins. For example, planar transistors can benefit from this technology.
[0111] Example 2a includes the device of example la wherein the first material includes silicon and the second material includes germanium.
[0112] Example 3a includes the device of example 2a wherein the first material includes germanium.
[0113] Example 4a includes the device of example 3 a wherein the first material includes Sil-xGex and x is between .6 and .8.
[0114] Example 5a includes the device of example 2a wherein the first material includes tin.
[0115] Example 6a includes the device of example 4a wherein the first material includes Sil-xSnx and x is between .25 and .45.
[0116] Example 7a includes the device according to any of examples la-4a wherein the second material includes a conduction band greater than or equal to a conduction band of the first material.
[0117] For instance, the conduction band of germanium is equal to or greater than the conduction band of a material including silicon and germanium. [0118] Example 8a includes the device according to any of examples la-4a and 7a wherein the device includes a NMOS transistor.
[0119] Example 9a includes the device according to any of examples la-4 and 7-8 wherein the second material is tensile stressed.
[0120] Example lOaincludes the device according to any of examples la-4a and 7-9a comprising a substrate portion, wherein (a) the fin is on the substrate portion, (a) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is tensile stressed along the [110] direction.
[0121] In this example, the fin may be (a) formed from the substrate (i.e., monolithic with substrate), or (b) coupled to the substrate but not monolithic with the substrate.
[0122] Example lla includes the device according to any of examples la-4a and 7a-l0a wherein the second material is compressive stressed orthogonal to the [110] direction.
[0123] For instance, an embodiment includes the subject matter of examples la, 2a, 3a, 7a, lOa, and lla.
[0124] Example l2aincludes the device according to any of examples la-2a and 5a-6a wherein the second material includes a valence band less than or equal to a valence band of the first material.
[0125] Example l3aincludes the device according to any of examples la-2a, 5a-6a, and l2a wherein the device includes a PMOS transistor.
[0126] Example l4a includes the device according to any of examples la-2a, 5a-6a, and l2a-l3a comprising a substrate portion, wherein (a) the fin is on the substrate portion, (b) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is compressive stressed along the [110] direction.
[0127] Example l5a includes the device according to any of examples la-2a, 5a-6a, and l2a-l4a wherein the second material is tensile stressed orthogonal to the [110] direction.
[0128] For instance, an embodiment includes the subject matter of examples la, 2a, 5a, l2a, l4a, and l5a. [0129] Example l6a includes the device according to any of examples la-l5a comprising: a spacer between the source and drain contacts; wherein a third axis, parallel to the first axis, intersects the spacer and the second material.
[0130] Example l7a includes the device according to any of examples la-l6a comprising a substrate, wherein: the fin includes a fin height, measured parallel to the first axis, extending from a top of the fin to a bottom of the fin; the second material includes second material height, measured parallel to the first axis, that is at least 75% of the fin height.
[0131] Example l8a includes the device according to any of examples la-l7a wherein the channel has a length, measured along the long axis of the channel, which is between 5 and 20 nm.
[0132] Example l9a includes a system comprising: a memory; and a processor coupled to the memory, wherein at least one of the processor and the memory include the device according to any one of examples la to l8a.
[0133] Example 20a includes a package comprising: a package substrate; a first die on the package substrate; a second die on the package substrate; wherein the first die includes (a)(i) a fin including a first material; (a)(ii) a channel including the first material and included in the fin; (a)(iii) a source and a drain corresponding to the channel; (a)(iv) gate, source, and drain contacts corresponding to the channel, the source, and the drain; (a)(v) a fin portion that includes a second material, wherein (b)(i) a first axis, which is orthogonal to a long axis of the channel, intersects a middle portion of the source contact and the fin, (b)(ii) a second axis, parallel to the first axis, intersects a middle portion of the gate contact and the fin, and (b)(iii) the fin portion is located entirely between the first and second axes.
[0134] Example 2la includes the package of example 20a wherein: the first material includes silicon and at least one of germanium and tin; the second material includes germanium.
[0135] Example 22a includes the package according to any of examples 20a-2la wherein: the second material includes a conduction band greater than or equal to a conduction band of the first material; and the second material is tensile stressed. [0136] Example 23a includes the package according to any of examples 20a-2la wherein: the second material includes a valence band less than or equal to a valence band of the first material; the second material is compressive stressed.
[0137] Example 24a includes the package according to any of examples 20a-23a comprising at least one of (a) a stiffener coupled to the first die, and (b) a heat spreader coupled to the first die.
[0138] Various embodiments include a semiconductive substrate. Such a substrate may be a bulk semiconductive material this is part of a wafer. In an embodiment, the semiconductive substrate is a bulk semiconductive material as part of a chip that has been singulated from a wafer. In an embodiment, the semiconductive substrate is a semiconductive material that is formed above an insulator such as a semiconductor on insulator (SOI) substrate. In an embodiment, the semiconductive substrate is a prominent structure such as a fin that extends above a bulk semiconductive material.
[0139] The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top" surface of that substrate; the substrate may actually be in any orientation so that a "top" side of a substrate may be lower than the "bottom" side in a standard terrestrial frame of reference and still fall within the meaning of the term "top." The term "on" as used herein (including in the claims) does not indicate that a first layer "on" a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

What is claimed is:
1. A device comprising:
a fin including a first material;
a channel including the first material, the channel being included in the fin;
a source and a drain both corresponding to the channel;
gate, source, and drain contacts corresponding to the channel, the source, and the drain;
a fin portion that includes a second material;
wherein (a) a first axis, which is orthogonal to a long axis of the channel, intersects the fin and a middle portion of the source contact, (b) a second axis, parallel to the first axis, intersects the fin and a middle portion of the gate contact, (c) the fin portion is located between the first and second axes, (d) the first material has a first material composition and the second material has a second material composition, and (e) the second material composition differs from the first material composition.
2. The device of claim 1 wherein the first material includes silicon and the second material includes germanium.
3. The device of claim 2 wherein the first material includes germanium.
4. The device of claim 3 wherein the first material includes Sii_xGex and x is between .6 and .8.
5. The device of claim 2 wherein the first material includes tin.
6. The device of claim 4 wherein the first material includes Sii_xSnx and x is between .25 and .45.
7. The device according to any of claims 1-4 wherein the second material includes a conduction band greater than or equal to a conduction band of the first material.
8. The device according to any of claims 1-4 and 7 wherein the device includes a NMOS transistor.
9. The device according to any of claims 1-4 and 7-8 wherein the second material is tensile stressed.
10. The device according to any of claims 1-4 and 7-9 comprising a substrate portion, wherein (a) the fin is on the substrate portion, (a) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is tensile stressed along the [110] direction.
11. The device according to any of claims 1-4 and 7-10 wherein the second material is compressive stressed orthogonal to the [110] direction.
12. The device according to any of claims 1-2 and 5-6 of claim 1 wherein the second material includes a valence band less than or equal to a valence band of the first material.
13. The device according to any of claims 1-2, 5-6, and 12 wherein the device includes a PMOS transistor.
14. The device according to any of claims 1-2, 5-6, and 12-13 comprising a substrate portion, wherein (a) the fin is on the substrate portion, (b) the substrate portion has a (100) crystal orientation, (c) the channel is oriented to conduct current in a [110] direction, and (d) the second material is compressive stressed along the [110] direction.
15. The device according to any of claims 1-2, 5-6, and 12-14 wherein the second material is tensile stressed orthogonal to the [110] direction.
16. The device according to any of claims 1-15 comprising:
a spacer between the source and drain contacts;
wherein a third axis, parallel to the first axis, intersects the spacer and the second material.
17. The device according to any of claims 1-16 comprising a substrate, wherein:
the fin includes a fin height, measured parallel to the first axis, extending from a top of the fin to a bottom of the fin;
the second material includes second material height, measured parallel to the first axis, which is at least 75% of the fin height.
18. The device according to any of claims 1-17 wherein the channel has a length, measured along the long axis of the channel, that is between 5 and 20 nm.
19. A system comprising:
a memory; and
a processor coupled to the memory,
wherein at least one of the processor and the memory include the device according to any one of claims 1 to 18.
20. A package comprising:
a package substrate;
a first die on the package substrate;
a second die on the package substrate;
wherein the first die includes (a)(i) a fin including a first material; (a)(ii) a channel including the first material, the channel being included in the fin; (a)(iii) a source and a drain both corresponding to the channel; (a)(iv) gate, source, and drain contacts corresponding to the channel, the source, and the drain; and (a)(v) a fin portion that includes a second material, wherein (b)(i) a first axis, which is orthogonal to a long axis of the channel, intersects the fin and a middle portion of the source contact, (b)(ii) a second axis, parallel to the first axis, intersects the fin and a middle portion of the gate contact, and (b)(iii) the fin portion is located between the first and second axes.
21. The package of claim 20 wherein:
the first material includes silicon and at least one of germanium and tin; and the second material includes germanium.
22. The package according to any of claims 20-21 wherein:
the second material includes a conduction band greater than or equal to a conduction band of the first material; and
the second material is tensile stressed.
23. The package according to any of claims 20-21 wherein:
the second material includes a valence band less than or equal to a valence band of the first material;
the second material is compressive stressed.
24. The package according to any of claims 20-23 comprising at least one of (a) a stiffener coupled to the first die, and (b) a heat spreader coupled to the first die.
PCT/US2017/066992 2017-12-18 2017-12-18 Switching device with pocket having high mobility carriers WO2019125361A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2017/066992 WO2019125361A1 (en) 2017-12-18 2017-12-18 Switching device with pocket having high mobility carriers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2017/066992 WO2019125361A1 (en) 2017-12-18 2017-12-18 Switching device with pocket having high mobility carriers

Publications (1)

Publication Number Publication Date
WO2019125361A1 true WO2019125361A1 (en) 2019-06-27

Family

ID=66993955

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2017/066992 WO2019125361A1 (en) 2017-12-18 2017-12-18 Switching device with pocket having high mobility carriers

Country Status (1)

Country Link
WO (1) WO2019125361A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130161694A1 (en) * 2011-12-23 2013-06-27 International Business Machines Corporation Thin hetereostructure channel device
US20160155682A1 (en) * 2012-06-27 2016-06-02 Intel Corporation Integrated heat spreader that maximizes heat transfer from a multi-chip package
US20160190317A1 (en) * 2014-12-31 2016-06-30 Stmicroelectronics, Inc. Hetero-channel finfet
WO2017003414A1 (en) * 2015-06-27 2017-01-05 Intel Corporation Low damage self-aligned amphoteric finfet tip doping
US20170125527A1 (en) * 2014-03-27 2017-05-04 Intel Corporation Germanium tin channel transistors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130161694A1 (en) * 2011-12-23 2013-06-27 International Business Machines Corporation Thin hetereostructure channel device
US20160155682A1 (en) * 2012-06-27 2016-06-02 Intel Corporation Integrated heat spreader that maximizes heat transfer from a multi-chip package
US20170125527A1 (en) * 2014-03-27 2017-05-04 Intel Corporation Germanium tin channel transistors
US20160190317A1 (en) * 2014-12-31 2016-06-30 Stmicroelectronics, Inc. Hetero-channel finfet
WO2017003414A1 (en) * 2015-06-27 2017-01-05 Intel Corporation Low damage self-aligned amphoteric finfet tip doping

Similar Documents

Publication Publication Date Title
US10548249B2 (en) Shielding in electronic assemblies
US20190058043A1 (en) Transistor gate-channel arrangements
US10886286B2 (en) Vertical memory control circuitry located in interconnect layers
US11145763B2 (en) Vertical switching device with self-aligned contact
US11682605B2 (en) Integrated circuit packages with asymmetric adhesion material regions
US20200373220A1 (en) Integrated circuit packages with thermal interface materials with different material compositions
US11616014B2 (en) Peripheral inductors
US11658222B2 (en) Thin film transistor with charge trap layer
US11127861B2 (en) Multi-gate thin film transistor memory
WO2019125361A1 (en) Switching device with pocket having high mobility carriers
US20200105747A1 (en) Finfet varactor quality factor improvement
US11296203B2 (en) Switching device having gate stack with low oxide growth
US20220199609A1 (en) Novel esd protection decoupled from diffusion
US10522683B2 (en) Transistors with ballistic or quasi-ballistic carrier behavior and low resistance in source and drain nodes
WO2018111226A1 (en) Transistor with asymmetric threshold voltage channel
US11737362B2 (en) Harvesting energy in an integrated circuit using the seebeck effect
WO2019125362A1 (en) High mobility oxide thin film transistor
US20240113220A1 (en) Technologies for transistors with a thin-film ferroelectric
US20230411390A1 (en) Two-dimensional pmos devices for providing cmos in back-end layers of integrated circuit devices
US20220418083A1 (en) Top side frame stiffener structure for a printed circuit board (pcb) stack
US20240074046A1 (en) Technologies for sealing liquid metal interconnect array packages
EP4138143A1 (en) Leakage insensitive transistor circuits
US20240136243A1 (en) Copper fill for heat management in integrated circuit device
US20230422496A1 (en) Logic circuits using vertical transistors with backside source or drain regions
US20230207421A1 (en) Technologies for thermoelectric-enhanced cooling

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17935641

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17935641

Country of ref document: EP

Kind code of ref document: A1