WO2019120309A1 - 一种晶圆级芯片级csp封装结构及其制备方法 - Google Patents

一种晶圆级芯片级csp封装结构及其制备方法 Download PDF

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Publication number
WO2019120309A1
WO2019120309A1 PCT/CN2018/123064 CN2018123064W WO2019120309A1 WO 2019120309 A1 WO2019120309 A1 WO 2019120309A1 CN 2018123064 W CN2018123064 W CN 2018123064W WO 2019120309 A1 WO2019120309 A1 WO 2019120309A1
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concentration
chip
wafer
phosphor
layer
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PCT/CN2018/123064
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English (en)
French (fr)
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王书昶
范艾杰
孙智江
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海迪科（南通）光电科技有限公司
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Priority claimed from CN201811202918.9A external-priority patent/CN109980070B/zh
Application filed by 海迪科（南通）光电科技有限公司 filed Critical 海迪科（南通）光电科技有限公司
Publication of WO2019120309A1 publication Critical patent/WO2019120309A1/zh
Priority to US16/908,546 priority Critical patent/US20200365788A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations

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  • the invention belongs to the technical field of semiconductor packaging, and in particular relates to a wafer level chip level CSP package structure and a preparation method thereof.
  • LEDs Light-emitting diodes
  • the package structure of the light emitting diode usually wraps the phosphor.
  • the phosphor is typically mixed in an encapsulant to change the color of the light emitted by the LED.
  • LEDs from the package form sooner or later can be roughly divided into: the earliest in-line package (LAMP), commonly seen in some low-end lighting display devices; surface mount package (SMD, Surface Mount Device), this package The method generally started in China around 2008; COB (Chip On Board), this packaging method was first promoted by Toshiba, and popular in China after 2010; Chip Scale Package (CSP), This type of packaging has emerged in recent years based on the development of flip chip technology, and commercial mass production has occurred after 2015.
  • LAMP in-line package
  • SMD Surface Mount Device
  • COB Chip On Board
  • CSP Chip Scale Package
  • the COB package is a solder and phosphor colloidal package in which the LED chip is directly fixed on the PCB with a conductive adhesive or an insulating paste, and then the LED chip is turned on.
  • the main process flow of COB packaging technology is shown in Figure 8.
  • CSP light source refers to a type of LED device, the core of which is that the CSP light source uses a phosphor or a fluorescent colloid film to wrap the flip chip structure. Therefore, most of the packaging steps and structures of the conventional LED light source are eliminated, so that the package size is greatly reduced, which is 1/5 to 1/10 of the original.
  • the current CSP light source packaging technology is often after the wafer is diced and split, after sorting and rearranging the light-emitting chip, followed by phosphor or fluorescent colloid lamination, spraying and other subsequent processes, and often forming a single layer of opaque phosphor colloid The layer is thicker.
  • Such a process is still cumbersome and the process cost is high; and because the phosphor or the fluorescent colloid layer is thick, the heat dissipation of the light-emitting chip is poor; the distance of the light-emitting chip after the split is small, which is to cut and separate the phosphor or fluorescent.
  • the colloidal light-emitting chip has greater precision requirements.
  • CSP is not easy to mount, and it is difficult to weld on the upper plate. Since the positive and negative electrode spacing of the chip is only 90-200 micrometers, the precision of the SMT patch is high, which is easy to cause the CSP to rotate or tilt. Therefore, the chip and the solder paste need to be precisely aligned, otherwise the risk of leakage and open circuit reliability is easy. . In addition, the traditional CSP phosphor is opaque, whether the chip is neatly arranged in the package, and whether the offset is unknown, which will increase the difficulty of mounting, and the chip and the pad cannot be accurately positioned, as shown in FIG. 9 and FIG. 10 ( Inside the red box is the chip core).
  • the phosphor layer is thicker, resulting in poor heat dissipation.
  • the phosphor generates a large amount of heat while emitting yellow-green light in the down-conversion, so it is necessary to perform good heat dissipation.
  • the phosphor colloid is thick, heat dissipation will occur. Blocked.
  • the results show that when the surface temperature of the CSP chip reaches 150 degrees or more, the light efficiency of the light source is significantly reduced, and the phosphor colloid is cracked.
  • too thick a phosphor layer can cause yellowing problems; of course, the thickness of the phosphor layer is too thin, which also causes mounting and cutting problems.
  • FIGS. 14 and 15 A schematic diagram of the structure of the conventional CSP technique and the technique of the present invention is shown in FIGS. 14 and 15.
  • the CSP structure of the present invention further extends the packaging process and the chip process to the upstream chip process, and encapsulates on the wafer scale to form an opaque core, and an outer peripheral semi-transparent phosphor, which effectively solves
  • the above-mentioned problems faced by conventional CSPs can greatly improve the CSP technology.
  • the translucent layer package facilitates placement.
  • the solid crystal machine mainly has two main parts, a PC Contronl (control) system, and a PRS (image recognition processing system), which are separately controlled by two hosts.
  • a PC Contronl (control) system for the CSP chip, only the chip core is accurately identified.
  • the second layer of the semi-transparent phosphor layer coated in the structure of the invention can greatly facilitate the solid crystal machine to accurately and accurately identify the position of the packaged chip core, and can more accurately control the position between the light source and the substrate;
  • the solid crystal machine will not be able to accurately identify the chip core when it is solid crystal, which will easily lead to a greatly reduced chip placement yield, which will cause leakage and the like, greatly reducing the light source.
  • the phosphor layer is thickened and thinned, and the heat dissipation performance is greatly improved.
  • the heat source of the light source in addition to the LED chip that is traditionally concerned, the phosphor will generate a large amount of heat while down-converting to emit yellow-green light, so it is necessary to perform good heat dissipation when the phosphor colloid is thick. The heat will be blocked.
  • the surface temperature will reach 150 degrees or more, and the light effect will be easily reduced, and the colloid will be cracked.
  • the wafer level chip scale CSP package structure of the present invention is the first phosphor spray on the wafer level scale, so the phosphor can be easily precipitated downward, and the precipitation only requires two-dimensional uniformity and longitudinal uniformity. No requirements. After the phosphor is precipitated, the denseness is strong, which can be closely arranged from the SEM photographs of Figs. 17 and 18. Therefore, when the phosphor absorbs about 70% of the blue light, the light is quickly conducted downward by the phosphor. In the conventional CSP technology, after the phosphor absorbs heat, in the silica gel with a thermal conductivity of only 0.2-0.7, the phosphor will continue to be heated by the excitation of the blue light, and this heat is difficult to conduct. In the same case, the surface temperature of the package structure of the present invention is only 110 to 120 degrees, thereby improving high reliability; facilitating heat dissipation, which is the second advantage of the present invention.
  • the light color is more uniform.
  • the front side of the chip is 70% light and the side is 30% light. That is, when a certain concentration of phosphor on the front side of the chip and 70% of blue light form a positive white color, the light of the same concentration of phosphor and 30% of the blue side of the chip will be yellowish, and yellow edges appear on the edges, as shown in FIG. .
  • a wafer level chip-scale CSP package structure is a high concentration phosphor in the middle, and a low concentration phosphor on the side, so that 30% of the blue light on the side and 20% to 30% of the intermediate high concentration phosphor
  • a combination of low-concentration second-layer phosphors on the left and right sides, the color of light thus obtained is uniform and uniform, as shown in FIG.
  • the invention can effectively prevent side leakage blue light and yellow edge phenomenon caused by uneven distribution of phosphors; the light angle can be adjusted arbitrarily, and is adapted to different application requirements.
  • the light color is more uniform, which is the third advantage of the present invention.
  • the wafer level chip-scale CSP package structure capable of improving the heat dissipation performance of the light-emitting chip, reducing the device fabrication cost, and improving the reliability and uniformity of the device is very promising.
  • the technical problem to be solved by the present invention is to provide a wafer level chip scale CSP package structure and a preparation method thereof capable of improving heat dissipation performance of a light emitting chip, reducing device fabrication cost, and improving device reliability and uniformity.
  • a wafer level chip-scale CSP package structure which is innovative in that it comprises a rectangular chip, and a first concentration phosphor layer is disposed on the light emitting surface of the chip to form Package A, and the side of the light-emitting surface of the chip is ⁇ 10% area covered by the first concentration fluorescent layer; and the top surface and the side surface of the package A are further provided with a second concentration of fluorescent layer which is translucent or transparent Forming a package B; a phosphor concentration in the first concentration phosphor layer is denoted as w 1 , a phosphor concentration in the second concentration phosphor layer is denoted as w 2 , and w 1 >w 2 ; the first concentration The phosphor layers are uniform in thickness on the top surface of the chip, the second concentration phosphor layer is uniform in thickness on the top surface of the chip, and the package body B has a rectangular structure.
  • the fluorescent layers of the first concentration fluorescent layer and the second concentration fluorescent layer are formed of any one of a phosphor or a fluorescent colloid.
  • the phosphor concentration in the first concentration fluorescent layer is 50-90%, and the phosphor content in the second concentration fluorescent layer is 0-40%.
  • a method for fabricating a wafer level chip-scale CSP package structure described above is innovative: the preparation method includes the following steps:
  • step (2) Perform step 2.1 or step 2.2 on the qualified wafer in step (1).
  • the step 2.1 is specifically for filming the qualified wafers in the step (1), and cutting and dicing the wafer after the filming, and forming a first fluorescent layer directly on the entire wafer after the dicing;
  • the step 2.2 is specifically to form a first fluorescent layer directly on the qualified wafer on the step (1), and then to perform filming, and to cut and split the wafer after the filming;
  • the chip is again divided to form a wafer level chip scale package structure
  • the concentration difference between the first and second concentration phosphor layers is utilized, so that the first concentration of the fluorescent layer can be observed from the outside of the package structure, and the first concentration of the fluorescent layer is passed.
  • the position is subjected to a solid crystal test on the chip, and the qualified product package after the sorting is tested and put into storage.
  • the first phosphor layer is in a non-cured state before the wafer is expanded in step (3).
  • the thickness of the first concentration fluorescent layer is ⁇ 150 ⁇ m
  • the thickness of the top layer of the second concentration fluorescent layer is 10 to 1000 ⁇ m
  • the thickness of the sidewall is 10 to 2000 ⁇ m.
  • the adjacent chip pitch is greater than 1 time of the chip size.
  • the sorted rearranged chip is placed on the screen type jig to evenly divide the chip.
  • step (7) after the baking is cured, the chip is again divided.
  • the second concentration of the fluorescent layer in the step (7) is formed by coating, laminating or molding.
  • the wafer level chip-scale CSP package structure of the present invention has a higher concentration of phosphors used in the first concentration phosphor layer, and the formed phosphor layer has a single side, a thin thickness, a high density, and a similar size of the light-emitting chip, which is advantageous.
  • the light-emitting chip dissipates heat, reduces the occurrence of colloid cracking, and improves the light efficiency of the LED chip;
  • the second concentration of the fluorescent layer uses a lower concentration of the phosphor, and the second concentration of the fluorescent layer formed is translucent or transparent, which is beneficial to the other hand.
  • the first concentration of the phosphor layer is non- Transparent and contour is basically the same as the chip, and the second concentration layer is translucent or transparent.
  • the double-layer WLCSP package thus produced needs to accurately and precisely align the positive and negative electrodes on the back surface to the corresponding positive and negative electrodes on the substrate.
  • the transparent layer is transparent or translucent, the first fluorescent layer with opaque but contour and chip equivalent can be used for accurate crystal bonding and electrode pairing.
  • other subsequent processes to reduce the difficulty of the process, thereby reducing production cost devices;
  • FIG. 1 is a schematic diagram of a wafer level chip scale CSP package structure of the present invention.
  • FIG. 2 is a cross-sectional view showing a wafer level chip-scale CSP package structure of the present invention after forming a first concentration phosphor layer.
  • FIG 3 is a bottom view of the wafer level chip scale CSP package structure of the present invention after forming a first concentration phosphor layer.
  • FIG. 4 is a cross-sectional view showing the wafer level chip-scale CSP package structure of the present invention after forming a second concentration phosphor layer.
  • FIG. 5 is a schematic top view showing the use of a screen-like jig to assist in forming a second concentration of phosphor layer.
  • Fig. 6 is a schematic cross-sectional view showing the completion of the second concentration of the phosphor layer by a lamination method.
  • Figure 7 is a schematic cross-sectional view showing the formation of a second concentration of phosphor layer by means of a die top.
  • Figure 8 is a main process flow diagram of the COB packaging technology.
  • Figure 9 and Figure 10 show the effect of the CSP chip being inaccurately aligned and the placement failure.
  • Fig. 11 is a diagram showing the effect of unevenness in light color of the CSP chip and yellowing phenomenon.
  • Fig. 12 is a view showing an effect of inconsistency in the thickness of the CSP side due to the cutting error.
  • Figure 13 is a graph showing the data of the Bin rate test.
  • FIG. 14 is a schematic structural view of a conventional CSP technology.
  • Figure 15 is a schematic structural view of a CSP technology of the present invention.
  • Figure 16 is a photo of a chip mount microscope.
  • Figure 17 is a schematic view of a conventional CSP structure and a cross-sectional SEM image.
  • Figure 18 is a schematic view of a CSP structure and a cross-sectional SEM image of the present invention.
  • Fig. 19 is a view showing the conventional CSP light-emitting effect.
  • Fig. 20 is a view showing the effect of the CSP light emission of the present invention.
  • the wafer level chip-level CSP package structure of the present embodiment includes a chip 1 and a chip electrode 4 disposed on the chip 1 , and a first concentration phosphor layer is disposed on a top surface of the light emitting surface of the chip 1 .
  • the phosphor in the first concentration phosphor layer 2 The concentration is denoted as w 1 , the phosphor concentration in the second concentration fluorescent layer 3 is denoted as w 2 , and w 1 >w 2 ; the first concentration of the fluorescent layer 2 is located on the top surface of the chip 1 having the same thickness, and the second concentration of the fluorescent layer 3
  • the thickness of the top surface of the chip 1 is uniform, and the package body B has a rectangular structure.
  • the translucent or transparent second concentration fluorescent layer 3 the second concentration fluorescent layer (ie, the skirt) and the inner chip (ie, the inner core) are imaged by the image recognition technology under the LED mounting device.
  • the gray scale contrast is used to identify and distinguish the two.
  • Image recognition technology is a well-known technology, and its working principle will not be described again here.
  • the LED mounting device can smoothly recognize the boundary between the core and the skirt, that is, the second concentration fluorescent layer 3 is considered to be transparent or translucent;
  • the LED mounting device cannot smoothly distinguish the boundary between the core and the skirt, that is, the second concentration fluorescent layer 3 is considered to be opaque;
  • the benchmark for the above-mentioned placement equipment to be successfully identified is that in the batch industrial production, the recognition accuracy of the equipment is usually 99.5% or even higher.
  • the image recognition technology is used for transparency recognition.
  • the machine recognition threshold is obtained by calculating the binary value of the gray value.
  • the kernel gray value is 255.
  • the skirt gray value is 200
  • the machine kernel recognition success rate is greater than 99.95%.
  • the kernel gray value is 255 and the skirt gray value is 225
  • the machine kernel recognition success rate is 99.5%.
  • the skirt gray value is 240
  • the machine core recognition success rate is only 15%
  • the second concentration phosphor layer 3 is an opaque layer.
  • the fluorescent layers of the first concentration fluorescent layer 2 and the second concentration fluorescent layer 3 are formed by a fluorescent colloid, and the phosphor concentration in the first concentration fluorescent layer 2 is 50-90%, and the second concentration is fluorescent.
  • the phosphor powder in layer 3 has a mass ratio of 0 to 40%; the thickness of the first concentration phosphor layer 2 is ⁇ 150 ⁇ m, the thickness of the top layer of the second concentration phosphor layer 3 is 10 to 1000 ⁇ m, and the thickness of the sidewall is 10 to 2000 ⁇ m.
  • the side surface of the light-emitting surface of the chip may be covered by a small amount of the first concentration fluorescent layer near the top surface, and the side surface of the light-emitting surface of the chip is covered by the first concentration fluorescent layer.
  • step (2) Perform step 2.1 or step 2.2 on the qualified wafer in step (1).
  • Step 2.1 is specifically as shown in FIG. 2, the film of the qualified wafer is sampled in step (1), and the wafer is cut and lobed after the film is affixed, and the mass of the phosphor powder is sprayed on the entire wafer after the cleavage.
  • a 50 to 90% fluorescent glue directly forming a first sprayed fluorescent layer 5 on the chip in the wafer;
  • Step 2.2 is specifically as shown in FIG. 2, in the step (1), the qualified wafer is sprayed with a fluorescent glue having a phosphor mass ratio of 50-90%, and the first sprayed fluorescent layer is directly formed on the chip in the wafer. 5, and then film, and the wafer after the film is cut and split;
  • the baking curing temperature is 30 ° C ⁇ 200 ° C
  • baking curing time is 3 ⁇ 12h
  • the chip in the wafer is tested for brightness, index and color temperature photoelectric parameters, and sorted according to the test result;
  • a fluorescent paste having a phosphor mass ratio of 0 to 40% is sprayed on the sorting and rearranging chip to form a top layer having a thickness of 10 to 1000 ⁇ m and a sidewall thickness of 10 to 2000 ⁇ m.
  • a semi-transparent or transparent second concentration phosphor layer 3 after forming the second concentration phosphor layer 3, the adjacent chip pitch is greater than 1 times the chip size, and the chip covered with the second concentration phosphor layer 3 is baked and cured, and baked.
  • Baking curing temperature is 30 ° C ⁇ 200 ° C
  • baking curing time is 3 ⁇ 12h;
  • the concentration difference between the first and second concentration phosphor layers is utilized, so that the first concentration of the fluorescent layer can be observed from the outside of the package structure, and the first concentration of the fluorescent layer is passed.
  • the position is subjected to a solid crystal test on the chip, and the qualified product package after the sorting is tested and put into storage.
  • the wafer level chip-level CSP package structure is unchanged, and only the steps (6) and (7) in the preparation step of the wafer level chip-level CSP package structure are changed, step (6) Specifically, as shown in FIG. 5, before the second concentration of the fluorescent layer 3 is applied, the sorting and rearranging chip 1 is placed on the screen-like jig 6 to evenly divide the chip 1, and then on the chip 1 which is again divided.
  • Step (7) is specifically: after baking and curing, forming a wafer level chip scale package structure.
  • a lamination or a mold top may be used for the formation of the second concentration fluorescent layer 3 in Embodiment 1 and Embodiment 2.
  • the lamination process is as shown in FIG. 6, and the silica gel and the phosphor are mixed in proportion to form a film. Phosphors with a phosphor content of 0-40%, then pour the fluorescent glue into the mold, bake and solidify to obtain a fluorescent film, and then adhere the fluorescent film to the surface of the sorted rearranged chip 1 and solidify again to form
  • the second concentration of the fluorescent layer 3; using the lamination process, the second concentration of the fluorescent layer 3 is controllable in shape, uniform in thickness, and high in stability.
  • the mold top process is as shown in Fig. 7.
  • the mold 7 is nested on the sorting and rearranging chip 1, and then the phosphor is mixed in proportion to the silica gel to form a fluorescent glue having a phosphor powder content of 0-40%. It is injected into the mold 7, and is subjected to red baking curing. After curing, the mold 7 is removed to form a solid and stable second concentration fluorescent layer 3, and then cutting is performed to obtain a single packaged chip.
  • the wafer level chip-scale CSP package structure prepared by the first embodiment and the second embodiment has a higher concentration of the phosphor used in the first concentration of the fluorescent layer 2, and the phosphor mass ratio is generally 50 to 90%.
  • the single-sided, thin thickness and high density of the fluorescent layer are similar to the size of the light-emitting chip, which is beneficial to the heat dissipation of the light-emitting chip, and reduces the occurrence of colloid cracking and improves the light-effect of the LED chip; the phosphor concentration of the second-concentration fluorescent layer 3 is low.
  • the phosphor powder proportion is generally 0-40%, and the formed second concentration fluorescent layer 3 is semi-transparent or even transparent.
  • the semi-transparent or transparent second-concentration fluorescent layer is advantageous for accurate solid-crystal bonding through the first formed fluorescent layer. Subsequent processes such as electrode alignment reduce process difficulty and thus reduce device fabrication costs.

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Abstract

本发明涉及一种晶圆级芯片级CSP封装结构及其制备方法，包括一芯片，在所述芯片出光面上设置有第一浓度荧光层，形成封装体A，且所述芯片出光面的侧面＜10％面积被第一浓度荧光层覆盖；在所述封装体A的顶面和侧面还设有呈半透明或透明状的第二浓度荧光层，形成封装体B；所述第一浓度荧光层中的荧光粉浓度记作w 1，第二浓度荧光层中的荧光粉浓度记作w 2，且w 1＞w 2；所述第一浓度荧光层和第二浓度荧光层通过前后两次喷荧光粉形成，更有利于工艺生产达到目标值，降低工艺难度，提高器件良率。本发明的优点在于：本发明晶圆级芯片级CSP封装结构，能够提高发光芯片散热性能、降低器件制备成本以及提高器件可靠性和均一性。

Description

一种晶圆级芯片级CSP封装结构及其制备方法 技术领域
本发明属于半导体封装技术领域，特别涉及一种晶圆级芯片级CSP封装结构及其制备方法。
背景技术
发光二极管(LED)具有体积小、使用寿命长节能环保、响应速度快和坚固耐用等优点，广泛应用于汽车和室内照明、交通信号灯、屏幕显示和液晶背光等邻域，是替代传统光源的理想光源。发光二极管的封装结构通常包裹荧光粉。所述荧光粉通常混合在封装胶中，用以改变发光二极管所发出光的颜色。而LED从封装形式出现的早晚，可以大致分为：最早的直插式封装(LAMP)，常见于一些低端的照明显示器件；表面贴片式封装(SMD，Surface Mount Device)，这种封装方式大致在2008年前后在国内兴起；板上芯片封装(COB，Chip On Board)，这种封装方式最早由东芝公司推动，2010年以后在国内盛行；芯片级封装(CSP，Chip Scale Package)，这种封装方式是最近几年基于倒装芯片技术的发展应运而生的，在2015年之后出现商业化量产。封装技术的发展具体可参考文献：王杰田，LED封装技术的现状与发展[J]。科技创新与应用，2017(12)：42。
COB封装是将LED芯片直接用导电胶或绝缘胶固定在PCB板上，然后进行LED芯片导通性能的焊接和荧光粉胶体封装。 COB封装技术的主要工艺流程如图8所示。
近年来，随着LED在器件材料、芯片工艺、封装技术等方面的研究不断进步，尤其是倒装芯片的逐渐成熟与荧光粉涂覆技术的多样化，一种新的芯片尺寸级封装CSP技术应运而生。所谓CSP光源是指一类LED器件，其核心是CSP光源采用荧光粉或荧光胶体膜包裹住倒装芯片结构。因此免除了传统LED光源的大部分封装步骤和结构，使得封装体尺寸大大减小，是原来的1/5到1/10。但是，目前CSP光源封装技术往往是将晶圆切割裂片后，通过对发光芯片分选重排后再进行荧光粉或荧光胶体压膜、喷涂等后续工艺，且往往所形成单层不透明荧光粉胶体层较厚。这样的工序仍然较为繁琐，工艺成本较高；且因为荧光粉或荧光胶体层较厚，造成发光芯片散热较差；发光芯片在裂片后间距较小，这就对再次切割分离覆盖荧光粉或荧光胶体的发光芯片有较大的精度要求。而且一次喷粉往往难以达到喷粉量要求或者对喷粉量精度要求极高。这些问题都会造成器件成本增加，器件的可靠性与均一性大大下降。
常规CSP光源技术主要面临的四大挑战：
(1)CSP不易贴装，上板焊接较为困难。由于芯片正负电极间距仅90-200微米，对SMT贴片的精度要求高，易造成CSP的旋转或翘起，所以芯片和锡膏需要非常精准的对准，否则容易漏电、开路可靠性风险。加之传统CSP荧光粉不透明，芯片在封装体内是否排列整齐，是否发生偏移均不可知，这样就会加大贴装 难度，芯片与焊盘无法实现精准定位，如图9和图10所示(红色框内为芯片内核)。
(2)CSP侧面胶体宽度一般参差不齐，导致光色不均匀，部分产品甚至会产生黄边现象，如图11所示；芯片摆放、切割误差带来CSP侧面胶厚不一致，从而导致侧面出光均匀性受到影响，如图12所示。同时，高精度的贴装、切割设备价格高、产能低。
(3)由于荧光粉分布均匀性、宽度、侧发光难以控制，一次涂布后入Bin率低，如图13所示。
(4)荧光粉层较厚，导致散热效果较差。通常高光密度下，光源的发热源除了LED芯片本身外，荧光粉在下转换发射出黄绿光的同时，也会产生大量的热，所以更需要进行良好散热，当荧光粉胶体很厚时，散热就会受阻。研究结果发现，当CSP芯片表面温度达到150度以上的时候，光源的光效明显下降，同时荧光粉胶体就会开裂。同时，荧光粉层太厚也会带来黄边问题；当然，荧光粉层厚度太薄，也会带来贴装和切割的问题。由于设备精度的限制，在贴装和切割带来的误差范围约为30微米，如果荧光粉层太薄，必然会导致侧壁荧光粉层的不均匀，同样会引起光色的不均匀和蓝光泄露的问题。本发明选取的荧光粉层的厚度，可以有效避免上述由于较厚荧光粉层带来的切割和贴装的难题。常规CSP技术与本发明技术的结构示意图，如图14和图15所示。
当前，常规CSP光源的四大技术难题让CSP应用面临两方面的局限：一是小尺寸芯片CSP贴装比较困难，当前CSP应用主要 还局限于1W以上应用；二是成本偏高，导致其主要在高光密度、高亮度、高指向性光源上的利用，其中包括车灯、闪光灯、背光以及高端可调色温的照明应用等，难以延伸到其他领域。几种常见的LED芯片封装技术对比参见下表。
几种常见的LED芯片封装技术对比
Figure PCTCN2018123064-appb-000001
针对常规CSP技术难题，本发明涉及的CSP结构是把封装工艺和芯片工艺进一步向上游芯片工艺延伸，在晶圆规模上进行封装形成一个不透明的内核，以及外面环绕的半透明荧光体，有效解决了常规CSP面临的上述难题，可以实现CSP技术的大幅提升。
第一，半透明层封装利于贴装。固晶机主要是有两个主要部分，一个PC的Contronl(控制)***，一个是PRS(图像识别处理***)，分别由两个主机单独控制，对于CSP芯片而言，只有精准识别芯片内核，才能精准贴装。而本发明结构中所涂覆的第二层半透明状荧光粉层，可以极大地有利于固晶机高效准确地识别封装芯片内核的位置，可以更加精确地控制光源与基板之间的位置；而对于常规CSP具有不透明的荧光粉层，固晶机在固晶的时 候，将无法准确识别芯片内核，也就容易导致芯片贴装良率大大降低，从而引起漏电等情况，极大地降低了光源的可靠性。同时，就本发明的晶圆级芯片级CSP技术而言，在可调色温灯丝灯的应用上，在其一毫米范围内甚至可贴装两种不同CSP光源；便于精准贴装，这是本发明的优势之一，如图16所示，芯片内核精准判别后，能够实现高效贴装。
第二，荧光粉层由厚变薄，散热性能极大提升。通常高光密度下，光源的发热源除了传统上大家关注的LED芯片外，荧光粉在下转换发射出黄绿光的同时，也会产生大量的热，所以更需要进行良好散热，当荧光粉胶体很厚时，散热就会受阻。对于一般产品而言，当其功率达到4W以上时，表面温度就会达到150度以上，容易光效下降，胶体开裂。本发明的晶圆级芯片级CSP封装结构是在晶圆级规模进行的第一次荧光粉喷涂，因此荧光粉可以很容易往下沉淀，而沉淀只需要二维的均匀性，纵向的均匀性并无要求。荧光粉沉淀后，致密性很强，这一点可以从图17和图18的SEM照片中可以颗粒是一个个紧密排列的。因此，当荧光粉吸收了70％左右的蓝光的时候，这些光被荧光粉很快地往下传导出去了。而在常规CSP技术里面荧光粉吸收了热以后，在热导率只有0.2～0.7的硅胶里面，荧光粉将持续被蓝光所激发泵浦加热的，而这个热是很难传导出去的。而同样情况下本发明的封装结构表面温度只有110～120度，进而提高了高可靠性；利于散热，这是本发明的优势之二。
第三，光色更加均匀。常规CSP而言，芯片正面出光是70％，侧面出光30％。即芯片正面一定浓度的荧光粉和70％的蓝光组成正白的时候，而同样浓度的荧光粉和芯片侧面30％的蓝光组成的光就会偏黄，边缘出现黄边，如图19所示。而本发明所涉及的一种晶圆级芯片级CSP封装结构中间是高浓度的荧光粉，侧面是低浓度的荧光粉，从而侧面30％的蓝光和相对中间高浓度荧光粉20％到30％左右的低浓度的第二层荧光粉组合，这样得到的光色是均匀的一致的，如图20所示。本发明可有效防止因荧光粉分布不均导致的侧漏蓝光和黄边现象等；光角度可任意调节，适应于不同应用需求。光色更加均匀，这是本发明的优势之三。
因此，本发明所涉及的一种能够提高发光芯片散热性能、降低器件制备成本以及提高器件可靠性和均一性的晶圆级芯片级CSP封装结构是非常具有市场前景的。
发明内容
本发明要解决的技术问题是提供一种能够提高发光芯片散热性能、降低器件制备成本以及提高器件可靠性和均一性的晶圆级芯片级CSP封装结构及其制备方法。
为解决上述技术问题，本发明的技术方案为：一种晶圆级芯片级CSP封装结构，其创新点在于：包括一矩形芯片，在所述芯片出光面上设置有第一浓度荧光层，形成封装体A，且所述芯片出光面的侧面＜10％面积被第一浓度荧光层覆盖；在所述封装体A的顶面和侧面还设有呈半透明或透明状的第二浓度荧光层，形成封装体B；所述第一 浓度荧光层中的荧光粉浓度记作w 1，第二浓度荧光层中的荧光粉浓度记作w 2，且w 1＞w 2；所述第一浓度荧光层位于芯片顶面的厚度一致，所述第二浓度荧光层位于芯片顶面的厚度一致，且所述封装体B呈矩形结构。
进一步地，所述第一浓度荧光层和第二浓度荧光层的荧光层是由荧光粉或荧光胶体中的任一种形成的。
进一步地，所述第一浓度荧光层中荧光粉质量占比为50～90％，所述第二浓度荧光层中荧光粉质量占比为0～40％。
一种上述的晶圆级芯片级CSP封装结构的制备方法，其创新点在于：所述制备方法包括如下步骤：
(1)晶圆片进行抽测；
(2)对步骤(1)抽测合格的晶圆片进行步骤2.1或步骤2.2，
所述步骤2.1具体为对步骤(1)抽测合格的晶圆片进行贴膜，并对贴膜后的晶圆片切割和裂片，裂片后在整个晶圆片上直接形成第一荧光层；
所述步骤2.2具体为在步骤(1)抽测合格的晶圆片上直接形成第一荧光层，然后进行贴膜，并对贴膜后的晶圆片切割和裂片；
(3)对覆盖有第一荧光层的晶圆片进行扩膜，形成第一浓度荧光层，进而形成封装体A，且所述封装体A顶面的正投影轮廓与芯片出光面的正投影轮廓的各边长对应边之间的误差＜30微米；
(4)对扩膜后的晶圆片烘烤固化；
(5)烘烤固化后，对晶圆片内的芯片测试分选重排；
(6)在分选重排的芯片上形成呈半透明或透明状的第二浓度荧光层，并对覆盖有第二浓度荧光层的芯片进行烘烤固化；
(7)在步骤(6)前或步骤(6)后对芯片再次分割，形成晶圆级芯片级封装结构；
(8)对步骤(7)形成的晶圆级芯片级封装结构，利用第一、二浓度荧光层的浓度差，使得可从封装结构外部观察到第一浓度荧光层，通过第一浓度荧光层位置对芯片进行固晶测试，测试分选后的合格产品包装入库。
进一步地，在步骤(3)晶圆片进行扩膜前，第一荧光层处于非固化状态。
进一步地，所述第一浓度荧光层的厚度≤150μm，所述第二浓度荧光层的顶层厚度为10～1000μm，侧壁厚度为10～2000μm。
进一步地，形成第二浓度荧光层后，相邻芯片间距大于芯片尺寸1倍。
进一步地，所述步骤(7)在形成第二浓度荧光层之前，将分选重排的芯片放置丝网类治具把芯片均匀分割。
进一步地，所述步骤(7)在烘烤固化后，对芯片再次分割。
进一步地，所述步骤(7)中第二浓度荧光层是通过涂布、压膜或模顶的方式形成的。
本发明的优点在于：
(1)本发明晶圆级芯片级CSP封装结构，第一浓度荧光层所采用的荧光粉浓度较高，所形成的荧光层单面、厚度薄、致密度高与发 光芯片尺寸相近，有利于发光芯片散热，并降低胶体龟裂发生，提升LED芯片光效；第二浓度荧光层所采用的荧光粉浓度较低，所形成的第二浓度荧光层呈半透明甚至透明状，一方面有利于后期工艺流程中获得相邻发光芯片较大间距，降低切割分离覆盖荧光粉或荧光胶体的发光芯片的精度要求，从而提高器件的可靠性和均一性；另一方面由于第一浓度荧光粉层是非透明且轮廓基本和芯片一致，而第二浓度层是半透明或透明状的，由此制作的双层WLCSP封装需要把背面的正负电极精准固晶对准到的基板上对应的正负电极时，可以透过透明或半透明的第二浓度荧光层，利用不透明但轮廓和芯片相当的第一荧光层准确进行固晶、电极对准等后续工艺，降低工艺难度，进而降低器件制备成本；
(2)本发明晶圆级芯片级CSP封装结构的制备方法，本发明封装技术采用分别在晶圆级与芯片级先后两次形成荧光层，且荧光层表面致密；其中，在第一次形成荧光层后，对发光芯片进行扩膜、烘烤固化、测试重排等工艺流程，第二次对发光芯片喷涂荧光粉后对荧光胶体层进行切割***等后续工艺，工艺流程简单且稳定，器件良率大大提高；
(3)本发明晶圆级芯片级CSP封装结构的制备方法，其中，扩膜前所形成荧光层处于非固化态，更有利于芯片分离，便于后续芯片测试重排等工艺进行。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明。
图1为本发明晶圆级芯片级CSP封装结构的示意图。
图2为本发明晶圆级芯片级CSP封装结构形成第一浓度荧光层后的横截面示意图。
图3为本发明晶圆级芯片级CSP封装结构形成第一浓度荧光层后的底视图。
图4为本发明晶圆级芯片级CSP封装结构形成第二浓度荧光层后的横截面示意图。
图5为利用丝网类治具辅助形成第二浓度荧光层的俯视示意图。
图6为采用压膜方式完成第二浓度荧光层后的横截面示意图。
图7为采用模顶的方式形成第二浓度荧光层后的横截面示意图。
图8为COB封装技术的主要工艺流程图。
图9和图10为CSP芯片无法精确对准，贴装失败效果图。
图11为CSP芯片光色不均匀，产生黄边现象效果图。
图12为切割误差带来CSP侧面胶厚不一致的效果图。
图13为入Bin率测试数据图。
图14为常规CSP技术的结构示意图。
图15为本发明CSP技术的结构示意图。
图16为芯片贴装显微镜照片。
图17为常规CSP结构示意图及截面SEM图。
图18为本发明CSP结构示意图及截面SEM图。
图19为常规CSP出光效果图。
图20为本发明CSP出光效果图。
具体实施方式
下面的实施例可以使本专业的技术人员更全面地理解本发明，但并不因此将本发明限制在所述的实施例范围之中。
实施例1
本实施例晶圆级芯片级CSP封装结构，如图1所示，包括一芯片1以及设置于芯片1上的芯片电极4，在芯片1的出光面的顶面上设置有第一浓度荧光层2，形成封装体A；在封装体A的顶面和侧面还设有呈半透明或透明状的第二浓度荧光层3，形成封装体B；所述第一浓度荧光层2中的荧光粉浓度记作w 1，第二浓度荧光层3中的荧光粉浓度记作w 2，且w 1＞w 2；第一浓度荧光层2位于芯片1顶面的厚度一致，第二浓度荧光层3位于芯片1顶面的厚度一致，且封装体B呈矩形结构。
本实施例中，关于半透明或透明状的第二浓度荧光层3，是指在LED贴装设备下通过图像识别技术来对第二浓度荧光层(即裙边)以及其内芯片(即内核)的灰度对比来进行两者的识别、区分。图像识别技术为目前公知技术，这里不再对其工作原理进行赘述。
当|裙边灰度值-内核灰度值|≥30，LED贴装设备能够顺利识别区分内核与裙边的边界，即认为第二浓度荧光层3为透明或半透明；
当|裙边灰度值-内核灰度值|＜30，LED贴装设备无法顺利识别区分内核与裙边的边界，即认为第二浓度荧光层3为不透明；
当然，上述贴装设备能否顺利识别的基准是在批量化工业生产中，设备的识别准确率通常要达到99.5％，甚至更高。
比如说，在LED贴装设备下通过图像识别技术进行透明度识别，当浓度配比为荧光粉：硅胶：溶剂＝0.35：1：0.5，机台识别阈值，通过计算其灰度值二进制数可得内核灰度值为255，裙边灰度值为200时，机器内核识别成功率大于99.95％，当内核灰度值为255，裙边灰度值为225时，机器内核识别成功率为99.5％，第二浓度荧光层3为半透明层；当浓度配比为荧光粉：硅胶：溶剂＝0.6：1：0.5，机台识别阈值，通过计算其灰度值二进制数下内核灰度值为255，裙边灰度值为240时，机器内核识别成功率仅为15％，第二浓度荧光层3为不透明层。
本实施例中第一浓度荧光层2和第二浓度荧光层3的荧光层是由荧光胶体形成的，且第一浓度荧光层2中荧光粉质量占比为50～90％，第二浓度荧光层3中荧光粉质量占比为0～40％；第一浓度荧光层2的厚度≤150μm，第二浓度荧光层3的顶层厚度为10～1000μm，侧壁厚度为10～2000μm。本实施例中，芯片出光面的侧面中靠近顶面处还可以被少量第一浓度荧光层覆盖，芯片出光面的侧面＜10％面积被第一浓度荧光层覆盖。
本实施例晶圆级芯片级CSP封装结构是通过以下步骤制备而成的：
(1)晶圆片进行抽测；
(2)对步骤(1)抽测合格的晶圆片进行步骤2.1或步骤2.2，
步骤2.1具体为如图2所示，对步骤(1)抽测合格的晶圆片进行贴膜，并对贴膜后的晶圆片切割和裂片，裂片后，在整个晶圆片上喷涂荧光粉质量占比为50～90％的荧光胶，在晶圆内的芯片上直接形成第一喷涂荧光层5；
步骤2.2具体为如图2所示，在步骤(1)抽测合格的晶圆片上喷涂荧光粉质量占比为50～90％的荧光胶，在晶圆内的芯片上直接形成第一喷涂荧光层5，然后进行贴膜，并对贴膜后的晶圆片切割和裂片；
(3)对覆盖有第一喷涂荧光层5的晶圆片进行扩膜，扩膜前，第一喷涂荧光层5处于非固化状态，扩膜后，如图3所示，形成厚度≤150μm的第一浓度荧光层2，进而形成封装体A，且封装体A顶面的正投影轮廓与芯片1出光面的正投影轮廓的各边长对应边之间的误差＜30微米；
(4)对扩膜后的晶圆片烘烤固化，烘烤固化温度为30℃～200℃，烘烤固化时间为3～12h；
(5)烘烤固化后，对晶圆片内的芯片进行亮度、显指和色温光电参数测试，并根据测试结果分选重排；
(6)如图4所示，在分选重排的芯片上喷涂荧光粉质量占比为0～40％的荧光胶，形成顶层厚度为10～1000μm，侧壁厚度为10～2000μm，且呈半透明或透明状的第二浓度荧光层3，形成第二浓度荧光层3后，相邻芯片间距大于芯片尺寸1倍，并对覆盖有第二浓度荧光层3的芯片进行烘烤固化，烘烤固化温度为30℃～200℃，烘烤 固化时间为3～12h；
(7)烘烤固化后对芯片再次切割***，形成晶圆级芯片级封装结构；
(8)对步骤(7)形成的晶圆级芯片级封装结构，利用第一、二浓度荧光层的浓度差，使得可从封装结构外部观察到第一浓度荧光层，通过第一浓度荧光层位置对芯片进行固晶测试，测试分选后的合格产品包装入库。
实施例2
本实施例与实施例1相比，晶圆级芯片级CSP封装结构不变，且只改变晶圆级芯片级CSP封装结构制备步骤中的步骤(6)和步骤(7)，步骤(6)具体为：如图5所示，在涂布第二浓度荧光层3之前，将分选重排的芯片1放置丝网类治具6把芯片1均匀分割，然后再在再次分割的芯片1上喷涂荧光粉质量占比为0～40％的荧光胶，形成顶层厚度为10～1000μm，侧壁厚度为10～2000μm，且呈半透明或透明状的第二浓度荧光层3，形成第二浓度荧光层3后，相邻芯片间距大于芯片尺寸1倍，并对覆盖有第二浓度荧光层3的芯片进行烘烤固化，烘烤固化温度为30℃～200℃，烘烤固化时间为3～12h；步骤(7)具体为：烘烤固化后，形成晶圆级芯片级封装结构。
对于实施例1和实施例2中第二浓度荧光层3的形成，还可采用压膜或模顶的方式，压膜工艺为，如图6所示，将硅胶和荧光粉按比例混合，形成荧光粉质量占比为0～40％的荧光胶，然后将荧光胶倒入模具，烘烤固化得到荧光膜，再将荧光膜紧贴在分选重排的芯片1 表面并再次固化，从而形成第二浓度荧光层3；采用压膜工艺，第二浓度荧光层3形状可控，厚度均匀，稳定性高。
模顶工艺为，如图7所示，首先将模具7嵌套在分选重排的芯片1上，然后将荧光粉按比例混合硅胶，形成荧光粉质量占比为0～40％的荧光胶，注入模具7中，进行红烤固化，固化后除去模具7，形成坚固稳定的第二浓度荧光层3，再进行切割，即可得到单颗封装芯片。
通过实施例1和实施例2制备出的晶圆级芯片级CSP封装结构，第一浓度荧光层2所采用的荧光粉浓度较高，荧光粉质量占比一般为50～90％，所形成的荧光层单面、厚度薄、致密度高与发光芯片尺寸相近，有利于发光芯片散热，并降低胶体龟裂发生，提升LED芯片光效；第二浓度荧光层3所采用的荧光粉浓度较低，荧光粉质量占比一般为0～40％，形成的第二浓度荧光层3呈半透明甚至透明状，一方面有利于后期工艺流程中获得相邻发光芯片较大间距，降低切割分离覆盖荧光粉或荧光胶体的发光芯片的精度要求，从而提高器件的可靠性和均一性；另一方面半透明或透明状的第二浓度荧光层有利于通过第一次所形成的荧光层准确进行固晶、电极对准等后续工艺，降低工艺难度，进而降低器件制备成本。
以上显示和描述了本发明的基本原理和主要特征以及本发明的优点。本行业的技术人员应该了解，本发明不受上述实施例的限制，上述实施例和说明书中描述的只是说明本发明的原理，在不脱离本发明精神和范围的前提下，本发明还会有各种变化和改进，这些变化和改进都落入要求保护的本发明范围内。本发明要求保护范围由所附的 权利要求书及其等效物界定。

Claims (10)

  1. 一种晶圆级芯片级CSP封装结构，其特征在于：包括一矩形芯片，在所述芯片出光面上设置有第一浓度荧光层，形成封装体A，且所述芯片出光面的侧面＜10％面积被第一浓度荧光层覆盖；在所述封装体A的顶面和侧面还设有呈半透明或透明状的第二浓度荧光层，形成封装体B；所述第一浓度荧光层中的荧光粉浓度记作w 1，第二浓度荧光层中的荧光粉浓度记作w 2，且w 1＞w 2；所述第一浓度荧光层位于芯片顶面的厚度一致，所述第二浓度荧光层位于芯片顶面的厚度一致，且所述封装体B呈矩形结构。
  2. 根据权利要求1所述的晶圆级芯片级CSP封装结构，其特征在于：所述第一浓度荧光层和第二浓度荧光层的荧光层是由荧光粉或荧光胶体中的任一种形成的。
  3. 根据权利要求1或2所述的晶圆级芯片级CSP封装结构，其特征在于：所述第一浓度荧光层中荧光粉质量占比为50～90％，所述第二浓度荧光层中荧光粉质量占比为0～40％。
  4. 一种权利要求1所述的晶圆级芯片级CSP封装结构的制备方法，其特征在于：所述制备方法包括如下步骤：
    (1)晶圆片进行抽测；
    (2)对步骤(1)抽测合格的晶圆片进行步骤2.1或步骤2.2，
    所述步骤2.1具体为对步骤(1)抽测合格的晶圆片进行贴膜，并对贴膜后的晶圆片切割和裂片，裂片后在整个晶圆片上直接形成第一荧光层；
    所述步骤2.2具体为在步骤(1)抽测合格的晶圆片上直接形成第一荧光层，然后进行贴膜，并对贴膜后的晶圆片切割和裂片；
    (3)对覆盖有第一荧光层的晶圆片进行扩膜，形成第一浓度荧光层，进而形成封装体A，且所述封装体A顶面的正投影轮廓与芯片出光面的正投影轮廓的各边长对应边之间的误差＜30微米；
    (4)对扩膜后的晶圆片烘烤固化；
    (5)烘烤固化后，对晶圆片内的芯片测试分选重排；
    (6)在分选重排的芯片上形成呈半透明或透明状的第二浓度荧光层，并对覆盖有第二浓度荧光层的芯片进行烘烤固化；
    (7)在步骤(6)前或步骤(6)后对芯片再次分割，形成晶圆级芯片级封装结构；
    (8)对步骤(7)形成的晶圆级芯片级封装结构，利用第一、二浓度荧光层的浓度差，使得可从封装结构外部观察到第一浓度荧光层，通过第一浓度荧光层位置对芯片进行固晶测试，测试分选后的合格产品包装入库。
  5. 根据权利要求4所述的晶圆级芯片级CSP封装结构的制备方法，其特征在于：在步骤(3)晶圆片进行扩膜前，第一荧光层处于非固化状态。
  6. 根据权利要求4所述的晶圆级芯片级CSP封装结构的制备方法，其特征在于：所述第一浓度荧光层的厚度≤150μm，所述第二浓度荧光层的顶层厚度为10～1000μm，侧壁厚度为10～2000μm。
  7. 根据权利要求4所述的晶圆级芯片级CSP封装结构的制备方法，其特征在于：形成第二浓度荧光层后，相邻芯片间距大于芯片尺寸1倍。
  8. 根据权利要求4所述的晶圆级芯片级CSP封装结构的制备方法，其特征在于：所述步骤(7)在形成第二浓度荧光层之前，将分选重排的芯片放置丝网类治具把芯片均匀分割。
  9. 根据权利要求4所述的晶圆级芯片级CSP封装结构的制备方法，其特征在于：所述步骤(7)在烘烤固化后，对芯片再次分割。
  10. 根据权利要求4所述的晶圆级芯片级CSP封装结构的制备方法，其特征在于：所述步骤(7)中第二浓度荧光层是通过涂布、压膜或模顶的方式形成的。
PCT/CN2018/123064 2017-12-22 2018-12-24 一种晶圆级芯片级csp封装结构及其制备方法 WO2019120309A1 (zh)

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