WO2019119889A1 - 阵列基板及其制造方法、液晶显示面板及其制造方法 - Google Patents

阵列基板及其制造方法、液晶显示面板及其制造方法 Download PDF

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WO2019119889A1
WO2019119889A1 PCT/CN2018/105062 CN2018105062W WO2019119889A1 WO 2019119889 A1 WO2019119889 A1 WO 2019119889A1 CN 2018105062 W CN2018105062 W CN 2018105062W WO 2019119889 A1 WO2019119889 A1 WO 2019119889A1
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Prior art keywords
layer
metal
forming
substrate
array substrate
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PCT/CN2018/105062
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English (en)
French (fr)
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杨春辉
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/772,819 priority Critical patent/US11294218B2/en
Publication of WO2019119889A1 publication Critical patent/WO2019119889A1/zh

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    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78663Amorphous silicon transistors
    • H01L29/78669Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same, a liquid crystal display panel, and a method of fabricating the same.
  • the embodiment of the present application provides an array substrate, a method of manufacturing the same, a liquid crystal display panel, and a method of fabricating the same, which can effectively prevent the occurrence of light leakage on the data line side.
  • the present application provides an array substrate comprising: a substrate; a black light shielding layer disposed on the substrate; a first metal layer correspondingly disposed on the black light shielding layer, such that the black light shielding layer is located on the substrate and Between the first metal layers; an active material layer disposed on the first metal layer; a second metal layer disposed on the active material layer; and a protective layer disposed on the second metal layer And a contact hole is disposed thereon; a color resist material layer disposed on the protective layer; and a pixel electrode layer disposed on the color resist material layer and connected to the second metal layer through the contact hole.
  • the first metal layer includes: a gate of the active switching element and a shielding metal for forming a storage capacitor with the pixel electrode layer.
  • the active material layer includes: a gate insulating layer of the active switching element, a semiconductor layer, and an ohmic contact layer, the gate insulating layer, the semiconductor layer, and the ohmic layer
  • the contact layers are layered in sequence.
  • the second metal layer includes: a source of the active switching element, a drain of the active switching element connected to the pixel electrode layer, and a source connected to the source Data line.
  • the color resist material layer includes: a red color block, a green color block, and a blue color block;
  • the pixel electrode layer includes: the red color block, the green
  • the color block and the blue color block correspond to each other and are composed of a plurality of pixel electrodes made of a transparent conductive material.
  • the shielding metal surrounds the pixel electrode and overlaps the pixel electrode in parallel with both edge portions of the data line, and the shielding metal and the data line are perpendicular to the There is a gap in the direction of the data line.
  • the material of the black light shielding layer is a black photoresist containing carbon black.
  • the present application further provides a liquid crystal display panel comprising: the array substrate according to the foregoing embodiment; the opposite substrate disposed opposite to the array substrate; and the liquid crystal layer disposed on the array substrate and the opposite substrate Between the array substrate and the opposite substrate and surrounding the liquid crystal layer; wherein the opposite substrate comprises: a second substrate; a black matrix layer disposed at the second a side of the substrate facing the array substrate; and a common electrode layer disposed on a side of the black matrix layer facing the array substrate.
  • the material of the black light shielding layer is the same as the material of the black matrix layer.
  • the present application also provides a method for fabricating an array substrate, comprising the steps of: forming a black light shielding layer and a first metal layer on the substrate such that the black light shielding layer is located between the substrate and the first metal layer; Forming an active material layer on the first metal layer; forming a second metal layer on the active material layer; forming a protective layer on the second metal layer and forming a contact hole in the protective layer; Forming a color resist material layer on the protective layer; forming a pixel electrode layer on the color resist material layer; and connecting the pixel electrode layer to the second metal layer through the contact hole.
  • forming the black light shielding layer and forming the first metal layer are the same mask process.
  • a black light shielding layer and a first metal layer are formed on the substrate, such that the black light shielding layer is located between the substrate and the first metal layer, including: forming black on the substrate a light shielding material layer; forming a metal material layer on the black light shielding material layer; forming a photoresist material layer on the metal material layer; exposing and developing the photoresist material layer by using a photomask to obtain a patterned photoresist material a layer; sequentially performing wet etching and dry etching on the metal material layer and the black light shielding material layer using the patterned photoresist material layer as a mask; and removing residual photoresist material layer after the dry etching And obtaining the black light shielding layer and the first metal layer.
  • a black light shielding layer and a first metal layer are formed on the substrate, such that the black light shielding layer is located between the substrate and the first metal layer: on the black light shielding layer Forming a gate of the active switching element and a shielding metal for forming a storage capacitor with the pixel electrode layer; wherein the gate and the shielding metal are constituent parts of the first metal layer.
  • the forming the active material layer on the first metal layer comprises: sequentially forming a gate insulating layer, a semiconductor layer, and the active switching element on the first metal layer Ohmic contact layer.
  • forming the second metal layer on the active material layer includes: forming a source of the active switching element, and an active switching element on the active material layer a drain connected to the pixel electrode layer and a data line connected to the source; wherein the source, the drain and the data line are constituent parts of the second metal layer.
  • the forming the color resist material layer on the protective layer comprises: forming a red color block, a green color block, and a blue color block on the protective layer in a predetermined order.
  • forming the pixel electrode layer on the color resist layer includes: forming the red color block, the green color block, and the blue color resist on the color resist layer A plurality of pixel electrodes each corresponding to a block and made of a transparent conductive material.
  • the material of the black light shielding layer is a black photoresist containing carbon black.
  • the black light-shielding layer fabricated on the array substrate by the embodiment of the present application can prevent the design from being in the opposite direction on the basis of simplifying the manufacturing complexity and ensuring the product penetration rate.
  • the relative positional movement between the black matrix layer on the substrate and the data line causes the black matrix layer on the opposite substrate to block the light leakage caused by the light between the data line and the shielding metal.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
  • FIG. 2A is a schematic structural view of an array substrate along a section line A in FIG. 1;
  • 2B is a schematic structural view of the array substrate along the section line B in FIG. 1;
  • FIG. 3A is a schematic structural view of a liquid crystal display panel along a section line A in FIG. 1;
  • FIG. 3B is a schematic structural view of a liquid crystal display panel along a section line B in FIG. 1;
  • 4A to 4H are schematic diagrams showing a manufacturing process of a first metal layer and a black light shielding layer according to an embodiment of the present application.
  • an embodiment of the present application provides an array substrate 10 including a data line DL, a scan line GL, an active switching element T, a pixel electrode PE, and a shield metal SM.
  • the data line DL and the scanning line GL are, for example, crossed to form a plurality of regions, and one pixel electrode PE is disposed on each of the regions.
  • the active switching element T includes a source S, a drain D and a gate G.
  • the source S is electrically connected to the data line DL
  • the pixel electrode PE is electrically connected to the drain D through the contact hole CH
  • the gate G is electrically connected to the scan line GL. .
  • the shielding metal SM is disposed, for example, around the pixel electrode PE, and overlaps with the pixel electrode PE parallel to both edge portions of the data line DL (such as the left and right edges in FIG. 1) to form a storage capacitor with the pixel electrode PE, and shields the metal SM and the data line
  • the DL has a gap in a direction perpendicular to the data line DL (for example, a horizontal direction in FIG. 1).
  • the source S, the drain D, and the data line DL are, for example, located in the same layer structure, and the mask metal layer SM, the gate G, and the scan line GL are, for example, also located in the same layer structure; the data line DL and the scan line GL are, for example
  • the opaque conductive metal material is, for example, metal chrome or other opaque conductive metal material, which can be used as a light-shielding structure in combination with a black light-shielding material to achieve better light-shielding effect, so that light It is completely blocked when passing through the opaque conductive metal material.
  • the pixel electrode PE is made of, for example, a transparent conductive metal material, for example, an ITO (Indium Tin Oxide) thin film material, and the ITO film has high conductivity and high visible light transmission. Rate, high mechanical hardness and good chemical stability.
  • the number of pixel electrodes PE is, for example, a plurality.
  • the array substrate 10 further includes: a black opaque layer composed of a substrate GS1 and a black opaque block BM1, and an active material layer. AS, protective layer PV and a layer of color resist material comprising a plurality of color resist blocks CR.
  • the black light blocking block BM1 is disposed above the substrate GS1, and the shielding metal SM is located in the layer structure above the black light blocking block BM1, so that the black light blocking block BM1 is located between the substrate GS1 and the shielding metal SM, and the active material layer AS is located in the shielding metal SM and the data.
  • the protective layer PV is located in the layer structure between the data line DL and the color resist material layer
  • the pixel electrode PE is located in the layer structure above the color resist material layer.
  • the substrate GS1 is made of, for example, a light transmissive glass material.
  • a black light blocking block BM1 is disposed, for example, correspondingly under the shielding metal SM, and the black light blocking block BM1 is made of, for example, a black opaque insulating material such as a black photoresist containing carbon black, and the gate G
  • a black light blocking block BM1 see FIG.
  • a black light blocking block BM1 (not shown) is disposed under the scan line GL, and is disposed on the opposite substrate disposed corresponding to the array substrate 10.
  • the upper black matrix material is used to achieve a better shading effect, preventing the black matrix material on the opposite substrate from being unaligned between the opposite substrate and the array substrate 10 during the manufacturing process of the liquid crystal display panel. It can completely cover the part between the data line and the shielding metal and cause light leakage.
  • the color resist material layer including the color resist block CR of a plurality of colors includes, for example, a red color block CR, a green color block CR, and a blue color block CR, a red color block CR, and a green color block.
  • the CR and the blue color blocking block CR are disposed in one-to-one correspondence with the plurality of pixel electrodes PE.
  • one pixel electrode PE corresponds to one red color blocking block CR or one pixel electrode PE corresponds to one green color blocking block CR or one pixel electrode PE.
  • the active material layer AS shown in FIG. 2A includes not only the active switch when passing over the gate G of the active switching element T.
  • the gate insulating layer GI of the element T further includes a semiconductor layer SC of the active switching element T and an ohmic contact layer C.
  • the gate insulating layer GI, the semiconductor layer SC and the ohmic contact layer C are sequentially stacked, and the intermediate layer of the protective layer PV is disposed.
  • the semiconductor layer SC is made of, for example, an a-Si (amorphous silicon) material
  • the gate insulating layer GI and the protective layer PV are made of, for example, a silicon nitride material.
  • FIG. 3A a liquid crystal display panel 20 according to an embodiment of the present application is shown in FIG. 3A as a structural diagram of the liquid crystal display panel 20 along the line A in FIG.
  • FIG. 3A A schematic structural view of the liquid crystal display panel 20 along the section line B in FIG. 1 is shown.
  • the liquid crystal display panel 20 includes the array substrate 10 as described in any of the preceding embodiments, the opposite substrate disposed opposite the array substrate 10, and the frame glue SD disposed between the opposite substrate and the array substrate 10.
  • the opposite substrate including a substrate GS2, a black matrix block BM2 disposed on a side of the substrate GS2 facing the array substrate 10, and a setting The common electrode layer CE on the side of the array substrate 10 where the black matrix block BM2 faces.
  • the projection of the black matrix block BM2 on the array substrate 10 covers all areas except the pixel electrode PE on the array substrate 10 and the black light shielding layer 212 on the array substrate 10.
  • the black matrix block BM2 is made of, for example, a black opaque insulating material such as a black light-resistant insulating material containing carbon black, like the black light blocking block BM1.
  • the projection of the black matrix block BM2 on the substrate GS1 of the array substrate 10 covers, for example, the shield metal SM, the black light blocking block BM1, the data line DL, and a partial region covering the pixel electrode PE; as shown in FIG.
  • the SD is disposed, for example, around the liquid crystal layer LC, so that the liquid crystal molecules of the liquid crystal layer LC can be enclosed in a certain region; and the photo spacers PS are uniformly dispersed, for example, between the liquid crystal molecules of the liquid crystal layer LC, thereby supporting the upper and lower sides.
  • the substrate is maintained at a certain pitch; the common electrode layer CE may cooperate with the pixel electrode PE disposed on the array substrate 10 to form a desired electric field when a suitable voltage is applied to drive the liquid crystal layer LC disposed therebetween
  • the liquid crystal molecules are turned to realize display of a desired image;
  • the common electrode layer CE is made of, for example, a transparent conductive metal material, for example, made of an ITO film material.
  • the foregoing embodiment of the present application can solve the problem that the array substrate 10 can be disposed by providing a black light blocking block BM1 under the shielding metal SM, below the gate G, and below the scanning line GL on the basis of ensuring the product transmittance.
  • the upper side of the metal SM is even misaligned above the gap between the shield metal SM and the data line DL to cause light leakage on both sides of the data line DL, or the gate G caused by the misalignment of the black matrix block BM2 shown in FIG. 3B. And the light leakage phenomenon on the left and right sides of the scanning line GL (not shown in FIG. 3B).
  • the method includes the steps of: forming a black light blocking block BM1 on the substrate GS1 by using the same mask.
  • the material layer BM is formed on the black light-shielding material layer BM, for example, by PVD (physical vapor deposition, including evaporation and sputtering, etc.), as shown in FIG. 4B, so that the black light-shielding material layer BM is located on the substrate GS1.
  • PVD physical vapor deposition, including evaporation and sputtering, etc.
  • FIG. 4B shows that the black light-shielding material layer BM is located on the substrate GS1.
  • a photoresist material layer PR is formed on the metal material layer M1, and then the photoresist material layer PR is exposed and developed by using the photomask PM and the illumination L as shown in FIG. 4D.
  • the patterned photoresist material layer PR1 is obtained as shown in FIG.
  • the metal material layer M1 and the black light-shielding material layer BM are sequentially wetted by using the patterned photoresist material layer PR1 as a mask as shown in FIG. 4F and FIG. 4G.
  • the manufacturing method of the array substrate 10 further includes the steps of: the gate G of the active switching element T, the shielding metal SM, and the scanning line GL connected to the gate G.
  • the active material layer AS is formed on the layer structure. More specifically, the active material layer AS is formed by first performing a PECVD (plasma enhanced chemical vapor phase) on the layer structure of the gate G of the active switching element T, the shield metal SM, and the scan line GL connected to the gate G.
  • the deposition method forms a gate insulating layer GI; and the semiconductor layer SC and the ohmic contact layer C are formed by a PECVD method over the gate insulating layer GI over the gate G of the active switching element T.
  • the manufacturing method of the array substrate 10 further includes, for example, a step of forming a source S of the active switching element T in a layer structure above the active material layer AS, for example, by using a PVD method.
  • the manufacturing method of the array substrate 10 further includes the steps of: a source S of the active switching element T, a drain D of the active switching element T, and a source S.
  • the protective layer PV is formed in the layer structure above the data line DL, for example, by a PECVD method and the contact hole CH is formed in the protective layer PV.
  • the manufacturing method of the array substrate 10 further includes, for example, a step of forming a color resist block CR including a plurality of colors in a predetermined order in a layer structure above the protective layer PV.
  • a layer of color resist material is, for example, any one of a red color blocking block CR, a green color blocking block CR, and a blue color blocking block CR.
  • the predetermined order is, for example, forming all the red color blocking blocks CR first. All of the green color block CR is formed, and finally all of the blue color blocks CR) or other sequences are formed.
  • the manufacturing method of the array substrate 10 further includes, for example, a step of forming a color blocking block CR in the layer structure above the color resist material layer, for example, by a PVD method.
  • the pixel electrode PE is connected to the drain D of the active switching element T through the contact hole CH.
  • forming the shield metal SM on the substrate GS1 is, for example, forming a peripheral portion of the pixel electrode PE that is parallel to the pixel electrode PE and parallel to the data line DL to form a storage capacitor (such as the left and right edges in FIG. 1) and
  • the data line DL has a gapped shield metal SM in a direction perpendicular to the data line DL (in the horizontal direction as in FIG. 1).
  • a further embodiment of the present application provides a method of fabricating the liquid crystal display panel 20 according to any of the preceding embodiments, as shown in FIGS. 3A and 3B, including the steps of: employing the array according to any of the preceding embodiments.
  • the manufacturing method of the substrate 10 please refer to the description of the foregoing embodiment, and details are not described herein; the black matrix block BM2 and the common electrode layer CE are sequentially formed on the substrate GS2; A photo spacer PS and a sealant SD are formed between the common electrode layer CE and the array substrate 10 and injected into the liquid crystal layer LC to finally form the liquid crystal display panel 20.
  • the foregoing embodiment of the present application ensures that the photomask is not added by forming the black shading block BM1, the gate G of the active switching element T, the shielding metal SM, and the scanning line GL on the substrate GS1 by using the same photomask.
  • the fabrication of the black shading block BM1 is realized, and the gate G of the active switching element T, the shielding metal SM and the scanning line GL of the black shading block BM1 and the layer structure above it are eliminated.
  • the misalignment phenomenon which is easily caused by the misalignment causes the left or right boundary of the black matrix block BM2 as shown in FIG. 3A to be misaligned to the shielding metal.
  • the upper side of the SM is even misplaced above the gap between the shield metal SM and the data line DL to cause light leakage on both sides of the data line DL, or to cause the black matrix block B shown in FIG. 3B.
  • the misalignment of M2 results in light leakage on the left and right sides of the gate G and the scanning line GL (not shown in FIG. 3B).
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

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Abstract

一种阵列基板(10),包括:基底;黑色遮光层,设置在基底上;第一金属层,对应设置在黑色遮光层上,从而黑色遮光层位于基底和第一金属层之间;有源材料层,设置在第一金属层上;第二金属层,设置在有源材料层上;保护层,设置在第二金属层上且其上设置有接触孔;色阻材料层,设置在保护层上;以及像素电极层,设置在色阻材料层上且通过接触孔连接第二金属层。还提供了一种液晶显示面板(20)以及一种阵列基板(10)的制造方法。

Description

阵列基板及其制造方法、液晶显示面板及其制造方法 技术领域
本申请涉及显示技术领域,尤其涉及一种阵列基板及其制造方法和一种液晶显示面板及其制造方法。
背景技术
范例性的COT(color on TFT,TFT上滤色器)型LCD器件的实际生产制程中,特别是完成所有制程的阵列基板的与完成所有制程的对向基板对组在一起并切割成小片时,极易导致对向基板上的BM(Black Matrix,黑矩阵)与数据线两者之间相对位置的移动,当这种移动超出一定范围,例如BM的移动超过了SM(shielding metal,屏蔽金属)后就容易产生SM与数据线之间的漏光,会降低产品的良率。增大对向基板上的BM宽度固然能够起到作用,但是会降低产品的穿透率。
发明内容
因此,本申请实施例提供了一种阵列基板及其制造方法和一种液晶显示面板及其制造方法,能够有效地防止数据线侧的漏光现象的发生。
本申请提供了一种阵列基板,包括:基底;黑色遮光层,设置在所述基底上;第一金属层,对应设置在所述黑色遮光层上,从而所述黑色遮光层位于所述基底和所述第一金属层之间;有源材料层,设置在所述第一金属层上;第二金属层,设置在所述有源材料层上;保护层,设置在所述第二金属层上且其上设置有接触孔;色阻材料层,设置在所述保护层上;以 及像素电极层,设置在色阻材料层上且通过所述接触孔连接所述第二金属层。
在本申请的一个实施例中,所述第一金属层包括:主动开关元件的栅极和用于与所述像素电极层形成存储电容的屏蔽金属。
在本申请的一个实施例中,所述有源材料层包括:所述主动开关元件的栅极绝缘层、半导体层和欧姆接触层,所述栅极绝缘层、所述半导体层和所述欧姆接触层依序层叠设置。
在本申请的一个实施例中,所述第二金属层包括:所述主动开关元件的源极、所述主动开关元件的与所述像素电极层连接的漏极以及与所述源极连接的数据线。
在本申请的一个实施例中,所述色阻材料层包括:红色色阻块、绿色色阻块和蓝色色阻块;所述像素电极层包括:与所述红色色阻块、所述绿色色阻块和所述蓝色色阻块一一对应且由透明导电材料制成的多个像素电极。
在本申请的一个实施例中,所述屏蔽金属环绕所述像素电极并与所述像素电极平行于所述数据线的两边缘部分重叠,且所述屏蔽金属与所述数据线在垂直于所述数据线的方向上存在间隙。
在本申请的一个实施例中,所述黑色遮光层的材料为含碳黑的黑色光阻。
本申请还提供了一种液晶显示面板,包括:如前述实施例所述的阵列基板;对向基板,与所述阵列基板相对设置;液晶层,设置在所述阵列基板和 所述对向基板之间;框胶,设置在所述阵列基板和所述对向基板之间并环绕所述液晶层;其中,所述对向基板包括:第二基底;黑色矩阵层,设置在所述第二基底面向所述阵列基板的一侧;以及公共电极层,设置在所述黑色矩阵层面向所述阵列基板的一侧。
在本申请的一个实施例中,所述黑色遮光层的材料和所述黑色矩阵层的材料相同。
本申请还提供了一种阵列基板的制造方法,包括步骤:在基底上形成黑色遮光层和第一金属层,从而所述黑色遮光层位于所述基底与所述第一金属层之间;在所述第一金属层上形成有源材料层;在所述有源材料层上形成第二金属层;在所述第二金属层上形成保护层并在所述保护层中形成接触孔;在所述保护层上形成色阻材料层;在所述色阻材料层上形成像素电极层、并使所述像素电极层通过所述接触孔连接所述第二金属层。
在本申请的一个实施例中,形成所述黑色遮光层和形成所述第一金属层为共用同一道光罩制程。
在本申请的一个实施例中,在基底上形成黑色遮光层和第一金属层,从而所述黑色遮光层位于所述基底与所述第一金属层之间包括:在所述基底上形成黑色遮光材料层;在所述黑色遮光材料层上形成金属材料层;在所述金属材料层上形成光阻材料层;利用光罩对所述光阻材料层进行曝光显影以得到图案化光阻材料层;以所述图案化光阻材料层为掩膜对所述金属材料层和所述黑色遮光材料层依序进行湿蚀刻和干蚀刻;以及在所述干蚀刻后去除残余的光阻材料层,以得到所述黑色遮光层和第一金属层。
在本申请的一个实施例中,在基底上形成黑色遮光层和第一金属层,从而所述黑色遮光层位于所述基底与所述第一金属层之间包括:在所述黑色遮光层上形成主动开关元件的栅极和用于与所述像素电极层形成存储电容的屏蔽金属;其中所述栅极和所述屏蔽金属为所述第一金属层的构成部分。
在本申请的一个实施例中,所述在所述第一金属层上形成有源材料层包括:依次在所述第一金属层上形成所述主动开关元件的栅极绝缘层、半导体层和欧姆接触层。
在本申请的一个实施例中,在所述有源材料层上形成第二金属层包括:在所述有源材料层上形成所述主动开关元件的源极、所述主动开关元件的与所述像素电极层连接的漏极以及与所述源极连接的数据线;其中所述源极、所述漏极和所述数据线为所述第二金属层的构成部分。
在本申请的一个实施例中,所述在所述保护层上形成色阻材料层包括:在所述保护层上按照预设顺序形成红色色阻块、绿色色阻块和蓝色色阻块。
在本申请的一个实施例中,在所述色阻层上形成像素电极层包括:在所述色阻层上形成与所述红色色阻块、所述绿色色阻块和所述蓝色色阻块一一对应且由透明导电材料制成的多个像素电极。
在本申请的一个实施例中,所述黑色遮光层的材料为含碳黑的黑色光阻。
本申请可以具有如下优点:通过本申请实施例制造在阵列基板上的黑色遮光层,在尽量简化制造复杂度以及保证产品穿透率的基础上,可以很 好地起到防止由于设计在对向基板上的黑色矩阵层与数据线两者之间相对位置的移动使得对向基板上的黑色矩阵层无法遮挡在数据线与遮蔽金属之间的光线从而产生的漏光现象。
附图说明
为了更清楚地说明本申请实施例的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种阵列基板的结构示意图;
图2A为沿着图1中的剖面线A的阵列基板的结构示意图;
图2B为沿着图1中的剖面线B的阵列基板的结构示意图;
图3A为沿着图1中的剖面线A的液晶显示面板的结构示意图;
图3B为沿着图1中的剖面线B的液晶显示面板的结构示意图;
图4A至图4H为本申请实施例提供的一种第一金属层和黑色遮光层的制作过程示意图。
具体实施方式
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本申请护的范围。
如图1所示,本申请的一个实施例提供的一种阵列基板10,包括数据线DL、扫描线GL、主动开关元件T、像素电极PE和屏蔽金属SM。数据线DL和扫描线GL例如交叉设置以形成多个区域,在每一个所述区域上设置有一个像素电极PE。主动开关元件T包括源极S、漏极D和栅极G,源极S与数据线DL电气连接,像素电极PE通过接触孔CH与漏极D电气连接,栅极G与扫描线GL电气连接。屏蔽金属SM例如环绕像素电极PE设置,并与像素电极PE平行于数据线DL的两边缘部分(如图1中的左右边缘)重叠以与像素电极PE形成存储电容,且屏蔽金属SM与数据线DL在垂直于数据线DL的方向上(例如图1中的水平方向)存在间隙。更具体地,源极S、漏极D和数据线DL例如位于同一层结构中,遮蔽金属层SM、栅极G和扫描线GL例如也位于同一层结构中;数据线DL和扫描线GL例如由不透光导电金属材料制成,所述不透光导电金属材料例如为金属铬或其他不透光导电金属材料,其可以作为遮光结构配合黑色遮光材料使用达到更佳的遮光效果,使得光在通过所述不透光导电金属材料时被全部遮挡。像素电极PE例如为采用透明导电金属材料制成,所述透明导电金属材料例如为ITO(Indium Tin Oxide,铟锡氧化物)薄膜材质制成,ITO薄膜具有高的导电率、高的可见光透过率、高的机械硬度和良好的化学稳定性。像素电极PE例如为多个。
如图2A所示为沿着图1中的剖面线A的阵列基板10的结构示意图,可以看出,阵列基板10还包括:基底GS1、黑色遮光块BM1组成的黑色遮光层、有源材料层AS、保护层PV和包括多种颜色的色阻块CR的色阻 材料层。黑色遮光块BM1设置在基底GS1上方,屏蔽金属SM位于黑色遮光块BM1上方的层结构中,从而黑色遮光块BM1位于基底GS1和屏蔽金属SM之间,有源材料层AS位于屏蔽金属SM和数据线DL之间的层结构中,保护层PV位于数据线DL和所述色阻材料层之间的层结构中,像素电极PE位于所述色阻材料层上方的层结构中。基底GS1例如为透光玻璃材料制成。屏蔽金属SM的下方例如对应设置有黑色遮光块BM1,黑色遮光块BM1例如由黑色不透光绝缘材料制成,所述黑色不透光绝缘材料例如为含碳黑的黑色光阻,栅极G的下方也对应设置有黑色遮光块BM1(见图2B),扫描线GL的下方也对应设置有黑色遮光块BM1(图中未示出),配合设置在与阵列基板10对应设置的对向基板上的黑色矩阵材料以实现更好的遮光效果,防止因在液晶显示面板的制造过程中由于对向基板与阵列基板10之间未能很好的对齐导致的对向基板上的黑色矩阵材料未能完全覆盖到数据线和屏蔽金属之间的部分从而导致的漏光现象的发生。更具体地,所述包括多种颜色的色阻块CR的色阻材料层例如包括红色色阻块CR、绿色色阻块CR和蓝色色阻块CR,红色色阻块CR、绿色色阻块CR和蓝色色阻块CR与所述多个像素电极PE一一对应设置,例如一个像素电极PE对应一个红色色阻块CR或一个像素电极PE对应一个绿色色阻块CR或一个像素电极PE对应一个蓝色色阻块CR;图2A示出的有源材料层AS在经过屏蔽金属SM的上方时例如只包括主动开关元件T的栅极绝缘层GI
如图2B所示为沿着图1中的剖面线B的阵列基板的结构示意图,可见,图2A示出的有源材料层AS在经过主动开关元件T的栅极G上方时不仅包 括主动开关元件T的栅极绝缘层GI,还包括主动开关元件T的半导体层SC和欧姆接触层C,栅极绝缘层GI、半导体层SC和欧姆接触层C依序层叠设置,保护层PV的中间设置有接触孔CH,像素电极PE通过接触孔CH与漏极D电气连接。更具体地,图2B示出的源极S和漏极D例如和图2A中示出的数据线DL位于同一层结构中,遮蔽金属层SM、栅极G和扫描线GL(图2A和图2B中未示出)例如也位于同一层结构中;半导体层SC例如采用a-Si(非晶硅)材料制成,栅极绝缘层GI和保护层PV例如采用氮化硅材料制成。
如图3A和图3B所示,本申请的一个实施例提供的一种液晶显示面板20,如图3A所示为沿着图1中剖面线A的液晶显示面板20的结构示意图,如图3B所示为沿着图1中剖面线B的液晶显示面板20的结构示意图。可见,液晶显示面板20包括:如前述任一实施例所述的阵列基板10、与阵列基板10相对设置的对向基板以及设置在所述对向基板和阵列基板10之间的:框胶SD、感光间隔物PS以及被框胶SD包围的由多个液晶分子形成的液晶层LC,所述对向基板包括基底GS2、设置在基底GS2面向阵列基板10的一侧的黑色矩阵块BM2以及设置在黑色矩阵块BM2面向阵列基板10的一侧的公共电极层CE。阵列基板10的具体功能和结构细节请参考前述实施例的描述,在此不再赘述。更具体地,黑色矩阵块BM2在阵列基板10上的投影覆盖阵列基板10上的像素电极PE之外的所有区域和阵列基板10上的黑色遮光层212。更具体地,黑色矩阵块BM2例如和黑色遮光块BM1一样是由黑色不透光绝缘材料制成,所述黑色不透光绝缘材料例如为含碳 黑的黑色光阻。如图3A所示,黑色矩阵块BM2在阵列基板10的基底GS1上的投影例如完全覆盖屏蔽金属SM、黑色遮光块BM1、数据线DL以及覆盖像素电极PE的部分区域;如图3B所示,黑色矩阵块BM2在阵列基板10的基底GS1上的投影例如还完全覆盖主动开关元件T的各个组成部分:栅极G、半导体层SC、欧姆接触层C、源极S和漏极D;框胶SD例如是环绕液晶层LC设置,如此可以使液晶层LC的液晶分子封闭在一定区域内;感光间隔物PS例如均匀分散设置在液晶层LC的所述液晶分子之间,从而可以支撑上下两个基板,使之保持一定的间距;公共电极层CE可以与设置在阵列基板10上的像素电极PE配合在施加合适的电压时共同形成需要的电场来驱动布置在两者之间的液晶层LC中的液晶分子转向,从而实现所需图像的显示;公共电极层CE例如采用透明导电金属材料制成,例如由ITO薄膜材质制成。
综上所述,本申请前述实施例在保证产品穿透率的基础上,通过在屏蔽金属SM的下方、栅极G的下方以及扫描线GL的下方设置黑色遮光块BM1可以解决当阵列基板10和所述对向基板对组制成液晶显示面板20的时候极易产生的因无法对齐而导致的错位现象,例如导致如图3A所示的黑色矩阵块BM2的左边界或者右边界错位至屏蔽金属SM的上方甚至错位至屏蔽金属SM和数据线DL之间的间隙上方从而导致数据线DL两侧的漏光现象的发生,或者导致图3B所示的黑色矩阵块BM2的错位导致的栅极G和扫描线GL(图3B中未示出)左右两侧的漏光现象。
本申请的另一实施例提供了如前述实施例所述的阵列基板10的一种制 造方法,如图2A和2B所示,包括步骤:利用同一道光罩在基底GS1上形成黑色遮光块BM1、主动开关元件T的栅极G、屏蔽金属SM和与栅极G连接的扫描线GL。更具体地,利用同一道光罩在基底GS1上形成黑色遮光块BM1、主动开关元件T的栅极G、屏蔽金属SM和扫描线GL包括步骤:如图4A所示先在基底GS1上形成黑色遮光材料层BM,如图4B所示其次在黑色遮光材料层BM上例如通过PVD(物理汽相沉积,包括蒸镀和溅镀等)方法形成金属材料层M1,从而黑色遮光材料层BM位于基底GS1和金属材料层M1之间,如图4C所示然后在金属材料层M1上形成光阻材料层PR,如图4D所示之后利用光罩PM和光照L对光阻材料层PR进行曝光显影以得到如图4E所示的图案化光阻材料层PR1,如图4F和图4G所示再以图案化光阻材料层PR1为掩膜对金属材料层M1和黑色遮光材料层BM依序进行湿蚀刻和干蚀刻,以及如图4H所示在所述干蚀刻后去除残余的光阻材料层PR1以得到黑色遮光块BM1、主动开关元件T的栅极G、屏蔽金属SM和与栅极G连接的扫描线GL(图中未示出)。
进一步地,如图2A和2B所示,所述的阵列基板10的制造方法,例如还包括步骤:在主动开关元件T的栅极G、屏蔽金属SM和与栅极G连接的扫描线GL所在的层结构上形成有源材料层AS。更具体地,形成有源材料层AS为:先在主动开关元件T的栅极G、屏蔽金属SM和与栅极G连接的扫描线GL所在的层结构上例如通过PECVD(等离子增强化学汽相淀积)方法形成栅极绝缘层GI;再在位于主动开关元件T的栅极G的上方的栅极绝缘层GI上方通过PECVD方法形成半导体层SC和欧姆接触层C。
进一步地,如图2A和2B所示,所述的阵列基板10的制造方法,例如还包括步骤:在有源材料层AS上方的层结构中例如利用PVD方法形成主动开关元件T的源极S、主动开关元件T的漏极D以及与源极S连接的数据线DL。
进一步地,如图2A和2B所示,所述的阵列基板10的制造方法,例如还包括步骤:在主动开关元件T的源极S、主动开关元件T的漏极D以及与源极S连接的数据线DL上方的层结构中例如通过PECVD方法形成保护层PV并在保护层PV中形成接触孔CH。
进一步地,如图2A和2B所示,所述的阵列基板10的制造方法,例如还包括步骤:在保护层PV上方的层结构中按照预设顺序形成包括多种颜色的色阻块CR的色阻材料层。更具体地,色阻块CR例如为红色色阻块CR、绿色色阻块CR和蓝色色阻块CR中的任意一种,所述预设顺序例如为先形成所有的红色色阻块CR,再形成所有的绿色色阻块CR,最后形成所有的蓝色色阻块CR)或者其他的顺序。
进一步地,如图2A和2B所示,所述的阵列基板10的制造方法,例如还包括步骤:在所述色阻材料层上方的层结构中例如通过PVD方法形成与色阻块CR一一对应设置的多个像素电极PE,并使像素电极PE通过接触孔CH连接主动开关元件T的漏极D。
更具体地,在基底GS1上形成屏蔽金属SM例如为:形成环绕像素电极PE并与像素电极PE平行于数据线DL的两边缘部分重叠从而形成存储电容(如图1中左右两边缘)且与数据线DL在垂直于数据线DL的方向上 (如图1中的水平方向上)存在间隙的屏蔽金属SM。
本申请的再一实施例提供了如前述任一实施例所述的液晶显示面板20的一种制造方法,如图3A和3B所示,包括步骤:采用如前述任一实施例所述的阵列基板10的制造方法制造的阵列基板10,阵列基板10的制造方法的具体步骤请参考前述实施例的描述,在此不再赘述;在基底GS2上依次形成黑色矩阵块BM2和公共电极层CE;在公共电极层CE和阵列基板10之间形成感光间隔物PS和框胶SD并注入液晶层LC,最终形成液晶显示面板20。
综上所述,本申请前述实施例通过利用同一道光罩在基底GS1上形成黑色遮光块BM1、主动开关元件T的栅极G、屏蔽金属SM和扫描线GL的方法,在保证不增加光罩简化制作复杂度的前提下,实现了黑色遮光块BM1的制作,并免去了黑色遮光块BM1和位于其上方的层结构中的主动开关元件T的栅极G、屏蔽金属SM和扫描线GL之间的对齐过程;同时,在保证产品穿透率的基础上,最终通过在屏蔽金属SM的下方、栅极G的下方以及扫描线GL的下方设置黑色遮光块BM1可以解决当阵列基板10和所述对向基板对组制成液晶显示面板20的时候极易产生的因无法对齐而导致的错位现象,例如导致如图3A所示的黑色矩阵块BM2的左边界或者右边界错位至屏蔽金属SM的上方甚至错位至屏蔽金属SM和数据线DL之间的间隙上方从而导致数据线DL两侧的漏光现象的发生,或者导致图3B所示的黑色矩阵块BM2的错位导致的栅极G和扫描线GL(图3B中未示出)左右两侧的漏光现象。
在本申请所提供的几个实施例中,应所述理解到,所揭露的***,装置和方法,可以通过其它的方式实现。例如,以上所描述的装置实施例仅仅是示意性的,例如,所述单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,例如多路单元或组件可以结合或者可以集成到另一个***,或一些特征可以忽略,或不执行。另一点,所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口,装置或单元的间接耦合或通信连接,可以是电性,机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的,作为单元显示的部件可以是或者也可以不是物理单元,即可以位于一个地方,或者也可以分布到多路网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外,在本申请各个实施例中的各功能单元可以集成在一个处理单元中,也可以是各个单元单独物理存在,也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现,也可以采用硬件加软件功能单元的形式实现。
最后应说明的是:以上实施例仅用以说明本申请的技术方案,而非对其限制;尽管参照前述实施例对本申请进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和 范围。

Claims (20)

  1. 一种阵列基板,其中,包括:
    基底;
    黑色遮光层,设置在所述基底上;
    第一金属层,对应设置在所述黑色遮光层上,从而所述黑色遮光层位于所述基底和所述第一金属层之间;
    有源材料层,设置在所述第一金属层上;
    第二金属层,设置在所述有源材料层上;
    保护层,设置在所述第二金属层上且其上设置有接触孔;
    色阻材料层,设置在所述保护层上;以及
    像素电极层,设置在色阻材料层上且通过所述接触孔连接所述第二金属层;
    所述第一金属层包括:主动开关元件的栅极和用于与所述像素电极层形成存储电容的屏蔽金属;
    所述有源材料层包括:所述主动开关元件的栅极绝缘层、半导体层和欧姆接触层,所述栅极绝缘层、所述半导体层和所述欧姆接触层依序层叠设置;
    所述第二金属层包括:所述主动开关元件的源极、所述主动开关元件的与所述像素电极层连接的漏极以及与所述源极连接的数据线;
    所述色阻材料层包括:红色色阻块、绿色色阻块和蓝色色阻块;所述像素电极层包括:与所述红色色阻块、所述绿色色阻块和所述蓝色色阻块一一对应且由透明导电材料制成的多个像素电极。
  2. 如权利要求1所述的阵列基板,其中,所述屏蔽金属环绕所述像素电极并与所述像素电极平行于所述数据线的两边缘部分重叠,且所述屏蔽金属与所述数据线在垂直于所述数据线的方向上存在间隙。
  3. 如权利要求1所述的阵列基板,其中,所述黑色遮光层的材料为含碳黑的黑色光阻。
  4. 一种液晶显示面板,其中,包括:
    阵列基板;
    对向基板,与所述阵列基板相对设置;
    液晶层,设置在所述阵列基板和所述对向基板之间;
    框胶,设置在所述阵列基板和所述对向基板之间并环绕所述液晶层;
    其中,所述对向基板包括:
    第二基底;
    黑色矩阵层,设置在所述第二基底面向所述阵列基板的一侧;以及
    公共电极层,设置在所述黑色矩阵层面向所述阵列基板的一侧;
    所述阵列基板包括:
    基底;
    黑色遮光层,设置在所述基底上;
    第一金属层,对应设置在所述黑色遮光层上,从而所述黑色遮光层位于所述基底和所述第一金属层之间;
    有源材料层,设置在所述第一金属层上;
    第二金属层,设置在所述有源材料层上;
    保护层,设置在所述第二金属层上且其上设置有接触孔;
    色阻材料层,设置在所述保护层上;以及
    像素电极层,设置在色阻材料层上且通过所述接触孔连接所述第二金属层。
  5. 如权利要求4所述的液晶显示面板,其中,所述第一金属层包括:主动开关元件的栅极和用于与所述像素电极层形成存储电容的屏蔽金属。
  6. 如权利要求5所述的液晶显示面板,其中,所述有源材料层包括:所述主动开关元件的栅极绝缘层、半导体层和欧姆接触层,所述栅极绝缘层、所述半导体层和所述欧姆接触层依序层叠设置。
  7. 如权利要求6所述的液晶显示面板,其中,所述第二金属层包括:所述主动开关元件的源极、所述主动开关元件的与所述像素电极层连接的漏极以及与所述源极连接的数据线。
  8. 如权利要求7所述的液晶显示面板,其中,所述色阻材料层包括:红色色阻块、绿色色阻块和蓝色色阻块;所述像素电极层包括:与所述红色色阻块、所述绿色色阻块和所述蓝色色阻块一一对应且由透明导电材料制成的多个像素电极。
  9. 如权利要求8所述的液晶显示面板,其中,所述屏蔽金属环绕所述像素电极并与所述像素电极平行于所述数据线的两边缘部分重叠,且所述屏蔽金属与所述数据线在垂直于所述数据线的方向上存在间隙。
  10. 如权利要求4所述的液晶显示面板,其中,所述黑色遮光层的材料为含碳黑的黑色光阻。
  11. 如权利要求4所述的液晶显示面板,其中,所述黑色遮光层的材料和所述黑色矩阵层的材料相同。
  12. 一种阵列基板的制造方法,其中,包括步骤:
    在基底上形成黑色遮光层和第一金属层,从而所述黑色遮光层位于所述基底与所述第一金属层之间;
    在所述第一金属层上形成有源材料层;
    在所述有源材料层上形成第二金属层;
    在所述第二金属层上形成保护层并在所述保护层中形成接触孔;
    在所述保护层上形成色阻材料层;
    在所述色阻材料层上形成像素电极层、并使所述像素电极层通过所述接触孔连接所述第二金属层。
  13. 如权利要求12所述的阵列基板的制造方法,其中,形成所述黑色遮光层和形成所述第一金属层为共用同一道光罩制程。
  14. 如权利要求12所述的阵列基板的制造方法,其中,在基底上形成黑色遮光层和第一金属层,从而所述黑色遮光层位于所述基底与所述第一金属层之间包括:
    在所述基底上形成黑色遮光材料层;
    在所述黑色遮光材料层上形成金属材料层;
    在所述金属材料层上形成光阻材料层;
    利用光罩对所述光阻材料层进行曝光显影以得到图案化光阻材料层;
    以所述图案化光阻材料层为掩膜对所述金属材料层和所述黑色遮光材 料层依序进行湿蚀刻和干蚀刻;以及
    在所述干蚀刻后去除残余的光阻材料层,以得到所述黑色遮光层和第一金属层。
  15. 如权利要求14所述的阵列基板的制造方法,其中,在基底上形成黑色遮光层和第一金属层,从而所述黑色遮光层位于所述基底与所述第一金属层之间包括:在所述黑色遮光层上形成主动开关元件的栅极和用于与所述像素电极层形成存储电容的屏蔽金属;其中所述栅极和所述屏蔽金属为所述第一金属层的构成部分。
  16. 如权利要求15所述的阵列基板的制造方法,其中,所述在所述第一金属层上形成有源材料层包括:依次在所述第一金属层上形成所述主动开关元件的栅极绝缘层、半导体层和欧姆接触层。
  17. 如权利要求16所述的阵列基板的制造方法,其中,在所述有源材料层上形成第二金属层包括:在所述有源材料层上形成所述主动开关元件的源极、所述主动开关元件的与所述像素电极层连接的漏极以及与所述源极连接的数据线;其中所述源极、所述漏极和所述数据线为所述第二金属层的构成部分。
  18. 如权利要求17所述的阵列基板的制造方法,其中,所述在所述保护层上形成色阻材料层包括:在所述保护层上按照预设顺序形成红色色阻块、绿色色阻块和蓝色色阻块。
  19. 如权利要求18所述的阵列基板的制造方法,其中,在所述色阻层上形成像素电极层包括:在所述色阻层上形成与所述红色色阻块、所述绿色色 阻块和所述蓝色色阻块一一对应且由透明导电材料制成的多个像素电极。
  20. 如权利要求12所述的阵列基板的制造方法,其中,所述黑色遮光层的材料为含碳黑的黑色光阻。
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