WO2019112582A1 - A heat dissipation structure for an integrated circuit package - Google Patents

A heat dissipation structure for an integrated circuit package Download PDF

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Publication number
WO2019112582A1
WO2019112582A1 PCT/US2017/065062 US2017065062W WO2019112582A1 WO 2019112582 A1 WO2019112582 A1 WO 2019112582A1 US 2017065062 W US2017065062 W US 2017065062W WO 2019112582 A1 WO2019112582 A1 WO 2019112582A1
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WO
WIPO (PCT)
Prior art keywords
integrated circuit
circuit device
heat dissipation
dam structure
electronic substrate
Prior art date
Application number
PCT/US2017/065062
Other languages
French (fr)
Inventor
Ameya Limaye
Divya MANI
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/065062 priority Critical patent/WO2019112582A1/en
Publication of WO2019112582A1 publication Critical patent/WO2019112582A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • Embodiments of the present description generally relate to the field of heat dissipation from an integrated circuit device, and, more specifically, to a heat dissipation structure that includes a dam structure for improving heat removal from the integrated circuit device.
  • the integrated circuit industry is continually striving to produce ever faster and smaller integrated circuit devices for use in various server and mobile electronic products.
  • heat dissipation devices are used to remove heat from the integrated circuit devices in an integrated circuit package.
  • at least one integrated circuit device may be mounted to an electronic substrate and the heat dissipation device may be attached to the electronic substrate and extend over the integrated circuit device(s) to form the integrated circuit package.
  • the distance between the integrated circuit device(s) and the heat dissipation device is known as the bondline thickness, and a thermal interface material is generally disposed between the integrated circuit device(s) and the heat dissipation device to form thermal contact therebetween.
  • heat dissipation devices One issue with such heat dissipation devices is warpage in the integrated circuit package when it heats and cools during operation.
  • the shape of the integrated circuit device changes from convex to flat or concave, which causes compression on the thermal interface material at edges or sidewalls of the integrated circuit device.
  • the integrated circuit package returns to room temperature, the integrated circuit device returns to a convex shape creating an elongation of the thermal interface material at the edge or sidewalls of the integrated circuit device.
  • the mechanisms of compression and elongation may cause the thermal interface material to“pump-out” from between the heat dissipation device and the integrated circuit device.
  • This thermal interface material pump-out may result in the formation of an air-gap, also known as an air insulation layer, between the integrated circuit device and the heat dissipation device, which increases thermal resistance
  • thermal interface material pump-out may be a particular problem at the edges and comers of the integrated circuit device, because peak power density, and thus the highest heat generation, has moved to the integrated circuit device edges and comers.
  • FIG. 1 illustrates a side cross-sectional view of an integrated circuit package, according to an embodiment of the present disclosure.
  • FIG. 2 illustrate top plan views along line A-A of FIG. 1 showing a dam structure configuration with an integrated circuit device of the integrated circuit package, according to one embodiment of the present description.
  • FIGs. 3-6 illustrate side cross-sectional views of a method of fabricating the integrated circuit package of FIG. 1, according to one embodiment of the present disclosure.
  • FIG. 7 is a flow chart of a process of fabricating an integrated circuit package, according to an embodiment of the present description.
  • FIG. 8 illustrates an electronic system, according to one embodiment of the present description. DETAILED DESCRIPTION
  • the terms“over”,“to”,“between” and“on” as used herein may refer to a relative position of one layer with respect to other layers.
  • One layer“over” or“on” another layer or bonded“to” another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • One layer“between” layers may be directly in contact with the layers or may have one or more intervening layers.
  • Embodiment of the present description relate to an integrated circuit structure having a dam structure to contain a thermal interface material between a back surface of an integrated circuit device and a heat dissipation device.
  • the use of the dam structure may significantly reduce pump-out of the thermal interface material during assembly and/or operation, and, thus, may prevent the formation of air-gaps, which can increase thermal resistance.
  • an integrated circuit package 100 may be formed by first providing or forming an electronic substrate 110, such as an interposer, a printed circuit board, a motherboard, or the like.
  • At least one integrated circuit device 130 such as a microprocessor, a multichip package, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit device, and the like, may be attached to a first surface 112 of the electronic substrate 110 with a plurality of
  • interconnects 120 may extend between bond pads 122 formed in or on an active surface 132 of the integrated circuit device 130, and substantially mirror-image bond pads 124 in or on the electronic substrate first surface 112.
  • the integrated circuit device bond pads 122 may be in electrical communication with integrated circuitry (not shown) within the integrated circuit device 130.
  • An underfill material 116 such as an epoxy material, may be disposed between the integrated circuit device active surface 132 and the electronic substrate first surface 112, and surrounding the plurality of interconnects 120.
  • the underfill material 116 may be dispensed between the integrated circuit device active surface 132 and the electronic substrate first surface 112 as a viscous liquid and then hardened with a curing process.
  • the underfill material 116 may also be a molded underfill material.
  • the underfill material 116 may provide structural integrity and may prevent contamination, as will be understood to those skilled in the art.
  • the electronic substrate 110 may comprise any appropriate dielectric material, including, but not limited to, liquid crystal polymer, epoxy resin, bismaleimide triazine resin, FR4, polyimide materials, and the like, and may include conductive routes (illustrated as dashed lines 118) formed therein and/or thereon to form any desired electrical route within the electronic substrate 110, including, but not limited to, conductive routes 118 between the bond pads 124 in or on the electronic substrate first surface 112 and
  • external interconnects such as solder balls 128, may be formed on the electronic substrate second surface bond pads 126 for attaching the microelectronic package 100 to external components (such as a board, as will described with regard to FIG. 8).
  • a heat dissipation device 140 may be attached to the electronic substrate 110.
  • the heat dissipation device 140 may include a planar portion 142 having a first surface 144 and an opposing second surface 146, and may have at least one projection 152 extending from the planar portion first surface 144.
  • the heat dissipation device projection(s) 152 may be attached to the electronic substrate first surface 112 such that the planar portion second surface 146 spans, but does not necessarily directly contact a back surface 134 (opposing the integrated circuit device active surface 132) of the integrated circuit device 130, and a thermal interface material 160 may be disposed between the planar portion first surface 144 of the heat dissipation device 140 and the back surface 134 of the integrated circuit device 130.
  • the heat dissipation device projection(s) 152 may be attached to the electronic substrate 110 by any appropriate means, including but not limited to a sealant material 156, such as an epoxy, disposed between an attachment surface 154 of the heat dissipation device projection(s) 152 and the electronic substrate first surface 112.
  • the heat dissipation device projection(s) 152 extend substantially perpendicular to the planar portion first surface 144 of the heat dissipation device 140. It is understood that the term substantially perpendicular includes the heat dissipation device projection(s) 152 being plus or minus 5 degrees from 90 degrees.
  • the heat dissipation device 140 may be formed from any appropriate thermally conductive material, including, but not limited to copper, aluminum, and the like.
  • the heat dissipation device 140 may be formed from a molding or a stamping process, such that the heat dissipation device 140 is a single continuous material.
  • the planar portion 142 of the heat dissipation device 140 may be formed separately from the projection(s) 152 of heat dissipation device 140 and attached together.
  • the integrated circuit package 100 may further include a dam structure 170.
  • the dam structure 170 may contact the first surface 144 of the planar portion 142 of the heat dissipation device 140, at least one sidewall 136 extending between the active surface 132 and the back surface 134 of the integrated circuit device 130, and the first surface 112 of the electronic substrate 110.
  • the dam structure 170 may comprise a main body portion 172 and at least one projection portion 174 that may have a width Wl (see FIG. 2) that is less than a width W2 (see FIG. 2) of the main body portion 172. As further shown in FIG.
  • the at least one projection portion 174 may extend a distance D from the back surface 134 of the integrated circuit device 130 to the first surface 144 of the planar portion 142 of the heat dissipation device 140, such that the at least one projection portion distance D defines a bond line thickness BLT between the back surface 134 of the integrated circuit device 130 and the first surface 144 of the planar portion 142 of the heat dissipation device 140.
  • FIG. 2 illustrates top plan views of one embodiment of the dam structure 170 and the integrated circuit device 130 (without the thermal interface material 160 or the electronic substrate 110 being illustrated for clarity purposes) along line A-A of FIG. 1.
  • the dam structure 170 may completely surround the integrated circuit device 130, such that (referring back to FIG. 1) the thermal interface material 160 may contained between the first surface 144 of the planar portion 142 of the heat dissipation device 140, the back surface 134 of the integrated circuit device 130, and the at least one projection portion 174 of the dam structure 170.
  • the embodiment of FIG. 2 is merely a single example and that the dam structure 170 could have any appropriate shape or configuration.
  • the dam structure 170 may be made by any known technique, and may be any appropriate material, including, but not limited to polymers (such as epoxy materials and silicone-based materials, e.g. polydimethylsiloxane), polymer-metal composites (such as epoxy with metal particles like silver or silver-coated copper particles), polymer-ceramic composites (such as epoxy with ceramic particles like silicon oxide or aluminum oxide), and as well as any combination of the above materials.
  • polymers such as epoxy materials and silicone-based materials, e.g. polydimethylsiloxane
  • polymer-metal composites such as epoxy with metal particles like silver or silver-coated copper particles
  • polymer-ceramic composites such as epoxy with ceramic particles like silicon oxide or aluminum oxide
  • the thermal interface material 160 may be any appropriate material, including, but not limited to polymer-metal composites (such as epoxy with metal particles like silver or silver-coated copper particles and polydimethylsiloxane with metal particles like silver or silver-coated copper particles), polymer-ceramic composites (such as epoxy or
  • the thermal interface material 160 may be a nanographene platelet thermal interface material.
  • FIGs. 1 and 2 illustrate a single integrated circuit device 130, it is understood that a plurality of integrated circuit devices 130 may be disposed between the heat dissipation device 140 and the electronic substrate 110. The plurality of integrated circuit devices 130 may each be thermally connected to the heat dissipation device 140.
  • FIGs. 3-6 illustrate side cross sectional views of a method of fabricating the integrated circuit package 100 of FIG. 1.
  • a mold 180 may be formed of a substantially rigid material and may include recess 182 formed therein.
  • the recess 182 may comprise an electronic substrate recess 186 that extends into the mold 180 from a first surface 184 thereof, an integrated circuit device recess 190 that extends into the mold 180 from a bohom surface 188 of the electronic substrate recess 186, and at least one projection recess 192 that extends into the mold 180 from a bohom surface 190 of the integrated circuit device recess 188. It is understood that a depth Dp that the at least one projection recess 192 extends into the mold 180 will be substantially the same as the distance D of FIG. 1.
  • the at least one integrated circuit device 130 may be attached to the electronic substrate 110 and inserted into the mold 180, such that the electronic substrate 110 resides within the electronic substrate recess 184, wherein the first surface 112 of the electronic substrate 110 abuts the bohom surface 186 of the electronic substrate recess 184, and such that the at least one integrated circuit device 130 resides within the integrated circuit device recess 188, wherein the back surface 134 of the at least one integrated circuit device 130 abuts the bottom surface 190 of the integrated circuit device recess 188.
  • a mold material shown as arrows 196 may be injected into the mold 180 to fill the integrated circuit device recess 188 not occupied by the integrated circuit device 130 and components associated therewith, such as the plurality of
  • inlet and outlet ports for injecting the mold material 196 are not illustrated for brevity and clarity, as such ports are well known and understood in the art.
  • the mold material 196 may be at least partially cured and, as shown in FIG. 6 the at least one integrated circuit device 130, the electronic substrate 110, and dam structure 170 may be removed from the mold 180 (see FIG. 5).
  • the heat dissipation device 140 may then be attached to the electronic substrate 110, such that the dam structure 170 contacts the first surface 144 of the planar portion 142 of the heat dissipation device 140, and the thermal interface material 160 may be disposed between the planar portion first surface 144 of the heat dissipation device 140 and the back surface 134 of the integrated circuit device 130, as shown in FIG. 1.
  • FIG. 7 is a flow chart of a process 200 of fabricating an integrated circuit package according to the various embodiments of the present description.
  • an electronic substrate having a first surface may be formed.
  • At least one integrated circuit device having an active surface, a back surface, and at least one sidewall extending between the active surface and the back surface may be formed, as set forth in block 204.
  • the active surface of the at least one integrated circuit device may be attached to the first surface of the electronic substrate.
  • a heat dissipation device may be formed, as set forth in block 208.
  • the heat dissipation device may be positioned such that at least a portion of the heat dissipation device extends over the back surface of the at least one integrated circuit device.
  • a dam structure may be formed, wherein the dam structure abuts the heat dissipation device and abuts the at least one sidewall of the at least one integrated circuit device, as set forth in block 212.
  • a thermal interface material may be disposed between the back surface of the at least one integrated circuit device and the heat dissipation device, and may abut the dam structure.
  • FIG. 8 illustrates a computing device 300 in accordance with one implementation of the present description.
  • the computing device 300 may house a board 302.
  • the board 302 may include a number of integrated circuit components attached thereto, including but not limited to a processor 304, at least one communication chip 306A, 306B, volatile
  • memory 308 e.g., DRAM
  • non-volatile memory 310 e.g., ROM
  • flash memory 312 e.g., a graphics processor or CPU 314, a digital signal processor (not shown), a crypto processor (not shown), a chipset 316, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • DRAM dynamic random access memory
  • non-volatile memory 310 e.g., ROM
  • flash memory 312 e.g., NAND
  • graphics processor or CPU 314 e.g., a
  • any of the integrated circuit components may be physically and electrically coupled to the board 302.
  • at least one of the integrated circuit components may be a part of the processor 304.
  • the communication chip enables wireless communications for the transfer of data to and from the computing device.
  • the term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device may include a plurality of communication chips.
  • a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others
  • processor may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • any of the integrated circuit components within the computing device 300 may include an integrated circuit package including an electronic substrate having a first surface and a second surface, wherein the second surface of the electronic substrate is electrically attached to the board 302, at least one integrated circuit device having an active surface, a back surface, and at least one sidewall extending between the active surface and the back surface, wherein the active surface of the at least one integrated circuit device is electrically attached to the first surface of the electronic substrate; a heat dissipation device, wherein at least a portion of the heat dissipation device extends over the back surface of the at least one integrated circuit device; a dam structure abutting the heat dissipation device and abutting the at least one sidewall of the at least one integrated circuit device; and a thermal interface material abutting the back surface of the at least one integrated circuit device, the dam structure, and the heat dissipation device.
  • the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device may be any other electronic device that processes data.
  • Example 1 is an integrated circuit structure comprising an electronic substrate having a first surface; at least one integrated circuit device having an active surface, a back surface, and at least one sidewall extending between the active surface and the back surface, wherein the active surface of the at least one integrated circuit device is electrically attached to the first surface of the electronic substrate; a heat dissipation device, wherein at least a portion of the heat dissipation device extends over the back surface of the at least one integrated circuit device; a dam structure abutting the heat dissipation device and abutting the at least one sidewall of the at least one integrated circuit device; and a thermal interface material abutting the back surface of the at least one integrated circuit device, the dam structure, and the heat dissipation device.
  • Example 2 the subject matter of Example 1 can optionally include the dam structure abutting the first surface of the electronic substrate.
  • Example 3 the subject matter of either Example 1 or 2 can optionally include the dam structure comprising a main body portion and at least one projection portion, wherein the main body portion abuts the at least one side of the at least one integrated circuit device, and wherein the projection portion extends between the back surface of the at least one integrated circuit device and the heat dissipation device.
  • Example 4 the subject matter of Example 3 can optionally include a width of the at least one projection portion is less than a width of the main body portion.
  • Example 5 the subject matter of any of Examples 1 to 4 can optionally include the at least one sidewall of the at least one integrated circuit device defining a periphery about the integrated circuit device, wherein the edge structure comprises a plurality of L-shaped comer projections positioned proximate the periphery of the at least one integrated circuit device.
  • Example 6 the subject matter of any of Examples 1 to 5 can optionally include the dam structure comprising polymers, polymer-metal composites, polymer-ceramic composites, or combinations thereof.
  • Example 7 the subject matter of any of Exampled 1 to 6 can optionally include the heat dissipation device including a planar portion and at least one projection extending from the planar portion, wherein the at least one projection is attached to the electronic substrate.
  • Example 8 the subject matter of Example 7 can optionally include the planar portion of the heat dissipation device extending over the at least one integrated circuit device.
  • Example 9 is an electronic system comprising a board; and an integrated circuit package, wherein the integrated circuit package includes an electronic substrate having a first surface and a second surface, wherein the second surface is electrically attached to the board; at least one integrated circuit device having an active surface, a back surface, and at least one sidewall extending between the active surface and the back surface, wherein the active surface of the at least one integrated circuit device is electrically attached to the first surface of the electronic substrate; a heat dissipation device, wherein at least a portion of the heat dissipation device extends over the back surface of the at least one integrated circuit device; a dam structure abutting the heat dissipation device and abutting the at least one side of the at least one integrated circuit device; and a thermal interface material abutting the back surface of the at least one integrated circuit device, the dam structure, and the heat dissipation device.
  • the integrated circuit package includes an electronic substrate having a first surface and a second surface, wherein the second surface is electrically attached to
  • Example 10 the subject matter of Example 9 can optionally include the dam structure abutting the first surface of the electronic substrate.
  • Example 11 the subject matter of either Example 9 or 10 can optionally include the dam structure comprising a main body portion and at least one projection portion, wherein the main body portion abuts the at least one side of the at least one integrated circuit device, and wherein the projection portion extends between the back surface of the at least one integrated circuit device and the heat dissipation device.
  • Example 12 the subject matter of Example 11 can optionally include a width of the at least one projection portion is less than a width of the main body portion.
  • Example 13 the subject matter of any of Examples 9 to 12 can optionally include the at least one sidewall of the at least one integrated circuit device defining a periphery about the integrated circuit device, wherein the edge structure comprises a plurality of L-shaped comer projections positioned proximate the periphery of the at least one integrated circuit device.
  • Example 14 the subject matter of any of Examples 9 to 13 can optionally include the dam structure comprising polymers, polymer-metal composites, polymer-ceramic composites, or combinations thereof.
  • Example 15 the subject matter of any of Exampled 9 to 14 can optionally include the heat dissipation device including a planar portion and at least one projection extending from the planar portion, wherein the at least one projection is attached to the electronic substrate.
  • Example 16 the subject matter of Example 15 can optionally include the planar portion of the heat dissipation device extending over the at least one integrated circuit device.
  • Example 17 is a method comprising forming an electronic substrate having a first surface; forming at least one integrated circuit device having an active surface, a back surface, and at least one sidewall extending between the active surface and the back surface; electrically attaching the active surface of the at least one integrated circuit device to the first surface of the electronic substrate; forming a heat dissipation device; positioning the heat dissipation device, such that at least a portion of the heat dissipation device extends over the back surface of the at least one integrated circuit device; forming a dam structure, wherein the dam structure abuts the heat dissipation device and abuts the at least one side of the at least one integrated circuit device; and disposing a thermal interface material between the back surface of the at least one integrated circuit device and the heat dissipation device, and abutting the dam structure.
  • the subject matter of Example 17 can optionally include forming the dam structure to abut the first surface of the electronic substrate.
  • Example 19 the subject matter of either Example 17 or 18 can optionally include forming the dam structure comprising forming a main body portion and at least one projection portion, wherein the main body portion abuts the at least one side of the at least one integrated circuit device, and wherein the projection portion extends between the back surface of the at least one integrated circuit device and the heat dissipation device.
  • Example 20 the subject matter of Example 19 can optionally include forming a width of the at least one projection portion to be less than a width of the main body portion.
  • Example 21 the subject matter of any of Examples 17 to 20 can optionally forming the dam to surround the at least one integrated circuit device.
  • Example 22 the subject matter of any of Examples 9 to 13 can optionally include forming the dam structure comprising polymers, polymer-metal composites, polymer-ceramic composites, or combinations thereof.
  • Example 23 the subject matter of any of Exampled 9 to 14 can optionally include forming the heat dissipation device including forming a planar portion and at least one projection extending from the planar portion and further comprising attaching the at least one projection to the electronic substrate.
  • Example 24 the subject matter of Example 15 can optionally include the planar portion of the heat dissipation device extending over the at least one integrated circuit device.
  • Example 25 the subject matter of any of Examples 17 to 24 can optionally include forming the dam structure comprising forming a mold having a recess formed therein, wherein the recess comprises: forming an electronic substrate recess extending into the mold from a first surface of the mold; forming an integrated circuit device recess extending into the mold from a bottom surface of the electronic substrate recess; and forming at least one projection recess extending into the mold from a bottom surface of the integrated circuit device recess; inserting the electronic substrate having the at least one integrated circuit device attached thereto into the mold, such that the electronic substrate resides within the electronic substrate recess, wherein the first surface of the electronic substrate abuts the bottom surface of the electronic substrate recess, and such that the at least one integrated circuit device resides within the integrated circuit device recess, wherein the back surface of the at least one integrated circuit device abuts the bottom surface of the integrated circuit device recess; and injecting a mold material into the integrated circuit device recess to form the dam structure.

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Abstract

An integrated circuit structure may be fabricated to include a dam structure to contain a thermal interface material between a back surface of an integrated circuit device and a heat dissipation device. The use of the dam structure may significantly reduce pump-out of the thermal interface material during assembly and/or operation, and, thus, may prevent the formation of air-gaps, which can increase thermal resistance.

Description

A HEAT DISSIPATION STRUCTURE FOR AN INTEGRATED CIRCUIT
PACKAGE
TECHNICAL FIELD
Embodiments of the present description generally relate to the field of heat dissipation from an integrated circuit device, and, more specifically, to a heat dissipation structure that includes a dam structure for improving heat removal from the integrated circuit device.
BACKGROUND ART
The integrated circuit industry is continually striving to produce ever faster and smaller integrated circuit devices for use in various server and mobile electronic products.
As these goals are achieved, the density of power consumption of components within the integrated circuit devices has increased, which, in turn, increases the average junction temperature of the integrated circuit device. If the temperature of the integrated circuit device becomes too high, circuits within the integrated circuit device may be damaged or destroyed. Thus, heat dissipation devices are used to remove heat from the integrated circuit devices in an integrated circuit package. In one example, at least one integrated circuit device may be mounted to an electronic substrate and the heat dissipation device may be attached to the electronic substrate and extend over the integrated circuit device(s) to form the integrated circuit package. The distance between the integrated circuit device(s) and the heat dissipation device is known as the bondline thickness, and a thermal interface material is generally disposed between the integrated circuit device(s) and the heat dissipation device to form thermal contact therebetween.
One issue with such heat dissipation devices is warpage in the integrated circuit package when it heats and cools during operation. When the integrated circuit package is exposed to temperature gradients during assembly and/or operation, the shape of the integrated circuit device changes from convex to flat or concave, which causes compression on the thermal interface material at edges or sidewalls of the integrated circuit device. When the integrated circuit package returns to room temperature, the integrated circuit device returns to a convex shape creating an elongation of the thermal interface material at the edge or sidewalls of the integrated circuit device. The mechanisms of compression and elongation may cause the thermal interface material to“pump-out” from between the heat dissipation device and the integrated circuit device. This thermal interface material pump-out may result in the formation of an air-gap, also known as an air insulation layer, between the integrated circuit device and the heat dissipation device, which increases thermal resistance
therebetween. The issue of thermal interface material pump-out may be a particular problem at the edges and comers of the integrated circuit device, because peak power density, and thus the highest heat generation, has moved to the integrated circuit device edges and comers.
BRIEF DESCRIPTION OF THE DRAWINGS
The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:
FIG. 1 illustrates a side cross-sectional view of an integrated circuit package, according to an embodiment of the present disclosure. FIG. 2 illustrate top plan views along line A-A of FIG. 1 showing a dam structure configuration with an integrated circuit device of the integrated circuit package, according to one embodiment of the present description.
FIGs. 3-6 illustrate side cross-sectional views of a method of fabricating the integrated circuit package of FIG. 1, according to one embodiment of the present disclosure. FIG. 7 is a flow chart of a process of fabricating an integrated circuit package, according to an embodiment of the present description.
FIG. 8 illustrates an electronic system, according to one embodiment of the present description. DETAILED DESCRIPTION
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to“one embodiment” or“an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase“one embodiment” or“in an embodiment” does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.
The terms“over”,“to”,“between” and“on” as used herein may refer to a relative position of one layer with respect to other layers. One layer“over” or“on” another layer or bonded“to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer“between” layers may be directly in contact with the layers or may have one or more intervening layers.
Embodiment of the present description relate to an integrated circuit structure having a dam structure to contain a thermal interface material between a back surface of an integrated circuit device and a heat dissipation device. The use of the dam structure may significantly reduce pump-out of the thermal interface material during assembly and/or operation, and, thus, may prevent the formation of air-gaps, which can increase thermal resistance.
As shown in FIG. 1, an integrated circuit package 100 may be formed by first providing or forming an electronic substrate 110, such as an interposer, a printed circuit board, a motherboard, or the like. At least one integrated circuit device 130, such as a microprocessor, a multichip package, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit device, and the like, may be attached to a first surface 112 of the electronic substrate 110 with a plurality of
interconnects 120. The plurality of interconnects 120, such as soldered interconnects, may extend between bond pads 122 formed in or on an active surface 132 of the integrated circuit device 130, and substantially mirror-image bond pads 124 in or on the electronic substrate first surface 112. As will be understood to those skilled in the art, the integrated circuit device bond pads 122 may be in electrical communication with integrated circuitry (not shown) within the integrated circuit device 130.
An underfill material 116, such as an epoxy material, may be disposed between the integrated circuit device active surface 132 and the electronic substrate first surface 112, and surrounding the plurality of interconnects 120. As will be understood to those skilled in the art, the underfill material 116 may be dispensed between the integrated circuit device active surface 132 and the electronic substrate first surface 112 as a viscous liquid and then hardened with a curing process. The underfill material 116 may also be a molded underfill material. The underfill material 116 may provide structural integrity and may prevent contamination, as will be understood to those skilled in the art.
It is noted that the electronic substrate 110 may comprise any appropriate dielectric material, including, but not limited to, liquid crystal polymer, epoxy resin, bismaleimide triazine resin, FR4, polyimide materials, and the like, and may include conductive routes (illustrated as dashed lines 118) formed therein and/or thereon to form any desired electrical route within the electronic substrate 110, including, but not limited to, conductive routes 118 between the bond pads 124 in or on the electronic substrate first surface 112 and
corresponding bond pads 126 in or on a second surface 114 of the electronic substrate 110. As further shown in FIG. 1, external interconnects, such as solder balls 128, may be formed on the electronic substrate second surface bond pads 126 for attaching the microelectronic package 100 to external components (such as a board, as will described with regard to FIG. 8).
As further shown in FIG. 1, a heat dissipation device 140 may be attached to the electronic substrate 110. The heat dissipation device 140 may include a planar portion 142 having a first surface 144 and an opposing second surface 146, and may have at least one projection 152 extending from the planar portion first surface 144. The heat dissipation device projection(s) 152 may be attached to the electronic substrate first surface 112 such that the planar portion second surface 146 spans, but does not necessarily directly contact a back surface 134 (opposing the integrated circuit device active surface 132) of the integrated circuit device 130, and a thermal interface material 160 may be disposed between the planar portion first surface 144 of the heat dissipation device 140 and the back surface 134 of the integrated circuit device 130. The heat dissipation device projection(s) 152 may be attached to the electronic substrate 110 by any appropriate means, including but not limited to a sealant material 156, such as an epoxy, disposed between an attachment surface 154 of the heat dissipation device projection(s) 152 and the electronic substrate first surface 112. In one embodiment, the heat dissipation device projection(s) 152 extend substantially perpendicular to the planar portion first surface 144 of the heat dissipation device 140. It is understood that the term substantially perpendicular includes the heat dissipation device projection(s) 152 being plus or minus 5 degrees from 90 degrees.
The heat dissipation device 140 may be formed from any appropriate thermally conductive material, including, but not limited to copper, aluminum, and the like. In one embodiment, the heat dissipation device 140 may be formed from a molding or a stamping process, such that the heat dissipation device 140 is a single continuous material. In another embodiment, the planar portion 142 of the heat dissipation device 140 may be formed separately from the projection(s) 152 of heat dissipation device 140 and attached together.
As shown in FIG. 1, the integrated circuit package 100 may further include a dam structure 170. The dam structure 170 may contact the first surface 144 of the planar portion 142 of the heat dissipation device 140, at least one sidewall 136 extending between the active surface 132 and the back surface 134 of the integrated circuit device 130, and the first surface 112 of the electronic substrate 110. The dam structure 170 may comprise a main body portion 172 and at least one projection portion 174 that may have a width Wl (see FIG. 2) that is less than a width W2 (see FIG. 2) of the main body portion 172. As further shown in FIG. 1, the at least one projection portion 174 may extend a distance D from the back surface 134 of the integrated circuit device 130 to the first surface 144 of the planar portion 142 of the heat dissipation device 140, such that the at least one projection portion distance D defines a bond line thickness BLT between the back surface 134 of the integrated circuit device 130 and the first surface 144 of the planar portion 142 of the heat dissipation device 140.
FIG. 2 illustrates top plan views of one embodiment of the dam structure 170 and the integrated circuit device 130 (without the thermal interface material 160 or the electronic substrate 110 being illustrated for clarity purposes) along line A-A of FIG. 1. As shown in FIG. 2, the dam structure 170 may completely surround the integrated circuit device 130, such that (referring back to FIG. 1) the thermal interface material 160 may contained between the first surface 144 of the planar portion 142 of the heat dissipation device 140, the back surface 134 of the integrated circuit device 130, and the at least one projection portion 174 of the dam structure 170. It is understood that the embodiment of FIG. 2 is merely a single example and that the dam structure 170 could have any appropriate shape or configuration.
The dam structure 170 may be made by any known technique, and may be any appropriate material, including, but not limited to polymers (such as epoxy materials and silicone-based materials, e.g. polydimethylsiloxane), polymer-metal composites (such as epoxy with metal particles like silver or silver-coated copper particles), polymer-ceramic composites (such as epoxy with ceramic particles like silicon oxide or aluminum oxide), and as well as any combination of the above materials.
The thermal interface material 160 may be any appropriate material, including, but not limited to polymer-metal composites (such as epoxy with metal particles like silver or silver-coated copper particles and polydimethylsiloxane with metal particles like silver or silver-coated copper particles), polymer-ceramic composites (such as epoxy or
polydimethylsiloxame with ceramic particles like silicon oxide or aluminum oxide), liquid metal (such as gallium based alloys), Bi-phase metals (such as indium/bismuth/tin alloys), and sinterable materials. In one embodiment, the thermal interface material 160 may be a nanographene platelet thermal interface material. Although FIGs. 1 and 2 illustrate a single integrated circuit device 130, it is understood that a plurality of integrated circuit devices 130 may be disposed between the heat dissipation device 140 and the electronic substrate 110. The plurality of integrated circuit devices 130 may each be thermally connected to the heat dissipation device 140.
FIGs. 3-6 illustrate side cross sectional views of a method of fabricating the integrated circuit package 100 of FIG. 1. As shown in FIG. 3, a mold 180 may be formed of a substantially rigid material and may include recess 182 formed therein. The recess 182 may comprise an electronic substrate recess 186 that extends into the mold 180 from a first surface 184 thereof, an integrated circuit device recess 190 that extends into the mold 180 from a bohom surface 188 of the electronic substrate recess 186, and at least one projection recess 192 that extends into the mold 180 from a bohom surface 190 of the integrated circuit device recess 188. It is understood that a depth Dp that the at least one projection recess 192 extends into the mold 180 will be substantially the same as the distance D of FIG. 1.
As shown in FIG. 4, the at least one integrated circuit device 130 may be attached to the electronic substrate 110 and inserted into the mold 180, such that the electronic substrate 110 resides within the electronic substrate recess 184, wherein the first surface 112 of the electronic substrate 110 abuts the bohom surface 186 of the electronic substrate recess 184, and such that the at least one integrated circuit device 130 resides within the integrated circuit device recess 188, wherein the back surface 134 of the at least one integrated circuit device 130 abuts the bottom surface 190 of the integrated circuit device recess 188. As shown in FIG. 5, a mold material (shown as arrows 196) may be injected into the mold 180 to fill the integrated circuit device recess 188 not occupied by the integrated circuit device 130 and components associated therewith, such as the plurality of
interconnects 120 and the underfill material 116, thereby forming the dam structure 170 (see FIG. 1). It is noted that inlet and outlet ports for injecting the mold material 196 are not illustrated for brevity and clarity, as such ports are well known and understood in the art. The mold material 196 may be at least partially cured and, as shown in FIG. 6 the at least one integrated circuit device 130, the electronic substrate 110, and dam structure 170 may be removed from the mold 180 (see FIG. 5). The heat dissipation device 140 may then be attached to the electronic substrate 110, such that the dam structure 170 contacts the first surface 144 of the planar portion 142 of the heat dissipation device 140, and the thermal interface material 160 may be disposed between the planar portion first surface 144 of the heat dissipation device 140 and the back surface 134 of the integrated circuit device 130, as shown in FIG. 1.
FIG. 7 is a flow chart of a process 200 of fabricating an integrated circuit package according to the various embodiments of the present description. As set forth in block 202, an electronic substrate having a first surface may be formed. At least one integrated circuit device having an active surface, a back surface, and at least one sidewall extending between the active surface and the back surface may be formed, as set forth in block 204. As set forth in block 206, the active surface of the at least one integrated circuit device may be attached to the first surface of the electronic substrate. A heat dissipation device may be formed, as set forth in block 208. As set forth in block 210, the heat dissipation device may be positioned such that at least a portion of the heat dissipation device extends over the back surface of the at least one integrated circuit device. A dam structure may be formed, wherein the dam structure abuts the heat dissipation device and abuts the at least one sidewall of the at least one integrated circuit device, as set forth in block 212. As set forth in block 214, a thermal interface material may be disposed between the back surface of the at least one integrated circuit device and the heat dissipation device, and may abut the dam structure.
FIG. 8 illustrates a computing device 300 in accordance with one implementation of the present description. The computing device 300 may house a board 302. The board 302 may include a number of integrated circuit components attached thereto, including but not limited to a processor 304, at least one communication chip 306A, 306B, volatile
memory 308, (e.g., DRAM), non-volatile memory 310 (e.g., ROM), flash memory 312, a graphics processor or CPU 314, a digital signal processor (not shown), a crypto processor (not shown), a chipset 316, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the integrated circuit components may be physically and electrically coupled to the board 302. In some implementations, at least one of the integrated circuit components may be a part of the processor 304. The communication chip enables wireless communications for the transfer of data to and from the computing device. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device may include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others
The term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
Any of the integrated circuit components within the computing device 300 may include an integrated circuit package including an electronic substrate having a first surface and a second surface, wherein the second surface of the electronic substrate is electrically attached to the board 302, at least one integrated circuit device having an active surface, a back surface, and at least one sidewall extending between the active surface and the back surface, wherein the active surface of the at least one integrated circuit device is electrically attached to the first surface of the electronic substrate; a heat dissipation device, wherein at least a portion of the heat dissipation device extends over the back surface of the at least one integrated circuit device; a dam structure abutting the heat dissipation device and abutting the at least one sidewall of the at least one integrated circuit device; and a thermal interface material abutting the back surface of the at least one integrated circuit device, the dam structure, and the heat dissipation device. In various implementations, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device may be any other electronic device that processes data.
It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in FIGs. 1-8. The subject matter may be applied to other integrated circuit device and assembly applications, as will be understood to those skilled in the art.
The following examples pertain to further embodiments, wherein Example 1 is an integrated circuit structure comprising an electronic substrate having a first surface; at least one integrated circuit device having an active surface, a back surface, and at least one sidewall extending between the active surface and the back surface, wherein the active surface of the at least one integrated circuit device is electrically attached to the first surface of the electronic substrate; a heat dissipation device, wherein at least a portion of the heat dissipation device extends over the back surface of the at least one integrated circuit device; a dam structure abutting the heat dissipation device and abutting the at least one sidewall of the at least one integrated circuit device; and a thermal interface material abutting the back surface of the at least one integrated circuit device, the dam structure, and the heat dissipation device.
In Example 2, the subject matter of Example 1 can optionally include the dam structure abutting the first surface of the electronic substrate.
In Example 3, the subject matter of either Example 1 or 2 can optionally include the dam structure comprising a main body portion and at least one projection portion, wherein the main body portion abuts the at least one side of the at least one integrated circuit device, and wherein the projection portion extends between the back surface of the at least one integrated circuit device and the heat dissipation device.
In Example 4, the subject matter of Example 3 can optionally include a width of the at least one projection portion is less than a width of the main body portion. In Example 5, the subject matter of any of Examples 1 to 4 can optionally include the at least one sidewall of the at least one integrated circuit device defining a periphery about the integrated circuit device, wherein the edge structure comprises a plurality of L-shaped comer projections positioned proximate the periphery of the at least one integrated circuit device.
In Example 6, the subject matter of any of Examples 1 to 5 can optionally include the dam structure comprising polymers, polymer-metal composites, polymer-ceramic composites, or combinations thereof.
In Example 7, the subject matter of any of Exampled 1 to 6 can optionally include the heat dissipation device including a planar portion and at least one projection extending from the planar portion, wherein the at least one projection is attached to the electronic substrate.
In Example 8, the subject matter of Example 7 can optionally include the planar portion of the heat dissipation device extending over the at least one integrated circuit device.
The following examples pertain to further embodiments, wherein Example 9 is an electronic system comprising a board; and an integrated circuit package, wherein the integrated circuit package includes an electronic substrate having a first surface and a second surface, wherein the second surface is electrically attached to the board; at least one integrated circuit device having an active surface, a back surface, and at least one sidewall extending between the active surface and the back surface, wherein the active surface of the at least one integrated circuit device is electrically attached to the first surface of the electronic substrate; a heat dissipation device, wherein at least a portion of the heat dissipation device extends over the back surface of the at least one integrated circuit device; a dam structure abutting the heat dissipation device and abutting the at least one side of the at least one integrated circuit device; and a thermal interface material abutting the back surface of the at least one integrated circuit device, the dam structure, and the heat dissipation device.
In Example 10, the subject matter of Example 9 can optionally include the dam structure abutting the first surface of the electronic substrate.
In Example 11, the subject matter of either Example 9 or 10 can optionally include the dam structure comprising a main body portion and at least one projection portion, wherein the main body portion abuts the at least one side of the at least one integrated circuit device, and wherein the projection portion extends between the back surface of the at least one integrated circuit device and the heat dissipation device.
In Example 12, the subject matter of Example 11 can optionally include a width of the at least one projection portion is less than a width of the main body portion. In Example 13, the subject matter of any of Examples 9 to 12 can optionally include the at least one sidewall of the at least one integrated circuit device defining a periphery about the integrated circuit device, wherein the edge structure comprises a plurality of L-shaped comer projections positioned proximate the periphery of the at least one integrated circuit device. In Example 14, the subject matter of any of Examples 9 to 13 can optionally include the dam structure comprising polymers, polymer-metal composites, polymer-ceramic composites, or combinations thereof.
In Example 15, the subject matter of any of Exampled 9 to 14 can optionally include the heat dissipation device including a planar portion and at least one projection extending from the planar portion, wherein the at least one projection is attached to the electronic substrate.
In Example 16, the subject matter of Example 15 can optionally include the planar portion of the heat dissipation device extending over the at least one integrated circuit device.
The following examples pertain to further embodiments, wherein Example 17 is a method comprising forming an electronic substrate having a first surface; forming at least one integrated circuit device having an active surface, a back surface, and at least one sidewall extending between the active surface and the back surface; electrically attaching the active surface of the at least one integrated circuit device to the first surface of the electronic substrate; forming a heat dissipation device; positioning the heat dissipation device, such that at least a portion of the heat dissipation device extends over the back surface of the at least one integrated circuit device; forming a dam structure, wherein the dam structure abuts the heat dissipation device and abuts the at least one side of the at least one integrated circuit device; and disposing a thermal interface material between the back surface of the at least one integrated circuit device and the heat dissipation device, and abutting the dam structure. In Example 18, the subject matter of Example 17 can optionally include forming the dam structure to abut the first surface of the electronic substrate.
In Example 19, the subject matter of either Example 17 or 18 can optionally include forming the dam structure comprising forming a main body portion and at least one projection portion, wherein the main body portion abuts the at least one side of the at least one integrated circuit device, and wherein the projection portion extends between the back surface of the at least one integrated circuit device and the heat dissipation device.
In Example 20, the subject matter of Example 19 can optionally include forming a width of the at least one projection portion to be less than a width of the main body portion. In Example 21, the subject matter of any of Examples 17 to 20 can optionally forming the dam to surround the at least one integrated circuit device.
In Example 22, the subject matter of any of Examples 9 to 13 can optionally include forming the dam structure comprising polymers, polymer-metal composites, polymer-ceramic composites, or combinations thereof. In Example 23, the subject matter of any of Exampled 9 to 14 can optionally include forming the heat dissipation device including forming a planar portion and at least one projection extending from the planar portion and further comprising attaching the at least one projection to the electronic substrate.
In Example 24, the subject matter of Example 15 can optionally include the planar portion of the heat dissipation device extending over the at least one integrated circuit device.
In Example 25, the subject matter of any of Examples 17 to 24 can optionally include forming the dam structure comprising forming a mold having a recess formed therein, wherein the recess comprises: forming an electronic substrate recess extending into the mold from a first surface of the mold; forming an integrated circuit device recess extending into the mold from a bottom surface of the electronic substrate recess; and forming at least one projection recess extending into the mold from a bottom surface of the integrated circuit device recess; inserting the electronic substrate having the at least one integrated circuit device attached thereto into the mold, such that the electronic substrate resides within the electronic substrate recess, wherein the first surface of the electronic substrate abuts the bottom surface of the electronic substrate recess, and such that the at least one integrated circuit device resides within the integrated circuit device recess, wherein the back surface of the at least one integrated circuit device abuts the bottom surface of the integrated circuit device recess; and injecting a mold material into the integrated circuit device recess to form the dam structure.
Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.

Claims

CLAIMS What is claimed is:
1. An integrated circuit structure, comprising:
an electronic substrate having a first surface;
at least one integrated circuit device having an active surface, a back surface, and at least one sidewall extending between the active surface and the back surface, wherein the active surface of the at least one integrated circuit device is electrically attached to the first surface of the electronic substrate;
a heat dissipation device, wherein at least a portion of the heat dissipation device extends over the back surface of the at least one integrated circuit device;
a dam structure abutting the heat dissipation device and abutting the at least one sidewall of the at least one integrated circuit device; and
a thermal interface material abutting the back surface of the at least one integrated circuit device, the dam structure, and the heat dissipation device.
2. The integrated circuit structure of claim 1, wherein the dam structure abuts the first surface of the electronic substrate.
3. The integrated circuit structure of either claim 1 or 2, wherein the dam structure comprises a main body portion and at least one projection portion, wherein the main body portion abuts the at least one sidewall of the at least one integrated circuit device, and wherein the projection portion extends between the back surface of the at least one integrated circuit device and the heat dissipation device.
4. The integrated circuit structure of claim 3, wherein a width of the at least one projection portion is less than a width of the main body portion.
5. The integrated circuit structure of either claim 1 or 2, wherein the dam structure surrounds the at least one integrated circuit device.
6. The integrated circuit structure of either claim 1 or 2, wherein the dam structure comprises polymers, polymer-metal composites, polymer-ceramic composites, or combinations thereof.
7. The integrated circuit structure of either claim 1 or 2, wherein the heat dissipation device includes a planar portion and at least one projection extending from the planar portion, wherein the at least one projection is attached to the electronic substrate.
8. The integrated circuit structure of claim 7, wherein the planar portion of the heat dissipation device extends over the at least one integrated circuit device.
9. An electronic system, comprising:
a board; and
an integrated circuit package, wherein the integrated circuit package includes:
an electronic substrate having a first surface and a second surface, wherein the second surface is electrically attached to the board;
at least one integrated circuit device having an active surface, a back surface, and at least one sidewall extending between the active surface and the back surface, wherein the active surface of the at least one integrated circuit device is electrically attached to the first surface of the electronic substrate;
a heat dissipation device, wherein at least a portion of the heat dissipation device extends over the back surface of the at least one integrated circuit device; a dam structure abutting the heat dissipation device and abutting the at least one sidewall of the at least one integrated circuit device; and
a thermal interface material abutting the back surface of the at least one integrated circuit device, the dam structure, and the heat dissipation device.
10. The electronic system of claim 9, wherein the dam structure abuts the first surface of the electronic substrate.
11. The electronic system of either claim 9 or 10, wherein the dam structure comprises a main body portion and at least one projection portion, wherein the main body portion abuts the at least one sidewall of the at least one integrated circuit device, and wherein the projection portion extends between the back surface of the at least one integrated circuit device and the heat dissipation device.
12. The electronic system of claim 11, wherein a width of the at least one projection portion is less than a width of the main body portion.
13. The electronic system of either claim 9 or 10, wherein the dam structure surrounds the at least one integrated circuit device.
14. The electronic system of either claim 9 or 10, wherein the dam structure comprises polymers, polymer-metal composites, polymer-ceramic composites, or combinations thereof.
15. The electronic system of either claim 9 or 10, wherein the heat dissipation device includes a planar portion and at least one projection extending from the planar portion, wherein the at least one projection is attached to the electronic substrate.
16. The electronic system of claim 15, wherein the planar portion of the heat dissipation device extends over the at least one integrated circuit device.
17. A method of forming an integrated circuit structure, comprising:
forming an electronic substrate having a first surface;
forming at least one integrated circuit device having an active surface, a back surface, and at least one sidewall extending between the active surface and the back surface;
electrically attaching the active surface of the at least one integrated circuit device to the first surface of the electronic substrate;
forming a heat dissipation device;
positioning the heat dissipation device, such that at least a portion of the heat dissipation device extends over the back surface of the at least one integrated circuit device; forming a dam structure, wherein the dam structure abuts the heat dissipation device and abuts the at least one sidewall of the at least one integrated circuit device; and
disposing a thermal interface material between the back surface of the at least one integrated circuit device and the heat dissipation device, and abutting the dam structure.
18. The method of claim 17, wherein forming the dam structure comprises forming the dam structure to abut the first surface of the electronic substrate.
19. The method of either claim 17 or 18, wherein forming the dam structure comprises forming a main body portion and at least one projection portion, wherein the main body portion abuts the at least one sidewall of the at least one integrated circuit device, and wherein the projection portion extends between the back surface of the at least one integrated circuit device and the heat dissipation device.
20. The method of claim 19, wherein forming the main body portion and the at least one projection portion comprises forming the at least one portion to have a width less than the width of the main body portion.
21. The method of either claim 17 or 18, wherein forming the dam structure comprises forming the dam structure to surround the at least one integrated circuit device.
22. The method of either claim 17 or 18, wherein forming the dam structure comprises forming the dam structure from polymers, polymer-metal composites, polymer-ceramic composites, or combinations thereof.
23. The method of either claim 17 or 18, wherein forming the heat dissipation device includes forming a planar portion and at least one projection extending from the planar portion and further comprising attaching the at least one projection to the electronic substrate.
24. The method of claim 23, wherein the planar portion of the heat dissipation device extends over the at least one integrated circuit device.
25. The method of claim 17, wherein forming the dam structure, comprises:
forming a mold having a recess formed therein, wherein the recess comprises:
forming an electronic substrate recess extending into the mold from a first surface of the mold;
forming an integrated circuit device recess extending into the mold from a bottom surface of the electronic substrate recess; and forming at least one projection recess extending into the mold from a bottom surface of the integrated circuit device recess;
inserting the electronic substrate having the at least one integrated circuit device attached thereto into the mold, such that the electronic substrate resides within the electronic substrate recess, wherein the first surface of the electronic substrate abuts the bottom surface of the electronic substrate recess, and such that the at least one integrated circuit device resides within the integrated circuit device recess, wherein the back surface of the at least one integrated circuit device abuts the bottom surface of the integrated circuit device recess; and injecting a mold material into the integrated circuit device recess to form the dam structure.
PCT/US2017/065062 2017-12-07 2017-12-07 A heat dissipation structure for an integrated circuit package WO2019112582A1 (en)

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