WO2019102073A1

WO2019102073A1 - Photovoltaic semiconductor structure

Info

Publication number: WO2019102073A1
Application number: PCT/FI2018/050854
Authority: WO
Inventors: Toni PASANEN; Hele Savin; Ville VÄHÄNISSI; Hannu Laine; Chiara MODANESE; Franziska Wolny; Matthias Wagner
Original assignee: Aalto-Korkeakoulusäätiö Sr
Priority date: 2017-11-24
Filing date: 2018-11-23
Publication date: 2019-05-31

Abstract

This specification relates to a layered photovoltaic semiconductor structure (100, 200) extending in a lateral direction (101, 201 ), comprising a p-type silicon layer (102, 202) having a bulk refractive index; an n-type silicon layer (103, 203) on the p-type silicon layer (102, 202), the n-type silicon layer (103, 203) having a textured surface (104, 204); a first dielectric layer (107, 207) on the textured surface (104, 204), the first dielectric layer (107, 207) having a front surface (108, 208) defining a front side of the photovoltaic semiconductor structure (100, 200); and a second dielectric layer (109, 209) on a side of the p-type silicon layer (102, 202) opposite the n-type silicon layer (103, 203). In the photovoltaic semiconductor structure (100, 200), the textured surface (104, 204) comprises high aspect ratio nanostructures (105, 205) extending in a direction substantially perpendicular to the lateral direction (101, 201), the nanostructures (105, 205) forming an optical conversion layer (106, 206) having an effective refractive index gradually changing towards the bulk refractive index to reduce reflection of light incident on the photovoltaic semiconductor structure (100, 200) from the front side thereof.

Description

PHOTOVOLTAIC SEMICONDUCTOR STRUCTURE TECHNICAL FIELD

[001] The present disclosure concerns the field of semiconductor photovoltaics . In particular, this dis closure concerns silicon photovoltaics.

BACKGROUND

[002] Photovoltaics refers to converting light into electrical energy using an active material, such as a semiconductor. In photovoltaics, silicon is the most commonly used active material for various types of de vices, including solar cells and photodetectors.

[003] Photovoltaic structures may utilize textured active material front surfaces in order to increase their overall absorbance. However, the surface area of any textured front surfaces must be kept reasonably low, since the surface of an active material is gener ally a significant site for carrier recombination. This limits the degree to which the absorbance of con ventional photovoltaic structures may be increased.

[004] Another key challenge in conventional Si pho tovoltaics is the degradation of light-to-electricity conversion efficiency over time during operation. This phenomenon is commonly referred to as light-induced degradation or carrier-induced degradation. Some pho tovoltaic structures, such as the passivated emitter and rear cell structure, are especially susceptible to light-induced degradation.

[005] In light of both of the aforementioned chal lenges, it may be desirable to devise solutions that would provide a photovoltaic semiconductor structure with a high absorbance, exhibiting only minute or no light-induced degradation. SUMMARY

[006] According to a first aspect, a layered photo voltaic semiconductor structure extending in a lateral direction is provided. The photovoltaic semiconductor structure comprises a p-type silicon (Si) layer having a bulk refractive index; an n-type Si layer on the p-type Si layer, the n-type Si layer having a textured surface opposite the p-type Si layer; a first dielec tric layer on the textured surface, the first dielec- trie layer having a front surface opposite the n-type Si layer, the front surface defining a front side of the photovoltaic semiconductor structure; and a second dielectric layer on a side of the p-type Si layer op posite the n-type Si layer.

[007] In the photovoltaic semiconductor structure, the textured surface comprises high aspect ratio nanostructures extending in a direction substantially perpendicular to the lateral direction, the nanostruc tures forming an optical conversion layer having an effective refractive index gradually changing towards the bulk refractive index to reduce reflection of light incident on the photovoltaic semiconductor structure from the front side thereof.

[008] In an embodiment of the first aspect, the second dielectric layer is patterned with a through- hole and the photovoltaic semiconductor structure fur ther comprises a conductive back layer on a side of the second dielectric layer opposite the p-type Si layer, a galvanic contact existing between the conduc- tive back layer and the p-type Si layer via the through-hole; and a front contact, for example, a front contact finger, on a side of the first dielec tric layer opposite the n-type Si layer, a galvanic contact existing between the front contact and the n-type Si layer. [009] In an embodiment of the first aspect, which may be in accordance with the previous embodiment, the photovoltaic semiconductor structure is or forms a part of a passivated emitter and rear cell (PERC) pho tovoltaic device or structure.

[010] In an embodiment of the first aspect, which may be in accordance with any of the preceding embodi ments, the first dielectric layer covers the nanostructures in a substantially conformal manner.

[Oil] In an embodiment of the first aspect in ac cordance with the previous embodiment, the first die lectric layer is formed by atomic layer deposition (ALD) .

[012] In an embodiment of the first aspect, which may be in accordance with any of the preceding embodi ments, the nanostructures are formed by deep reactive ion etching (DRIE) .

[013] In an embodiment of the first aspect, which may be in accordance with any of the preceding embodi ments, a ratio, S_f, between a surface area of a macro scopic portion of the textured surface and a surface area of a polished surface corresponding to the macro scopic portion, e.g., a highest projected area of the macroscopic portion, is more than 3, or at least 4, or at least 5, or in a range from 5 to 7.

[014] In an embodiment of the first aspect, which may be in accordance with any of the preceding embodi ments, the nanostructures are black silicon (b-Si) spikes .

[015] In an embodiment of the first aspect, which may be in accordance with any of the preceding embodi ments, the nanostructures may have their average height in a direction perpendicular to the lateral di rection in a range from 500 nanometers (nm) to 1500 nm, or from about 600 nm to 1000 nm, or from 800 nm to 1000 nm, and their average width in the lat eral direction in a range from 50 nm to 400 nm, or from 100 nm to 400 nm, or from 200 nm to 300 nm.

[016] In an embodiment of the first aspect, which may be in accordance with any of the preceding embodi ments, the p-type Si layer and the n-type Si layer are multicrystalline silicon (mc-Si) layers or quasi monocrystalline silicon (qm-Si) layers.

[017] In an embodiment of the first aspect, which may be in accordance with any of the preceding embodi ments, the p-type Si layer comprises boron as a dopant and/or the n-type Si layer comprises phosphorus as a dopant .

[018] In an embodiment of the first aspect, which may be in accordance with any of the preceding embodi ments, the first dielectric layer comprises a trans parent oxide and/or nitride, e.g., silicon oxide (SiCy) , non-stoichiometric silicon oxide (SiO_x) , alu minium oxide (AI2O3) , non-stoichiometric aluminium ox ide (AIO_c) , silicon nitride (Si₃N₄) , and/or non- stoichiometric silicon nitride (SiN_x) .

[019] In an embodiment of the first aspect, which may be in accordance with any of the preceding embodi ments, the second dielectric layer comprises a trans parent oxide and/or nitride, e.g., silicon oxide (SiCy) , non-stoichiometric silicon oxide (SiO_x) , alu minium oxide (AI₂O₃) , non-stoichiometric aluminium ox ide (A10_x) , silicon nitride (Si₃N₄) , and/or non- stoichiometric silicon nitride (SiN_x) .

[020] In an embodiment of the first aspect, which may be in accordance with any of the preceding embodi ments, the photovoltaic semiconductor structure is configured for use as or in a photovoltaic device, e.g., a photodetector or a solar cell, and configured to receive and absorb light incident on the photovol- taic semiconductor structure from the front side thereof .

[021] It is to be understood that the embodiments of the first aspect described above may be used in combination with each other. Several of the embodi- ments may be combined together to form a further em- bodiment .

[022] According to a second aspect, a method for manufacturing a layered photovoltaic semiconductor structure extending in a lateral direction is provid ed. The method comprises the steps of providing a p-type Si substrate having a bulk refractive index; forming a textured surface on one side of the p-type Si substrate; forming an n-type Si layer in the p-type substrate, the n-type Si layer extending from the tex tured surface, whereby a p-type layer is defined in the p-type substrate; forming a first dielectric layer on the textured surface, the first dielectric layer having a front surface opposite the n-type Si layer, the front surface defining a front side of the semi conductor structure; and forming a second dielectric layer on a side of the p-type Si substrate opposite the n-type Si layer, wherein the textured surface com prises high aspect ratio nanostructures extending in a direction substantially perpendicular to the lateral direction, the nanostructures forming an optical con version layer having an effective refractive index gradually changing towards the bulk refractive index to reduce reflection of light incident on the photo- voltaic semiconductor structure from the front side thereof .

[023] In an embodiment of the second aspect, the method further comprises the steps of forming a through-hole in the second dielectric layer; forming a conductive back layer on a side of the second dielec tric layer opposite the p-type Si layer such that a galvanic contact is formed between the conductive back layer and the p-type Si layer via the through-hole; and forming a front contact, for example, a front con tact finger, on a side of the first dielectric layer opposite the n-type Si layer such that a galvanic con tact is formed between the front contact and the n-type Si layer.

[024] In an embodiment of the second aspect, which may be in accordance with the previous embodiment, the nanostructures are formed by metal-assisted chemical etching (MACE) , atmospheric dry etching (ADE) , or re active ion etching (RIE) , such as deep reactive ion etching (DRIE) .

[025] In an embodiment of the second aspect, which may be in accordance with any of the preceding embodi ments of the second aspect, the photovoltaic semicon ductor structure is a photovoltaic semiconductor structure according to the first aspect or any embodi ment of the first aspect. It is specifically to be un derstood that the method according to the second as pect may be used to provide a photovoltaic semiconduc tor structure according to the first aspect and any number of embodiments described in relation to the first aspect.

[026] According to a third aspect, the present dis closure relates to use of high aspect ratio nanostruc tures in a photovoltaic semiconductor structure for reducing light-induced degradation (LID), e.g., boron- oxygen related LID (BO-LID) , sponge LID, copper- related LID (Cu-LID) , hydrogen-induced degrada tion (HID), and/or light and elevated-temperature in duced degradation (LeTID) .

[027] In an embodiment of the third aspect, the photovoltaic semiconductor structure is configured for use as or in a photovoltaic device, e.g., a photode tector or a solar cell, and configured to receive and absorb light incident on the photovoltaic semiconduc tor structure from a front side thereof.

[028] In an embodiment of the third aspect, which may be in accordance with the previous embodiment, the photovoltaic semiconductor structure is a photovoltaic semiconductor structure according to the first aspect or any embodiment of the first aspect. It is specifi cally to be understood that high aspect ratio nanostructures may be used according to the third as pect or any embodiment of the third aspect for reduc ing LID in a photovoltaic semiconductor structure ac cording to the first aspect or any embodiment of the first aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

[029] The present disclosure will be better under stood from the following detailed description read in light of the accompanying drawings, wherein:

FIG. 1 shows a partial cross-sectional view of a part of a photovoltaic semiconductor structure,

FIG. 2 depicts a partial cross-sectional view of another photovoltaic semiconductor structure as well as a detailed view of certain structural features in said photovoltaic semiconductor structure, and

FIG. 3 illustrates a method for manufacturing a layered photovoltaic semiconductor structure. In FIG. 3, optional steps are preceded by a dotted arrow and bounded by a dashed box.

[030] Unless specifically stated to the contrary, any drawing of the aforementioned drawings may be not drawn to scale such that any element in said drawing may be drawn with unrealistic proportions with respect to other elements in said drawing in order to empha size certain structural aspects of the embodiment of said drawing. [031] Moreover, corresponding elements in the em bodiments of any two drawings of the aforementioned drawings may be disproportionate to each other in said two drawings in order to emphasize certain structural aspects of the embodiments of said two drawings.

DETAILED DESCRIPTION

[032] Concerning the photovoltaic semiconductor structures and methods discussed in this detailed de scription, the following shall be noted.

[033] "Light-induced degradation" (LID), or "carri er-induced degradation", may refer to degradation of light-to-electricity conversion efficiency over time during operation of photovoltaics . LID may be quanti fiable, for example, after an illumination time of about 1 hour (h) , about 10 h, about 100 h, and/or about 1000 h .

[034] In semiconductor photovoltaics, several dif ferent defects may cause or be related to similar LID. Nevertheless, LID may be categorized according to sus pected LID-responsible defects and/or other mechanism- related factors at least as boron-oxygen related LID (BO-LID) , sponge LID, copper-related LID (Cu-LID) , hy drogen-induced degradation (HID) , or light and elevat ed-temperature induced degradation (LeTID) .

[035] In this specification, a "semiconductor" may refer to a material possessing a conductivity interme diate between the conductivity of conductive materi als, such as metals, and the conductivity of insulat ing materials, such as many plastics and glasses. A semiconductor may have, for example, a crystalline, such as monocrystalline, quasi-monocrystalline, or mul ticrystalline; semi-crystalline; or amorphous (i.e., non-crystalline) structure. Silicon (Si) is one exam ple of a semiconductor, or semiconducting, material. As such, Si may have a monocrystalline, quasi- monocrystalline, multicrystalline, semicrystalline, or amorphous structure.

[036] In this specification, "quasi monocrystalline" silicon (qm-Si) may refer to a sili con material grown by casting using monocrystalline silicon seeds. Additionally or alternatively, qm-Si may have a dislocation density higher than convention al monocrystalline silicon grown, for example, by a Czochralski process. Additionally or alternatively, qm-Si may comprise small-angle grain boundaries, which may be absent from or atypical for conventional mono crystalline silicon. Additionally or alternatively, qm-Si may have an oxygen concentration lower than a typical oxygen concentration of conventional monocrys talline silicon.

[037] On the other hand, "photovoltaics" may refer to a field of technology aimed at converting light to electrical energy using a light-absorbing active mate rial, such as a semiconductor, and/or to devices and structures configured to convert light to electrical energy using such active material (s) . Consequently, "semiconductor photovoltaics" may refer to photovolta ics, wherein a semiconductor is used as an active ma terial .

[038] In this specification, a "semiconductor structure" may refer to a structure which may comprise all or only part of structural parts, layers, and/or elements of a complete, operational semiconductor com ponent, element, or device such as a solar cell or a photodetector. In the case of forming only a part of such component, element, or device, the term "struc ture" may thus be considered as a structure "for", or a building block of, such component, element, or de vice. In particular, a semiconductor structure may generally comprise non-semiconducting materials, such as conductors and/or insulators, in addition to semi conductor materials.

[039] Consequently, a "photovoltaic semiconductor structure" may herein refer to a semiconductor struc ture configured, when used as or in an operational semiconductor component, element, or device, to con vert light to electrical energy using an active semi conductor material. Additionally or alternatively, a photovoltaic semiconductor structure may refer to a semiconductor structure comprising a functional p-n junction.

[040] A "functional p-n junction" may herein refer to a boundary or interface between a p-type and an n-type semiconductor that allows electrical current to flow preferentially in one direction through the boundary or interface. Additionally or alternatively, a p-n junction may refer to a boundary or interface between a p-type and an n-type semiconductor bounded under thermal equilibrium by a space charge region (i.e., a depletion region).

[041] A "p-type" semiconductor may refer to a semi conductor having a higher equilibrium concentration of holes than electrons. A p-type semiconductor may be formed by doping an intrinsic semiconductor with an electron-accepting (i.e., p-type) dopant. For example, p-type Si may comprise a significant concentration, such as from 1 0 ¹³ CITT³ to 1 0^{2 1} CITT³ , of a p-type dopant, e.g., boron (B) or gallium (Ga) .

[042] Correspondingly, an "n-type" semiconductor may refer to a semiconductor having a higher equilib rium concentration of electrons than holes. An n-type semiconductor may be formed by doping an intrinsic semiconductor with an electron-donating (i.e., n-type) dopant. For example, n-type Si may comprise a signifi cant concentration, such as from 1 0 ¹³ CITT³ to 1 0^{2 1} CITT³ , of an n-type dopant, e.g., phosphorus (P) or arsenic (As) .

[043] An "intrinsic" or "undoped" semiconductor may refer to a semiconductor not comprising a significant concentration of dopant species, such as dopant atoms. In intrinsic semiconductors, a number of electrons in a conduction band may equal a number of holes in a va lence band. P-type or n-type doping of an intrinsic semiconductor, such as pure Si, may be achieved, for example, by adding dopant species during semiconductor growth, via diffusion processes, and/or by ion implan tation .

[044] FIG. 1 depicts a cross section of a layered photovoltaic semiconductor structure 100 extending in a lateral direction 101. Although not explicitly shown in FIG. 1, the embodiment of FIG. 1 may generally com prise any features and/or elements of the embodiment of FIG. 2, which are omitted from FIG. 1.

[045] A photovoltaic semiconductor structure being "layered" and "extending in a lateral direction" may refer to a generally layer-formed structure of the photovoltaic semiconductor structure having a width in the lateral direction substantially larger than a height in a direction perpendicular to the lateral di- rection. Additionally or alternatively, a photovoltaic semiconductor structure "extending in a lateral direc tion" may herein refer to said structure extending along said lateral direction and/or along a surface, which may be planar, flat, or only slightly curved, said surface extending laterally along said lateral direction .

[046] In the embodiment of FIG. 1, the photovoltaic semiconductor structure 100 is configured for use in a photovoltaic device, e.g., a photodetector or a solar cell, and configured to receive and absorb light inci dent on the photovoltaic semiconductor structure 100 from a front side thereof (see below) . The photovolta ic semiconductor structure 100 is configured for use in a solar cell and configured to receive and absorb solar radiation.

[047] In this specification, "light" may refer to electromagnetic radiation of any wavelength within a range of relevant wavelengths. The range of relevant wavelengths may overlap or coincide with ultraviolet (wavelength from about 10 nanometers (nm) to about 400 nm) , visible (wavelength from about 400 nm to about 700 nm) , and/or infrared (wavelength from about 700 nm to about 1 millimeter (mm)) parts of electro magnetic spectrum.

[048] In other embodiments, a photovoltaic semicon ductor structure may be configured and/or suitable for use as and/or in a photovoltaic device and/or any oth er type of photovoltaic semiconductor structure known in the art. In said other embodiments, said photovol taic semiconductor structure may be configured to re ceive and absorb and/or suitable for receiving and ab sorbing light incident on the photovoltaic semiconduc tor structure from any or all side (s) thereof. A pho tovoltaic semiconductor structure may generally be configured for use in a solar cell and configured to receive and absorb solar radiation.

[049] With reference to FIG. 1, the photovoltaic semiconductor structure 100 comprises a p-type Si lay er 102 having a bulk refractive index n_b, and an n-type Si layer 103 is arranged thereon. The p-type Si layer 102 and the n-type Si layer 103 form a function al p-n junction at an interface of the p-type Si lay er 102 and the n-type Si layer 103. In other embodi ments, a p-type Si layer and an n-type Si layer may form a functional p-n junction at an interface of said p-type Si layer and said n-type Si layer. [050] In the embodiment of FIG. 1, the interface between the p-type Si layer 102 and the n-type Si lay er 103 is flat. In other embodiments, an interface be tween a p-type Si layer and an n-type Si layer may have a flat, curved, or any other suitable shape.

[051] In the embodiment of FIG. 1, the p-type Si layer 102 comprises boron as a dopant and the n-type Si layer 103 comprises phosphorus as a dopant. In oth er embodiments, a p-type Si layer may comprise boron and/or any other suitable p-type dopant.

[052] Generally, an n-type Si layer may comprise a substantial amount of phosphorus and/or any other suitable n-type dopant. Additionally or alternatively, at least part of an n-type Si layer may comprise a high concentration, i.e., at least 10¹⁸ CITT³ , or at least 10¹⁹ CITT³ , or at least 10²⁰ CITT³ , of phosphorus as a dopant .

[053] At least part of an n-type Si layer compris ing a high concentration of phosphorus as a dopant may enhance gettering of LID-responsible defects. Herein, "gettering" may refer to the removal of defects, espe cially LID-responsible defects, such as impurities, for example, impurity atoms (e.g., iron atoms), from an active material of a photovoltaic semiconductor structure, and/or it may refer to gathering defects, especially LID-responsible defects, to grain and/or material boundaries.

[054] With reference to FIG. 1, the p-type Si lay er 102 and the n-type Si layer 103 are multicrystal line silicon (mc-Si) layers.

[055] In other embodiments, a p-type Si layer may be monocrystalline, quasi-monocrystalline, multicrys talline, semicrystalline, or amorphous. In said other embodiments, an n-type Si layer may be monocrystal line, quasi-monocrystalline, multicrystalline, semi- crystalline, or amorphous. A p-type Si layer and an n-type Si layer may have identical, corresponding, or similar structures, and/or said p-type Si layer and said n-type Si layer may form a single monolithic Si substrate.

[056] In this specification, a "substrate" may re fer to a solid body providing a surface, which may be flat or only slightly curved, such that material may be arranged, deposited, etched, and/or inscribed on the surface. For example, a substrate may comprise a wafer, comprising a semiconductor material, such as Si, suitable for manufacturing various semiconductor structures and/or devices, e.g., integrated circuits, solar cells, or photodetectors.

[057] In general, a p-type Si layer and an n-type

Si layer being multicrystalline may enable the utili zation of a mc-Si substrate in the fabrication of a photovoltaic semiconductor structure. Utilization of such mc-Si substrates may, for example, improve an En- ergy Return on Energy Invested (ERoEI) metric of a photovoltaic semiconductor structure. On the other hand, a p-type Si layer and an n-type Si layer being quasi-monocrystalline may enable the utilization of a qm-Si substrate, which may provide a balanced trade- off between light-to-electricity efficiency and scala bility.

[058] In the embodiment of FIG. 1, the n-type Si layer 103 has a textured surface 104 opposite the p-type Si layer 102. A "textured" surface may refer to a non-smooth and/or patterned surface. A textured sur face may generally have a regular texture or an irreg ular texture. A textured surface having an irregular texture may improve optical properties of a photovol taic semiconductor structure.

[059] With reference to FIG. 1, the textured sur face 104 has at least a sufficient size in the lateral direction 101 that a macroscopic portion of the tex tured surface 104 may be defined. Additionally, a ra tio, S_f, between a surface area of a macroscopic por tion of the textured surface 104 and a surface area of a polished surface corresponding to the macroscopic portion, e.g., a highest projected area of the macro scopic portion, is more than 3, or at least 4, or at least 5, or in a range from 5 to 7.

[060] Generally, a photovoltaic semiconductor structure with an S_f of more than 3, or at least 4, or at least 5, or in a range from 5 to 7, may experience weaker LID than photovoltaic semiconductor structures with lower values of S_f. This may be especially so if said photovoltaic semiconductor structure comprises an n-type Si layer comprising phosphorus as a dopant.

[061] In this specification, "macroscopic portion" may refer to a portion sufficiently large to be visi ble to the naked eye. Additionally or alternatively, a macroscopic portion may have a size such that a high est projected area of the macroscopic portion is at least 0.01 mm², or at least 0.1 mm², or at least 1 mm², or at least 10, or at least 100 mm². Additionally or alternatively, a macroscopic portion may encompass at least 2500, or at least 10000, or at least 1000000 texture units, such as high aspect ratio nanostruc tures (see below) .

[062] Herein, "projected area" may refer to an area of a projection of an object onto an arbitrary plane. Consequently, a "highest" projected area may refer to an area of a projection of an object onto a plane such that the projection has an area higher than or equal to the area of any other planar projection of said ob ject. Such plane may extend, for example, along a lat eral direction.

[063] In the embodiment of FIG. 1, the textured surface 104 comprises high aspect ratio nanostruc- tures 105 that extend in a direction substantially perpendicular to the lateral direction 101. In FIG. 1, the nanostructures 105 have been depicted with greatly exaggerated sizes for illustrative purposes.

[064] "Nanostructure" may herein refer to a struc ture having at least one characteristic dimension in the sub-micron range, i.e., equal to or less than a micrometer. From an optical point of view, such dimen sions fall substantially in the range of, or below, relevant wavelengths in typical photovoltaics .

[065] "High aspect ratio" nanostructures extending in a direction substantially perpendicular to the lat eral direction may refer to nanostructures having their height multiple times their lateral dimensions. Such nanostructures may comprise, for example, cylin drical pillars, conical pillars, or narrow pyramids.

[066] In this specification, a first direction be ing "substantially perpendicular" to a second direc tion may refer to the first direction forming a small- est positive angle of at least 75°, or at least 80°, or at least 85°, or about 90°, with the second direc tion in a vector sense.

[067] In general, high aspect ratio nanostructures extending in a direction substantially perpendicular to a lateral direction may reduce, or suppress, LID in a photovoltaic semiconductor structure.

[068] In the embodiment of FIG. 1, the high aspect ratio nanostructures 105 are formed by deep reactive ion etching (DRIE) . As known for those skilled in the art, "deep reactive ion etching" may refer to a spe cific type of reactive ion etching (RIE) process, which may be an anisotropic etching process suitable for forming various high aspect ratio Si nanostruc tures. In other embodiments, high aspect ratio nanostructures may be formed by RIE, such as DRIE, or by any other suitable method known in the art.

[069] With reference to FIG. 1, the photovoltaic semiconductor structure 100 further comprises a first dielectric layer 107 on the textured surface 104 oppo site the p-type Si layer 102. The first dielectric layer 107 has a front surface 108 opposite the n-type Si layer 103, the front surface 108 defining the front side of the photovoltaic semiconductor structure 100.

[070] In general, a first dielectric layer on a textured surface may passivate said textured surface. Herein, a surface becoming "passivated" may refer to a surface, following the provision of a passivating sur face layer (e.g., said first dielectric layer), becom ing less affected by external stimuli and/or causing reduced surface recombination of charge carriers.

[071] In the embodiment of FIG. 1, the first die lectric layer 107 covers the high aspect ratio nanostructures 105 in a substantially conformal man ner. Such conformal coating may be achieved, for exam ple, by forming the first dielectric layer by atomic layer deposition (ALD) . In other embodiments, a first dielectric layer may cover the textured surface in substantially conformal manner or in any other suita ble manner, and the first dielectric layer may be formed by ALD or by any other suitable method known in the art .

[072] A layer covering a nanostructure in a "sub stantially conformal manner" may refer to the layer following the nanostructure with a substantially uni form thickness. Herein, a "substantially uniform thickness" may refer to a relative standard deviation in thickness of less than 50 %, or less than 25 %, or less than 15 %, and/or to a standard deviation in thickness of less than 20 nm, or less than 10 nm, or less than 5 nm. [073] In general, a thickness of a first dielectric layer may be measureable from a front surface to a textured surface along a surface normal of the tex tured surface. For example, the thickness may be equal to a length of a shortest line segment extending from a measurement point on the front surface to the tex tured surface along a surface normal of the textured surface .

[074] A first dielectric layer covering high aspect ratio nanostructures in a substantially conformal man ner may provide an efficiently passivated textured surface .

[075] With reference to FIG. 1, the thickness of the first dielectric layer 107 is, on average, in a range from about 5 nm to 40 nm, or from about 5 nm to 20 nm, or from about 5 nm to 15 nm, or from about 5 nm to about 10 nm. Such thickness may generally facili tate forming electrical contacts for an n-type Si lay er. In other embodiments, a first dielectric layer may have a similar thickness or any other suitable thick ness. A first dielectric layer may generally be sub stantially pinhole-free, comprising an insubstantial number of pinholes per unit area.

[076] In the embodiment of FIG. 1, the first die lectric layer 107 comprises non-stoichiometric alumin ium oxide (AIOc) . In other embodiments, a first die lectric layer may comprise A10_x and/or any other suit able material (s) , for example, a transparent oxide and/or nitride, e.g., silicon oxide (Si0₂₎ , non- stoichiometric silicon oxide (SiO_x) , aluminium oxide (AI2O3) , silicon nitride (S 3N₄₎ , and/or non- stoichiometric silicon nitride (SiN_x) .

[077] Herein, "transparent" or "transparency" may refer to a capability of a layer formed of a transpar ent material to transmit a main portion of irradiance of light at a relevant wavelength range incident on such layer. In case of a photovoltaic semiconductor structure, said relevant wavelength range may refer to intended operation wavelengths of said photovoltaic semiconductor structure. For example, a transparent layer may transmit 50 % or more, or 80 % or more, of irradiance of light energy at a relevant wavelength range incident onto it. An increase in transparency of dielectric layers may generally improve a light-to- electricity conversion efficiency of a photovoltaic semiconductor structure.

[078] Different material compositions of first die lectric layers may provide various technical benefits. For example, a first dielectric layer comprising A10_x may passivate a Si surface, such as a b-Si surface, efficiently due to a high-quality interface with Si. Furthermore, A10_x may passivate b-Si surfaces particu larly efficiently due to a high density of negative fixed charges in A10_x.

[079] With reference to FIG. 1, the high aspect ra tio nanostructures 105 form an optical conversion lay er 106 having an effective refractive index n_eff gradu ally changing towards the bulk refractive index n_b to reduce reflection of light incident on the photovolta ic semiconductor structure 100 from the front side thereof .

[080] An "optical conversion layer" may refer to a layer, which may be indefinable based on continuous material interfaces, such as lateral interfaces, hav ing an effective refractive index n_eff which gradually changes from an ambient refractive index n_b towards a bulk refractive index n_b to reduce reflection of light incident on a photovoltaic semiconductor structure from a front side thereof. For example, where the pho todetector structure is designed to be used under ex posure to ambient air with a refractive index of 1, the effective refractive index may gradually change from 1 to the bulk refractive index n_b.

[081] "Effective refractive index" is an auxiliary definition related to interaction of light with a nanostructured material layer. Sub-wavelength features or features substantially in the range of relevant wavelengths make light behave in such a nanostructured layer differently from a corresponding layer of the same material without the nanostructures. This differ ent behavior can be described by the auxiliary term "effective refractive index"; light behaves in, and interacts with, such a nanostructured material layer as if the layer would be made of a gradually changing bulk material having, at each level of the conversion layer, a refractive index equal to the effective re fractive index n_eff at that level.

[082] In the embodiment of FIG. 1, the nanostruc tures 105 are black silicon (b-Si) spikes. Herein, "black silicon" may refer to a class of nanoscale sur face formations on Si, producing an optical conversion layer having a gradually changing effective refractive index. A b-Si surface may comprise a plurality of nee dle- and/or spike-like surface formations. Individual surface formations of such a plurality of surface for mations may be of varying sizes and/or arranged irreg ularly. In other embodiments, nanostructures may be b-Si spikes or any other nanostructures suitable for forming an optical conversion layer having an effec tive refractive index gradually changing towards a bulk refractive index.

[083] In general, nanostructures being b-Si spikes may, for example, improve efficiency of a photovoltaic semiconductor structure at high incidence angles, such as incidence angles larger than 60°.

[084] In this specification, an "incidence angle", or "angle of incidence", may refer to a smallest angle between a propagation direction of a ray of light in cident on a surface and a normal of the surface ex tending from a point of incidence of said ray of light. Additionally or alternatively, an incidence an gle may refer to a smallest angle between a propaga tion direction of light incident on a macroscopic por tion of a textured surface and a normal of a polished surface corresponding to the macroscopic portion, e.g., a normal of a plane corresponding to a highest projected area of the macroscopic portion.

[085] With reference to FIG. 1, the nanostruc tures 105 have their average height in a direction perpendicular to the lateral direction in a range from 500 nm to 1500 nm, or from about 600 nm to 1000 nm, or from 800 nm to 1000 nm, and their average width in the lateral direction 101 in a range from 50 nm to 400 nm, or from 100 nm to 400 nm, or from 200 nm to 300 nm. In other embodiments, nanostructures may have average heights and/or widths identical, similar, or different to the average height and/or width, respectively, of the nanostructures 105 of the embodiment of FIG. 1.

[086] High aspect ratio nanostructures having their average height in a direction perpendicular to the lateral direction in a range from 500 nm to 1500 nm, or from about 600 nm to 1000 nm, or from 800 nm to 1000 nm, and their average width in a lateral direc tion in a range from 50 nm to 400 nm, or from 100 nm to 400 nm, or from 200 nm to 300 nm may yield a solar spectrum-weighted average reflectance that is practi cally negligible, e.g., less than 2 %, or less than 1 %, or less than 0.8 %, without the addition of anti reflection coatings (ARCs) .

[087] With reference to FIG. 1, the photovoltaic semiconductor structure 100 further comprises a second dielectric layer 109 on a side of the p-type Si lay er 102 opposite the n-type Si layer 103. The second dielectric layer 109 is directly coupled to the p-type Si layer 102. In other embodiments, a second dielec tric layer may be coupled directly or indirectly, via any appropriate additional layers, to a p-type Si lay er .

[088] Generally, a second dielectric layer on a side of a p-type Si layer opposite an n-type Si layer may reduce surface recombination of charge carriers and/or increase overall absorbance of light incident on a photovoltaic semiconductor structure.

[089] In the embodiment of FIG. 1, the second die lectric layer 109 comprises A10_x and SiN_x. In other em bodiments, a second dielectric layer may comprise any suitable material (s) , for example, a transparent oxide and/or nitride, e.g., Si0₂, SiO_x, AI₂O₃, A10_x, S ₃N₄, and/or SiN_x.

[090] Different material compositions of second di electric layers may provide various technical bene fits. For example, a second dielectric lay er comprising A10_x may passivate a Si surface, such as a b-Si surface, efficiently due to a high-quality in terface with Si. Furthermore, A10_x may passivate b-Si surfaces particularly efficiently due to a high densi ty of negative fixed charges in A10_x. As a further ex ample, a second dielectric layer comprising SiN_x may be fabricable rapidly.

[091] FIG. 2 shows a cross-sectional view of a lay ered photovoltaic semiconductor structure 200 extend ing in a lateral direction 201. Although not explicit ly shown in FIG. 1, the embodiment of FIG. 2 may gen erally comprise any features and/or elements of the embodiment of FIG. 1, which are omitted from FIG. 2. In particular, the embodiment of FIG. 2 may comprise high aspect ratio nanostructures and a first dielec tric layer similar or identical in shape to the high aspect ratio nanostructures and the first dielectric layers, respectively, of any of the embodiments dis cussed above with reference to FIG. 1.

[092] In the embodiment of FIG. 2, the photovoltaic semiconductor structure 200 is configured for use as a photovoltaic device, e.g., a photodetector or a solar cell, and configured to receive and absorb light inci dent on the photovoltaic semiconductor structure 200 from a front side thereof (see below) . The photovolta ic semiconductor structure 200 is configured for use as a solar cell and configured to receive and absorb solar radiation. In particular, the photovoltaic semi conductor structure 200 of the embodiment of FIG. 2 forms a part of a passivated emitter and rear cell (PERC) photovoltaic device. In other embodiments, a photovoltaic semiconductor structure may be, form a part of, and/or be suitable for a PERC photovoltaic device or structure or any other suitable photovoltaic device or structure.

[093] Herein, a "passivated emitter and rear cell" or "PERC" photovoltaic structure may refer to a photo voltaic structure belonging to a family of structural ly similar photovoltaic structures, wherein any photo voltaic structure of said family of photovoltaic structures may be characterizable at least by a pas sivating dielectric front layer and a dielectrically displaced conductive back layer. A PERC photovoltaic structure may correspond, for example, to a passivated emitter, rear directly contacted (PERD) structure; a passivated emitter, rear locally doped (PERL) struc ture; a passivated emitter, rear totally diffused (PERT) structure; or a passivated emitter, rear float ing junction (PERF) structure. Correspondingly, a PERC, PERD, PERL, PERT, or PERF photovoltaic device may refer to a device comprising a PERC, PERD, PERL, PERT, or PERF photovoltaic structure, respectively. [094] With reference to FIG. 2, the photovoltaic semiconductor structure 200 comprises a p-type Si lay er 202 having a bulk refractive index, and an n-type Si layer 203 is arranged thereon. The n-type Si lay er 203 has a textured surface 204 opposite the p-type Si layer 202, the textured surface 204 comprising high aspect ratio nanostructures 205 that form an optical conversion layer 206 having an effective refractive index gradually changing towards the bulk refractive index to reduce reflection of light incident on the photovoltaic semiconductor structure 200 from the front side thereof, as defined by a front surface 208 of a first dielectric layer 207 on the textured sur face 204 of the n-type Si layer 203.

[095] In the embodiment of FIG. 2, the photovoltaic semiconductor structure 200 further comprises a front contact finger 212, constituting an example of a front contact, on a side of the first dielectric layer oppo site the n-type Si layer 203, a second dielectric lay er 209 on a side of the p-type Si layer 202 opposite the n-type Si layer 203, as well as a conductive back layer 211 on a side of the second dielectric layer 209 opposite the p-type Si layer 202. The second dielec tric layer 209 is patterned with a through-hole 210, and a galvanic contact exists between the conductive back layer 211 and the p-type Si layer 202 via the through-hole 210. A galvanic contact exists also be tween the front contact finger 212 and the n-type Si layer 203.

[096] In some embodiments, a front contact may be a front contact finger or any other suitable type of front contact known in the art.

[097] In an embodiment, which may be basically in accordance with the embodiment of FIG. 2, a galvanic contact exists between a p-type Si layer and a conduc tive back layer in the absence of a through-hole. [098] Herein a "front contact" may refer to a body or layer of non-insulating, or conductive, material, suitable for transmitting electrical current. Addi tionally or alternatively, in case a photovoltaic sem- iconductor structure is configured for use as or in a photovoltaic device, a front contact may be configured to collect electrical current generated by said photo voltaic device to an external electrical circuit or device. Consequently, a "front contact finger" may re- fer to a front contact shaped as a slim, continuous body. Generally, a front contact may reduce a series resistance of a photovoltaic semiconductor structure.

[099] Herein, a layer being "patterned with a through-hole" may refer to the shape of said layer be- ing such that said layer comprises a discontinuity.

Additionally or alternatively, a layer patterned with a through-hole may comprise a hole in a topological (homeomorphism) sense. A second dielectric layer being patterned with a through-hole may facilitate forming an electrical connection with a p-type Si layer.

[100] Additionally, the existence of a "galvanic contact" between two elements may refer to an electri cal connection between said elements that enables a constant flow of direct (i.e., unidirectional) elec- trical current between said elements. A galvanic con tact may refer to an electrical connection between two solid elements that provides an electrical direct cur rent path passing through solid matter only. Addition ally or alternatively, a galvanic contact may exist between said two elements even if a magnitude of a voltage (i.e., an electrical potential difference) be tween said two elements is 20 volts (V) or less, or 10 V or less, or 5 V or less, or 2 V or less, or 1 V or less. Generally, a galvanic contact may exist be tween two non-insulating elements separated by a die lectric element by virtue of charge carrier tunneling. [101] Above, mainly structural and material aspects of photovoltaic semiconductor structures are dis cussed. In the following, more emphasis will lie on manufacturing aspects related to photovoltaic semicon ductor structures. What is said above about the ways of implementation, definitions, details, and ad vantages related to the structural and material as pects apply, mutatis mutandis, to the method aspects discussed below. The same applies vice versa.

[102] FIG. 3 illustrates a method 300 for manufac turing a layered photovoltaic semiconductor structure extending in a lateral direction. Such layered photo voltaic semiconductor structure may be in accordance with any of those discussed above with reference to FIGs. 1 and/or 2. In FIG. 3, optional steps (i.e., a step 306 of forming a through-hole, a step 307 of forming a conductive back layer, and a step 308 of forming a front contact) are preceded by a dotted ar row and bounded by a dashed box, which is further la beled as "OPTIONAL".

[103] In the embodiment of FIG. 3, the method 300 comprises a step 301 of providing a p-type substrate having a bulk refractive index; a step 302 of forming a textured surface on one side of the p-type Si sub strate; a step 303 of forming an n-type Si layer in the p-type substrate, the n-type Si layer extending from the textured surface, whereby a p-type layer is defined in the p-type substrate; a step 304 of forming a first dielectric layer on the textured surface, the first dielectric layer having a front surface opposite the n-type Si layer, and the front surface defining a front side of the semiconductor structure; and a step 305 of forming a second dielectric layer on a side of the p-type Si substrate opposite the n-type Si layer . [104] In general, any steps, corresponding to the step 303 of forming an n-type Si layer, of a method for manufacturing a layered photovoltaic semiconductor structure may comprise a phosphorus diffusion step. Said phosphorus diffusion step may comprise or corre spond to a phosphoryl trichloride (POCI₃) diffusion step. A phosphorus diffusion step may generally yield a high concentration, i.e., at least 10¹⁸ CITT³ , or at least 10¹⁹ CITT³ , or at least 10²⁰ CITT³ , of dopant phos phorus atoms in at least part of an n-type Si layer, especially if said n-type Si layer has a textured sur face comprising nanostructures with high S_f values.

[105] With reference to FIG. 3, the first dielec tric layer is formed in the step 304 by ALD such that the first dielectric layer covers the nanostructures in a substantially conformal manner. In other embodi ments, a first dielectric layer may be formed by ALD or by any other suitable method known in the art. In some embodiments, a first dielectric layer may cover the textured surface in substantially conformal man ner, whereas in other embodiments, a first dielectric layer may cover the textured surface in any other suitable manner.

[106] Herein, "atomic layer deposition" may refer to a process, wherein a substrate is alternately ex posed to at least two precursors, one precursor at a time, to form a coating on said substrate by alter nately repeating essentially self-limiting surface re actions between a surface of said substrate (on the later stages, naturally, a surface of an already- formed coating layer on said substrate) and said at least two precursors. As a result, coating material is "grown" on said substrate molecule layer by molecule layer. This enables accurate and well-controlled pro duction of thin film coatings. [107] In general, forming a first dielectric layer by ALD may facilitate forming said first dielectric layer in a substantially conformal manner, which may facilitate forming an efficiently passivated textured surface .

[108] With reference to FIG. 3, the textured sur face comprises high aspect ratio nanostructures ex tending in a direction substantially perpendicular to the lateral direction, the nanostructures forming an optical conversion layer having an effective refrac tive index gradually changing towards the bulk refrac tive index to reduce reflection of light incident on the photovoltaic semiconductor structure from the front side thereof.

[109] In the embodiment of FIG. 3, the nanostruc tures are formed by RIE, more specifically by DRIE. In other embodiments, nanostructures may be formed by RIE, such as DRIE, or by any other suitable method known in the art, such as metal-assisted chemical etching (MACE) or atmospheric dry etching (ADE) .

[110] In general, forming high aspect ratio nanostructures by RIE, especially DRIE, may, for exam ple, facilitate making the nanostructures, such as b-Si spikes, deeper, increasing their aspect ratio, which may eliminate a need for any ARCs and/or further improve optical properties. Additionally or alterna tively, forming high aspect ratio nanostructures by RIE, especially DRIE, may facilitate producing lattice defect-free high aspect ratio nanostructures, such as b-Si spikes, eliminating the need for any post-etching polishing steps. On the other hand, forming high as pect ratio nanostructures by MACE or ADE may, for ex ample, facilitate producing said high aspect ratio nanostructures in a highly scalable and/or rapid man ner . [111] With reference to FIG. 3, the method 300 fur ther comprises the optional step 306 of forming a through-hole in the second dielectric layer, the op tional step 307 of forming a conductive back layer on a side of the second dielectric layer opposite the p-type Si layer such that a galvanic contact is formed between the conductive back layer and the p-type Si layer via the through-hole, and the optional step 308 of forming a front contact, for example, a front con tact finger, on a side of the first dielectric layer opposite the n-type Si layer such that a galvanic con tact is formed between the front contact and the n-type Si layer.

[112] In the embodiment of FIG. 3, the front con tact is formed by applying silver metallization paste onto the first dielectric layer and subsequently fir ing said paste at a firing temperature in a range of from about 650°C to about 850°C for a few seconds (s) , e.g., 3, 5, or 8 s. In other embodiments, a front con tact, for example, a front contact finger, may be formed by applying and firing any suitable metalliza tion paste, e.g., a silver, aluminum, or sil ver-aluminum paste, or by any other suitable method known in the art.

[113] In an embodiment, a method for manufacturing a layered photovoltaic semiconductor structure extend ing in a lateral direction comprises steps correspond ing to the steps of the method 300 of the embodiment of FIG. 3. In other embodiments, a method for manufac turing a layered photovoltaic semiconductor structure extending in a lateral direction may comprise steps corresponding to the compulsory (i.e., non-optional ) steps 301, 302, 303, 304, 305 of the method 300 of the embodiment of FIG. 3. In some embodiments, a method for manufacturing a layered photovoltaic semiconductor structure extending in a lateral direction may com- prise steps corresponding to the compulsory steps 301,

302, 303, 304, 305 of the method 300 of the embodiment of FIG. 3, as well as at least one step corresponding to at least one of the optional steps 306, 307, 308 of the method 300 of the embodiment of FIG. 3.

[114] Generally, steps corresponding to the compul sory steps 301, 302, 303, 304, 305 and any steps cor responding to the optional steps 306, 307, 308 of a method for manufacturing a layered photovoltaic semi conductor structure extending in a lateral direction need not be executed in a fixed order or even sequen tially. However, any steps corresponding to the step 301 of providing a p-type substrate are executed prior to any steps corresponding to the steps 302,

303, 304, 305, 306, 307, and 308; any steps corre sponding to the step 302 of forming a textured surface are executed prior to any steps corresponding to the steps 304 and 308; any steps corresponding to the step 303 of forming an n-type Si layer may be executed prior to any steps corresponding to the steps 304 and 308; any steps corresponding to the step 304 of form ing a first dielectric layer are executed prior to any steps corresponding to the step 308; any steps corre sponding to the step 305 of forming a second dielec tric layer are executed prior to any steps correspond ing to the step 307 and optionally prior to any steps corresponding to the step 306; and any steps corre sponding to the step 306 of forming a through-hole may be executed prior to any steps corresponding to the step 307.

[115] In general, a method for manufacturing a lay ered photovoltaic semiconductor structure extending in a lateral direction may comprise any number of addi tional steps that are not disclosed herein in connec tion to the method 300 of the embodiment of FIG. 3. Such additional steps may comprise, for example, cleaning, annealing, etching, deposition, and/or la beling steps.

[116] It is obvious to a person skilled in the art that with the advancement of technology, the basic idea of the invention may be implemented in various ways. The invention and its embodiments are thus not limited to the embodiments described above, instead they may vary within the scope of the claims.

[117] It will be understood that any benefits and advantages described above may relate to one embodi ment or may relate to several embodiments. The embodi ments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages.

[118] The term "comprising" is used in this speci fication to mean including the feature (s) or act(s) followed thereafter, without excluding the presence of one or more additional features or acts. It will fur ther be understood that reference to 'an' item refers to one or more of those items.

REFERENCE SIGNS

100 photovoltaic semiconductor structure

101 lateral direction

102 p-type Si layer

103 n-type Si layer

104 textured surface

105 nanostructure

106 optical conversion layer

107 first dielectric layer

108 front surface 109 second dielectric layer

200 photovoltaic semiconductor structure

201 lateral direction

202 p-type Si layer

203 n-type Si layer

204 textured surface

205 nanostructure

206 optical conversion layer

207 first dielectric layer

208 front surface

209 second dielectric layer

210 through-hole

211 conductive back layer

212 front contact finger

300 method

301 step of providing a p-type substrate

302 step of forming a textured surface

303 step of forming an n-type Si layer

304 step of forming a first dielectric layer

305 step of forming a second dielectric layer

306 step of forming a through-hole

307 step of forming a conductive back layer

308 step of forming a front contact

Claims

1. A layered photovoltaic semiconductor structure (100, 200) extending in a lateral direc tion (101, 201), comprising:

- a p-type silicon, Si, layer (102, 202) having a bulk refractive index;

- an n-type Si layer (103, 203) on the p-type Si layer (102, 202), the n-type Si layer (103, 203) having a textured surface (104, 204) opposite the p-type Si layer (102, 202);

- a first dielectric layer (107, 207) on the tex tured surface (104, 204), the first dielectric layer (107, 207) having a front sur face (108, 208) opposite the n-type Si lay er (103, 203), the front surface (108, 208) de fining a front side of the photovoltaic semicon ductor structure (100, 200); and

- a second dielectric layer (109, 209) on a side of the p-type Si layer (102, 202) opposite the n-type Si layer (103, 203);

wherein the textured surface (104, 204) comprises high aspect ratio nanostructures (105, 205) extending in a direction substantially perpendicular to the lateral direction (101, 201), the nanostructures forming an optical conversion layer (106, 206) having an effec tive refractive index gradually changing towards the bulk refractive index to reduce reflection of light incident on the photovoltaic semiconductor struc ture (100, 200) from the front side thereof.

2. A photovoltaic semiconductor struc ture (100, 200) according to claim 1, wherein the sec ond dielectric layer (109, 209) is patterned with a through-hole (210), and the photovoltaic semiconductor structure (100, 200) further comprises: - a conductive back layer (211) on a side of the second dielectric layer (109, 209) opposite the p-type Si layer (102, 202), a galvanic contact existing between the conductive back layer (211) and the p-type Si layer (102, 202) via the through-hole (210); and

- a front contact, for example, a front contact finger (212), on a side of the first dielectric layer (107, 207) opposite the n-type Si lay er (103, 203), a galvanic contact existing be tween the front contact and the n-type Si lay er (103, 203) .

3. A photovoltaic semiconductor struc ture (100, 200) according to claim 1 or claim 2, wherein the photovoltaic semiconductor structure (100, 200) is or forms a part of a passivated emitter and rear cell, PERC, photovoltaic device or structure.

4. A photovoltaic semiconductor struc ture (100, 200) according to any of the preceding claims, wherein the first dielectric layer covers the nanostructures in a substantially conformal manner.

5. A photovoltaic semiconductor struc ture (100, 200) according to claim 4, wherein the first dielectric layer (107, 207) is formed by atomic layer deposition, ALD.

6. A photovoltaic semiconductor struc ture (100, 200) according to any of the preceding claims, wherein the nanostructures (105, 205) are formed by deep reactive ion etching, DRIE.

7. A photovoltaic semiconductor struc ture (100, 200) according to any of the preceding claims, wherein a ratio, S_f, between a surface area of a macroscopic portion of the textured surface (104, 204) and a surface area of a polished surface corre sponding to the macroscopic portion, e.g., a highest projected area of the macroscopic portion, is more than 3, or at least 4, or at least 5, or in a range from 5 to 7.

8. A photovoltaic semiconductor struc ture (100, 200) according to any of the preceding claims, wherein the nanostructures (105, 205) are black silicon, b-Si, spikes.

9. A photovoltaic semiconductor struc ture (100, 200) according to any of the preceding claims, wherein the nanostructures (105, 205) have their average height in a direction perpendicular to the lateral direction (101, 201) in a range from

500 nm to 1500 nm, or from about 600 nm to 1000 nm, or from 800 nm to 1000 nm, and their average width in the lateral direction (101, 201) in a range from 50 nm to

400 nm, or from 100 nm to 400 nm, or from 200 nm to 300 nm.

10. A photovoltaic semiconductor struc ture (100, 200) according to any of the preceding claims, wherein the p-type Si layer (102, 202) and the n-type Si layer (103, 203) are multicrystalline sili con, mc-Si, layers or quasi-monocrystalline silicon, qm-Si, layers.

11. A photovoltaic semiconductor struc ture (100, 200) according to any of the preceding claims, wherein the p-type Si layer (102, 202) com prises boron as a dopant and/or the n-type Si lay er (103, 203) comprises phosphorus as a dopant.

12. A photovoltaic semiconductor struc ture (100, 200) according to any of the preceding claims, wherein the first dielectric layer (107, 207) comprises a transparent oxide and/or nitride, e.g., silicon oxide SiCy, non-stoichiometric silicon oxide SiO_x, aluminium oxide AI₂O₃, non-stoichiometric alumin- ium oxide A10_x, silicon nitride S1₃N₄, and/or non- stoichiometric silicon nitride SiN_x.

13. A photovoltaic semiconductor struc ture (100, 200) according to any of the preceding claims, wherein the second dielectric layer (109, 209) comprises a transparent oxide and/or nitride, e.g., silicon oxide SiCy, non-stoichiometric silicon oxide SiO_x, aluminium oxide AI2O3, non-stoichiometric alumin ium oxide AIO_c, silicon nitride S 3N₄, and/or non- stoichiometric silicon nitride SiN_x.

14. A photovoltaic semiconductor struc ture (100, 200) according to any of the preceding claims, wherein the photovoltaic semiconductor struc ture (100, 200) is configured for use as or in a pho tovoltaic device, e.g., a photodetector or a solar cell, and configured to receive and absorb light inci dent on the photovoltaic semiconductor structure (100, 200) from the front side thereof.

15. A method (300) for manufacturing a lay ered photovoltaic semiconductor structure extending in a lateral direction, the method (300) comprising the steps of:

- providing a p-type Si substrate (301) having a bulk refractive index;

- forming a textured surface (302) on one side of the p-type Si substrate;

- forming an n-type Si layer (303) in the p-type substrate, the n-type Si layer extending from the textured surface, whereby a p-type layer is de fined in the p-type substrate;

- forming a first dielectric layer (304) on the textured surface, the first dielectric layer hav ing a front surface opposite the n-type Si layer, the front surface defining a front side of the semiconductor structure; and - forming a second dielectric layer (305) on a side of the p-type Si substrate opposite the n-type Si layer;

wherein the textured surface comprises high aspect ra tio nanostructures extending in a direction substan tially perpendicular to the lateral direction, the nanostructures forming an optical conversion layer having an effective refractive index gradually chang ing towards the bulk refractive index to reduce re flection of light incident on the photovoltaic semi conductor structure from the front side thereof.

16. A method (300) according to claim 15, further comprising the steps of:

- forming a through-hole (306) in the second die lectric layer;

- forming a conductive back layer (307) on a side of the second dielectric layer opposite the p-type Si layer such that a galvanic contact is formed between the conductive back layer and the p-type Si layer via the through-hole; and

- forming a front contact (308), for example, a front contact finger, on a side of the first die lectric layer opposite the n-type Si layer such that a galvanic contact is formed between the front contact and the n-type Si layer.

17. A method (300) according to any of claims 15 to 16, wherein the nanostructures are formed by metal-assisted chemical etching, MACE; atmospheric dry etching, ADE; or reactive ion etching, RIE, such as deep reactive ion etching, DRIE.

18. A method (300) according to any of claims 15 to 17, wherein the photovoltaic semiconduc tor structure is a photovoltaic semiconductor struc ture (100, 200) according to any of claims 1 to 14.

19. Use of high aspect ratio nanostructures in a photovoltaic semiconductor structure for reducing light-induced degradation, LID, e.g., boron-oxygen re lated LID, BO-LID; sponge LID; copper-related LID, Cu-LID; hydrogen-induced degradation, HID; and/or light and elevated-temperature induced degradation, LeTID.

20. A use according to claim 19, wherein the photovoltaic semiconductor structure is configured for use as or in a photovoltaic device, e.g., a photode tector or a solar cell, and configured to receive and absorb light incident on the photovoltaic semiconduc tor structure from a front side thereof.

21. A use according to any of claims 19 to 20, wherein the photovoltaic semiconductor structure is a photovoltaic semiconductor structure (100, 200) according to any of claims 1 to 14.