WO2019087699A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2019087699A1
WO2019087699A1 PCT/JP2018/037537 JP2018037537W WO2019087699A1 WO 2019087699 A1 WO2019087699 A1 WO 2019087699A1 JP 2018037537 W JP2018037537 W JP 2018037537W WO 2019087699 A1 WO2019087699 A1 WO 2019087699A1
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WO
WIPO (PCT)
Prior art keywords
electrode
chip
pulse signal
pad
power supply
Prior art date
Application number
PCT/JP2018/037537
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English (en)
French (fr)
Japanese (ja)
Inventor
好則 佐藤
原　英夫
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by ローム株式会社 filed Critical ローム株式会社
Priority to JP2019550949A priority Critical patent/JP6901583B2/ja
Priority to CN201880070579.5A priority patent/CN111295746B/zh
Publication of WO2019087699A1 publication Critical patent/WO2019087699A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines

Definitions

  • the invention disclosed in the present specification relates to a semiconductor device (for example, a combined isolator) that handles pulse signals.
  • a semiconductor device for example, a combined isolator
  • the isolation between the primary circuit system and the secondary circuit system is magnetically coupled using an isolator.
  • patent document 1 can be mentioned as an example of the prior art relevant to the above.
  • the invention disclosed in the present specification aims at providing a semiconductor device capable of reducing noise of a pulse signal in view of the above-mentioned problem found by the inventor of the present application.
  • the semiconductor device disclosed in the present specification includes a first chip on the transmitting side of a pulse signal, a second chip on the receiving side of the pulse signal, and the first chip and the first chip using an integration transformer. And a third chip for transmitting the pulse signal from the first chip to the second chip while electrically insulating between the second chip and the second chip, wherein the second chip and the third chip are each upstream
  • the second electrode may be formed using a metal layer or a polysilicon layer (second configuration).
  • the second electrode may have a configuration (third configuration) having an area equal to or larger than that of the first electrode in a plan view thereof.
  • At least one of the first electrode and the second electrode may be short-circuited between the first electrode and the second electrode. It is preferable that the intermediate electrode is provided (fourth configuration).
  • At least one first intermediate electrode short-circuited to the first electrode as the intermediate electrode between the first electrode and the second electrode, and the first intermediate electrode A configuration (fifth configuration) may be adopted in which at least one second intermediate electrode short-circuited to the second electrode is alternately stacked.
  • the first chip may have a configuration (sixth configuration) having a function of adjusting the pulse width of the pulse signal.
  • the semiconductor device having any of the first to sixth configurations functions as a control main body of the insulating switching power supply by performing signal transmission between the primary circuit system and the secondary circuit system while electrically insulating them from each other.
  • Configuration (seventh configuration).
  • the isolated switching power supply disclosed in the present specification has a configuration (eighth configuration) including a semiconductor device having a seventh configuration and a switching output stage controlled by the semiconductor device. ing.
  • the switching output stage is a DC input supplied to the primary circuit system while electrically insulating the primary circuit system and the secondary circuit system using a transformer.
  • a configuration may be configured to function as a component of a DC / DC conversion unit that generates a DC output voltage from a voltage and supplies the voltage to the load of the secondary circuit system.
  • the isolated switching power supply having the ninth configuration further has a configuration (a tenth configuration) further including a rectifying unit that generates the DC input voltage from an AC input voltage.
  • the electronic device disclosed in the present specification has an isolated switching power supply having the eighth to tenth configurations, and a load that operates by receiving power supply from the isolated switching power supply.
  • the configuration (eleventh configuration) is taken.
  • the chip disclosed in the present specification is provided with a first electrode for receiving an input of a pulse signal through a bonding wire, and a region under the first electrode and electrically connected to the first electrode. And the second electrode connected to the reference potential end is integrated (12th configuration).
  • the chip disclosed herein has a pad for receiving an input of a pulse signal through a wire, and the wire functions as an inductor forming a filter and is connected to or connected to the pad
  • the wiring layer is configured to function as a first electrode of a capacitor forming the filter (a thirteenth configuration).
  • the inductance value of the inductor may be adjusted according to the length, the diameter, the number, or the material of the wire (a fourteenth configuration).
  • the length of the wire may be configured to be adjusted according to the position of the pad (a fifteenth configuration).
  • the capacitance value of the capacitor is adjusted by the facing area of the first electrode and the second electrode or the distance between the electrodes (sixteenth configuration) You should
  • the inter-electrode distance between the first electrode and the second electrode is determined by using any one of the plurality of wiring layers formed as stacked as the first electrode and the second electrode.
  • a configuration (a seventeenth configuration) which is adjusted depending on whether a wiring layer is used is preferable.
  • the inter-electrode distance between the first electrode and the second electrode may be adjusted (the eighteenth configuration) according to the thickness of the interlayer insulating layer.
  • the first electrode and the second electrode are formed in the same wiring layer, and have a configuration in which the comb teeth are engaged with each other at a distance between the electrodes ( It is good to set it as the 19th composition).
  • the chip having any of the thirteenth to nineteenth configurations may be configured to further include a protective layer (twentieth configuration) which covers the surface of the chip while exposing the pad.
  • Block diagram showing the overall configuration of an electronic device equipped with an isolated switching power supply Schematic diagram showing a first embodiment of a power supply IC Equivalent circuit diagram of signal transmission path in the first embodiment
  • a schematic view showing a first structural example of a capacitor A schematic view showing a second structural example of a capacitor
  • a schematic view showing a third structural example of a capacitor Schematic diagram for explaining adjustment method of inductance value
  • a schematic diagram for specifically explaining the adjustment method of the inductance value A schematic view showing a fourth structural example of a capacitor
  • the schematic diagram which shows the 5th structural example of a capacitor The schematic diagram which shows the 5th structural example of a capacitor
  • FIG. 1 is a block diagram showing the overall configuration of an electronic device equipped with an isolated switching power supply.
  • the electronic device X of this configuration example includes an isolated switching power supply 1 and a load 2 that operates by receiving power supply from the isolated switching power supply 1.
  • the insulation type switching power supply 1 is an alternating current supplied from the commercial alternating current power supply PW to the primary circuit system 1p while electrically insulating between the primary circuit system 1p (GND1 system) and the secondary circuit system 1s (GND2 system).
  • An AC / DC converter that converts an input voltage Vac (for example, AC 85 to 265 V) into a desired DC output voltage Vo (for example, DC 10 to 30 V) and supplies it to a load 2 of a secondary circuit system 1s.
  • a DC / DC conversion unit 20 is an alternating current supplied from the commercial alternating current power supply PW to the primary circuit system 1p while electrically insulating between the primary circuit system 1p (GND1 system) and the secondary circuit system 1s (GND2 system).
  • An AC / DC converter that converts an input voltage Vac (for example, AC 85 to 265 V) into a desired DC output voltage Vo (for example, DC 10 to 30 V) and supplies it to a load 2 of a secondary circuit system 1s.
  • the rectifying unit 10 is a circuit block that generates a DC input voltage Vi (for example, DC 120 to 375 V) from the AC input voltage Vac and supplies it to the DC / DC converting unit 20.
  • the rectifying unit 10 is a filter 11, a diode bridge 12, a capacitor 13, and And 14.
  • the filter 11 removes noise and surge from the AC input voltage Vac.
  • the diode bridge 12 full-wave rectifies the AC input voltage Vac to generate a DC input voltage Vi.
  • Capacitor 13 removes harmonic noise of AC input voltage Vac.
  • Capacitor 14 smoothes DC input voltage Vi.
  • a protective element such as a fuse may be provided at the front stage of the rectifying unit 10.
  • the DC / DC conversion unit 20 is a circuit block that generates a desired DC output voltage Vo from the DC input voltage Vi and supplies it to the load 2.
  • the power supply IC 100 and various discrete components transformation TR , An N-channel type MOS field effect transistor N1, a sense resistor Rs, a diode D1, a capacitor C1, and resistors R1 and R2).
  • Vdiv a divided voltage of DC output voltage Vo
  • the transformer TR has a primary winding Lp (number of turns Np) and a secondary winding Ls (number of turns Ns) magnetically coupled to each other in reverse polarity while electrically insulating between the primary circuit system 1p and the secondary circuit system 1s. including.
  • the first end of the primary winding Lp is connected to the application end of the DC input voltage Vi.
  • the second end of the primary winding Lp is connected to the drain of the transistor N1.
  • the first end of the secondary winding Ls is connected to the anode of the diode D1.
  • the second end of the secondary winding Ls is connected to the ground terminal GND2 of the secondary circuit system 1s.
  • the number of turns Np and Ns may be adjusted arbitrarily to obtain a desired DC output voltage Vo. For example, the DC output voltage Vo decreases as the number of turns Np increases or as the number of turns Ns decreases, and conversely, as the number of turns Np decreases or as the number of turns Ns increases, the DC output
  • the transistor N1 functions as an output switch element that is turned on / off in response to the gate signal G1 input from the power supply IC 100. Specifically, the transistor N1 turns on when the gate signal G1 is at high level, and turns off when the gate signal G1 is at low level.
  • the drain of the transistor N1 is connected to the second end of the primary winding Lp as described above.
  • the source of the transistor N1 is connected to the first end of the sense resistor Rs.
  • the second end of the sense resistor Rs is connected to the ground terminal GND1 of the primary circuit system 1p.
  • the anode of the diode D1 is connected to the first end of the secondary winding Ls as described above.
  • the cathode of the diode D1 and the first end of the capacitor C1 are both connected to the output end of the DC output voltage Vo.
  • the second end of the capacitor C1 is connected to the ground terminal GND2.
  • the diode D1 and the capacitor C1 thus connected function as a rectifying and smoothing unit that rectifies and smoothes an induced voltage generated in the secondary winding Ls to generate a DC output voltage Vo.
  • the transformer TR, the transistor N1, the diode D1, and the capacitor C1 function as a switching output stage that generates a DC output voltage Vo from the DC input voltage Vi by a flyback method.
  • the transistor N1 When the transistor N1 is turned off, an induced voltage is generated in the secondary winding Ls magnetically coupled to the primary winding Lp, and a secondary directed from the secondary winding Ls to the ground terminal GND2 via the diode D1.
  • the current Is flows.
  • the load 2 is supplied with a DC output voltage Vo obtained by rectifying and smoothing the induced voltage of the secondary winding Ls.
  • the DC output voltage Vo is generated from the AC input voltage Vac while electrically insulating between the primary circuit system 1p and the secondary circuit system 1s.
  • Load 2 can be supplied.
  • FIG. 2 is a schematic view showing the first embodiment of the power supply IC 100.
  • the power supply IC 100 of this embodiment is a multi-chip type semiconductor device (so-called composite isolator) formed by sealing the primary side control chip 110, the secondary side control chip 120, and the isolator chip 130 in a single package. It is.
  • the primary side control chip 110 has an RS flip flop 111 and pads T11 and T12 as a receiving unit for receiving the pulse signals S10 and S20 from the secondary side control chip 120 via the isolator chip 130.
  • the primary side control chip 110 also has pulse signal generation units 112 and 113 and pads T13 and T14 as transmitting units that transmit the pulse signals S30 and S40 to the secondary side control chip 120 via the isolator chip 130.
  • the reference potential end of the primary side control chip 110 is connected to the ground end GND1.
  • the secondary side control chip 120 has pulse signal generation units 121 and 122 and pads T21 and T22 as transmission units that transmit the pulse signals S10 and S20 to the primary side control chip 110 via the isolator chip 130.
  • the secondary side control chip 120 also has an RS flip flop 123 and pads T23 and T24 as a receiving unit for receiving the pulse signals S30 and S40 from the primary side control chip 110 via the isolator chip 130.
  • the reference potential end of the secondary side control chip 120 is connected to the ground end GND2.
  • a one-shot pulse generation circuit can be suitably used.
  • the isolator chip 130 electrically insulates between the primary side control chip 110 and the secondary side control chip 120 and, as a means for transmitting pulse signals S10 to S40 between the two chips, an integrated transformer 131 to 134, pads T31a to T34a, and pads T31b to T34b.
  • the integration transformers 131 to 134 each include an input winding (solid line) and an output winding (broken line) magnetically coupled to each other with the same polarity.
  • the secondary side control chip 120 corresponds to the first chip on the transmission side of the pulse signals S10 and S20
  • the primary side control chip 110 corresponds to the pulse signals S10 and S20. It corresponds to the second chip on the receiving side.
  • the isolator chip 130 electrically insulates between the primary side control chip 110 and the secondary side control chip 120 using the integration transformers 131 and 132 while the secondary side control chip 120 is connected to the primary side control chip. It corresponds to a third chip for transmitting the pulse signals S10 and S20 to 110.
  • the primary side control chip 110 corresponds to the first chip on the transmission side of the pulse signals S30 and S40
  • the secondary side control chip 120 corresponds to the pulse signals S30 and S40. It corresponds to the second chip on the receiving side.
  • the isolator chip 130 electrically insulates between the primary side control chip 110 and the secondary side control chip 120 using the integration transformers 133 and 134, while the primary side control chip 110 to the secondary side control chip
  • the third chip 120 transmits the pulse signals S30 and S40 to the second chip 120.
  • the output terminals of the pulse signal generators 121 and 122 are connected to the pads T21 and T22, respectively.
  • the pads T21 and T22 are connected to the pads T31 b and T32 b via bonding wires W21 and W22, respectively.
  • the pads T31b and T32b are connected to the input windings (solid lines) of the integration transformers 131 and 132, respectively.
  • the output windings (broken lines) of the integration transformers 131 and 132 are connected to the pads T31a and T32a.
  • the pads T31a and T32a are connected to the pads T11 and T12 via bonding wires W11 and W12, respectively.
  • the pads T11 and T12 are connected to the set end (S) and the reset end (R) of the RS flip flop 111, respectively.
  • the pulse signal generation unit 122 pulse drives the input winding (solid line) of the integration transformer 132. .
  • the RS flip flop 111 sets the output end (Q) to the first logic level (for example, high level) according to the pulse signal S10 input to the set end (S), and is input to the reset end (R) In response to the pulse signal S20, the output terminal (Q) is reset to a second logic level (for example, low level).
  • the secondary side control chip 120 is configured to have, for example, an output feedback control unit (not shown) that performs duty control of the pulse width modulation signal PWM such that the divided voltage Vdiv matches the reference voltage Vref.
  • the generating units 121 and 122 may be configured to pulse drive the input windings (solid lines) of the integration transformers 131 and 132, for example, at the rising timing and the falling timing of the pulse width modulation signal PWM.
  • the primary side control chip 110 may be configured to switch the logic level of the gate signal G1 according to the logic level of the output terminal (Q) of the RS flip flop 111, for example.
  • the output terminals of the pulse signal generators 112 and 113 are connected to the pads T13 and T14, respectively.
  • Pads T13 and T14 are connected to pads T33a and T34a via bonding wires W13 and W14, respectively.
  • Pads T33a and T34a are connected to respective input windings (solid lines) of integration transformers 133 and 134, respectively.
  • the output windings (broken lines) of the integration transformers 133 and 134 are connected to the pads T33 b and T34 b.
  • the pads T33 b and T34 b are connected to the pads T23 and T24 via bonding wires W23 and W24, respectively.
  • the pads T23 and T24 are connected to the set end (S) and the reset end (R) of the RS flip flop 123, respectively.
  • the pulse signal generator 113 pulse drives the input winding (solid line) of the integration transformer 134 when resetting the output terminal (Q) of the RS flip flop 123 to the second logic level (for example, low level). .
  • the RS flip flop 123 sets the output end (Q) to the first logic level (for example, high level) according to the pulse signal S30 input to the set end (S), and is input to the reset end (R) In response to the pulse signal S40, the output terminal (Q) is reset to the second logic level (for example, low level).
  • the primary side control chip 110 is configured to have, for example, an abnormality notification unit (not shown) that generates an abnormality notification signal ERR to the secondary side control chip 120, and the pulse signal generation units 112 and 113 are, for example, abnormality
  • Each input winding (solid line) of the integration transformers 133 and 134 may be pulse-driven at the rising timing and the falling timing of the notification signal ERR.
  • the secondary side control chip 120 may be configured to switch whether or not to shut down the operation of generating the DC output voltage Vo according to, for example, the logic level of the output terminal (Q) of the RS flip flop 123 .
  • the inductor L for forming the LC low pass filter the inductance components of the bonding wires (W21, W22, W13, W14) are actively used.
  • the capacitor C for forming the LC low pass filter is formed using the signal input pad (T31b, T32b, T33a, T34a) of the isolation chip 130 and the conductor layer and the dielectric layer in the lower region thereof. (See the hatching area in the figure, details will be described later).
  • the pulse signal generation units 121 and 122 and the pulse signal generation units 112 and 113 each have a function of arbitrarily adjusting the pulse width of the pulse signals S10 to S40.
  • the noises of the pulse signals S10 to S40 can be appropriately reduced.
  • FIG. 3 is an equivalent circuit diagram of the signal transmission path in the first embodiment.
  • integrated transformer 210 includes an input winding 211 and an output winding 212 magnetically coupled to each other in the same polarity.
  • the LC low pass filter 220 includes an inductor 221 and a capacitor 222.
  • the first end of the inductor 221 is connected to the signal input end IN.
  • the second end of the inductor 221 and the first end of the capacitor 222 are connected to the first end of the input winding 211 as the output end of the LC low pass filter 220.
  • the second end of the capacitor 222 and the second end of the input winding 211 are both connected to the first ground end.
  • the first end of the output winding 212 is connected to the signal output end OUT.
  • the second end of the output winding 212 is connected to the second ground end.
  • the integration transformer 210 is understood as the above-described integration transformer 133 or 134
  • the signal input end IN corresponds to the pad T13 or T14
  • the capacitor 222 corresponds to the capacitor C formed in the lower region of the pad T33a or T34a
  • the signal output end OUT corresponds to the pad T33b or T34b
  • the first ground end corresponds to the ground end GND1
  • the second ground terminal corresponds to the ground terminal GND2.
  • FIG. 4 is a schematic view showing a second embodiment of the power supply IC 100.
  • the inductance components of the bonding wires W11, W12, W23, W24
  • W11, W12, W23, W24 are actively used as the inductor L for forming the LC low pass filter.
  • the capacitor C for forming the LC low pass filter includes the signal input pads (T11, T12, T23, T24) of the primary side control chip 110 and the secondary side control chip 120, and the conductor layer and dielectric in the lower region thereof. It is formed using a body layer (see hatching area in the figure, details will be described later).
  • the pulse signal generation units 121 and 122 and the pulse signal generation units 112 and 113 have a function of arbitrarily adjusting the pulse widths of the pulse signals S10 to S40 as in the first embodiment (FIG. 2) described above. It is desirable to have However, when adjusting the pulse width, it is necessary to consider not only the cutoff frequency fc of the LC low pass filter but also the coupling degree of each of the integrated transformers 131 to 134, unlike the first embodiment (FIG. 2) described above. It should be noted that there is a point.
  • FIG. 5 is an equivalent circuit diagram of a signal transmission path in the second embodiment.
  • the LC low pass filter 230 includes an inductor 231 and a capacitor 232.
  • the first end of the input winding 211 is connected to the signal input end IN.
  • the second end of the input winding 211 is connected to the first ground end.
  • the first end of the output winding 212 is connected to the first end of the inductor 231.
  • the second end of the output winding 212 is connected to the second ground end.
  • the second end of the inductor 231 and the first end of the capacitor 232 are connected as the output end of the LC low pass filter 230 to the signal output end OUT.
  • the second end of the capacitor 232 is connected to the second ground end.
  • the second ground terminal corresponds to the ground terminal GND2.
  • the first embodiment in which the LC low pass filter 220 is introduced upstream of the integration transformer 210 and the second embodiment (in which the LC low pass filter 230 is introduced downstream of the integration transformer 210) Although FIG. 5) is described separately, the first embodiment and the second embodiment may be combined and adopted. That is, it is also possible to introduce the LC low pass filters 220 and 230 on both the upstream and downstream sides of the integration transformer 210, respectively.
  • FIG. 6 is a schematic view showing a first structural example of the capacitor C, in which a longitudinal sectional view (upper stage) and a partial top view (lower stage) of a chip on which the capacitor C is formed are depicted.
  • a longitudinal sectional view (upper stage) and a partial top view (lower stage) of a chip on which the capacitor C is formed are depicted.
  • a cross section when the chip is cut vertically along line A1-A2 of the partial top view (lower part) is depicted.
  • the chip corresponds to the isolator chip 130 of the first embodiment (FIG. 2) or the primary side control chip 110 or the secondary side control chip 120 of the second embodiment (FIG. 4).
  • a bonding wire 301 serving as a transmission path of a pulse signal is connected to the pad 302.
  • the bonding wire W21 or W22 or the bonding wire W13 or W14 in FIG. 2 corresponds to the bonding wire 301 in FIG. 2, and the pad T31b or T32b or the pad T33a in FIG.
  • T34a corresponds to the pad 302 in this figure.
  • the bonding wire W11 or W12 or the bonding wire W23 or W24 in FIG. 4 corresponds to the bonding wire 301 in this figure
  • T24 corresponds to the pad 302 in this figure.
  • the chip in this figure has a two-layer wiring structure in which a first metal layer (1st MTL), an interlayer insulating layer (ILD), and a second metal layer (2nd MTL) are sequentially formed from the lower layer side (substrate side). It is assumed.
  • a first metal layer (1st MTL), an interlayer insulating layer (ILD), and a second metal layer (2nd MTL) are sequentially formed from the lower layer side (substrate side).
  • Al, Cu, etc. can be mentioned as a raw material of each metal layer (1stMTL, 2ndMTL).
  • SiO 2 etc. can be mentioned as a raw material of an interlayer insulation layer (ILD).
  • Metal wires 303 and 306 are laid in the second metal layer (2nd MTL) described above.
  • a rectangular (for example, 100 ⁇ m ⁇ 100 ⁇ m) pad connection region is formed in the plan view, and an electrical connection with the pad 302 is established in the region. That is, the pad connection region of the metal wire 303 functions as a first electrode for receiving an input of a pulse signal from the chip of the previous stage through the bonding wire 301 and the pad 302. Therefore, in the following description, the pad connection region of the metal wire 303 may be referred to as the first electrode 303 in some cases.
  • a pad connection region similar to the above is formed also in the metal wiring 306, and electrical connection with the pad 307 is established in the region.
  • the metal wiring 306 is connected to the metal wiring 304 laid in the first metal layer (1st MTL) through the via 305 which penetrates the interlayer insulating layer (ILD).
  • electrical insulation is maintained between the rectangular region and the first electrode 303 by separating an interlayer insulating layer (ILD). That is, the rectangular region functions as a second electrode electrically isolated from the first electrode 303 and connected to the reference potential end. Therefore, in the following description, the rectangular region of the metal wire 304 may be referred to as a second electrode 304.
  • the capacitor C can be formed by the first electrode 303 and the second electrode 304 which are conductors, and the dielectric (interlayer insulating layer (ILD)) sandwiched between both electrodes. it can. Further, in the present structural example, since the lower region of the pad 302 can be effectively used, the area of the chip is not unnecessarily increased when forming the capacitor C.
  • ILD interlayer insulating layer
  • FIG. 7 is a schematic view showing a second structure example of the capacitor C.
  • a polysilicon layer (poly-Si) is formed on the lower layer side (substrate side) of the first metal layer (1st MTL) based on the first structure example (FIG. 6) described above. It has a three-layer wiring structure.
  • metal wires 303 and 306 are laid in the second metal layer (2nd MTL) described above.
  • the rectangular pad connection region formed in the metal wiring 303 functions as the first electrode described above, which is the same as the above.
  • the metal wiring layer 306 is connected to the metal wiring 315 laid in the first metal layer (1st MTL) via the via 316 penetrating the second interlayer insulating layer (2nd ILD). Furthermore, the metal wire 315 is connected to the polysilicon wire 313 laid in the polysilicon layer (poly-Si) via the via 314 penetrating the first interlayer insulating layer (1st ILD).
  • the polysilicon wiring 313 is extended to the lower region of the first electrode 303, and a rectangular region having the same area as the first electrode 303 is formed in the plan view.
  • the rectangular area functions as the aforementioned second electrode. Therefore, in the following description, the rectangular region of the polysilicon wiring 313 may be referred to as a second electrode 313.
  • the distance between the first electrode 303 and the second electrode 313 in FIG. 7 is longer than the distance between the first electrode 303 and the second electrode 304 in FIG.
  • the capacitance value of the capacitor C is reduced.
  • an intermediate electrode 312 formed using a first metal layer (1st MTL) is additionally provided between the first electrode 303 and the second electrode 313.
  • the intermediate electrode 312 is short-circuited with the first electrode 303 through the via 311 penetrating the second interlayer insulating layer (2nd ILD).
  • electrical insulation is maintained by separating the first interlayer insulating layer (1st ILD).
  • the capacitor C is formed by the intermediate electrode 312 and the second electrode 313 which are conductors, and the dielectric (first interlayer insulating layer (1st ILD)) sandwiched between both electrodes. Can. Therefore, even when the distance between the first electrode 303 and the second electrode 313 is extended with the multilayer wiring of the chip, the capacitance value of the capacitor C can be maintained.
  • the intermediate electrode 312 may be formed in a rectangular shape having an area equal to or larger than that of the first electrode 303 and the second electrode 313 in plan view.
  • the intermediate electrode 312 and the first electrode 303 are short-circuited to insulate the intermediate electrode 312 and the second electrode 313 by way of example.
  • the first electrode 303 may be insulated and the middle electrode 312 and the second electrode 313 may be short-circuited.
  • the capacitor C is formed by the first electrode 303 and the intermediate electrode 312 which are conductors, and the dielectric (second interlayer insulating layer (2nd ILD)) sandwiched between both electrodes.
  • FIG. 8 is a schematic view showing a third structure example of the capacitor C.
  • the second electrode 401 polysilicon layer
  • the first intermediate electrode 402 first metal layer
  • the second intermediate electrode 403 second metal layer
  • the first electrode 404 third metal layer
  • the first intermediate electrode 402 is short-circuited with the first electrode 404.
  • the second intermediate electrode 403 is short-circuited with the second electrode 401.
  • first intermediate electrode 402 shorted to the first electrode 401 and at least one shorted to the second electrode 401 are used as the above-described intermediate electrodes.
  • Layers of second intermediate electrodes 403 are alternately stacked.
  • the first chip 510 on the transmission side of the pulse signal is provided with a pad 511 for outputting the pulse signal.
  • the second chip 520 on the receiving side of the pulse signal is provided with a pad 521 for receiving an input of the pulse signal.
  • the bonding wire 530 is connected between the pad 511 and the pad 521.
  • the length l, the diameter ⁇ , the number n, or the material of the bonding wire 530 it is conceivable to adjust the length l, the diameter ⁇ , the number n, or the material of the bonding wire 530.
  • the distance d between both chips may be changed, or the position of the pad 511 or the pad 521 may be changed.
  • FIG. 10 is a schematic diagram for specifically explaining the adjustment method of the inductance value.
  • FIG. 10 an example is given in which the positions of the pads T32a and T32b are changed based on FIG. 4 described above.
  • bonding wires W12 and W22 connected to pads T32a and T32b, respectively can be made longer than other bonding wires to increase their inductance values.
  • the length l of the bonding wire (and hence the inductance value of the inductor L forming the LC low pass filter) can be arbitrarily adjusted by the position of the pad.
  • the inductance value of the inductor L forming the LC low-pass filter varies not only with the length l of the bonding wire, but also with the diameter ⁇ , the number n, or the material. Therefore, in order to optimize the cutoff frequency of the LC low pass filter, it is necessary to adjust the capacitance value of the capacitor C in accordance with the inductance value of the inductor L.
  • a method of adjusting the capacitance value of the capacitor C will be described in detail by giving a specific example.
  • FIG. 11 is a schematic view showing a fourth structural example of the capacitor C, in which a longitudinal sectional view of a chip in which the capacitor C is formed is depicted.
  • the chip corresponds to the isolator chip 130 of the first embodiment (FIG. 2).
  • the chip of this structural example has a five-layer wiring structure in which a polysilicon layer 600 and metal layers 610 to 640 are sequentially stacked from the lower layer side (substrate side).
  • an interlayer insulating layer 650 is formed between the polysilicon layer 600 and the metal layer 610.
  • interlayer insulating layers 660 to 680 are formed between the metal layers 610 to 640, respectively.
  • the polysilicon layer 600, the interlayer insulating layer 650, the metal layer 610, the interlayer insulating layer 660, the metal layer 620, the interlayer insulating layer 670, the metal layer 630, and the layers are sequentially from the lower layer side (substrate side).
  • the insulating layer 680 and the metal layer 640 are stacked.
  • Examples of the material of the metal layers 610 to 640 include Al and Cu.
  • a polysilicon wiring 601 is laid.
  • Metal wires 611 and 612 are laid in the metal layer 610.
  • Metal interconnection 612 is connected to polysilicon interconnection 601 through via 651 penetrating interlayer insulating layer 650.
  • metal wires 621 to 623 are laid.
  • the metal wire 621 is connected to the metal wire 611 through a via 661 penetrating the interlayer insulating layer 660.
  • electrical insulation is maintained between the polysilicon wiring 601 and the metal wiring 621 with the interlayer insulating layers 650 and 660 separated.
  • Metal interconnections 622 and 623 are connected to metal interconnection 612 through vias 662 and 663 penetrating interlayer insulating layer 660, respectively.
  • metal wires 631 and 632 are laid.
  • Metal interconnection 631 is connected to metal interconnections 621 and 622 through vias 671 and 672 penetrating interlayer insulating layer 670.
  • Metal interconnection 632 is connected to metal interconnection 623 through via 673 penetrating interlayer insulating layer 670.
  • the input winding of the integration transformer is formed by the conductive path (metal wiring 631 ⁇ via 672 ⁇ metal wiring 622 ⁇ via 662 ⁇ metal wiring 612) laid in the central portion of this figure.
  • metal wires 641 and 642 are laid.
  • Metal interconnection 641 is connected to metal interconnection 631 through via 681 penetrating interlayer insulating layer 680.
  • the metal wire 641 is formed in a rectangular shape in a plan view, and functions as a pad for receiving an input of a pulse signal through a bonding wire. That is, the metal wiring 641 corresponds to the pad T31b or T32b or the pad T33a or T34a in the first embodiment (FIG. 2).
  • metal interconnection 642 is connected to metal interconnection 632 through via 682 penetrating through interlayer insulating layer 680.
  • an insulating layer 691 is formed so as to fill the peripheries of the metal wires 641 and 642. Furthermore, on the outermost surface of the chip, a protective layer 692 is formed which protects the surface of the chip while exposing at least a part of the metal wires 641 and 642 functioning as pads.
  • a material of the protective layer 692 polyimide and the like can be mentioned.
  • capacitor C having metal interconnections 611 and 621 as the first electrode, polysilicon interconnection 601 as the second electrode, and interlayer insulating layers 650 and 660 sandwiched between both electrodes as the dielectric. Can be formed.
  • the bonding wire connected to the pad functions as the inductor L forming the LC low pass filter, and the metal wire 641 functioning as the pad (further connected to this)
  • the metal wires 611 and 621 function as a first electrode of the capacitor C which forms an LC low pass filter.
  • the facing area S can be adjusted by the area and the number of the metal wires 611 and 621 facing the polysilicon wire 601.
  • the inter-electrode distance d can be adjusted depending on which wiring layer is used as the first electrode and the second electrode of the capacitor C among the plurality of stacked wiring layers. More specifically, in the chip of this structural example, both of the metal wires 611 and 621 are used as the first electrode of the capacitor C. For example, the metal wire 611 is omitted and only the metal wire 621 is used as the capacitor C. When the first electrode is used, the inter-electrode distance d can be extended to reduce the capacitance value of the capacitor C. The inter-electrode distance d can also be adjusted arbitrarily by optimizing the thickness itself of the interlayer insulating layer by changing the manufacturing process of the chip.
  • the characteristics (capacitance value and equivalent series resistance value) of the capacitor C can be easily adjusted as the number of wiring stages (the number of stacked layers) of the chip increases and the interlayer insulating layer becomes thinner.
  • FIG. 12 is a schematic view showing a fifth structure example of the capacitor C.
  • a longitudinal sectional view (upper stage), a partial plan view (middle stage), and a partially enlarged view (lower stage) of a chip on which the capacitor C is formed. Is depicted.
  • a cross section when the chip is cut vertically along line A3-A4 of the partial plan view (middle stage) is depicted.
  • the partial plan view (middle) metal wires 711 and 712 in perspective from the chip surface are depicted.
  • the partial enlarged view (lower part) the inside of the round frame of the partial plan view (middle part) is depicted in a partially enlarged manner.
  • the chip of this structural example has a three-layer wiring structure in which a polysilicon layer 700 and metal layers 710 and 720 are laminated in order from the lower layer side (substrate side).
  • an interlayer insulating layer 730 is formed between the polysilicon layer 700 and the metal layer 710.
  • an interlayer insulating layer 740 is formed between the metal layer 710 and the metal layer 720.
  • the polysilicon layer 700, the interlayer insulating layer 730, the metal layer 710, the interlayer insulating layer 740, and the metal layer 720 are sequentially formed in order from the lower layer side (substrate side).
  • the depiction of the insulating layer and the protective layer covering the chip surface is omitted.
  • a polysilicon wiring 701 is laid.
  • metal wires 711 to 713 are laid.
  • Metal interconnections 711 and 713 are connected to polysilicon interconnection 701 via vias 731 and 732 penetrating interlayer insulating layer 730, respectively.
  • electrical insulation is maintained between the polysilicon wiring 701 and the metal wiring 721 with the interlayer insulating layer 730 therebetween.
  • the metal wires 711 and 712 have features in their respective planar shapes, which will be described in detail later.
  • metal wires 721 and 722 are laid.
  • the metal wire 721 is connected to the metal wire 712 through a via 741 penetrating the interlayer insulating layer 740.
  • the metal wire 721 is formed in a rectangular shape in a plan view, and functions as a pad for receiving an input of a pulse signal through a bonding wire.
  • metal interconnection 722 is connected to metal interconnection 713 through via 742 penetrating interlayer insulating layer 740.
  • metal interconnection 712 is used as the first electrode
  • polysilicon interconnection 701 and metal interconnection 711 as the second electrode
  • interlayer insulating layers 730 and 740 sandwiched between both electrodes are used as dielectrics.
  • Capacitor C can be formed.
  • comb teeth 711a and 711b which intermesh with each other at a predetermined inter-electrode distance (a so-called MIM [Metal-Insulator-Metal] structure).
  • MIM Metal-Insulator-Metal
  • FIG. 13 is a schematic view showing a fifth structure example of the capacitor C.
  • a longitudinal sectional view (upper stage) and a top view (lower stage) of a chip in which the capacitor C is formed are depicted.
  • a vertical cross-sectional view (upper stage) a cross section when the chip is cut vertically along line A5-A6 in the top view (lower stage) is depicted.
  • the introduction target of the LC low pass filter is not limited to various chips handling the pulse signal inside the power supply IC 100 (the primary side control chip 110, the secondary side control chip 120, and the isolator chip 130). It can be extended to understand in general the chip to which the pulse signal is input through the wire.
  • the semiconductor device disclosed in the present specification can be used for, for example, in-vehicle devices and industrial devices.
  • Isolated switching power supply 1p Primary circuit system (GND1 system) 1s Secondary circuit system (GND2 system) 2 load 10 rectification unit 11 filter 12 diode bridge 13, 14 capacitor 20 DC / DC conversion unit 100 power supply IC DESCRIPTION OF SYMBOLS 110 Primary side control chip 111 RS flip flop 112, 113 Pulse signal generation part 120 Secondary side control chip 121, 122 Pulse signal generation part 123 RS flip flop 130 Isolator chip 131-134 Integration transformer 210 Integration transformer 211 Input winding 212 output winding 220, 230 LC low pass filter 221, 231 inductor 222, 232 capacitor 301 bonding wire 302, 307 pad 303 metal wiring (first electrode) 304 Metal wiring (second electrode) 312 middle electrode 313 polysilicon wiring (second electrode) 306, 315 Metal wiring 305, 311, 314, 316 Via 401 Second electrode 402 First intermediate electrode 403 Second intermediate electrode 404 First electrode 510 First chip 511 Pad 520 Second chip 521 Pad 530 Bonding

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PCT/JP2018/037537 2017-11-02 2018-10-09 半導体装置 WO2019087699A1 (ja)

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