WO2019082239A1 - Equalization device and equalization method - Google Patents

Equalization device and equalization method

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Publication number
WO2019082239A1
WO2019082239A1 PCT/JP2017/038173 JP2017038173W WO2019082239A1 WO 2019082239 A1 WO2019082239 A1 WO 2019082239A1 JP 2017038173 W JP2017038173 W JP 2017038173W WO 2019082239 A1 WO2019082239 A1 WO 2019082239A1
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WO
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unit
symbol
output
neural network
symbols
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PCT/JP2017/038173
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French (fr)
Japanese (ja)
Inventor
怜典 松本
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2017/038173 priority Critical patent/WO2019082239A1/en
Publication of WO2019082239A1 publication Critical patent/WO2019082239A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/66—Non-coherent receivers, e.g. using direct detection
    • H04B10/69—Electrical arrangements in the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/06—Control of transmission; Equalising by the transmitted signal

Definitions

  • the present invention relates to an equalizer and equalization method for equalizing non-linear distortion.
  • LAN local area network
  • LAN local area network
  • PAM pulse amplitude modulation
  • the signal equalizer compensates for distortion of the data signal generated in the optical transceiver and the communication path (optical transmission path).
  • a feed forward equalizer hereinafter referred to as FFE
  • FFE feed forward equalizer
  • a signal equalizer having a simple configuration a feed forward equalizer having a simple configuration.
  • FFE can not cope with non-linear distortion such as modulation instability, square wave detection distortion, and gain saturation that occurs in an optical transmitter / receiver that employs the PAM method.
  • non-linear distortion generated in an optical transmitter-receiver and an optical transmission path can be equalized by performing non-linear conversion in neuron elements constituting an intermediate layer.
  • Non-Patent Document 1 describes a non-linear equalizer in which the equalization accuracy of non-linear distortion with respect to PAM is improved by inputting a plurality of symbols in a digital quadrature modulation signal in block units and performing signal processing. It is done.
  • this non-linear equalizer in an optical communication device, high reception sensitivity that can not be obtained with FFE can be achieved without adding an optical amplifier and without adding an expensive and broadband electric amplifier with excellent linearity. it can.
  • the neural network of the nonlinear equalizer described in Non-Patent Document 1 performs signal processing by inputting a plurality of consecutive symbols in time series in block units, depending on the number of outputs, the neuron element of the input layer The number may be significantly less than the output layer.
  • the non-linear equalizer since the cross entropy is increased, the convergence accuracy of the local error is deteriorated in the updating of the connection weight using the error back propagation method.
  • the non-linear equalizer has a problem that the effect of reducing non-linear distortion is small.
  • the present invention solves the above-mentioned problems, and it is an object of the present invention to obtain an equalizer and an equalization method capable of enhancing the equalization accuracy of non-linear distortion.
  • the equalizer includes a neural network input unit, a neural network unit, a determination unit, a demodulation unit, and a connection weight update unit.
  • the neural network input unit inputs a signal including a plurality of consecutive symbols in time series, and outputs a surplus symbol not continuous in time series together with a target symbol continuous in time series included in the signal.
  • the neural network unit comprises an input layer, an intermediate layer and an output layer, the number of neuron elements in the input layer is larger than that in the output layer, the intermediate layer is one or more stages, and the output is from the neural network input unit
  • the likelihood of the target symbol is calculated by non-linear transformation of the multiplication sum of the selected symbol and the connection weight between the neuron elements.
  • the determination unit determines the likelihood of the symbol to be demodulated among the likelihoods output from the neural network unit.
  • the demodulation unit demodulates the symbol based on the likelihood determined by the determination unit.
  • the connection weight updating unit updates the connection weight in the neural network unit based on the symbols demodulated by the demodulation unit.
  • the neural network unit in which the number of neuron elements in the input layer is larger than that in the output layer inputs the surplus symbols not consecutive in time series together with the target symbol continuous in time series and Calculate the degree.
  • FIG. 2 is a block diagram showing an example of configuration of a neural network input unit in the first embodiment.
  • FIG. 2 is a block diagram showing a configuration example of a neural network unit in Embodiment 1. It is a figure which shows the internal structural example of the input layer of FIG. 3, an intermediate
  • 5 is a flowchart showing an equalization method according to Embodiment 1; It is a graph which shows the relationship between the reception average optical power of the received light received by the optical communication device, and a bit error rate.
  • FIG. 8 is a block diagram showing another configuration example of the neural network input unit in the first embodiment.
  • FIG. 8A is a block diagram showing a hardware configuration for realizing the function of the equalizer according to the first embodiment.
  • FIG. 8B is a diagram showing a hardware configuration that executes software for realizing the function of the equalization device according to the first embodiment.
  • FIG. 1 is a block diagram showing an example of the configuration of an equalization apparatus 1000 according to Embodiment 1 of the present invention.
  • the equalizer 1000 is mounted on, for example, an optical communication device.
  • Equalization apparatus 1000 includes an optical communication apparatus equipped with equalization apparatus 1000, an optical communication apparatus with which communication is performed with the optical communication apparatus, and non-linear distortion generated in each of the signal transmission paths between the two optical communication apparatuses.
  • the equalizer 1000 includes a photoelectric conversion unit 100, a received signal adjustment unit 200, a linear equalization unit 300, a neural network input unit 400, a neural network unit 500, a determination unit 600, a demodulation unit 700, and a connection weight update unit 800.
  • the photoelectric conversion unit 100 includes a photoelectric conversion element for converting an optical signal received from the above-mentioned optical communication device of the communication partner into an electric signal.
  • the optical signal is a signal of multi-level amplitude modulation format, and is composed of a plurality of time series continuous symbols. Each of the plurality of symbols is identified by an index number for each symbol, and the index number corresponds to the time series of symbols.
  • the photoelectric conversion unit 100 may include an oscillator that oscillates local oscillation light.
  • the photoelectric conversion unit 100 converts an analog electrical signal detected in the reception system of the optical communication device into a digital electrical signal (hereinafter referred to as a digital signal).
  • the converted digital signal is output from the photoelectric conversion unit 100 to the reception signal adjustment unit 200.
  • the reception signal adjustment unit 200 adjusts the delay of the electric signal output from the photoelectric conversion unit 100.
  • the received signal adjustment unit 200 changes the sampling rate of the digital signal output from the photoelectric conversion unit 100 using electrical processing.
  • the received signal adjustment unit 200 may perform processing such as restoration of the carrier frequency or phase.
  • the digital signal whose delay has been adjusted by the received signal adjustment unit 200 is output to the linear equalization unit 300.
  • the linear equalization unit 300 receives the digital signal output from the reception signal adjustment unit 200, and equalizes linear distortion of symbols included in the digital signal.
  • the linear distortion of a symbol is a linear distortion such as band limitation that occurs in an optical communication device of a communication counterpart, a photoelectric conversion element included in the photoelectric conversion unit 100, or a transmission line.
  • the digital signal from which linear distortion has been removed by the linear equalization unit 300 is output to the neural network input unit 400.
  • the neural network input unit 400 receives the digital signal from the linear equalization unit 300, and adjusts the timing and the number of symbols for inputting a plurality of symbols contained in the digital signal to the neural network unit 500. For example, the neural network input unit 400 outputs surplus symbols to the neural network unit 500 together with target symbols continuous in time series included in the digital signal.
  • the neural network unit 500 includes an input layer, an intermediate layer, and an output layer.
  • the number of neuron elements in the input layer is larger than that in the output layer, and the intermediate layer is one or more.
  • the neural network unit 500 inputs the block of the target symbol and the block of the surplus symbol in parallel from the neural network input unit 400.
  • the neural network unit 500 non-linearly transforms the multiplication sum of the input symbol and the connection weight between the neuron elements to calculate the likelihood of the target symbol.
  • the determination unit 600 determines the likelihood of the symbol to be demodulated among the likelihoods output from the neural network unit 500. For example, the determination unit 600 sets the likelihood with the greatest likelihood as the likelihood of a symbol to be demodulated. Since the posterior probability of obtaining the class of symbols corresponds to the likelihood of the symbol, the largest posterior probability is selected among the posterior probabilities output from the output layer of the neural network unit 500.
  • Demodulation section 700 demodulates the symbol based on the likelihood determined by determination section 600 to be the likelihood of the symbol to be demodulated. For example, the demodulation unit 700 restores the target symbol based on the posterior probability selected by the determination unit 600.
  • connection weight update unit 800 updates the connection weight in the neural network unit 500 based on the symbols demodulated by the demodulation unit 700. For example, the connection weight update unit 800 updates the connection weight between neuron elements in the neural network unit 500 using an error back propagation method.
  • the photoelectric conversion unit 100, the reception signal adjustment unit 200, and the linear equalization unit 300 may be included in an apparatus different from the equalization apparatus 1000.
  • the optical communication device on which the equalization device 1000 is mounted may include the photoelectric conversion unit 100, the reception signal adjustment unit 200, and the linear equalization unit 300.
  • the equalizer 1000 receives the digital signal from the linear equalizer 300 included in the optical communication device. That is, the equalizer 1000 only needs to include the neural network input unit 400, the neural network unit 500, the determination unit 600, the demodulation unit 700, and the connection weight update unit 800, and the photoelectric conversion unit 100, the reception signal adjustment unit 200, The linear equalizer 300 may not be provided.
  • FIG. 2 is a block diagram showing a configuration example of the neural network input unit 400.
  • the neural network input unit 400 includes a sliding window 401 and a serial / parallel converter 402.
  • the sliding window 401 receives the symbol 1, the symbol 2,..., The symbol L from the linear equalization unit 300, slides the window, and sequentially outputs the symbols of the window size.
  • the window size is the size of a block which is an output unit. In FIG. 2, the window size is “2”, ie, the size of two symbols, and the block includes two symbols.
  • FIG. 2 illustrates that time passes from the right to the left of the paper on the input side of the sliding window 401, and time passes from the left to the right on the paper at the output of the serial / parallel conversion unit 402. . That is, symbols are input to the sliding window 401 in the order of symbol 1, symbol 2, ..., symbol L. First, symbol 1, symbol 2, symbol 3, and symbol 4 are output from serial / parallel converter 402, and symbol 3, symbol 4, symbol 5, and symbol 6 are output at the next timing. At timing, symbol 5, symbol 6, symbol 7, symbol 8 are output.
  • a block is a group of a plurality of symbols specified by each of consecutive index numbers corresponding to a time series of symbols. That is, in the block output by the sliding window 401, the arrangement of symbols continuous in time series is maintained.
  • the sliding window 401 sequentially outputs the symbols of each block in series to the serial / parallel converter 402.
  • the serial / parallel converter 402 converts the output format of the symbols in the block into parallel output. In parallel output, a plurality of symbols in a block are output at the same timing.
  • the serial / parallel conversion unit 402 includes an output system 403A, an output system 403B, an output system 404A, and an output system 404B.
  • the output system 404A and the output system 404B are first output systems that output a target symbol among a plurality of symbols in a block output at the same timing.
  • the first output system is provided, for example, by the logarithm of the number of neuron elements in the output layer 503 with the modulation multilevel number at the bottom, and outputs a series of a plurality of target symbols continuous in time series.
  • the output system 403A and the output system 403B are second output systems that output surplus symbols among a plurality of symbols in the block output at the same timing.
  • the second output system is provided by a number obtained by subtracting the number of first output systems from the number of neuron elements in the output layer 503, and outputs a series of randomly arranged redundant symbols.
  • the window size is “2”, and the serial / parallel converter 402 sequentially outputs symbols for two blocks. From the sliding window 401, serial / parallel converter 402 performs block 1 including symbol 1 and symbol 2, block 2 including symbol 3 and symbol 4, block 3 including symbol 5 and symbol 6, symbol 7 and symbol 8 The blocks 4 to be included are sequentially input.
  • symbol 1 and symbol 2 in block 1 symbol 1 is output from output system 403A
  • symbol 2 is output from output system 404A
  • symbol 3 in block 2 is output from output system 404B
  • symbol 4 Are output from the output system 403B.
  • the neural network unit 500 receives symbol 1 and symbol 4 which are surplus symbols and symbol 2 and symbol 3 which are target symbols continuous in time series.
  • symbol 3 in block 2 is output from output system 403A
  • symbol 4 is output from output system 404A
  • symbol 5 in block 3 is output from output system 404B
  • symbol 6 is output from output system 403B. Ru.
  • the neural network unit 500 receives the symbols 3 and 6 which are surplus symbols and the symbols 4 and 5 which are target symbols continuous in time series.
  • symbol 5 in block 3 is output from output system 403A
  • symbol 6 is output from output system 404A
  • symbol 7 in block 4 is output from output system 404B
  • symbol 8 is output from output system 403B Be done.
  • the neural network unit 500 receives the symbols 5 and 8 which are surplus symbols and the symbols 6 and 7 which are target symbols continuous in time series.
  • the serial / parallel converter 402 outputs a plurality of symbols continuing in time series in parallel in block units.
  • the symbols output from the output system 403A, the output system 403B, the output system 404A, and the output system 404B are input to the neural network unit 500 at the same timing.
  • FIG. 3 is a block diagram showing a configuration example of the neural network unit 500.
  • the neural network unit 500 includes an input layer 501, an intermediate layer 502, and an output layer 503.
  • the middle layer 502 is configured in M stages.
  • the M stage is one stage or a plurality of stages.
  • FIG. 4 is a diagram showing an example of an internal configuration of the input layer 501, the intermediate layer 502 and the output layer 503 of FIG.
  • Each of the input layer 501, the intermediate layer 502, and the output layer 503 includes at least one or more neuron elements 511.
  • the neuron element 511 includes a multiplier 512 that multiplies an input signal with a connection weight with a previous-stage neuron element, and a non-linear conversion unit 513 that performs non-linear conversion on the multiplication sum of the input signal and the connection weight.
  • the number of inputs of each of the neuron element 1, the neuron element 2,..., The neuron element p is o, and the number of outputs of this layer is p Shall be
  • the non-linear conversion unit 513 of the neuron element 1 calculates the sum of the multiplication values calculated by the multiplier 512, and performs non-linear conversion with the non-linear function f (x) on the multiplication sum.
  • the following equation (1) is an example of the output value y j .
  • Examples of the non-linear function f (x) include a step function, a sigmoid function, and a ramp function.
  • the outputs of the n neuron elements 511 in the output layer 503 correspond to the n outputs of the neural network unit 500. From the output of the neural network unit 500, the posterior probability corresponding to the class C n of the target symbol is output.
  • the output of the k-th neuron element in the output layer 503 and the output k, the coupling load vector between the neuron elements and the preceding neuron element and w k, a plurality of symbols input to the k-th neuron element the symbol group is the ⁇ k.
  • the correct answer class is C 1
  • the wrong answer class is C 2 .
  • k, ⁇ ) that the target symbol ⁇ is the correct answer class C 1 at the output k can be calculated, for example, according to the following equation (2).
  • the neural network unit 500 outputs n posterior probabilities for the correct answer.
  • k, ⁇ ) corresponds to the likelihood that the target symbol ⁇ is the correct answer class C 1 at the output k.
  • the determination unit 600 determines the posterior probability corresponding to the symbol to be demodulated from the n posterior probabilities calculated by the neural network unit 500. For example, the determination unit 600 determines the largest posterior probability S hat among n posterior probabilities according to the following equation (3).
  • Demodulation section 700 demodulates the target symbol based on posterior probability S hat determined by determination section 600.
  • the determination unit 600 obtains symbols ( ⁇ 3, ⁇ 1, 1, 3) corresponding to the posterior probability.
  • Demodulation section 700 converts the symbol (-3, -1, 1, 3) obtained from determination section 600 into (00, 01, 11, 10).
  • symbols (1 + j, 1 + j, -1-j, 1 ⁇ j) are obtained from the determination unit 600.
  • the demodulation unit 700 converts the symbols (1 + j, 1 + j, -1-j, 1-j) into (11, 01, 00, 10).
  • the connection weight in the neural network unit 500 is fixed, the series of processes described above are repeatedly performed.
  • the connection load update unit 800 updates the connection load.
  • connection load update unit 800 uses the likelihood function represented by the following equation (4) for updating the connection load.
  • Equation (4) q k is the probability that the symbol group ⁇ k is a correct answer class C 1 .
  • the connection load update unit 800 calculates a connection load that minimizes e (w) shown in the above equation (5). For example, an error back propagation method based on least squares can be used to calculate the coupling weight that minimizes e (w). As described above, by using the non-linear function shown in the above equation (1), non-linear distortion occurring in the optical communication device and the transmission path of the communication partner can be canceled out.
  • the dimension of the symbol group ⁇ k can be increased, and the probability q k can also be increased.
  • the probability q k is increased, the minimum value of e (w) shown in the above equation (5) is further reduced, and as a result, the convergence accuracy of the local error can be enhanced in the update of the coupling load.
  • the equalization accuracy of nonlinear distortion is improved more than the nonlinear equalizer described in Non-Patent Document 1.
  • FIG. 5 is a flowchart showing the equalization method according to the first embodiment. It is assumed that the processing by the photoelectric conversion unit 100, the reception signal adjustment unit 200, and the linear equalization unit 300 is performed before the series of processing shown in FIG.
  • the neural network input unit 400 receives from the linear equalization unit 300 a digital signal including a plurality of symbols continuous in time series, performs the processing shown in FIG. 2, and is included in the digital signal. Output extra symbols along with the symbols.
  • the neural network unit 500 receives the target symbol and the surplus symbol output from the neural network input unit 400, non-linearly converts the multiplication sum of these symbols and the connection weight, and calculates the likelihood of the target symbol (Step ST2).
  • the likelihood of the target symbol is the posterior probability obtained from the above equation (2) and the above equation (3).
  • the determination unit 600 determines the likelihood of the symbol to be demodulated among the likelihoods output from the neural network unit 500 (step ST3). For example, the determination unit 600 determines the largest posterior probability among the posterior probabilities output from the neural network unit 500 according to the above equation (3).
  • connection load update unit 800 updates the connection load in the neural network unit 500 based on the symbols demodulated by the demodulation unit 700 (Ste ST6). For example, the connection load update unit 800 calculates, as an update value, the connection load with which e (w) shown in the above equation (5) is minimized.
  • FIG. 6 is a graph showing the relationship between the bit error rate and the received average light power of the received light received by the four types of optical communication devices.
  • the relationship shown in FIG. 6 is the result obtained by transmitting an optical signal for 20 km in a single mode fiber, with the modulation method of the optical signal being four-value amplitude modulation and the bit rate being 53.1 Gbit / s.
  • Each of the four types of optical communication devices includes a photodetector and an analog / digital converter (hereinafter referred to as an A / D converter).
  • the received light signal is detected by the light detector and converted to an electrical signal, and the electric signal converted from the received light signal is converted to a digital signal by an A / D converter.
  • the digital signal is sampled by the digital sampling oscilloscope at a sampling rate of 80 GSa / s and accumulated as serial data.
  • the relationship shown in FIG. 6 is the result of off-line analysis on a computer of the equalization ability of nonlinear distortion in each of the four types of optical communication devices using the stored serial data.
  • the four types of optical communication devices are an optical communication device A, an optical communication device B, an optical communication device C, and an optical communication device D.
  • the optical communication device A does not include the linear equalization unit 300, the neural network input unit 400, the neural network unit 500, the determination unit 600, and the connection weight update unit 800 among the components shown in FIG. Do not equalize both and non-linear distortion.
  • the relationship indicated by the symbol a in FIG. 6 is the relationship between the average received optical power (dBm) in the optical communication device A and the bit error rate (hereinafter referred to as BER).
  • the optical communication device B does not include the neural network input unit 400, the neural network unit 500, the determination unit 600, and the connection load update unit 800, and equalizes linear distortion. Do not equalize nonlinear distortion.
  • the relationship indicated by symbol b in FIG. 6 is the relationship between the average received optical power in the optical communication device B and the BER.
  • the optical communication device C does not include the neural network input unit 400, and equalizes both linear distortion and non-linear distortion.
  • a neural network unit in which the number of neuron elements in the input layer is 3, the number of neuron elements in the output layer is 64, and the number of intermediate layers is one, is used. That is, the optical communication device C corresponds to a communication device provided with the non-linear distortion equalizer described in Non-Patent Document 1.
  • the relationship indicated by symbol c in FIG. 6 is the relationship between the average received optical power in the optical communication device C and the BER.
  • the optical communication device D is an optical communication device provided with the equalizer 1000 shown in FIG.
  • the neural network input unit 400 sets the number of target symbols as 3 symbols and the number of surplus symbols as 72 symbols.
  • the number of neuron elements in the input layer 501 is 75
  • the number of neuron elements in the output layer 503 is 64
  • the intermediate layer 502 is one stage.
  • the relationship indicated by symbol d in FIG. 6 is the relationship between the average received optical power in the optical communication device D and the BER.
  • the optical communication device D provided with the equalizer 1000 has a reception sensitivity of ⁇ 13.7 (dBm) at a point of BER of 2.0 ⁇ 10 ⁇ 4 .
  • the reception sensitivity obtained by the optical communication device B is improved by 1.0 (dBm)
  • the reception sensitivity obtained by the optical communication device C is improved by 0.65 (dBm). .
  • the equalizer 1000 may not necessarily include the linear equalizer 300.
  • the neural network unit 500 may equalize both linear distortion and non-linear distortion occurring in the optical communication device and the transmission line.
  • the neural network unit 500 since the amount of calculation in the middle layer of the neural network unit 500 increases, the structure of the middle layer becomes complicated. Therefore, the neural network unit 500 removes non-linear distortion after the linear equalization unit 300 removes linear distortion. This makes it possible to simplify the configuration of the middle layer.
  • the neural network unit 500 has one intermediate layer.
  • the reception sensitivity obtained by the optical communication device D is improved by 1.0 (dBm) with respect to the reception sensitivity obtained by the optical communication device B that removes only linear distortion. .
  • FIG. 7 is a block diagram showing a configuration of neural network input unit 400A.
  • Neural network input unit 400A is a modification of neural network input unit 400. Referring to FIG. As shown in FIG. 7, the neural network input unit 400A includes a random signal generator 405A, a random signal generator 405B, and a serial / parallel converter 406.
  • Each of the random signal generation unit 405A and the random signal generation unit 405B generates and outputs a random symbol as a surplus symbol regardless of the time-sequential symbols input to the serial / parallel conversion unit 406.
  • a random symbol is a symbol sequence in which symbols are randomly arranged.
  • serial / parallel conversion unit 406 When the serial / parallel conversion unit 406 receives a plurality of consecutive symbols in time series from the linear equalization unit 300, the serial / parallel conversion unit 406 converts the output format of the symbols into parallel output in block units. In parallel output, a plurality of symbols in a block are output at the same timing.
  • the serial / parallel converter 406 includes an output system 408A and an output system 408B.
  • the random signal generator 405A includes an output system 407A.
  • the random signal generation unit 405B includes an output system 407B.
  • the output system 408A and the output system 408B are first output systems that output target symbols continuous in time series.
  • the first output system is provided, for example, by the logarithm of the number of neuron elements in the output layer 503 with the modulation multilevel number at the bottom, and outputs a series of a plurality of target symbols continuous in time series.
  • the output system 407A and the output system 407B are second output systems that output the random symbols generated by the random signal generation units 405A and 405B.
  • the second output system is provided by a number obtained by subtracting the number of first output systems from the number of neuron elements in the output layer 503, and outputs a series of randomly arranged redundant symbols.
  • time elapses from the right to the left of the paper on the input side of the serial / parallel converter 406, and the output sides of the random signal generator 405A, the random signal generator 405B, and the serial / parallel converter 406 are as follows. It is stated that time passes from the left side to the right side of the paper. That is, the serial / parallel converter 406 receives symbols in the order of symbol 1, symbol 2,..., Symbol 6. First, the symbol A is output from the random signal generator 405A, the symbol 1 and the symbol 2 are output from the serial / parallel converter 406, and the symbol D is output from the random signal generator 405B. At the next timing, symbol B, symbol 3, symbol 4, and symbol E are output, and at the next timing, symbol C, symbol 5, symbol 6, and symbol F are output.
  • the block size is “2”, and the serial / parallel converter 406 sequentially outputs one block of symbols. That is, when serial / parallel converter 406 serially inputs symbol 1, symbol 2, symbol 3, symbol 4, symbol 5, and symbol 6 from linear equalizer 300, it outputs in parallel every two symbols.
  • symbol 1 is output from the output channel 408A
  • symbol 2 is output from the output channel 408B
  • symbol A generated by the random signal generator 405A is output from the output channel 407A
  • the random signal generator 405B is generated.
  • the symbol D is output from the output system 407B.
  • the neural network unit 500 receives the symbol A and the symbol D which are surplus symbols, and the symbols 1 and 2 which are the target symbols continuous in time series.
  • symbol 3 is output from output system 408A
  • symbol 4 is output from output system 408B
  • symbol B generated by random signal generator 405A is output from output system 407A
  • random signal generator 405B generates The output symbol 407 is output from the output system 407B.
  • the neural network unit 500 receives the symbols C and F, which are surplus symbols, and the symbols 5 and 6, which are object symbols continuous in time series.
  • serial / parallel converter 406 outputs a plurality of symbols continuing in time series in parallel in block units.
  • the symbols output from each of the output system 407A, the output system 407B, the output system 408A, and the output system 408B are input to the neural network unit 500 at the same timing.
  • FIGS. 2 and 7 show neural network input units in which a plurality of first output systems are arranged side by side, and a second output system is arranged on both sides of the array of first output systems.
  • the equalizer 1000 is not limited to this arrangement. The arrangement order of the first output system and the second output system may be random.
  • FIG. 8A is a block diagram showing a hardware configuration for realizing the function of the equalizer 1000.
  • a photoelectric converter 901 is a device that converts an input optical signal into an electric signal, and corresponds to the photoelectric conversion unit 100 in FIG.
  • the photoelectric converter 901 may include an oscillator that oscillates local oscillation light.
  • FIG. 8B is a diagram showing a hardware configuration for executing software for realizing the function of the equalization device 1000.
  • a photoelectric converter 1001 is a device that converts an input optical signal into an electric signal, and corresponds to the photoelectric conversion unit 100 in FIG.
  • the photoelectric converter 1001 may include an oscillator that oscillates local oscillation light.
  • the photoelectric conversion unit 100, the received signal adjustment unit 200, the linear equalization unit 300, the neural network input unit 400 or 400A, the neural network unit 500, the determination unit 600, the demodulation unit 700, and the connection weight update unit 800 in the equalization device 1000 Each function is realized by a processing circuit. That is, the equalization device 1000 includes processing circuits for executing the respective processing of the flowchart shown in FIG.
  • the processing circuit may be dedicated hardware or may be a central processing unit (CPU) that executes a program stored in a memory.
  • the processing circuit 902 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an application specific integrated circuit (ASIC), an FPGA (FPGA) Field-Programmable Gate Array) or a combination thereof is applicable.
  • ASIC application specific integrated circuit
  • FPGA Field-Programmable Gate Array
  • connection load update unit 800 When the processing circuit is the processor 1002 shown in FIG. 8B, the photoelectric conversion unit 100, the reception signal adjustment unit 200, the linear equalization unit 300, the neural network input unit 400 or 400A, the neural network unit 500, the determination unit 600, the demodulation unit 700.
  • the respective functions of the connection load update unit 800 are realized by software, firmware or a combination of software and firmware. Software or firmware is described as a program and stored in the memory 1003.
  • the processor 1002 reads out and executes the program stored in the memory 1003 to thereby execute the photoelectric conversion unit 100, the reception signal adjustment unit 200, the linear equalization unit 300, the neural network input unit 400 or 400A, the neural network unit 500, The respective functions of unit 600, demodulation unit 700 and coupling load update unit 800 are realized. That is, the equalizing apparatus 1000 includes a memory 1003 for storing a program which is executed by the processor 1002 and each of the series of processes shown in FIG. 5 is consequently executed. These programs include the procedures of the photoelectric conversion unit 100, the received signal adjustment unit 200, the linear equalization unit 300, the neural network input unit 400 or 400A, the neural network unit 500, the determination unit 600, the demodulation unit 700, and the connection weight update unit 800. Or the method is to cause a computer to execute.
  • the memory 1003 is, for example, a nonvolatile or volatile semiconductor memory such as a random access memory (RAM), a read only memory (ROM), a flash memory, an erasable programmable read only memory (EPROM), or an EEPROM (electrically-EPROM).
  • RAM random access memory
  • ROM read only memory
  • EPROM erasable programmable read only memory
  • EEPROM electrically-EPROM
  • a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD, etc. correspond.
  • Partial functions of respective functions of photoelectric conversion unit 100, received signal adjustment unit 200, linear equalization unit 300, neural network input unit 400 or 400A, neural network unit 500, determination unit 600, demodulation unit 700, and connection weight update unit 800 May be realized by dedicated hardware, and some may be realized by software or firmware.
  • the functions of the photoelectric conversion unit 100, the reception signal adjustment unit 200, the linear equalization unit 300, the neural network input unit 400 or 400A, and the neural network unit 500 are realized by the processing circuit 902 as dedicated hardware.
  • the determination unit 600, the demodulation unit 700, and the connection load update unit 800 may realize the function by the processor 1002 executing a program stored in the memory 1003.
  • the processing circuit can realize each of the above functions by hardware, software, firmware, or a combination thereof.
  • the neural network unit 500 having the number of neuron elements in the input layer 501 larger than that in the output layer 503 inputs surplus symbols as well as target symbols continuous in time series. Then, the likelihood of the target symbol is calculated. Further, the neural network input unit 400 is provided by the number of log of the number of neuron elements in the output layer 503 with the modulation multilevel number at the bottom, and outputs from the output system that outputs the target symbol and the number of neuron elements in the output layer 503 The system is provided with a surplus output system which is provided by the number obtained by subtracting the number of systems, and which outputs a surplus symbol.
  • the surplus output system outputs random symbols as surplus symbols. Even with this configuration, since the convergence accuracy of the local error is high in updating the coupling weight using the error back propagation method, the equalization accuracy of the non-linear distortion of the equalizer 1000 can be enhanced.
  • the equalizer according to the present invention can improve the equalization accuracy of non-linear distortion, and can therefore be used for an optical communication device that transmits and receives multilevel optical information.
  • DESCRIPTION OF SYMBOLS 100 photoelectric conversion part, 200 received signal adjustment part, 300 linear equalization part, 400, 400A neural network input part, 401 sliding window, 402, 406 serial / parallel conversion part, 403A, 403B, 404A, 404B, 407A, 407B, 408A, 408B output system, 405A, 405B random signal generation unit, 500 neural network unit, 501 input layer, 502 intermediate layer, 503 output layer, 511 neuron element, 512 multiplier, 513 nonlinear conversion unit, 600 determination unit, 700 demodulation Part, 800 Coupling load update part, 901, 1001 photoelectric converter, 902 processing circuit, 1000 equalizer, 1002 processor, 1003 memory.

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Abstract

According to the present invention, a neural network unit (500), which has a relationship in which the number of neuron elements of an input layer (501) is larger than that of an output layer (503), receives a surplus symbol and a target symbol from a neural network input unit (400) and calculates the likelihood of the target symbol.

Description

等化装置および等化方法Equalizer and equalization method
　この発明は、非線形歪みを等化する等化装置および等化方法に関する。 The present invention relates to an equalizer and equalization method for equalizing non-linear distortion.
　近年のクラウドサービスまたは高速移動体通信の普及によって、データセンターなどのローカルエリアネットワーク（以下、ＬＡＮと記載する）で収容される通信トラヒックが逼迫している。そこで、例えば、ＩＥＥＥ８０２．３では、ＬＡＮの高速伝送を実現するため、４００Ｇイーサネット（登録商標）の標準化が進められている。この標準化では、信号強度を変化させて多値化するパルス振幅変調（以下、ＰＡＭと記載する）方式の採用が決定している。また、ＰＡＭ方式と合わせて、ディジタル領域の信号等化器が広く利用されている。 With the widespread use of cloud services or high-speed mobile communication in recent years, communication traffic accommodated in a local area network (hereinafter referred to as LAN) such as a data center is under pressure. Therefore, for example, in IEEE 802.3, in order to realize high-speed transmission of LAN, standardization of 400 G Ethernet (registered trademark) is in progress. In this standardization, it has been decided to adopt a pulse amplitude modulation (hereinafter referred to as PAM) method in which the signal strength is changed to multi-value. In addition to the PAM method, signal equalizers in the digital domain are widely used.
　信号等化器は、光送受信器および通信路（光伝送路）に生じたデータ信号の歪みを補償する。信号等化器のうち、簡素な構成の信号等化器として、フィードフォワード等化器（以下、ＦＦＥと記載する）が知られている。ただし、ＦＦＥは、ＰＡＭ方式を採用した光送受信器に生じる、変調不安定性、二乗検波歪みおよび利得飽和といった非線形歪みに対応できない。 The signal equalizer compensates for distortion of the data signal generated in the optical transceiver and the communication path (optical transmission path). Among signal equalizers, a feed forward equalizer (hereinafter referred to as FFE) is known as a signal equalizer having a simple configuration. However, FFE can not cope with non-linear distortion such as modulation instability, square wave detection distortion, and gain saturation that occurs in an optical transmitter / receiver that employs the PAM method.
　上記不具合を解消するために、近年では、ニューラルネットワークの利用が検討されている。一般に、ニューラルネットワークでは、中間層を構成するニューロン素子で非線形変換を実施することで、光送受信器および光伝送路に生じた非線形歪みを等化することができる。 In order to eliminate the above problems, in recent years, the use of neural networks has been considered. In general, in a neural network, non-linear distortion generated in an optical transmitter-receiver and an optical transmission path can be equalized by performing non-linear conversion in neuron elements constituting an intermediate layer.
　例えば、非特許文献１には、ディジタル直交変調信号における複数のシンボルをブロック単位で入力して信号処理を施すことで、ＰＡＭに対する非線形歪みの等化精度の向上を図った非線形等化器が記載されている。この非線形等化器を光通信器に採用することで、光増幅器を追加することなく、線形性に優れた高価かつ広帯域の電気増幅器を追加することなく、ＦＦＥでは得られない高い受信感度を達成できる。 For example, Non-Patent Document 1 describes a non-linear equalizer in which the equalization accuracy of non-linear distortion with respect to PAM is improved by inputting a plurality of symbols in a digital quadrature modulation signal in block units and performing signal processing. It is done. By adopting this non-linear equalizer in an optical communication device, high reception sensitivity that can not be obtained with FFE can be achieved without adding an optical amplifier and without adding an expensive and broadband electric amplifier with excellent linearity. it can.
　しかしながら、非特許文献１に記載された非線形等化器のニューラルネットワークは、時系列に連続した複数のシンボルをブロック単位で入力して信号処理を行うので、出力数によっては、入力層のニューロン素子数が出力層に比べて大幅に少ない場合がある。このようなニューラルネットワークでは、交差エントロピーが増大するため、誤差逆伝搬法を用いた結合荷重の更新において局所誤差の収束精度が悪くなる。これにより、上記非線形等化器では、非線形歪みを低減する効果が小さいという課題があった。 However, since the neural network of the nonlinear equalizer described in Non-Patent Document 1 performs signal processing by inputting a plurality of consecutive symbols in time series in block units, depending on the number of outputs, the neuron element of the input layer The number may be significantly less than the output layer. In such a neural network, since the cross entropy is increased, the convergence accuracy of the local error is deteriorated in the updating of the connection weight using the error back propagation method. Thus, the non-linear equalizer has a problem that the effect of reducing non-linear distortion is small.
　この発明は上記課題を解決するものであり、非線形歪みの等化精度を高めることができる等化装置および等化方法を得ることを目的とする。 SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and it is an object of the present invention to obtain an equalizer and an equalization method capable of enhancing the equalization accuracy of non-linear distortion.
　この発明に係る等化装置は、ニューラルネットワーク入力部、ニューラルネットワーク部、判定部、復調部および結合荷重更新部を備える。ニューラルネットワーク入力部は、時系列に連続した複数のシンボルを含む信号を入力し、信号に含まれる時系列に連続した対象シンボルとともに、時系列に連続しない余剰シンボルを出力する。ニューラルネットワーク部は、入力層、中間層および出力層から構成され、入力層のニューロン素子数が出力層よりも多い関係にあり、中間層が１段または複数段であり、ニューラルネットワーク入力部から出力されたシンボルとニューロン素子間の結合荷重との乗算和を非線形変換して対象シンボルの尤度を算出する。判定部は、ニューラルネットワーク部から出力された尤度のうち、復調すべきシンボルの尤度を判定する。復調部は、判定部によって判定された尤度に基づいてシンボルを復調する。結合荷重更新部は、復調部によって復調されたシンボルに基づいて、ニューラルネットワーク部における結合荷重を更新する。 The equalizer according to the present invention includes a neural network input unit, a neural network unit, a determination unit, a demodulation unit, and a connection weight update unit. The neural network input unit inputs a signal including a plurality of consecutive symbols in time series, and outputs a surplus symbol not continuous in time series together with a target symbol continuous in time series included in the signal. The neural network unit comprises an input layer, an intermediate layer and an output layer, the number of neuron elements in the input layer is larger than that in the output layer, the intermediate layer is one or more stages, and the output is from the neural network input unit The likelihood of the target symbol is calculated by non-linear transformation of the multiplication sum of the selected symbol and the connection weight between the neuron elements. The determination unit determines the likelihood of the symbol to be demodulated among the likelihoods output from the neural network unit. The demodulation unit demodulates the symbol based on the likelihood determined by the determination unit. The connection weight updating unit updates the connection weight in the neural network unit based on the symbols demodulated by the demodulation unit.
　この発明によれば、入力層のニューロン素子数が出力層よりも多い関係にあるニューラルネットワーク部が、時系列に連続した対象シンボルとともに、時系列に連続しない余剰シンボルを入力して対象シンボルの尤度を算出する。これにより、誤差逆伝搬法を用いた結合荷重の更新において局所誤差の収束精度が高くなり、非線形歪みの等化精度を高めることができる。 According to the present invention, the neural network unit in which the number of neuron elements in the input layer is larger than that in the output layer inputs the surplus symbols not consecutive in time series together with the target symbol continuous in time series and Calculate the degree. As a result, in the connection load update using the error back propagation method, the convergence accuracy of the local error is enhanced, and the equalization accuracy of the nonlinear distortion can be enhanced.
この発明の実施の形態１に係る等化装置の構成例を示すブロック図である。It is a block diagram which shows the structural example of the equalization device based on Embodiment 1 of this invention. 実施の形態１におけるニューラルネットワーク入力部の構成例を示すブロック図である。FIG. 2 is a block diagram showing an example of configuration of a neural network input unit in the first embodiment. 実施の形態１におけるニューラルネットワーク部の構成例を示すブロック図である。FIG. 2 is a block diagram showing a configuration example of a neural network unit in Embodiment 1. 図３の入力層、中間層および出力層の内部構成例を示す図である。It is a figure which shows the internal structural example of the input layer of FIG. 3, an intermediate | middle layer, and an output layer. 実施の形態１に係る等化方法を示すフローチャートである。5 is a flowchart showing an equalization method according to Embodiment 1; 光通信器で受信された受信光の受信平均光パワーとビット誤り率との関係を示すグラフである。It is a graph which shows the relationship between the reception average optical power of the received light received by the optical communication device, and a bit error rate. 実施の形態１におけるニューラルネットワーク入力部の別の構成例を示すブロック図である。FIG. 8 is a block diagram showing another configuration example of the neural network input unit in the first embodiment. 図８Ａは、実施の形態１に係る等化装置の機能を実現するハードウェア構成を示すブロック図である。図８Ｂは、実施の形態１に係る等化装置の機能を実現するソフトウェアを実行するハードウェア構成を示す図である。FIG. 8A is a block diagram showing a hardware configuration for realizing the function of the equalizer according to the first embodiment. FIG. 8B is a diagram showing a hardware configuration that executes software for realizing the function of the equalization device according to the first embodiment.
　以下、この発明をより詳細に説明するため、この発明を実施するための形態について、添付の図面に従って説明する。
実施の形態１．
　図１は、この発明の実施の形態１に係る等化装置１０００の構成例を示すブロック図である。等化装置１０００は、例えば、光通信器に搭載される。等化装置１０００は、等化装置１０００を搭載する光通信器、この光通信器と通信を行う相手の光通信器および両方の光通信器間の信号伝送路のそれぞれに生じた非線形歪みを等化する。等化装置１０００は、光電変換部１００、受信信号調整部２００、線形等化部３００、ニューラルネットワーク入力部４００、ニューラルネットワーク部５００、判定部６００、復調部７００および結合荷重更新部８００を備える。 Hereinafter, in order to explain the present invention in more detail, embodiments for carrying out the present invention will be described according to the attached drawings.
Embodiment 1
FIG. 1 is a block diagram showing an example of the configuration of an equalization apparatus 1000 according to Embodiment 1 of the present invention. The equalizer 1000 is mounted on, for example, an optical communication device. Equalization apparatus 1000 includes an optical communication apparatus equipped with equalization apparatus 1000, an optical communication apparatus with which communication is performed with the optical communication apparatus, and non-linear distortion generated in each of the signal transmission paths between the two optical communication apparatuses. Turn The equalizer 1000 includes a photoelectric conversion unit 100, a received signal adjustment unit 200, a linear equalization unit 300, a neural network input unit 400, a neural network unit 500, a determination unit 600, a demodulation unit 700, and a connection weight update unit 800.
　光電変換部１００は、前述した通信相手の光通信器から受信された光信号を電気信号に変換する光電変換素子を備えている。
　光信号は、多値振幅変調フォーマットの信号であり、時系列に連続した複数のシンボルで構成される。複数のシンボルのそれぞれは、シンボルごとのインデックス番号によって特定され、インデックス番号は、シンボルの時系列に対応している。
　なお、光電変換部１００は、内部に局部発振光を発振する発振器を備えていてもよい。
　光電変換部１００は、光通信器の受信系統において検波されたアナログ形式の電気信号を、ディジタル形式の電気信号（以下、ディジタル信号と記載する）に変換する。変換後のディジタル信号は、光電変換部１００から受信信号調整部２００に出力される。 The photoelectric conversion unit 100 includes a photoelectric conversion element for converting an optical signal received from the above-mentioned optical communication device of the communication partner into an electric signal.
The optical signal is a signal of multi-level amplitude modulation format, and is composed of a plurality of time series continuous symbols. Each of the plurality of symbols is identified by an index number for each symbol, and the index number corresponds to the time series of symbols.
The photoelectric conversion unit 100 may include an oscillator that oscillates local oscillation light.
The photoelectric conversion unit 100 converts an analog electrical signal detected in the reception system of the optical communication device into a digital electrical signal (hereinafter referred to as a digital signal). The converted digital signal is output from the photoelectric conversion unit 100 to the reception signal adjustment unit 200.
　受信信号調整部２００は、光電変換部１００から出力された電気信号を遅延調整する。
　受信信号調整部２００は、電気的処理を用いて、光電変換部１００から出力された上記ディジタル信号のサンプリングレートを変更する。
　なお、受信信号調整部２００は、搬送波周波数または位相の復元といった処理を行ってもよい。受信信号調整部２００によって遅延調整された上記ディジタル信号は、線形等化部３００に出力される。 The reception signal adjustment unit 200 adjusts the delay of the electric signal output from the photoelectric conversion unit 100.
The received signal adjustment unit 200 changes the sampling rate of the digital signal output from the photoelectric conversion unit 100 using electrical processing.
The received signal adjustment unit 200 may perform processing such as restoration of the carrier frequency or phase. The digital signal whose delay has been adjusted by the received signal adjustment unit 200 is output to the linear equalization unit 300.
　線形等化部３００は、受信信号調整部２００から出力された上記ディジタル信号を入力し、ディジタル信号に含まれるシンボルの線形歪みを等化する。
　シンボルの線形歪みとは、通信相手の光通信器、光電変換部１００に含まれる光電変換素子、あるいは伝送路に生じる、帯域制限などの線形歪みである。
　線形等化部３００によって線形歪みが除去されたディジタル信号は、ニューラルネットワーク入力部４００に出力される。 The linear equalization unit 300 receives the digital signal output from the reception signal adjustment unit 200, and equalizes linear distortion of symbols included in the digital signal.
The linear distortion of a symbol is a linear distortion such as band limitation that occurs in an optical communication device of a communication counterpart, a photoelectric conversion element included in the photoelectric conversion unit 100, or a transmission line.
The digital signal from which linear distortion has been removed by the linear equalization unit 300 is output to the neural network input unit 400.
　ニューラルネットワーク入力部４００は、線形等化部３００からディジタル信号を入力して、ディジタル信号に含まれる複数のシンボルを、ニューラルネットワーク部５００に入力するタイミングおよびシンボル数を調整する。例えば、ニューラルネットワーク入力部４００は、ディジタル信号に含まれる時系列に連続した対象シンボルとともに余剰シンボルを、ニューラルネットワーク部５００に出力する。 The neural network input unit 400 receives the digital signal from the linear equalization unit 300, and adjusts the timing and the number of symbols for inputting a plurality of symbols contained in the digital signal to the neural network unit 500. For example, the neural network input unit 400 outputs surplus symbols to the neural network unit 500 together with target symbols continuous in time series included in the digital signal.
　ニューラルネットワーク部５００は、入力層、中間層および出力層で構成され、入力層のニューロン素子数が出力層よりも多い関係にあり、中間層が１段または複数段である。また、ニューラルネットワーク部５００は、ニューラルネットワーク入力部４００から対象シンボルのブロックと余剰シンボルのブロックとを並列に入力する。ニューラルネットワーク部５００は、入力したシンボルとニューロン素子間の結合荷重との乗算和を非線形変換することにより、対象シンボルの尤度を算出する。 The neural network unit 500 includes an input layer, an intermediate layer, and an output layer. The number of neuron elements in the input layer is larger than that in the output layer, and the intermediate layer is one or more. Also, the neural network unit 500 inputs the block of the target symbol and the block of the surplus symbol in parallel from the neural network input unit 400. The neural network unit 500 non-linearly transforms the multiplication sum of the input symbol and the connection weight between the neuron elements to calculate the likelihood of the target symbol.
　判定部６００は、ニューラルネットワーク部５００から出力された尤度のうち、復調すべきシンボルの尤度を判定する。例えば、判定部６００は、尤もらしさが最大の尤度を、復調すべきシンボルの尤度とする。シンボルのクラスが得られる事後確率は、シンボルの尤度に相当するので、ニューラルネットワーク部５００の出力層から出力される事後確率のうち、最も大きい事後確率が選択される。 The determination unit 600 determines the likelihood of the symbol to be demodulated among the likelihoods output from the neural network unit 500. For example, the determination unit 600 sets the likelihood with the greatest likelihood as the likelihood of a symbol to be demodulated. Since the posterior probability of obtaining the class of symbols corresponds to the likelihood of the symbol, the largest posterior probability is selected among the posterior probabilities output from the output layer of the neural network unit 500.
　復調部７００は、判定部６００によって復調すべきシンボルの尤度であると判定された尤度に基づいて、シンボルを復調する。例えば、復調部７００は、判定部６００によって選択された事後確率に基づいて、対象シンボルを復元する。 Demodulation section 700 demodulates the symbol based on the likelihood determined by determination section 600 to be the likelihood of the symbol to be demodulated. For example, the demodulation unit 700 restores the target symbol based on the posterior probability selected by the determination unit 600.
　結合荷重更新部８００は、復調部７００によって復調されたシンボルに基づいて、ニューラルネットワーク部５００における結合荷重を更新する。
　例えば、結合荷重更新部８００は、誤差逆伝搬法を用いて、ニューラルネットワーク部５００におけるニューロン素子間の結合荷重を更新する。 The connection weight update unit 800 updates the connection weight in the neural network unit 500 based on the symbols demodulated by the demodulation unit 700.
For example, the connection weight update unit 800 updates the connection weight between neuron elements in the neural network unit 500 using an error back propagation method.
　なお、光電変換部１００、受信信号調整部２００および線形等化部３００は、等化装置１０００とは別の装置が備える構成であってもよい。
　例えば、等化装置１０００が搭載される光通信器が、光電変換部１００、受信信号調整部２００および線形等化部３００を備えてもよい。この場合、等化装置１０００は、上記光通信器が備える線形等化部３００から上記ディジタル信号を入力する。
　すなわち、等化装置１０００は、ニューラルネットワーク入力部４００、ニューラルネットワーク部５００、判定部６００、復調部７００および結合荷重更新部８００を備えていればよく、光電変換部１００、受信信号調整部２００および線形等化部３００を有していない構成であってもよい。 The photoelectric conversion unit 100, the reception signal adjustment unit 200, and the linear equalization unit 300 may be included in an apparatus different from the equalization apparatus 1000.
For example, the optical communication device on which the equalization device 1000 is mounted may include the photoelectric conversion unit 100, the reception signal adjustment unit 200, and the linear equalization unit 300. In this case, the equalizer 1000 receives the digital signal from the linear equalizer 300 included in the optical communication device.
That is, the equalizer 1000 only needs to include the neural network input unit 400, the neural network unit 500, the determination unit 600, the demodulation unit 700, and the connection weight update unit 800, and the photoelectric conversion unit 100, the reception signal adjustment unit 200, The linear equalizer 300 may not be provided.
　次に、ニューラルネットワーク入力部４００について詳細に説明する。
　図２は、ニューラルネットワーク入力部４００の構成例を示すブロック図である。図２において、ニューラルネットワーク入力部４００は、スライディングウィンドウ４０１と直列／並列変換部４０２とを備える。 Next, the neural network input unit 400 will be described in detail.
FIG. 2 is a block diagram showing a configuration example of the neural network input unit 400. As shown in FIG. In FIG. 2, the neural network input unit 400 includes a sliding window 401 and a serial / parallel converter 402.
　スライディングウィンドウ４０１は、シンボル１，シンボル２，・・・，シンボルＬを線形等化部３００から入力して、ウィンドウをスライドさせながら、ウィンドウサイズ分のシンボルを順次出力する。ウィンドウサイズは、出力単位であるブロックのサイズとなっている。図２では、ウィンドウサイズが“２”、すなわち、シンボル２つ分のサイズであり、ブロックには、２つのシンボルが含まれる。 The sliding window 401 receives the symbol 1, the symbol 2,..., The symbol L from the linear equalization unit 300, slides the window, and sequentially outputs the symbols of the window size. The window size is the size of a block which is an output unit. In FIG. 2, the window size is “2”, ie, the size of two symbols, and the block includes two symbols.
　また、図２は、スライディングウィンドウ４０１の入力側で紙面の右側から左側に時間が経過し、直列／並列変換部４０２の出力側で紙面の左側から右側に時間が経過するように記載している。
　すなわち、スライディングウィンドウ４０１には、シンボル１，シンボル２，・・・，シンボルＬの順でシンボルが入力される。直列／並列変換部４０２からは、最初に、シンボル１，シンボル２，シンボル３，シンボル４が出力され、次のタイミングで、シンボル３，シンボル４，シンボル５，シンボル６が出力され、さらに次のタイミングで、シンボル５，シンボル６，シンボル７，シンボル８が出力される。 Further, FIG. 2 illustrates that time passes from the right to the left of the paper on the input side of the sliding window 401, and time passes from the left to the right on the paper at the output of the serial / parallel conversion unit 402. .
That is, symbols are input to the sliding window 401 in the order of symbol 1, symbol 2, ..., symbol L. First, symbol 1, symbol 2, symbol 3, and symbol 4 are output from serial / parallel converter 402, and symbol 3, symbol 4, symbol 5, and symbol 6 are output at the next timing. At timing, symbol 5, symbol 6, symbol 7, symbol 8 are output.
　ブロックは、シンボルの時系列に対応した連続のインデックス番号のそれぞれによって特定される複数のシンボルの一群である。すなわち、スライディングウィンドウ４０１が出力するブロックでは、時系列に連続したシンボルの並びが維持される。
　スライディングウィンドウ４０１は、直列／並列変換部４０２に対してブロックごとのシンボルを直列に順次出力する。 A block is a group of a plurality of symbols specified by each of consecutive index numbers corresponding to a time series of symbols. That is, in the block output by the sliding window 401, the arrangement of symbols continuous in time series is maintained.
The sliding window 401 sequentially outputs the symbols of each block in series to the serial / parallel converter 402.
　直列／並列変換部４０２は、スライディングウィンドウ４０１からブロックを入力すると、ブロック内のシンボルの出力形式を並列出力に変換する。並列出力では、ブロック内の複数のシンボルが同じタイミングで出力される。
　直列／並列変換部４０２は、出力系統４０３Ａ、出力系統４０３Ｂ、出力系統４０４Ａおよび出力系統４０４Ｂを備える。 When the block is input from the sliding window 401, the serial / parallel converter 402 converts the output format of the symbols in the block into parallel output. In parallel output, a plurality of symbols in a block are output at the same timing.
The serial / parallel conversion unit 402 includes an output system 403A, an output system 403B, an output system 404A, and an output system 404B.
　出力系統４０４Ａおよび出力系統４０４Ｂは、同じタイミングで出力されるブロック内の複数のシンボルのうち、対象シンボルを出力する第１の出力系統である。
　第１の出力系統は、例えば、変調多値数を底とした出力層５０３のニューロン素子数の対数分だけ設けられて、時系列に連続した複数の対象シンボルの系列を出力する。 The output system 404A and the output system 404B are first output systems that output a target symbol among a plurality of symbols in a block output at the same timing.
The first output system is provided, for example, by the logarithm of the number of neuron elements in the output layer 503 with the modulation multilevel number at the bottom, and outputs a series of a plurality of target symbols continuous in time series.
　出力系統４０３Ａおよび出力系統４０３Ｂは、同じタイミングで出力されるブロック内の複数のシンボルのうち、余剰シンボルを出力する第２の出力系統である。
　第２の出力系統は、出力層５０３のニューロン素子数から第１の出力系統の数を減算した数だけ設けられて、無作為に並んだ余剰シンボルの系列を出力する。 The output system 403A and the output system 403B are second output systems that output surplus symbols among a plurality of symbols in the block output at the same timing.
The second output system is provided by a number obtained by subtracting the number of first output systems from the number of neuron elements in the output layer 503, and outputs a series of randomly arranged redundant symbols.
　以下、図２について詳細に説明する。ここで、ウィンドウサイズは“２”であり、直列／並列変換部４０２は、２ブロック分のシンボルを順次出力する。
　直列／並列変換部４０２は、スライディングウィンドウ４０１から、シンボル１およびシンボル２が含まれるブロック１、シンボル３およびシンボル４を含むブロック２、シンボル５およびシンボル６を含むブロック３、シンボル７およびシンボル８を含むブロック４を順次入力する。 Hereinafter, FIG. 2 will be described in detail. Here, the window size is “2”, and the serial / parallel converter 402 sequentially outputs symbols for two blocks.
From the sliding window 401, serial / parallel converter 402 performs block 1 including symbol 1 and symbol 2, block 2 including symbol 3 and symbol 4, block 3 including symbol 5 and symbol 6, symbol 7 and symbol 8 The blocks 4 to be included are sequentially input.
　同じタイミングで、ブロック１におけるシンボル１およびシンボル２のうち、シンボル１が出力系統４０３Ａから出力され、シンボル２が出力系統４０４Ａから出力され、ブロック２におけるシンボル３が出力系統４０４Ｂから出力され、シンボル４が出力系統４０３Ｂから出力される。
　これにより、ニューラルネットワーク部５００には、同じタイミングで、余剰シンボルであるシンボル１およびシンボル４と、時系列に連続した対象シンボルであるシンボル２およびシンボル３とが入力される。 At the same timing, of symbol 1 and symbol 2 in block 1, symbol 1 is output from output system 403A, symbol 2 is output from output system 404A, symbol 3 in block 2 is output from output system 404B, symbol 4 Are output from the output system 403B.
Thereby, at the same timing, the neural network unit 500 receives symbol 1 and symbol 4 which are surplus symbols and symbol 2 and symbol 3 which are target symbols continuous in time series.
　次のタイミングで、ブロック２におけるシンボル３が出力系統４０３Ａから出力され、シンボル４が出力系統４０４Ａから出力され、ブロック３におけるシンボル５が出力系統４０４Ｂから出力され、シンボル６が出力系統４０３Ｂから出力される。
　これにより、ニューラルネットワーク部５００には、同じタイミングで、余剰シンボルであるシンボル３およびシンボル６と、時系列に連続した対象シンボルであるシンボル４およびシンボル５とが入力される。 At the next timing, symbol 3 in block 2 is output from output system 403A, symbol 4 is output from output system 404A, symbol 5 in block 3 is output from output system 404B, and symbol 6 is output from output system 403B. Ru.
As a result, at the same timing, the neural network unit 500 receives the symbols 3 and 6 which are surplus symbols and the symbols 4 and 5 which are target symbols continuous in time series.
　さらに次のタイミングで、ブロック３におけるシンボル５が出力系統４０３Ａから出力され、シンボル６が出力系統４０４Ａから出力され、ブロック４におけるシンボル７が出力系統４０４Ｂから出力され、シンボル８が出力系統４０３Ｂから出力される。
　これにより、ニューラルネットワーク部５００には、同じタイミングで、余剰シンボルであるシンボル５およびシンボル８と、時系列に連続した対象シンボルであるシンボル６およびシンボル７とが入力される。 Further, at the next timing, symbol 5 in block 3 is output from output system 403A, symbol 6 is output from output system 404A, symbol 7 in block 4 is output from output system 404B, and symbol 8 is output from output system 403B Be done.
As a result, at the same timing, the neural network unit 500 receives the symbols 5 and 8 which are surplus symbols and the symbols 6 and 7 which are target symbols continuous in time series.
　このようにして、直列／並列変換部４０２は、時系列に連続している複数のシンボルをブロック単位で並列に出力する。
　そして、出力系統４０３Ａ、出力系統４０３Ｂ、出力系統４０４Ａおよび出力系統４０４Ｂのそれぞれから出力されたシンボルは、同じタイミングでニューラルネットワーク部５００に入力される。 Thus, the serial / parallel converter 402 outputs a plurality of symbols continuing in time series in parallel in block units.
The symbols output from the output system 403A, the output system 403B, the output system 404A, and the output system 404B are input to the neural network unit 500 at the same timing.
　次に、ニューラルネットワーク部５００について詳細に説明する。
　図３は、ニューラルネットワーク部５００の構成例を示すブロック図である。
　図３に示すように、ニューラルネットワーク部５００は、入力層５０１、中間層５０２および出力層５０３から構成されている。中間層５０２は、Ｍ段で構成される。Ｍ段とは１段または複数段である。 Next, the neural network unit 500 will be described in detail.
FIG. 3 is a block diagram showing a configuration example of the neural network unit 500. As shown in FIG.
As shown in FIG. 3, the neural network unit 500 includes an input layer 501, an intermediate layer 502, and an output layer 503. The middle layer 502 is configured in M stages. The M stage is one stage or a plurality of stages.
　入力１，入力２，入力３，・・・，入力ｍとして余剰シンボルと対象シンボルとが同じタイミングで入力層５０１に入力されると、これらのシンボルは、入力層５０１から中間層５０２に出力されて演算処理が施される。演算結果は、中間層５０２から出力層５０３に出力される。出力層５０３におけるｋ番目のニューロン素子の出力である出力ｋ（ｋ＝１，２，３，・・・，ｎ）は、対象シンボルの尤度を出力する。
　出力層５０３におけるニューロン素子数は、変調多値数に対してべき乗の関係にある。変調多値数は、１シンボルがとり得るシンボル数であり、４値位相変調信号に対しては４となる。つまり、対象シンボル数をＮ（Ｎ＝１，２，３，・・・，ｒ）とすると、４値位相変調信号の場合、出力層のニューロン素子数は４＾Ｎとなる。 When a surplus symbol and a target symbol are input to input layer 501 at the same timing as input 1, input 2, input 3,..., Input m, these symbols are output from input layer 501 to intermediate layer 502. Arithmetic processing is performed. The calculation result is output from the intermediate layer 502 to the output layer 503. An output k (k = 1, 2, 3,..., N) which is an output of the k-th neuron element in the output layer 503 outputs the likelihood of the target symbol.
The number of neuron elements in the output layer 503 is in the relation of power to the modulation multi-level number. The modulation multilevel number is the number of symbols that one symbol can take, and is 4 for a four-level phase modulation signal. That is, assuming that the number of target symbols is N (N = 1, 2, 3,..., R), the number of neuron elements in the output layer is 4 ^ N in the case of a four-level phase modulation signal.
　図４は、図３の入力層５０１、中間層５０２および出力層５０３の内部構成例を示す図である。入力層５０１、中間層５０２および出力層５０３のそれぞれは、少なくとも１つ以上のニューロン素子５１１を備える。ニューロン素子５１１は、入力信号に対して前段のニューロン素子との結合荷重を乗算する乗算器５１２と、入力信号と結合荷重との乗算和を非線形変換する非線形変換部５１３とを備えている。 FIG. 4 is a diagram showing an example of an internal configuration of the input layer 501, the intermediate layer 502 and the output layer 503 of FIG. Each of the input layer 501, the intermediate layer 502, and the output layer 503 includes at least one or more neuron elements 511. The neuron element 511 includes a multiplier 512 that multiplies an input signal with a connection weight with a previous-stage neuron element, and a non-linear conversion unit 513 that performs non-linear conversion on the multiplication sum of the input signal and the connection weight.
　例えば、いずれかの層にｐ個のニューロン素子５１１がある場合において、ニューロン素子１、ニューロン素子２、・・・、ニューロン素子ｐのそれぞれの入力数がｏであり、この層の出力数がｐであるものとする。
　ニューロン素子１では、乗算器５１２によって、入力ｉ（ｉ＝１，２，・・・，ｏ）に対応するシンボルｓｉと結合荷重ｗ１ｉとの乗算が実施される。
　ニューロン素子１の非線形変換部５１３は、乗算器５１２によって算出された乗算値の総和を算出し、この乗算和に対して非線形関数ｆ（ｘ）による非線形変換を行う。これらの処理を、ニューロン素子１からニューロン素子ｐのそれぞれが行うことにより、出力ｊ（ｊ＝１，２，３，・・・，ｐ）の出力値ｙｊが得られる。
　下記式（１）は、出力値ｙｊの一例である。
Figure JPOXMLDOC01-appb-I000001
For example, when there are p neuron elements 511 in any of the layers, the number of inputs of each of the neuron element 1, the neuron element 2,..., The neuron element p is o, and the number of outputs of this layer is p Shall be
In the neuron element 1, the multiplier 512 multiplies the symbol s i corresponding to the input i (i = 1, 2,..., O) by the coupling weight w 1i .
The non-linear conversion unit 513 of the neuron element 1 calculates the sum of the multiplication values calculated by the multiplier 512, and performs non-linear conversion with the non-linear function f (x) on the multiplication sum. The output value y j of the output j (j = 1, 2, 3,..., P) is obtained by each of the neuron element 1 to the neuron element p performing these processes.
The following equation (1) is an example of the output value y j .
Figure JPOXMLDOC01-appb-I000001
　非線形関数ｆ（ｘ）として、例えば、ステップ関数、シグモイド関数、ランプ関数などが挙げられる。
　また、出力層５０３におけるｎ個のニューロン素子５１１のそれぞれの出力は、ニューラルネットワーク部５００のｎ個の出力に相当する。ニューラルネットワーク部５００の出力からは、対象シンボルのクラスＣｎに対応する事後確率が出力される。 Examples of the non-linear function f (x) include a step function, a sigmoid function, and a ramp function.
The outputs of the n neuron elements 511 in the output layer 503 correspond to the n outputs of the neural network unit 500. From the output of the neural network unit 500, the posterior probability corresponding to the class C n of the target symbol is output.
　例えば、出力層５０３のｋ番目のニューロン素子の出力を出力ｋとし、このニューロン素子と前段のニューロン素子との間の結合荷重ベクトルをｗｋとし、ｋ番目のニューロン素子に入力される複数のシンボルであるシンボル群をφｋとする。さらに、正答クラスをＣ１とし、誤答クラスをＣ２とする。
　出力ｋで対象シンボルφが正答クラスＣ１である事後確率ｐ（Ｃ１｜ｋ，φ）は、例えば、下記式（２）に従って算出することができる。下記式（２）に示すように、ニューラルネットワーク部５００からは、正答に対するｎ通りの事後確率が出力される。
　なお、事後確率ｐ（Ｃ１｜ｋ，φ）は、出力ｋで対象シンボルφが正答クラスＣ１である尤度に相当する。
Figure JPOXMLDOC01-appb-I000002
For example, the output of the k-th neuron element in the output layer 503 and the output k, the coupling load vector between the neuron elements and the preceding neuron element and w k, a plurality of symbols input to the k-th neuron element the symbol group is the φ k. Furthermore, the correct answer class is C 1 , and the wrong answer class is C 2 .
The posterior probability p (C 1 | k, φ) that the target symbol φ is the correct answer class C 1 at the output k can be calculated, for example, according to the following equation (2). As shown in the following equation (2), the neural network unit 500 outputs n posterior probabilities for the correct answer.
The posterior probability p (C 1 | k, φ) corresponds to the likelihood that the target symbol φ is the correct answer class C 1 at the output k.
Figure JPOXMLDOC01-appb-I000002
　判定部６００は、ニューラルネットワーク部５００が算出したｎ通りの事後確率から、復調すべきシンボルに対応する事後確率を判定する。
　例えば、判定部６００は、下記式（３）に従ってｎ通りの事後確率のうち、最も大きい事後確率Ｓハットを判定する。
Figure JPOXMLDOC01-appb-I000003
The determination unit 600 determines the posterior probability corresponding to the symbol to be demodulated from the n posterior probabilities calculated by the neural network unit 500.
For example, the determination unit 600 determines the largest posterior probability S hat among n posterior probabilities according to the following equation (3).
Figure JPOXMLDOC01-appb-I000003
　復調部７００は、判定部６００によって判定された事後確率Ｓハットに基づいて、対象シンボルを復調する。４値振幅変調信号を復調する場合、判定部６００によって事後確率に対応したシンボル（－３，－１，１，３）が得られる。復調部７００は、判定部６００から得られたシンボル（－３，－１，１，３）を（００，０１，１１，１０）へ変換する。また、４値位相変調信号を復調する場合、判定部６００からシンボル（１＋ｊ，１＋ｊ，－１－ｊ，１－ｊ）が得られる。復調部７００は、シンボル（１＋ｊ，１＋ｊ，－１－ｊ，１－ｊ）を（１１，０１，００，１０）へ変換する。
　ニューラルネットワーク部５００における結合荷重が固定である場合、前述した一連の処理が繰り返し実行される。
　一方、ニューラルネットワーク部５００の学習で結合荷重を更新する場合は、結合荷重更新部８００によって結合荷重の更新が行われる。 Demodulation section 700 demodulates the target symbol based on posterior probability S hat determined by determination section 600. When the 4-value amplitude modulation signal is to be demodulated, the determination unit 600 obtains symbols (−3, −1, 1, 3) corresponding to the posterior probability. Demodulation section 700 converts the symbol (-3, -1, 1, 3) obtained from determination section 600 into (00, 01, 11, 10). Also, in the case of demodulating a four-level phase modulation signal, symbols (1 + j, 1 + j, -1-j, 1−j) are obtained from the determination unit 600. The demodulation unit 700 converts the symbols (1 + j, 1 + j, -1-j, 1-j) into (11, 01, 00, 10).
When the connection weight in the neural network unit 500 is fixed, the series of processes described above are repeatedly performed.
On the other hand, when the connection load is updated by learning of the neural network unit 500, the connection load update unit 800 updates the connection load.
　例えば、結合荷重更新部８００は、下記式（４）で表される尤度関数を結合荷重の更新に用いる。下記式（４）において、ｑｋは、シンボル群φｋが正答クラスＣ１である確率である。
Figure JPOXMLDOC01-appb-I000004
For example, the connection load update unit 800 uses the likelihood function represented by the following equation (4) for updating the connection load. In Equation (4) below, q k is the probability that the symbol group φ k is a correct answer class C 1 .
Figure JPOXMLDOC01-appb-I000004
　上記式（４）は単調な関数ではないため、結合荷重の更新に用いる目的関数ｅ（ｗ）が新たに定義される。下記式（５）は、目的関数の一例である。
Figure JPOXMLDOC01-appb-I000005
Since the above equation (4) is not a monotonous function, an objective function e (w) used for updating the coupling load is newly defined. The following equation (5) is an example of the objective function.
Figure JPOXMLDOC01-appb-I000005
　結合荷重更新部８００は、上記式（５）に示したｅ（ｗ）が最小となる結合荷重を算出する。例えば、ｅ（ｗ）を最小化する結合荷重の算出には、最小二乗を基準とした誤差逆伝搬法を用いることができる。
　このように上記式（１）に示す非線形関数を用いることで、通信相手の光通信器および伝送路に生じる非線形歪みが打ち消される。 The connection load update unit 800 calculates a connection load that minimizes e (w) shown in the above equation (5). For example, an error back propagation method based on least squares can be used to calculate the coupling weight that minimizes e (w).
As described above, by using the non-linear function shown in the above equation (1), non-linear distortion occurring in the optical communication device and the transmission path of the communication partner can be canceled out.
　ニューラルネットワーク部５００が、対象シンボルとともに余剰シンボルを入力することで、シンボル群φｋの次元が増え、確率ｑｋも高めることができる。
　確率ｑｋが高まると、上記式（５）に示したｅ（ｗ）の最小値がさらに引き下げられ、結果的に、結合荷重の更新において局所誤差の収束精度が高めることができる。
　このように、等化装置１０００では、非特許文献１に記載の非線形等化器よりも非線形歪みの等化精度が向上している。 When the neural network unit 500 inputs a surplus symbol together with the target symbol, the dimension of the symbol group φ k can be increased, and the probability q k can also be increased.
When the probability q k is increased, the minimum value of e (w) shown in the above equation (5) is further reduced, and as a result, the convergence accuracy of the local error can be enhanced in the update of the coupling load.
Thus, in the equalization device 1000, the equalization accuracy of nonlinear distortion is improved more than the nonlinear equalizer described in Non-Patent Document 1.
　次に動作について説明する。
　図５は、実施の形態１に係る等化方法を示すフローチャートである。
　光電変換部１００、受信信号調整部２００および線形等化部３００による処理は、図５に示す一連の処理の前に実行されているものとする。
　ステップＳＴ１において、ニューラルネットワーク入力部４００が、時系列に連続した複数のシンボルを含むディジタル信号を線形等化部３００から入力し、図２に示した処理を実施して、ディジタル信号に含まれる対象シンボルとともに余剰シンボルを出力する。 Next, the operation will be described.
FIG. 5 is a flowchart showing the equalization method according to the first embodiment.
It is assumed that the processing by the photoelectric conversion unit 100, the reception signal adjustment unit 200, and the linear equalization unit 300 is performed before the series of processing shown in FIG.
In step ST1, the neural network input unit 400 receives from the linear equalization unit 300 a digital signal including a plurality of symbols continuous in time series, performs the processing shown in FIG. 2, and is included in the digital signal. Output extra symbols along with the symbols.
　次に、ニューラルネットワーク部５００は、ニューラルネットワーク入力部４００から出力された対象シンボルおよび余剰シンボルを入力し、これらのシンボルと結合荷重との乗算和を非線形変換して、対象シンボルの尤度を算出する（ステップＳＴ２）。
　例えば、対象シンボルの尤度は、上記式（２）および上記式（３）から求められた事後確率である。 Next, the neural network unit 500 receives the target symbol and the surplus symbol output from the neural network input unit 400, non-linearly converts the multiplication sum of these symbols and the connection weight, and calculates the likelihood of the target symbol (Step ST2).
For example, the likelihood of the target symbol is the posterior probability obtained from the above equation (2) and the above equation (3).
　判定部６００が、ニューラルネットワーク部５００から出力された尤度のうち、復調すべきシンボルの尤度を判定する（ステップＳＴ３）。
　例えば、判定部６００は、上記式（３）に従って、ニューラルネットワーク部５００から出力された事後確率のうち、最も大きい事後確率を判定する。 The determination unit 600 determines the likelihood of the symbol to be demodulated among the likelihoods output from the neural network unit 500 (step ST3).
For example, the determination unit 600 determines the largest posterior probability among the posterior probabilities output from the neural network unit 500 according to the above equation (3).
　復調部７００が、判定部６００によって判定された尤度に基づいてシンボルを復調する（ステップＳＴ４）。
　次に、結合荷重更新部８００が更新モードであるか否かを判断する（ステップＳＴ５）。結合荷重更新部８００が更新モードでない場合（ステップＳＴ５；ＮＯ）、図５の一連の処理を終了する。一方、結合荷重更新部８００が更新モードである場合（ステップＳＴ５；ＹＥＳ）、結合荷重更新部８００は、復調部７００によって復調されたシンボルに基づいて、ニューラルネットワーク部５００における結合荷重を更新する（ステップＳＴ６）。例えば、結合荷重更新部８００は、上記式（５）に示したｅ（ｗ）が最小となる結合荷重を、更新値として算出する。 Demodulation section 700 demodulates the symbol based on the likelihood determined by determination section 600 (step ST4).
Next, it is determined whether the connection load update unit 800 is in the update mode (step ST5). If the combined load update unit 800 is not in the update mode (step ST5; NO), the series of processes in FIG. 5 are ended. On the other hand, when the connection load update unit 800 is in the update mode (step ST5; YES), the connection load update unit 800 updates the connection load in the neural network unit 500 based on the symbols demodulated by the demodulation unit 700 ( Step ST6). For example, the connection load update unit 800 calculates, as an update value, the connection load with which e (w) shown in the above equation (5) is minimized.
　次に非線形歪みの等化効果について説明する。
　図６は、４種類の光通信器で受信された受信光の受信平均光パワーとビット誤り率との関係を示すグラフである。図６に示す関係は、光信号の変調方式を４値振幅変調、ビットレートを５３．１Ｇｂｉｔ／ｓとして、シングルモードファイバで光信号を２０ｋｍ伝送して得られた結果である。 Next, the equalization effect of nonlinear distortion will be described.
FIG. 6 is a graph showing the relationship between the bit error rate and the received average light power of the received light received by the four types of optical communication devices. The relationship shown in FIG. 6 is the result obtained by transmitting an optical signal for 20 km in a single mode fiber, with the modulation method of the optical signal being four-value amplitude modulation and the bit rate being 53.1 Gbit / s.
　４種類の光通信器のそれぞれは、光検出器と、アナログ／ディジタル変換器（以下、Ａ／Ｄ変換器と記載する）を備える。光通信器において、受信光信号は、光検出器によって検出されて電気信号に変換され、受信光信号から変換された電気信号は、Ａ／Ｄ変換器によってディジタル信号に変換される。 Each of the four types of optical communication devices includes a photodetector and an analog / digital converter (hereinafter referred to as an A / D converter). In the optical communication device, the received light signal is detected by the light detector and converted to an electrical signal, and the electric signal converted from the received light signal is converted to a digital signal by an A / D converter.
　ディジタル信号は、ディジタルサンプリングオシロスコープによって８０ＧＳａ／ｓのサンプリングレートでサンプリングされて、シリアルデータとして蓄積される。
　図６に示す関係は、蓄積したシリアルデータを用いて、４種類の光通信器のそれぞれにおける非線形歪みの等化能力を、計算機上でオフライン解析した結果である。 The digital signal is sampled by the digital sampling oscilloscope at a sampling rate of 80 GSa / s and accumulated as serial data.
The relationship shown in FIG. 6 is the result of off-line analysis on a computer of the equalization ability of nonlinear distortion in each of the four types of optical communication devices using the stored serial data.
　４種類の光通信器は、光通信器Ａ、光通信器Ｂ、光通信器Ｃおよび光通信器Ｄである。
　光通信器Ａは、図１に示した構成要素のうち、線形等化部３００、ニューラルネットワーク入力部４００、ニューラルネットワーク部５００、判定部６００および結合荷重更新部８００を備えておらず、線形歪みおよび非線形歪みの両方を等化しない。
　図６の符号ａで示す関係は、光通信器Ａにおける受信平均光パワー（ｄＢｍ）とビット誤り率（以下、ＢＥＲと記載する）との関係である。 The four types of optical communication devices are an optical communication device A, an optical communication device B, an optical communication device C, and an optical communication device D.
The optical communication device A does not include the linear equalization unit 300, the neural network input unit 400, the neural network unit 500, the determination unit 600, and the connection weight update unit 800 among the components shown in FIG. Do not equalize both and non-linear distortion.
The relationship indicated by the symbol a in FIG. 6 is the relationship between the average received optical power (dBm) in the optical communication device A and the bit error rate (hereinafter referred to as BER).
　光通信器Ｂは、図１に示した構成要素のうち、ニューラルネットワーク入力部４００、ニューラルネットワーク部５００、判定部６００および結合荷重更新部８００を備えておらず、線形歪みを等化するが、非線形歪みを等化しない。
　図６の符号ｂで示す関係は、光通信器Ｂにおける受信平均光パワーとＢＥＲとの関係である。 Among the components shown in FIG. 1, the optical communication device B does not include the neural network input unit 400, the neural network unit 500, the determination unit 600, and the connection load update unit 800, and equalizes linear distortion. Do not equalize nonlinear distortion.
The relationship indicated by symbol b in FIG. 6 is the relationship between the average received optical power in the optical communication device B and the BER.
　光通信器Ｃは、図１に示した構成要素のうち、ニューラルネットワーク入力部４００を備えておらず、線形歪みおよび非線形歪みの両方を等化する。
　ただし、光通信器Ｃでは、入力層のニューロン素子数が３であり、出力層のニューロン素子数が６４であり、中間層が１段であるニューラルネットワーク部を用いている。
　すなわち、光通信器Ｃは、非特許文献１に記載された非線形歪み等化器を備えた通信器に相当する。
　図６の符号ｃで示す関係は、光通信器Ｃにおける受信平均光パワーとＢＥＲとの関係である。 Among the components shown in FIG. 1, the optical communication device C does not include the neural network input unit 400, and equalizes both linear distortion and non-linear distortion.
However, in the optical communication device C, a neural network unit in which the number of neuron elements in the input layer is 3, the number of neuron elements in the output layer is 64, and the number of intermediate layers is one, is used.
That is, the optical communication device C corresponds to a communication device provided with the non-linear distortion equalizer described in Non-Patent Document 1.
The relationship indicated by symbol c in FIG. 6 is the relationship between the average received optical power in the optical communication device C and the BER.
　光通信器Ｄは、図１に示した等化装置１０００を備える光通信器である。
　ここで、ニューラルネットワーク入力部４００は、対象シンボル数を３シンボルとし、余剰シンボル数を７２シンボルとしている。また、ニューラルネットワーク部５００は、入力層５０１のニューロン素子数が７５であり、出力層５０３のニューロン素子数が６４であり、中間層５０２が１段である。
　図６の符号ｄで示す関係は、光通信器Ｄにおける受信平均光パワーとＢＥＲとの関係である。 The optical communication device D is an optical communication device provided with the equalizer 1000 shown in FIG.
Here, the neural network input unit 400 sets the number of target symbols as 3 symbols and the number of surplus symbols as 72 symbols. In the neural network unit 500, the number of neuron elements in the input layer 501 is 75, the number of neuron elements in the output layer 503 is 64, and the intermediate layer 502 is one stage.
The relationship indicated by symbol d in FIG. 6 is the relationship between the average received optical power in the optical communication device D and the BER.
　等化装置１０００を備えた光通信器Ｄでは、ＢＥＲが２．０×１０－４の点において、－１３．７（ｄＢｍ）の受信感度となっている。
　このように、光通信器Ｂで得られた受信感度に対して１．０（ｄＢｍ）改善され、光通信器Ｃで得られた受信感度に対しては０．６５（ｄＢｍ）改善されている。 The optical communication device D provided with the equalizer 1000 has a reception sensitivity of −13.7 (dBm) at a point of BER of 2.0 × 10 −4 .
Thus, the reception sensitivity obtained by the optical communication device B is improved by 1.0 (dBm), and the reception sensitivity obtained by the optical communication device C is improved by 0.65 (dBm). .
　なお、等化装置１０００には、必ずしも線形等化部３００を設けなくてもよい。
　例えば、ニューラルネットワーク部５００が、光通信器および伝送路に生じる線形歪みおよび非線形歪みの両方を等化してもよい。
　ただし、ニューラルネットワーク部５００の中間層での演算量が増加するので、中間層の構成が繁雑化する。そこで、ニューラルネットワーク部５００は、線形等化部３００が線形歪みを除去した後に非線形歪みを除去している。これにより、中間層の構成を簡素化することが可能となる。 The equalizer 1000 may not necessarily include the linear equalizer 300.
For example, the neural network unit 500 may equalize both linear distortion and non-linear distortion occurring in the optical communication device and the transmission line.
However, since the amount of calculation in the middle layer of the neural network unit 500 increases, the structure of the middle layer becomes complicated. Therefore, the neural network unit 500 removes non-linear distortion after the linear equalization unit 300 removes linear distortion. This makes it possible to simplify the configuration of the middle layer.
　等化装置１０００を備えた光通信器Ｄにおいて、ニューラルネットワーク部５００は、中間層が１段である。
　ただし、光通信器Ｄで得られた受信感度は、図６に示すように、線形歪みのみを除去する光通信器Ｂで得られた受信感度に対して１．０（ｄＢｍ）改善されている。 In the optical communication device D provided with the equalizer 1000, the neural network unit 500 has one intermediate layer.
However, as shown in FIG. 6, the reception sensitivity obtained by the optical communication device D is improved by 1.0 (dBm) with respect to the reception sensitivity obtained by the optical communication device B that removes only linear distortion. .
　次に、ニューラルネットワーク入力部の別の構成について説明する。
　図７は、ニューラルネットワーク入力部４００Ａの構成を示すブロック図であり、ニューラルネットワーク入力部４００Ａは、ニューラルネットワーク入力部４００の変形例である。図７に示すように、ニューラルネットワーク入力部４００Ａは、ランダム信号生成部４０５Ａ、ランダム信号生成部４０５Ｂおよび直列／並列変換部４０６を備える。 Next, another configuration of the neural network input unit will be described.
FIG. 7 is a block diagram showing a configuration of neural network input unit 400A. Neural network input unit 400A is a modification of neural network input unit 400. Referring to FIG. As shown in FIG. 7, the neural network input unit 400A includes a random signal generator 405A, a random signal generator 405B, and a serial / parallel converter 406.
　ランダム信号生成部４０５Ａおよびランダム信号生成部４０５Ｂのそれぞれは、直列／並列変換部４０６に入力される、時系列に連続したシンボルとは無関係に、余剰シンボルとしてランダムシンボルを生成して出力する。ランダムシンボルは、シンボルが無作為に並んだシンボル系列である。 Each of the random signal generation unit 405A and the random signal generation unit 405B generates and outputs a random symbol as a surplus symbol regardless of the time-sequential symbols input to the serial / parallel conversion unit 406. A random symbol is a symbol sequence in which symbols are randomly arranged.
　直列／並列変換部４０６は、線形等化部３００から時系列に連続した複数のシンボルを入力すると、シンボルの出力形式をブロック単位で並列出力に変換する。並列出力では、ブロック内の複数のシンボルが同じタイミングで出力される。
　直列／並列変換部４０６は、出力系統４０８Ａおよび出力系統４０８Ｂを備える。
　ランダム信号生成部４０５Ａは、出力系統４０７Ａを備える。
　ランダム信号生成部４０５Ｂは、出力系統４０７Ｂを備える。 When the serial / parallel conversion unit 406 receives a plurality of consecutive symbols in time series from the linear equalization unit 300, the serial / parallel conversion unit 406 converts the output format of the symbols into parallel output in block units. In parallel output, a plurality of symbols in a block are output at the same timing.
The serial / parallel converter 406 includes an output system 408A and an output system 408B.
The random signal generator 405A includes an output system 407A.
The random signal generation unit 405B includes an output system 407B.
　出力系統４０８Ａおよび出力系統４０８Ｂは、時系列に連続した対象シンボルを出力する第１の出力系統である。
　第１の出力系統は、例えば、変調多値数を底とした出力層５０３のニューロン素子数の対数分だけ設けられて、時系列に連続した複数の対象シンボルの系列を出力する。 The output system 408A and the output system 408B are first output systems that output target symbols continuous in time series.
The first output system is provided, for example, by the logarithm of the number of neuron elements in the output layer 503 with the modulation multilevel number at the bottom, and outputs a series of a plurality of target symbols continuous in time series.
　出力系統４０７Ａおよび出力系統４０７Ｂは、ランダム信号生成部４０５Ａおよび４０５Ｂによってそれぞれ生成されたランダムシンボルを出力する第２の出力系統である。
　第２の出力系統は、出力層５０３のニューロン素子数から第１の出力系統の数を減算した数だけ設けられて、無作為に並んだ余剰シンボルの系列を出力する。 The output system 407A and the output system 407B are second output systems that output the random symbols generated by the random signal generation units 405A and 405B.
The second output system is provided by a number obtained by subtracting the number of first output systems from the number of neuron elements in the output layer 503, and outputs a series of randomly arranged redundant symbols.
　図７は、直列／並列変換部４０６の入力側で紙面の右側から左側に時間が経過し、ランダム信号生成部４０５Ａ、ランダム信号生成部４０５Ｂおよび直列／並列変換部４０６のそれぞれの出力側で、紙面の左側から右側に時間が経過するように記載している。
　すなわち、直列／並列変換部４０６には、シンボル１，シンボル２，・・・，シンボル６の順でシンボルが入力される。最初に、ランダム信号生成部４０５ＡからシンボルＡが出力され、直列／並列変換部４０６からシンボル１およびシンボル２が出力され、ランダム信号生成部４０５ＢからシンボルＤが出力される。次のタイミングで、シンボルＢ，シンボル３，シンボル４，シンボルＥが出力され、さらに次のタイミングで、シンボルＣ，シンボル５，シンボル６，シンボルＦが出力される。 In FIG. 7, time elapses from the right to the left of the paper on the input side of the serial / parallel converter 406, and the output sides of the random signal generator 405A, the random signal generator 405B, and the serial / parallel converter 406 are as follows. It is stated that time passes from the left side to the right side of the paper.
That is, the serial / parallel converter 406 receives symbols in the order of symbol 1, symbol 2,..., Symbol 6. First, the symbol A is output from the random signal generator 405A, the symbol 1 and the symbol 2 are output from the serial / parallel converter 406, and the symbol D is output from the random signal generator 405B. At the next timing, symbol B, symbol 3, symbol 4, and symbol E are output, and at the next timing, symbol C, symbol 5, symbol 6, and symbol F are output.
　以下、図７について詳細に説明する。ここで、ブロックサイズは“２”であり、直列／並列変換部４０６は、１ブロック分のシンボルを順次出力する。
　すなわち、直列／並列変換部４０６は、線形等化部３００から、シンボル１、シンボル２、シンボル３、シンボル４、シンボル５、シンボル６をシリアルに入力すると、２シンボルごとに並列に出力する。 Hereinafter, FIG. 7 will be described in detail. Here, the block size is “2”, and the serial / parallel converter 406 sequentially outputs one block of symbols.
That is, when serial / parallel converter 406 serially inputs symbol 1, symbol 2, symbol 3, symbol 4, symbol 5, and symbol 6 from linear equalizer 300, it outputs in parallel every two symbols.
　同じタイミングで、シンボル１が出力系統４０８Ａから出力され、シンボル２が出力系統４０８Ｂから出力され、ランダム信号生成部４０５Ａが生成したシンボルＡが出力系統４０７Ａから出力され、ランダム信号生成部４０５Ｂが生成したシンボルＤが出力系統４０７Ｂから出力される。
　これにより、ニューラルネットワーク部５００には、同じタイミングで、余剰シンボルであるシンボルＡおよびシンボルＤと、時系列に連続した対象シンボルであるシンボル１およびシンボル２とが入力される。 At the same timing, symbol 1 is output from the output channel 408A, symbol 2 is output from the output channel 408B, symbol A generated by the random signal generator 405A is output from the output channel 407A, and the random signal generator 405B is generated. The symbol D is output from the output system 407B.
As a result, at the same timing, the neural network unit 500 receives the symbol A and the symbol D which are surplus symbols, and the symbols 1 and 2 which are the target symbols continuous in time series.
　次のタイミングで、シンボル３が出力系統４０８Ａから出力され、シンボル４が出力系統４０８Ｂから出力され、ランダム信号生成部４０５Ａが生成したシンボルＢが出力系統４０７Ａから出力され、ランダム信号生成部４０５Ｂが生成したシンボルＥが出力系統４０７Ｂから出力される。
　これにより、ニューラルネットワーク部５００には、同じタイミングで、余剰シンボルであるシンボルＢおよびシンボルＥと、時系列に連続した対象シンボルであるシンボル３およびシンボル４とが入力される。 At the next timing, symbol 3 is output from output system 408A, symbol 4 is output from output system 408B, symbol B generated by random signal generator 405A is output from output system 407A, and random signal generator 405B generates The output symbol 407 is output from the output system 407B.
As a result, to the neural network unit 500, at the same timing, the symbols B and E which are surplus symbols and the symbols 3 and 4 which are target symbols continuous in time series are inputted.
　さらに次のタイミングで、シンボル５が出力系統４０８Ａから出力され、シンボル６が出力系統４０８Ｂから出力され、ランダム信号生成部４０５Ａが生成したシンボルＣが出力系統４０７Ａから出力され、ランダム信号生成部４０５Ｂが生成したシンボルＦが出力系統４０７Ｂから出力される。
　これにより、ニューラルネットワーク部５００には、同じタイミングで、余剰シンボルであるシンボルＣおよびシンボルＦと、時系列に連続した対象シンボルであるシンボル５およびシンボル６とが入力される。 Further, at the next timing, the symbol 5 is output from the output system 408A, the symbol 6 is output from the output system 408B, the symbol C generated by the random signal generator 405A is output from the output system 407A, and the random signal generator 405B The generated symbol F is output from the output system 407B.
As a result, at the same timing, the neural network unit 500 receives the symbols C and F, which are surplus symbols, and the symbols 5 and 6, which are object symbols continuous in time series.
　このようにして、直列／並列変換部４０６は、時系列に連続している複数のシンボルをブロック単位で並列に出力する。
　そして、出力系統４０７Ａ、出力系統４０７Ｂ、出力系統４０８Ａおよび出力系統４０８Ｂのそれぞれから出力されたシンボルは、同じタイミングでニューラルネットワーク部５００に入力される。 Thus, serial / parallel converter 406 outputs a plurality of symbols continuing in time series in parallel in block units.
The symbols output from each of the output system 407A, the output system 407B, the output system 408A, and the output system 408B are input to the neural network unit 500 at the same timing.
　なお、直列／並列変換部４０６が２つの対象シンボルを並列に順次出力する例を示したが、１つの対象シンボルのみを順次出力してもよく、３つ以上の対象シンボルを並列に順次出力してもよい。
　また、図２および図７には、複数の第１の出力系統が並んで配置され、第２の出力系統は、第１の出力系統の並びの両側にそれぞれ配置されたニューラルネットワーク入力部を示したが、等化装置１０００は、この配置に限定されるものではない。第１の出力系統と第２の出力系統の配置順序はランダムであってもよい。 Although an example in which the serial / parallel converter 406 sequentially outputs two target symbols in parallel has been shown, only one target symbol may be sequentially output, and three or more target symbols are sequentially output in parallel. May be
Also, FIGS. 2 and 7 show neural network input units in which a plurality of first output systems are arranged side by side, and a second output system is arranged on both sides of the array of first output systems. However, the equalizer 1000 is not limited to this arrangement. The arrangement order of the first output system and the second output system may be random.
　図８Ａは、等化装置１０００の機能を実現するハードウェア構成を示すブロック図である。図８Ａにおいて、光電変換器９０１は、入力した光信号を電気信号に変換する装置であり、図１における光電変換部１００に相当する。光電変換器９０１は、内部に局部発振光を発振する発振器を備えていてもよい。
　図８Ｂは、等化装置１０００の機能を実現するソフトウェアを実行するハードウェア構成を示す図である。図８Ｂにおいて、光電変換器１００１は、入力した光信号を電気信号に変換する装置であり、図１における光電変換部１００に相当する。光電変換器１００１は、内部に局部発振光を発振する発振器を備えていてもよい。 FIG. 8A is a block diagram showing a hardware configuration for realizing the function of the equalizer 1000. As shown in FIG. In FIG. 8A, a photoelectric converter 901 is a device that converts an input optical signal into an electric signal, and corresponds to the photoelectric conversion unit 100 in FIG. The photoelectric converter 901 may include an oscillator that oscillates local oscillation light.
FIG. 8B is a diagram showing a hardware configuration for executing software for realizing the function of the equalization device 1000. In FIG. 8B, a photoelectric converter 1001 is a device that converts an input optical signal into an electric signal, and corresponds to the photoelectric conversion unit 100 in FIG. The photoelectric converter 1001 may include an oscillator that oscillates local oscillation light.
　等化装置１０００における、光電変換部１００、受信信号調整部２００、線形等化部３００、ニューラルネットワーク入力部４００または４００Ａ、ニューラルネットワーク部５００、判定部６００、復調部７００および結合荷重更新部８００のそれぞれの機能は、処理回路によって実現される。
　すなわち、等化装置１０００は、図５に示したフローチャートのそれぞれの処理を実行するための処理回路を備える。処理回路は、専用のハードウェアであってもよく、メモリに記憶されたプログラムを実行するＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）であってもよい。 The photoelectric conversion unit 100, the received signal adjustment unit 200, the linear equalization unit 300, the neural network input unit 400 or 400A, the neural network unit 500, the determination unit 600, the demodulation unit 700, and the connection weight update unit 800 in the equalization device 1000. Each function is realized by a processing circuit.
That is, the equalization device 1000 includes processing circuits for executing the respective processing of the flowchart shown in FIG. The processing circuit may be dedicated hardware or may be a central processing unit (CPU) that executes a program stored in a memory.
　処理回路が図８Ａに示す専用のハードウェアである場合、処理回路９０２は、例えば、単一回路、複合回路、プログラム化したプロセッサ、並列プログラム化したプロセッサ、ＡＳＩＣ（Ａｐｐｌｉｃａｔｉｏｎ　Ｓｐｅｃｉｆｉｃ　Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）、ＦＰＧＡ（Ｆｉｅｌｄ－Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）またはこれらを組み合わせたものが該当する。 When the processing circuit is dedicated hardware shown in FIG. 8A, the processing circuit 902 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an application specific integrated circuit (ASIC), an FPGA (FPGA) Field-Programmable Gate Array) or a combination thereof is applicable.
　処理回路が図８Ｂに示すプロセッサ１００２である場合、光電変換部１００、受信信号調整部２００、線形等化部３００、ニューラルネットワーク入力部４００または４００Ａ、ニューラルネットワーク部５００、判定部６００、復調部７００および結合荷重更新部８００のそれぞれの機能は、ソフトウェア、ファームウェアまたはソフトウェアとファームウェアとの組み合わせによって実現される。ソフトウェアまたはファームウェアはプログラムとして記述され、メモリ１００３に記憶される。 When the processing circuit is the processor 1002 shown in FIG. 8B, the photoelectric conversion unit 100, the reception signal adjustment unit 200, the linear equalization unit 300, the neural network input unit 400 or 400A, the neural network unit 500, the determination unit 600, the demodulation unit 700. The respective functions of the connection load update unit 800 are realized by software, firmware or a combination of software and firmware. Software or firmware is described as a program and stored in the memory 1003.
　プロセッサ１００２は、メモリ１００３に記憶されたプログラムを読み出して実行することで、光電変換部１００、受信信号調整部２００、線形等化部３００、ニューラルネットワーク入力部４００または４００Ａ、ニューラルネットワーク部５００、判定部６００、復調部７００および結合荷重更新部８００のそれぞれの機能を実現する。
　すなわち、等化装置１０００は、プロセッサ１００２によって実行されたときに、図５に示す一連の処理のそれぞれが結果的に実行されるプログラムを記憶するためのメモリ１００３を備える。
　これらのプログラムは、光電変換部１００、受信信号調整部２００、線形等化部３００、ニューラルネットワーク入力部４００または４００Ａ、ニューラルネットワーク部５００、判定部６００、復調部７００および結合荷重更新部８００の手順または方法を、コンピュータに実行させるものである。 The processor 1002 reads out and executes the program stored in the memory 1003 to thereby execute the photoelectric conversion unit 100, the reception signal adjustment unit 200, the linear equalization unit 300, the neural network input unit 400 or 400A, the neural network unit 500, The respective functions of unit 600, demodulation unit 700 and coupling load update unit 800 are realized.
That is, the equalizing apparatus 1000 includes a memory 1003 for storing a program which is executed by the processor 1002 and each of the series of processes shown in FIG. 5 is consequently executed.
These programs include the procedures of the photoelectric conversion unit 100, the received signal adjustment unit 200, the linear equalization unit 300, the neural network input unit 400 or 400A, the neural network unit 500, the determination unit 600, the demodulation unit 700, and the connection weight update unit 800. Or the method is to cause a computer to execute.
　メモリ１００３には、例えば、ＲＡＭ（Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、ＲＯＭ（Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）、フラッシュメモリ、ＥＰＲＯＭ（Ｅｒａｓａｂｌｅ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）、ＥＥＰＲＯＭ（Ｅｌｅｃｔｒｉｃａｌｌｙ－ＥＰＲＯＭ）などの不揮発性または揮発性の半導体メモリ、磁気ディスク、フレキシブルディスク、光ディスク、コンパクトディスク、ミニディスク、ＤＶＤなどが該当する。 The memory 1003 is, for example, a nonvolatile or volatile semiconductor memory such as a random access memory (RAM), a read only memory (ROM), a flash memory, an erasable programmable read only memory (EPROM), or an EEPROM (electrically-EPROM). A magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD, etc. correspond.
　光電変換部１００、受信信号調整部２００、線形等化部３００、ニューラルネットワーク入力部４００または４００Ａ、ニューラルネットワーク部５００、判定部６００、復調部７００および結合荷重更新部８００のそれぞれの機能について一部を専用のハードウェアで実現し、一部をソフトウェアまたはファームウェアで実現してもよい。
　例えば、光電変換部１００、受信信号調整部２００、線形等化部３００、ニューラルネットワーク入力部４００または４００Ａおよびニューラルネットワーク部５００については、専用のハードウェアとしての処理回路９０２でその機能を実現する。判定部６００、復調部７００および結合荷重更新部８００は、プロセッサ１００２が、メモリ１００３に記憶されたプログラムを実行することによってその機能を実現してもよい。
　このように、処理回路は、ハードウェア、ソフトウェア、ファームウェア、または、これらの組み合わせによって上記機能のそれぞれを実現することができる。 Partial functions of respective functions of photoelectric conversion unit 100, received signal adjustment unit 200, linear equalization unit 300, neural network input unit 400 or 400A, neural network unit 500, determination unit 600, demodulation unit 700, and connection weight update unit 800 May be realized by dedicated hardware, and some may be realized by software or firmware.
For example, the functions of the photoelectric conversion unit 100, the reception signal adjustment unit 200, the linear equalization unit 300, the neural network input unit 400 or 400A, and the neural network unit 500 are realized by the processing circuit 902 as dedicated hardware. The determination unit 600, the demodulation unit 700, and the connection load update unit 800 may realize the function by the processor 1002 executing a program stored in the memory 1003.
Thus, the processing circuit can realize each of the above functions by hardware, software, firmware, or a combination thereof.
　以上のように、実施の形態１に係る等化装置１０００は、入力層５０１のニューロン素子数が出力層５０３よりも多いニューラルネットワーク部５００が、時系列に連続した対象シンボルとともに、余剰シンボルを入力して、対象シンボルの尤度を算出する。
　また、ニューラルネットワーク入力部４００は、変調多値数を底とした出力層５０３におけるニューロン素子数の対数分だけ設けられて、対象シンボルを出力する出力系統と、出力層５０３におけるニューロン素子数から出力系統の数を減算した数だけ設けられて、余剰シンボルを出力する余剰出力系統とを備える。
　これにより、ニューラルネットワーク部５００の交差エントロピーが小さくなるので、誤差逆伝搬法を用いた結合荷重の更新において局所誤差の収束精度が高くなり、等化装置１０００の非線形歪みの等化精度を高めることができる。 As described above, in the equalizer 1000 according to the first embodiment, the neural network unit 500 having the number of neuron elements in the input layer 501 larger than that in the output layer 503 inputs surplus symbols as well as target symbols continuous in time series. Then, the likelihood of the target symbol is calculated.
Further, the neural network input unit 400 is provided by the number of log of the number of neuron elements in the output layer 503 with the modulation multilevel number at the bottom, and outputs from the output system that outputs the target symbol and the number of neuron elements in the output layer 503 The system is provided with a surplus output system which is provided by the number obtained by subtracting the number of systems, and which outputs a surplus symbol.
Thereby, since the cross entropy of the neural network unit 500 is reduced, the convergence accuracy of the local error becomes high in the updating of the connection weight using the error back propagation method, and the equalization accuracy of the nonlinear distortion of the equalizer 1000 is improved. Can.
　実施の形態１に係る等化装置１０００において、余剰出力系統は、余剰シンボルとしてランダムシンボルを出力する。このように構成しても、誤差逆伝搬法を用いた結合荷重の更新において局所誤差の収束精度が高くなるので、等化装置１０００の非線形歪みの等化精度を高めることができる。 In equalization apparatus 1000 according to Embodiment 1, the surplus output system outputs random symbols as surplus symbols. Even with this configuration, since the convergence accuracy of the local error is high in updating the coupling weight using the error back propagation method, the equalization accuracy of the non-linear distortion of the equalizer 1000 can be enhanced.
　なお、本発明は上記実施の形態に限定されるものではなく、本発明の範囲内において、実施の形態の任意の構成要素の変形もしくは実施の形態の任意の構成要素の省略が可能である。 Note that the present invention is not limited to the above embodiment, and modifications of any component of the embodiment or omission of any component of the embodiment can be made within the scope of the present invention.
　この発明に係る等化装置は、非線形歪みの等化精度を高めることができるので、多値の光情報の送受信を行う光通信装置に利用することができる。 The equalizer according to the present invention can improve the equalization accuracy of non-linear distortion, and can therefore be used for an optical communication device that transmits and receives multilevel optical information.
　１００　光電変換部、２００　受信信号調整部、３００　線形等化部、４００，４００Ａ　ニューラルネットワーク入力部、４０１　スライディングウィンドウ、４０２，４０６　直列／並列変換部、４０３Ａ，４０３Ｂ，４０４Ａ，４０４Ｂ，４０７Ａ，４０７Ｂ，４０８Ａ，４０８Ｂ　出力系統、４０５Ａ，４０５Ｂ　ランダム信号生成部、５００　ニューラルネットワーク部、５０１　入力層、５０２　中間層、５０３　出力層、５１１　ニューロン素子、５１２　乗算器、５１３　非線形変換部、６００　判定部、７００　復調部、８００　結合荷重更新部、９０１，１００１　光電変換器、９０２　処理回路、１０００　等化装置、１００２　プロセッサ、１００３　メモリ。 DESCRIPTION OF SYMBOLS 100 photoelectric conversion part, 200 received signal adjustment part, 300 linear equalization part, 400, 400A neural network input part, 401 sliding window, 402, 406 serial / parallel conversion part, 403A, 403B, 404A, 404B, 407A, 407B, 408A, 408B output system, 405A, 405B random signal generation unit, 500 neural network unit, 501 input layer, 502 intermediate layer, 503 output layer, 511 neuron element, 512 multiplier, 513 nonlinear conversion unit, 600 determination unit, 700 demodulation Part, 800 Coupling load update part, 901, 1001 photoelectric converter, 902 processing circuit, 1000 equalizer, 1002 processor, 1003 memory.

Claims (7)

  1. 　時系列に連続した複数のシンボルを含む信号を入力して、前記信号に含まれる時系列に連続した対象シンボルとともに、時系列に連続しない余剰シンボルを出力するニューラルネットワーク入力部と、
    　入力層、中間層および出力層から構成され、前記入力層のニューロン素子数が前記出力層よりも多い関係にあり、前記中間層が１段または複数段であり、前記ニューラルネットワーク入力部から出力されたシンボルとニューロン素子間の結合荷重との乗算和を非線形変換して前記対象シンボルの尤度を算出するニューラルネットワーク部と、
    　前記ニューラルネットワーク部から出力された尤度のうち、復調すべきシンボルの尤度を判定する判定部と、
    　前記判定部によって判定された尤度に基づいてシンボルを復調する復調部と、
    　前記復調部によって復調されたシンボルに基づいて、前記ニューラルネットワーク部における結合荷重を更新する結合荷重更新部と
    　を備えたことを特徴とする等化装置。     A neural network input unit which inputs a signal including a plurality of symbols continuous in time series, and outputs a surplus symbol not continuous in time series together with a target symbol continuous in time series included in the signal;
    The input layer, the intermediate layer, and the output layer, wherein the number of neuron elements in the input layer is larger than that in the output layer, the intermediate layer has one or more stages, and is output from the neural network input unit A neural network unit that non-linearly transforms a multiplication sum of a selected symbol and a connection weight between neuron elements to calculate the likelihood of the target symbol;
    A determination unit that determines the likelihood of a symbol to be demodulated among the likelihoods output from the neural network unit;
    A demodulation unit that demodulates a symbol based on the likelihood determined by the determination unit;
    And a coupling weight updating unit that updates coupling weights in the neural network unit based on the symbols demodulated by the demodulation unit.
  2. 　前記ニューラルネットワーク部は、前記出力層におけるニューロン素子数が変調多値数に対してべき乗の関係にあること
    　を特徴とする請求項１記載の等化装置。     The equalization device according to claim 1, wherein the neural network unit has the number of neuron elements in the output layer in a power-multiling relation with respect to a modulation multi-level number.
  3. 　前記ニューラルネットワーク入力部は、
    　変調多値数を底とした前記出力層におけるニューロン素子数の対数分だけ設けられて、前記対象シンボルを出力する第１の出力系統と、
    　前記出力層におけるニューロン素子数から前記第１の出力系統の数を減算した数だけ設けられて、前記余剰シンボルを出力する第２の出力系統とを備えたこと
    　を特徴とする請求項１または請求項２記載の等化装置。     The neural network input unit is
    A first output system for providing the target symbol by providing a number of logarithms of the number of neuron elements in the output layer based on the modulation multi-value number;
    A second output system for outputting the extra symbols, provided by the number obtained by subtracting the number of the first output system from the number of neuron elements in the output layer, is provided. The equalizer according to Item 2.
  4. 　前記第２の出力系統は、前記余剰シンボルとしてランダムシンボルを出力すること
    　を特徴とする請求項３記載の等化装置。     The equalizer according to claim 3, wherein the second output system outputs a random symbol as the extra symbol.
  5. 　光信号を電気信号に変換する光電変換部と、
    　前記光電変換部から出力された前記電気信号を遅延調整する受信信号調整部と、
    　前記受信信号調整部から出力された前記電気信号に含まれるシンボルの線形歪みを等化して前記ニューラルネットワーク入力部に出力する線形等化部と
    　を備えたことを特徴とする請求項１記載の等化装置。     A photoelectric conversion unit that converts an optical signal into an electrical signal;
    A received signal adjustment unit for delay adjusting the electric signal output from the photoelectric conversion unit;
    A linear equalization unit for equalizing linear distortion of symbols contained in the electric signal output from the reception signal adjustment unit and outputting the result to the neural network input unit; Device.
  6. 　前記光電変換部は、多値振幅変調フォーマットの光信号を前記電気信号に変換すること
    　を特徴とする請求項５記載の等化装置。     6. The equalizer according to claim 5, wherein the photoelectric conversion unit converts an optical signal of a multi-value amplitude modulation format into the electric signal.
  7. 　ニューラルネットワーク入力部が、時系列に連続した複数のシンボルを含む信号を入力して、前記信号に含まれる対象シンボルとともに、時系列に連続しない余剰シンボルを出力するステップと、
    　入力層、中間層および出力層から構成され、前記入力層のニューロン素子数が前記出力層よりも多い関係にあり、前記中間層が１段または複数段であるニューラルネットワーク部が、前記ニューラルネットワーク入力部から出力されたシンボルとニューロン素子間の結合荷重との乗算和を非線形変換して前記対象シンボルの尤度を算出するステップと、
    　判定部が、前記ニューラルネットワーク部から出力された尤度のうち、復調すべきシンボルの尤度を判定するステップと、
    　復調部が、前記判定部によって判定された尤度に基づいてシンボルを復調するステップと、
    　結合荷重更新部が、前記復調部によって復調されたシンボルに基づいて、前記ニューラルネットワーク部における結合荷重を更新するステップと
    　を備えたことを特徴とする等化方法。     The neural network input unit inputs a signal including a plurality of symbols continuous in time series, and outputs a surplus symbol not continuous in time series together with the target symbol included in the signal;
    The neural network unit comprises an input layer, an intermediate layer, and an output layer, wherein the number of neuron elements in the input layer is larger than that in the output layer, and the intermediate layer includes one or more stages. Non-linearly converting the multiplication sum of the symbol output from the unit and the connection weight between the neuron elements to calculate the likelihood of the target symbol;
    Determining a likelihood of a symbol to be demodulated among the likelihoods output from the neural network unit;
    The demodulator demodulates the symbol based on the likelihood determined by the determiner;
    And e. Updating the connection weight in the neural network unit based on the symbols demodulated by the demodulation unit.
PCT/JP2017/038173 2017-10-23 2017-10-23 Equalization device and equalization method WO2019082239A1 (en)

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CN112036543B (en) * 2020-07-16 2022-05-03 北京大学 Time domain equalizer combining neural network equalization and linear equalization and equalization method

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