WO2019071485A1 - 一种用于硬件模组的检测*** - Google Patents

一种用于硬件模组的检测*** Download PDF

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Publication number
WO2019071485A1
WO2019071485A1 PCT/CN2017/105756 CN2017105756W WO2019071485A1 WO 2019071485 A1 WO2019071485 A1 WO 2019071485A1 CN 2017105756 W CN2017105756 W CN 2017105756W WO 2019071485 A1 WO2019071485 A1 WO 2019071485A1
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pull
module
hardware
gpio
input module
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PCT/CN2017/105756
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English (en)
French (fr)
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朱勇
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深圳传音通讯有限公司
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Priority to PCT/CN2017/105756 priority Critical patent/WO2019071485A1/zh
Publication of WO2019071485A1 publication Critical patent/WO2019071485A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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  • the present invention relates to the field of electronic device detection, and more particularly to a detection system for a hardware module.
  • an object of the present invention is to provide a detection system for a hardware module, which can realize rapid detection and differentiation for products of different vendors.
  • the invention discloses a detection system for a hardware module, the detection system comprises: an interconnected GPIO module and a hardware module, the GPIO module comprises: a pull-up input module, a pull-down input module and a GPIO port, wherein ,
  • the pull-up input module and the pull-down input module are connected to the GPIO port to control the pull-up enable or pull-down enable of the GPIO port;
  • the hardware module includes an input/output interface connected to the GPIO port and a detection interface component disposed in the hardware module, where the detection interface component includes:
  • the hardware IO end, the breaking end, and the ground end are respectively connected to the input/output interface, and feedback a high level or a low level to the pull-up input module or the pull-down input module to detect the configuration of the hardware module.
  • the pull-up input module comprises:
  • a pull-up resistor and a first switch connected to the pull-up resistor, and the pull-up resistor and the first switch are connected between the first end and the power source positive VDD;
  • the pull-down input module includes:
  • the hardware IO end is a Vendor_ID pin of the hardware module.
  • the detecting interface component further includes:
  • the single-pole three-throw switch is disposed in the hardware module, and includes a switch piece, a static contact, and a first movable contact, a second movable contact, and a third movable contact;
  • One end of the switch piece is pivotally connected to the static contact, and the other end is switched in contact between the first movable contact, the second movable contact and the third movable contact;
  • the static contact is connected to the Vendor_ID foot
  • the first movable contact is connected to the hardware IO end
  • the second movable contact is connected to the disconnecting end
  • the third movable contact is connected to the ground.
  • the GPIO module when the switch piece is in contact with the first movable contact, the GPIO module is in a first state, wherein the pull-up input module is at a high level, and the pull-down input module is at a high level ;
  • the GPIO module When the switch piece is in contact with the second movable contact, the GPIO module is in a second state, wherein the pull-up input module is at a low level, and the pull-down input module is at a low level;
  • the GPIO module When the switch piece is in contact with the third movable contact, the GPIO module is in a third state, wherein the pull-up input module is at a high level, and the pull-down input module is at a low level.
  • the Vendor_ID pin outputs the number 1;
  • the Vendor_ID pin When the GPIO module is in the second state, the Vendor_ID pin outputs the number 0;
  • the Vendor_ID pin When the GPIO module is in the third state, the Vendor_ID pin outputs the number 2.
  • the hardware module is an LCD display module.
  • the GPIO module is a BBIC chip.
  • FIG. 1 is a schematic structural diagram of a detection system for a hardware module in accordance with a preferred embodiment of the present invention
  • FIG. 2 is a schematic diagram showing the circuit structure of a pull-up input module and a pull-down input module in accordance with a preferred embodiment of the present invention.
  • first, second, third, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as second information without departing from the scope of the present disclosure.
  • second information may also be referred to as first information.
  • word "if” as used herein may be interpreted as "when” or "when” or "in response to determination.”
  • module means, “component” or “unit” used to represent components are only used. For the explanation of the present invention, it does not have a specific meaning per se. Therefore, “module” and “component” can be used in combination.
  • FIG. 1 is a schematic structural diagram of a detection system for a hardware module according to a preferred embodiment of the present invention.
  • the hardware module is detected, and a GPIO module is connected thereto, and the GPIO module is changed to increase the height of the pair.
  • the pull-up input module and the pull-down input module are respectively disposed in the GPIO module and are connected in parallel with the GPIO port, thereby realizing control of the pull-up enable and pull-down enable of the GPIO port, thereby controlling the GPIO module to be pulled up and enabled.
  • the difference between the hardware modules can be identified through a combination of various high-low state states.
  • the input and output interfaces connected to the GPIO port and the detection interface component disposed in the hardware module extend from the hardware module and extend toward the GPIO module until connected to The GPIO port, the input/output interface receives the detection signal sent from the GPIO port for the hardware module detection, and then forwards it to the detection interface component.
  • the detection interface component includes: a hardware IO end, which is connected with a chip in the hardware module to obtain a signal and a wiring relationship of the chip in the hardware module; the disconnection end is suspended at one end and is in an open state, and is disposed in the hardware module.
  • the hardware IO terminal, the disconnecting terminal and the grounding terminal are respectively connected with the input/output interface.
  • the hardware IO terminal, the disconnecting terminal and the grounding terminal respectively feed back the high voltage.
  • the circuit component in the pull-up input module comprises: a first end connected to the GPIO port; a positive power supply VDD; a pull-up resistor and a first switch connected to the pull-up resistor, and The pull-up resistor is connected to the first switch and the power supply positive VDD, and the resistor component in the pull-down input module comprises: a second end connected to the GPIO port and simultaneously connected to the first end; the power supply negative VSS; A pull-down resistor and a second switch connected to the pull-down resistor, and the pull-down resistor and the second switch are connected between the second end and the power supply negative VSS.
  • the pull-up resistor and the pull-down resistor For the configuration and function of the pull-up resistor and the pull-down resistor, it includes:
  • Pull-up is to clamp the indeterminate signal through a resistor at a high level, and the resistor acts as a current-limiter at the same time.
  • the pull-up is to inject current into the device and the pull-down is the output current.
  • Weak strength is only the resistance of the pull-up resistor is different, no What is strictly distinguished.
  • the function of pull-up resistors is mainly to output current channels for open-collector output circuits.
  • the pull resistor when the single button is used for triggering, if the IC itself does not have an internal resistor, in order to maintain the single button in the untriggered state or return to the original state after the trigger, it must be connected to the outside of the IC. resistance.
  • Digital circuits have three states: high, low, and high-impedance. Some applications do not want high-impedance. They can be stabilized by pull-up or pull-down resistors, depending on design requirements. .
  • I/O ports some can be set, some can not be set, some are built-in, some need to be external, the output of I/O port is similar to C of a triode, when C is connected through a resistor and power supply
  • the resistor becomes the upper C-pull resistor, that is, if the port is high when it is normal, and C is connected to the ground through a resistor, the resistor is called a pull-down resistor, so that the port is normally Low level, for example, when a port with a pull-up resistor is set to the input state, the normal state is high, which is used to detect the input of the low level.
  • Pull-up resistors are used to provide current when the bus drive capability is insufficient. The general term is to draw current, and the pull-down resistor is used to sink current.
  • the pull-down resistor is resistance matching, which effectively suppresses reflected wave interference.
  • Resistor series is a good way to achieve impedance matching.
  • the magnitude of the line resistance is in the order of tens of ohms. If the pull-down is added, the power consumption is too large.
  • the TTL circuit drives the COMS circuit, if the high level of the TTL circuit output is lower than the lowest level of the COMS circuit (typically 3.5V), then the pull-up resistor needs to be connected to the output of the TTL to increase the output. The value of the level. For high speed circuits, excessive pull-up resistors may flatten the edges. The drive requirements of the lower level circuit. Similarly, for the above pull-up resistor, when the output is high, the switch is turned off, and the pull-up resistor should be properly selected to provide sufficient current to the lower stage circuit.
  • the output stage of the CMOS circuit is basically push-pull.
  • the ground level is output, the lower MOSFET turns off and the upper side turns on. The high level is reversed.
  • the TTL circuit drives the COMS circuit, if the high level of the TTL circuit output is lower than the lowest level of the COMS circuit (generally 3.5V), then the pull-up resistor needs to be connected at the output end of the TTL to improve Output a high value.
  • the OC gate circuit must be equipped with a pull-up resistor before it can be used.
  • the pull-up resistor is connected to reduce the input impedance and provide a discharge path.
  • the pin of the chip is added with a pull-up resistor to increase the output level, thereby improving the noise margin of the input signal of the chip and enhancing the anti-interference ability.
  • the resistance mismatch in long-line transmission is easy to cause reflected wave interference
  • the pull-down resistor is resistance matching, which effectively suppresses reflected wave interference.
  • the selection criteria for the value of the pull-up resistor include:
  • the selection of the pull-up resistor and the pull-down resistor should be set in combination with the characteristics of the switching transistor and the input characteristics of the lower-level circuit. The following factors should be considered:
  • the above pull-up resistor, the capacitance between the pull-up resistor and the drain-source of the switch and the input capacitance between the lower-level circuits form an RC delay.
  • the pull-up resistor should be set to account for the needs of the circuit in this regard.
  • the principle of setting the pull-down resistor is the same as the pull-up resistor.
  • the pull-up current is provided by a pull-up resistor.
  • the input terminal is not more than 100uA per port, and the output current of the output port is about 500uA.
  • the standard operating voltage is 5V.
  • the high and low thresholds are 0.8V (below this value is low); 2V (high threshold).
  • 200uA x15K 3V, that is, the pull-up resistor has a voltage drop of 3V, and the output port can reach 2V.
  • This resistance is the maximum resistance value, and it will not be able to pull 2V. Choose 10K available.
  • the leakage current of the tube can not be neglected during design.
  • the actual current of the IO port is different at different levels. The above is only the principle. In one sentence, it is summarized as follows: when the output is high, the input port should be fed, and the output should not be low. The output port feeds, otherwise the excess current is fed to the cascaded input port, which is unreliable above the low level threshold.
  • Input pins that are not used in digital circuits must be connected to a fixed level and connected to a high level or ground through a 1k resistor.
  • the function of the pull-up resistor includes: the resistor is to prevent the input terminal from floating, to reduce the interference of the external current on the chip, to protect the protection diode in the CMOS, the current is not more than 10mA, pull-up and pull-down, current limit, change level The potential, the determined state when the pin is floating, the drive capability when the high level output is increased, and the OC gate provides the current.
  • the hardware IO end is the Vendor_ID pin of the hardware module.
  • the Vendor_ID pin is the manufacturer code manufacturer ID identifier, and the supplier can extract the identification pin from its own hardware module for detection by the GPIO module.
  • the detection interface component further comprises: a single-pole three-throw switch, disposed in the hardware module, comprising a switch piece, a static contact and the first movable contact, the second movable contact, the third movable contact; one end of the switch piece The static contact is pivotally connected, and the other end is switched between the first movable contact, the second movable contact and the third movable contact; and for the configuration of each contact, the static contact is connected with the Vendor_ID leg; The first moving contact is connected to the hardware IO end; the second moving contact is connected to the breaking end; and the third moving contact is connected to the ground end.
  • a single-pole three-throw switch disposed in the hardware module, comprising a switch piece, a static contact and the first movable contact, the second movable contact, the third movable contact; one end of the switch piece The static contact is pivotally connected, and the other end is switched between the first movable contact, the second movable contact and the third movable contact; and for
  • the switch piece rotates on the contact of the static contact with the static contact as the axis, and the other end is in the first movable contact, the second movable contact, and the third movable contact, and the first movement After the contact, the second movable contact and the third movable contact are in contact, the internal chip of the hardware module can be connected.
  • the GPIO module When the switch piece is in contact with the first movable contact, the GPIO module is in the first state, wherein the pull-up input module is at a low level, and the pull-down input module is at a low level;
  • the GPIO module When the switch piece is in contact with the second movable contact, the GPIO module is in the second state, wherein the pull-up input module is at a high level, and the pull-down input module is at a high level;
  • the GPIO module When the switch piece is in contact with the third moving contact, the GPIO module is in the third state, wherein the pull-up input module is at a high level, and the pull-down input module is at a low level.
  • the Vendor_ID pin when the GPIO module is in the first state, the Vendor_ID pin outputs the number 1; when the GPIO module is in the second state, the Vendor_ID pin outputs the number 0; when the GPIO module is in the third state, the Vendor_ID pin outputs the number 2. Differentiate the devices provided by different vendors by different output numbers.
  • the hardware module is an LCD display module
  • the GPIO module is a BBIC chip.
  • the mobile terminal can be implemented in various forms.
  • the terminal described in the present invention may include a mobile terminal such as a mobile phone, a smart phone, a notebook computer, a PDA (Personal Digital Assistant), a PAD (Tablet), a PMP (Portable Multimedia Player), a navigation device, and the like, and such as Fixed terminal for digital TV, desktop computer, etc.
  • a mobile terminal such as a mobile phone, a smart phone, a notebook computer, a PDA (Personal Digital Assistant), a PAD (Tablet), a PMP (Portable Multimedia Player), a navigation device, and the like
  • the terminal is a mobile terminal.
  • those skilled in the art will appreciate that configurations in accordance with embodiments of the present invention can be applied to fixed type terminals in addition to components that are specifically for mobile purposes.

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Abstract

一种用于硬件模组的检测***，检测***包括：GPIO模块及硬件模组，GPIO模块包括：上拉输入模块、下拉输入模块及GPIO口，上拉输入模块、下拉输入模块与GPIO口并接，控制GPIO口上拉使能或下拉使能；硬件模组包括与GPIO口连接的输入输出接口及设于硬件模组内的检测接口组件，检测接口组件包括：硬件IO端，与硬件模组内的芯片连接；断路端，悬空于硬件模组内；接地端，与地连接；硬件IO端、断路端、接地端分别与输入输出接口连接，反馈高电平或低电平至上拉输入模块或下拉输入模块，以检测硬件模组的配置。采用上述技术方案后，对于多个不同供应商的产品，可实现快速检测和区分。

Description

一种用于硬件模组的检测*** 技术领域
本发明涉及电子设备检测领域，尤其涉及一种用于硬件模组的检测***。
背景技术
目前，智能终端的发展越来越快，在人民群众中的普及率也越发提高。在对智能终端制造时，如显示屏、电池等配件为了供货的安全一般都有两到三家供应商。由于各家物料存在参数上的差异，所以软件上需要兼容各家的物料。通常为在软件上实现兼容，通常的方案就是给每一家供应商的物料一个标识ID号，通过标识ID号来区分对应的软件。而在硬件层面上，实现标识ID号的方案基本上有两种：其一为常规的ADC检测，其二为通用的GPIO检测。由于GPIO只能检测两种电平，即高电平和低电平，导致使用上有一定的局限性。一旦供货厂商增加，将无法区别供货厂商。
因此，需要一种新型的对于硬件模组标识的检测***及检测方法，可满足对多个硬件供应商不同供货产品的区分。
发明内容
为了克服上述技术缺陷，本发明的目的在于提供一种用于硬件模组的检测***，对于不同供应商的产品，可实现快速检测和区分。
本发明公开了一种用于硬件模组的检测***，所述检测***包括：互相连接的GPIO模块及硬件模组，所述GPIO模块包括：上拉输入模块、下拉输入模块及GPIO口，其中，
所述上拉输入模块、下拉输入模块与所述GPIO口并接，控制所述GPIO口上拉使能或下拉使能；
所述硬件模组包括与所述GPIO口连接的输入输出接口及设于所述硬件模组内的检测接口组件，所述检测接口组件包括：
硬件IO端，与所述硬件模组内的芯片连接；
断路端，悬空于所述硬件模组内；
接地端，与地连接；
所述硬件IO端、断路端、接地端分别与所述输入输出接口连接，反馈高电平或低电平至所述上拉输入模块或下拉输入模块，以检测所述硬件模组的配置。
优选地，所述上拉输入模块包括：
第一端，与所述GPIO口连接；
电源正极VDD；
上拉电阻及与所述上拉电阻连接的第一开关，且所述上拉电阻与第一开关连接于所述第一端及电源正极VDD间；
所述下拉输入模块包括：
第二端，与所述GPIO口连接，且同时与所述第一端连接；
电源负极VSS；
下拉电阻及与所述下拉电阻连接的第二开关，且所述下拉电阻与第二开关连接于所述第二端及电源负极VSS间。
优选地，所述硬件IO端为所述硬件模组的Vendor_ID脚。
优选地，所述检测接口组件还包括：
单刀三掷开关，设于所述硬件模组内，包括开关片、静触点及第一动触点、第二动触点、第三动触点；
所述开关片的一端与所述静触点枢轴连接，另一端于所述第一动触点、第二动触点、第三动触点间切换接触导通；
所述静触点与所述Vendor_ID脚连接；
所述第一动触点与所述硬件IO端连接；
所述第二动触点与所述断路端连接；
所述第三动触点与所述接地端连接。
优选地，所述开关片与所述第一动触点接触导通时，所述GPIO模块处于第一状态，其中所述上拉输入模块呈高电平，所述下拉输入模块呈高电平；
所述开关片与所述第二动触点接触导通时，所述GPIO模块处于第二状态，其中所述上拉输入模块呈低电平，所述下拉输入模块呈低电平；
所述开关片与所述第三动触点接触导通时，所述GPIO模块处于第三状态，其中所述上拉输入模块呈高电平，所述下拉输入模块呈低电平。
优选地，所述GPIO模块处于第一状态时，所述Vendor_ID脚输出编号1；
所述GPIO模块处于第二状态时，所述Vendor_ID脚输出编号0；
所述GPIO模块处于第三状态时，所述Vendor_ID脚输出编号2。
优选地，所述硬件模组为LCD显示模组。
优选地，所述GPIO模块为BBIC芯片。
采用了上述技术方案后，与现有技术相比，具有以下有益效果：
1.不同厂商在制造硬件时，无额外新增的配置，节省供货商处的流程；
2.为GPIO口新增多种硬件标识的检测，适用程度更广。
附图说明
图1为符合本发明一优选实施例中用于硬件模组的检测***的结构示意图；
图2为符合本发明一优选实施例中上拉输入模块及下拉输入模块的电路结构示意图。
具体实施方式
以下结合附图与具体实施例进一步阐述本发明的优点。
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
在本公开使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本公开。在本公开和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本公开可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本公开范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
在本发明的描述中，需要理解的是，术语“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，除非另有规定和限定，需要说明的是，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是机械连接或电连接，也可以是两个元件内部的连通，可以是直接相连，也可以通过中间媒介间接相连，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。
在后续的描述中，使用用于表示元件的诸如“模块”、“部件”或“单元”的后缀仅为了有 利于本发明的说明，其本身并没有特定的意义。因此，“模块”与“部件”可以混合地使用。
参阅图1，为符合本发明一优选实施例中用于硬件模组的检测***的结构示意图，为对硬件模组进行检测，与其连接有一GPIO模块，在改GPIO模块内，为增加其对高低电平的检测稳定性，以及在原有高低电平的基础上再增加一例如高阻状态的检测方案，在该GPIO模块内，包括了有上拉输入模块、下拉输入模块及GPIO口。上拉输入模块、下拉输入模块分别设置在GPIO模块内，并与GPIO口并接，从而可实现对GPIO口上拉使能和下拉使能的控制，进而将GPIO模块控制为上拉使能和下拉使能下的高电平状态、低电平状态，则通过多种高低电平状态的组合，便可识别出硬件模组的区别。而在硬件模组侧，其包括了与GPIO口连接的输入输出接口及设于硬件模组内的检测接口组件，该输入输出接口从硬件模组处延伸而出，向着GPIO模块延伸直至连接至GPIO口，该输入输出接口将接收从GPIO口发出的对于硬件模组检测的检测信号，后转发至检测接口组件。因此，检测接口组件包括了：硬件IO端，与硬件模组内的芯片连接，获取该硬件模组内芯片的信号及接线关系；断路端，一端悬空，呈断路状态，设置于硬件模组内；接地端，与地连接。上述硬件IO端、断路端、接地端分别与输入输出接口连接，当GPIO模块通过上拉输入模块和下拉输入模块上拉下拉使能时，硬件IO端、断路端、接地端将各自反馈高电平或低电平至上拉输入模块和下拉输入模块。可以理解的是，由于GPIO处于上拉或下拉的状态不同，可分别接收到：
①上拉为高、下拉为高；
②上拉为低、下拉为低；
③上拉为高、下拉为低；
④上拉为低、下拉为高；
这四种反馈信息，从而可获知当前硬件组件的标识为何，进而区别不同产品供货商给出的产品。
参阅图2，在一优选实施例中，上拉输入模块内的电路组成包括了：第一端，与GPIO口连接；电源正极VDD；上拉电阻及与上拉电阻连接的第一开关，且上拉电阻与第一开关连接于第一端及电源正极VDD间，而下拉输入模块内的电阻组成包括了：第二端，与GPIO口连接，且同时与第一端连接；电源负极VSS；下拉电阻及与下拉电阻连接的第二开关，且下拉电阻与第二开关连接于第二端及电源负极VSS间。
对于上拉电阻及下拉电阻的配置及作用，包括了：
上拉就是将不确定的信号通过一个电阻嵌位在高电平，电阻同时起限流作用，下拉同理。上拉是对器件注入电流，下拉是输出电流。弱强只是上拉电阻的阻值不同，没有 什么严格区分。对于非集电极(或漏极)开路输出型电路(如普通门电路)提升电流和电压的能力是有限的，上拉电阻的功能主要是为集电极开路输出型电路输出电流通道。
至于为什么要使用拉电阻，一般作单键触发使用时，如果IC本身没有内接电阻，为了使单键维持在不被触发的状态或是触发后回到原状态，必须在IC外部另接一电阻。数字电路有三种状态：高电平、低电平、和高阻状态，有些应用场合不希望出现高阻状态，可以通过上拉电阻或下拉电阻的方式使处于稳定状态，具体视设计要求而定。一般说的是I/O端口，有的可以设置，有的不可以设置，有的是内置，有的是需要外接，I/O端口的输出类似与一个三极管的C，当C接通过一个电阻和电源连接在一起的时候，该电阻成为上C拉电阻，也就是说，如果该端口正常时为高电平，C通过一个电阻和地连接在一起的时候，该电阻称为下拉电阻，使该端口平时为低电平，比如：当一个接有上拉电阻的端口设为输如状态时，常态就为高电平，用于检测低电平的输入。上拉电阻是用来解决总线驱动能力不足时提供电流的。一般说法是拉电流，下拉电阻是用来吸收电流的。
此外，长线传输中电阻不匹配容易引起反射波干扰，加上下拉电阻是电阻匹配，有效的抑制反射波干扰。电阻串联才是实现阻抗匹配的好方法。通常线阻的数量级都在几十ohm，如果加上下拉的话，功耗太大。当TTL电路驱动COMS电路时，如果TTL电路输出的高电平低于COMS电路的最低高电平(一般为3.5V)，这时就需要在TTL的输出端接上拉电阻，以提高输出高电平的值。对于高速电路，过大的上拉电阻可能边沿变平缓。下级电路的驱动需求。同样以上拉电阻为例，当输出高电平时，开关管断开，上拉电阻应适当选择以能够向下级电路提供足够的电流。
当输出高电平时，CMOS电路的输出级基本上是推拉时。输出地电平时，下面的MOSFET关断，上面的导通。高电平时反过来。
使用上拉电阻及下拉电阻时，需注意：
1、当TTL电路驱动COMS电路时，如果TTL电路输出的高电平低于COMS电路的最低高电平(一般为3.5V)，这时就需要在TTL的输出端接上拉电阻，以提高输出高电平的值。
2、OC门电路必须加上拉电阻，才能使用。
3、为加大输出引脚的驱动能力，有的单片机管脚上也常使用上拉电阻。
4、在COMS芯片上，为了防止静电造成损坏，不用的管脚不能悬空，一般接上拉电阻产生降低输入阻抗，提供泄荷通路。
5、芯片的管脚加上拉电阻来提高输出电平，从而提高芯片输入信号的噪声容限增强抗干扰能力。
6、提高总线的抗电磁干扰能力。管脚悬空就比较容易接受外界的电磁干扰。
7、长线传输中电阻不匹配容易引起反射波干扰，加上下拉电阻是电阻匹配，有效的抑制反射波干扰。
上拉电阻阻值的选择原则包括：
1、从节约功耗及芯片的灌电流能力考虑应当足够大；电阻大，电流小。
2、从确保足够的驱动电流考虑应当足够小；电阻小，电流大。
3、对于高速电路，过大的上拉电阻可能边沿变平缓。综合考虑
以上三点，通常在1k到10k之间选取。对下拉电阻也有类似道理
对上拉电阻和下拉电阻的选择应结合开关管特性和下级电路的输入特性进行设定，主要需要考虑以下几个因素：
1.驱动能力与功耗的平衡。以上拉电阻为例，一般地说，上拉电阻越小，驱动能力越强，但功耗越大，设计是应注意两者之间的均衡。
2.下级电路的驱动需求。同样以上拉电阻为例，当输出高电平时，开关管断开，上拉电阻应适当选择以能够向下级电路提供足够的电流。
3.高低电平的设定。不同电路的高低电平的门槛电平会有不同，电阻应适当设定以确保能输出正确的电平。以上拉电阻为例，当输出低电平时，开关管导通，上拉电阻和开关管导通电阻分压值应确保在零电平门槛之下。
4.频率特性。以上拉电阻为例，上拉电阻和开关管漏源级之间的电容和下级电路之间的输入电容会形成RC延迟，电阻越大，延迟越大。上拉电阻的设定应考虑电路在这方面的需求。
下拉电阻的设定的原则和上拉电阻是一样的。
OC门输出高电平时是一个高阻态，其上拉电流要由上拉电阻来提供，设输入端每端口不大于100uA，设输出口驱动电流约500uA，标准工作电压是5V，输入口的高低电平门限为0.8V(低于此值为低电平)；2V(高电平门限值)。
选上拉电阻时：
500uA x 8.4K＝4.2即选大于8.4K时输出端能下拉至0.8V以下，此为最小阻值，再小就拉不下来了。如果输出口驱动电流较大，则阻值可减小，保证下拉时能低于0.8V即可。
当输出高电平时，忽略管子的漏电流，两输入口需200uA。
200uA x15K＝3V即上拉电阻压降为3V，输出口可达到2V，此阻值为最大阻值，再大就拉不到2V了。选10K可用。
设计时管子的漏电流不可忽略，IO口实际电流在不同电平下也是不同的，上述仅仅是原理，一句话概括为：输出高电平时要喂饱后面的输入口，输出低电平不要把输出口喂撑，否则多余的电流喂给级联的输入口，高于低电平门限值就不可靠。
在数字电路中不用的输入脚都要接固定电平，通过1k电阻接高电平或接地。
上拉电阻的作用包括了：接电阻就是为了防止输入端悬空、减弱外部电流对芯片产生的干扰、保护cmos内的保护二极管，一般电流不大于10mA、上拉和下拉、限流、改变电平的电位、在引脚悬空时有确定的状态、增加高电平输出时的驱动能力、OC门提供电流。
继续参阅图1，在该实施例中，硬件IO端为硬件模组的Vendor_ID脚。该Vendor_ID脚为运营商代码厂商ID制造商标识，供货商可从自身的硬件模组引出该标识脚，供GPIO模块检测。同时，检测接口组件还包括：单刀三掷开关，设于硬件模组内，包括开关片、静触点及第一动触点、第二动触点、第三动触点；开关片的一端与静触点枢轴连接，另一端于第一动触点、第二动触点、第三动触点间切换接触导通；而对于各触点的配置，静触点与Vendor_ID脚连接；第一动触点与硬件IO端连接；第二动触点与断路端连接；第三动触点与所述接地端连接。该开关片在静触点的接触处，以静触点为轴旋转，另一端则在第一动触点、第二动触点、第三动触点择一的接触，一旦与第一动触点、第二动触点、第三动触点接触后，便可与硬件模组的内部芯片连接。
使用时，由于动触点分为三个，因此，开关片的不同位置也会将GPIO模块分处于三个状态，分别为：
①开关片与第一动触点接触导通时，GPIO模块处于第一状态，其中上拉输入模块呈低电平，下拉输入模块呈低电平；
②开关片与第二动触点接触导通时，GPIO模块处于第二状态，其中上拉输入模块呈高电平，下拉输入模块呈高电平；
③开关片与第三动触点接触导通时，GPIO模块处于第三状态，其中上拉输入模块呈高电平，下拉输入模块呈低电平。
在上述三种状态中，Vendor_ID脚的真值如下表所示：
Figure PCTCN2017105756-appb-000001
Figure PCTCN2017105756-appb-000002
也就是说：GPIO模块处于第一状态时，Vendor_ID脚输出编号1；GPIO模块处于第二状态时，Vendor_ID脚输出编号0；GPIO模块处于第三状态时，Vendor_ID脚输出编号2。通过不同的输出编号，实现对不同供应商提供的器件的区分。
上述任意实施例中，硬件模组为LCD显示模组，而GPIO模块为BBIC芯片。
移动终端可以以各种形式来实施。例如，本发明中描述的终端可以包括诸如移动电话、智能电话、笔记本电脑、PDA(个人数字助理)、PAD(平板电脑)、PMP(便携式多媒体播放器)、导航装置等等的移动终端以及诸如数字TV、台式计算机等等的固定终端。下面，假设终端是移动终端。然而，本领域技术人员将理解的是，除了特别用于移动目的的元件之外，根据本发明的实施方式的构造也能够应用于固定类型的终端。
应当注意的是，本发明的实施例有较佳的实施性，且并非对本发明作任何形式的限制，任何熟悉该领域的技术人员可能利用上述揭示的技术内容变更或修饰为等同的有效实施例，但凡未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何修改或等同变化及修饰，均仍属于本发明技术方案的范围内。

Claims (8)

  1. 一种用于硬件模组的检测***，所述检测***包括：互相连接的GPIO模块及硬件模组，其特征在于，
    所述GPIO模块包括：上拉输入模块、下拉输入模块及GPIO口，其中，
    所述上拉输入模块、下拉输入模块与所述GPIO口并接，控制所述GPIO口上拉使能或下拉使能；
    所述硬件模组包括与所述GPIO口连接的输入输出接口及设于所述硬件模组内的检测接口组件，所述检测接口组件包括：
    硬件IO端，与所述硬件模组内的芯片连接；
    断路端，悬空于所述硬件模组内；
    接地端，与地连接；
    所述硬件IO端、断路端、接地端分别与所述输入输出接口连接，反馈高电平或低电平至所述上拉输入模块或下拉输入模块，以检测所述硬件模组的配置。
  2. 如权利要求1所述的检测***，其特征在于，
    所述上拉输入模块包括：
    第一端，与所述GPIO口连接；
    电源正极VDD；
    上拉电阻及与所述上拉电阻连接的第一开关，且所述上拉电阻与第一开关连接于所述第一端及电源正极VDD间；
    所述下拉输入模块包括：
    第二端，与所述GPIO口连接，且同时与所述第一端连接；
    电源负极VSS；
    下拉电阻及与所述下拉电阻连接的第二开关，且所述下拉电阻与第二开关连接于所述第二端及电源负极VSS间。
  3. 如权利要求1所述的检测***，其特征在于，
    所述硬件IO端为所述硬件模组的Vendor_ID脚。
  4. 如权利要求3所述的检测***，其特征在于，
    所述检测接口组件还包括：
    单刀三掷开关，设于所述硬件模组内，包括开关片、静触点及第一动触点、第二动触点、 第三动触点；
    所述开关片的一端与所述静触点枢轴连接，另一端于所述第一动触点、第二动触点、第三动触点间切换接触导通；
    所述静触点与所述Vendor_ID脚连接；
    所述第一动触点与所述硬件IO端连接；
    所述第二动触点与所述断路端连接；
    所述第三动触点与所述接地端连接。
  5. 如权利要求4所述的检测***，其特征在于，
    所述开关片与所述第一动触点接触导通时，所述GPIO模块处于第一状态，其中所述上拉输入模块呈高电平，所述下拉输入模块呈高电平；
    所述开关片与所述第二动触点接触导通时，所述GPIO模块处于第二状态，其中所述上拉输入模块呈低电平，所述下拉输入模块呈低电平；
    所述开关片与所述第三动触点接触导通时，所述GPIO模块处于第三状态，其中所述上拉输入模块呈高电平，所述下拉输入模块呈低电平。
  6. 如权利要求5所述的检测***，其特征在于，
    所述GPIO模块处于第一状态时，所述Vendor_ID脚输出编号1；
    所述GPIO模块处于第二状态时，所述Vendor_ID脚输出编号0；
    所述GPIO模块处于第三状态时，所述Vendor_ID脚输出编号2。
  7. 如权利要求1所述的检测***，其特征在于，
    所述硬件模组为LCD显示模组。
  8. 如权利要求1所述的检测***，其特征在于，
    所述GPIO模块为BBIC芯片。
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