WO2019066900A1

WO2019066900A1 - An apparatus with a substrate provided by electroless metal plating using polyelectrolytes to adsorb metal ions into the substrate

Info

Publication number: WO2019066900A1
Application number: PCT/US2017/054299
Authority: WO
Inventors: Ali LEHAF
Original assignee: Intel Corporation
Priority date: 2017-09-29
Filing date: 2017-09-29
Publication date: 2019-04-04

Abstract

Embodiments of the present disclosure provide a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a treatment of the surface with a polyelectrolyte solution having an electrical charge to provide adsorption of metal ions to the surface. Subsequently, the adsorbed metal ions may enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.

Description

AN APPARATUS WITH A SUBSTRATE PROVIDED BY ELECTROLESS METAL PLATING USING POLYELECTROLYTES TO ADSORB METAL IONS

INTO THE SUBSTRATE Field

Embodiments of the present disclosure generally relate to the field of

semiconductor package and printed circuit board (PCB) fabrication and in particular to techniques for improving surfaces of substrates used in semiconductor packages or PCB.

Background

Electroless deposition is routinely employed in the electronic industry to form a seed layer in substrates for subsequent electroless plating of copper or other metals. The resulting metal plating may be used to form metallic interconnects on buildup films/composite polymeric materials of the substrates. Buildup films in semiconductor packaging typically include epoxy resins, surface finish films, molding compounds, photo imageable dielectrics, and other types of organic films.

Electroless deposition typically uses a Desmear process to roughen a dielectric onto which copper plating is to be applied. Once applied, ions may be applied to the roughened surface and may sit in the pores created by the roughening for later reducing to be used as a seed layer.

Brief Description of the Drawings

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

FIG. 1 illustrates a cross-section side view of an example integrated circuit (IC) assembly comprising a semiconductor device, in accordance with some embodiments.

FIG. 2 illustrates an example cross-sectional view of a substrate of a

semiconductor device at different process stages, in accordance with some embodiments.

FIG. 3 is an example process flow diagram for provision of a substrate of a semiconductor device, in accordance with some embodiments.

FIG. 4 shows example poly electrolytes and seed metals, in accordance with some embodiments.

FIG. 5 illustrates an example computing device that may employ the apparatuses and/or methods described herein, according to various embodiments. Detailed Description

Embodiments of the present disclosure include techniques and configurations for providing an apparatus with a substrate tuned with charged polyelectrolyte to facilitate metal seeding for subsequent electroless plating. In some embodiments, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a treatment of the surface with a polyelectrolyte solution having an electrical charge to provide adsorption of metal ions to the surface, and subsequent electroless plating of the surface with a metal. The adsorbed metal ions are to enhance electroless plating of the surface with the metal.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, wherein like numerals designate like parts throughout, and in which are shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.

For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), (A) or (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

The description may use perspective-based descriptions such as top/bottom, in/out, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.

The description may use the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous.

The term "coupled with," along with its derivatives, may be used herein.

"Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical, electrical, or optical contact. However, "coupled" may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term "directly coupled" may mean that two or more elements are in direct contact.

FIG. 1 illustrates a cross-section side view of an example integrated circuit (IC) assembly comprising a semiconductor device, in accordance with some embodiments. In some embodiments, the IC assembly 100 may comprise a semiconductor package device, for example, an integrated circuit (IC), such as a central processing unit (CPU) or a memory unit, and may further comprise a portion of a computing device, such as a graphics device, wireless device, multi-chip package including a combination with other devices, or the like.

In some embodiments, the IC assembly 100 may include one or more dies

(hereinafter "die 102") electrically and/or physically coupled with a package assembly 121 (sometimes referred to as a "package substrate"). In some embodiments, the package assembly 121 may be electrically coupled with a circuit board 122.

The die 102 may represent a discrete product made from a semiconductor material (e.g., silicon) using semiconductor fabrication techniques such as thin film deposition, lithography, etching, and the like used in connection with forming complementary metal- oxide-semiconductor (CMOS) devices. In some embodiments, the die 102 may be, include, or be a part of a radio frequency (RF) die. In other embodiments, the die may be, include, or be a part of a processor, memory, system-on-chip (SoC), SiP, or ASIC.

In some embodiments, an underfill material 108 (sometimes referred to as an

"encapsulant") may be disposed between the die 102 and the package assembly 121 to promote adhesion and/or protect features of the die 102 and the package assembly 121. The underfill material 108 may be composed of an electrically insulative material and may encapsulate at least a portion of the die 102 and/or the die-level interconnect structures 106. In some embodiments, the underfill material 108 may be in direct contact with the die-level interconnect structures 106.

The die 102 can be attached to the package assembly 121 according to a wide variety of suitable configurations including, for example, being directly coupled with the package assembly 121 in a flip-chip configuration, as depicted. In the flip-chip configuration, an active side, SI, of the die 102 including active circuitry is attached to a surface of the package assembly 121 using die-level interconnect structures 106 such as bumps, pillars, or other suitable structures that may also electrically couple the die 102 with the package assembly 121. The active side SI of the die 102 may include transistor devices, and an inactive side, S2, may be disposed opposite to the active side SI . The die 102 may generally include a semiconductor substrate 102a, one or more device layers (hereinafter "device layer 102b"), and one or more interconnect layers (hereinafter "interconnect layer 102c"). The semiconductor substrate 102a may be substantially composed of a bulk semiconductor material such as, for example, silicon, in some embodiments.

The device layer 102b may represent a region where active devices such as transistor devices are formed on the semiconductor substrate 102a. The device layer 102b may include, for example, structures such as channel bodies and/or source/drain regions of transistor devices. The interconnect layer 102c may include interconnect structures that are configured to route electrical signals to or from the active devices in the device layer 102b. For example, the interconnect layer 102c may include trenches and/or vias to provide electrical routing and/or contacts.

In some embodiments, the die-level interconnect structures 106 may be configured to route electrical signals between the die 102 and other electrical devices. The electrical signals may include, for example, input/output (I/O) signals and/or power/ground signals that are used in connection with operation of the die 102.

In some embodiments, the package assembly 121 may include a multi-layer package assembly with integrated components for wireless communication. The wireless communication may include, for example, short range wireless data transfer between portable devices and/or wireless displays or high speed wireless communication between peer devices.

The package assembly 121 may include electrical routing features (not shown in FIG. 1) such as, for example, traces, pads, through-holes, vias, or lines configured to route electrical signals to or from the die 102. For example, the package assembly 121 may be configured to route electrical signals between the die 102 and components for wireless communication that are integrated within the package assembly, or between the die 102 and the circuit board 122, or between the die 102 and another electrical component (e.g., another die, interposer, interface, component for wireless communication, etc.) coupled with the package assembly 121. For example, in some embodiments, the semiconductor substrate 102a (or the substrate comprising the package assembly 121) may include a surface 1 10 provided with poly electrolyte and metal ions used to form a metal layer for signal routing for the IC assembly 100 according to various embodiments described herein. The circuit board 122 may be a printed circuit board (PCB) composed of an electrically insulative material such as an epoxy laminate. For example, the circuit board 122 may include electrically insulating layers composed of materials, such as

polytetrafluoroethylene, phenolic cotton paper materials such as Flame Retardant 4 (FR- 4), FR-1, cotton paper, and epoxy materials such as CEM-1 or CEM-3, or woven glass materials that are laminated together using an epoxy resin prepreg material. Interconnect structures (not shown) such as traces, trenches or vias may be formed through the electrically insulating layers to route the electrical signals of the die 102 through the circuit board 122. The circuit board 122 may be composed of other suitable materials in other embodiments. In some embodiments, the circuit board 122 may be a motherboard or other PCB in a computing device (e.g., described in reference to FIG. 5).

Package-level interconnects, such as solder balls 112, may be coupled with the package assembly 121 and/or the circuit board 122 to form corresponding solder joints that are configured to further route the electrical signals between the package assembly 121 and the circuit board 122.

In some embodiments, the circuit board 122 may include a substrate 124 with a surface formed with an electroless plating process in accordance with embodiments described herein. Other suitable techniques to physically and/or electrically couple the package assembly 121 with the circuit board 122 may be used in other embodiments.

The IC assembly 100 may include a wide variety of other suitable configurations in other embodiments including, for example, suitable combinations of flip-chip and/or wire- bonding configurations, interposers, multi-chip package configurations including system- in-package (SiP) and/or package-on-package (PoP) configurations. Other suitable techniques to route electrical signals between the die 102 and other components of the IC package assembly 100 may be used in some embodiments.

The embodiments described herein provide for modifying a surface charge of a dielectric material or other polymer film material to facilitate adsorption of metal ions on the surface of the material. The metal ions, may then act as a seed layer for subsequent electroless plating of the surface of the material. An example polymer film material is solder resist. In embodiments, the dielectric material or polymer film may include solder resist, and may be part of a substrate.

Modifying the surface charge may also be referred to as "tuning" a surface charge to facilitate adsorption of metal ions. The process may include dipping and subsequently coating the surface into a positively or negatively charged polyelectrolyte (or polymer) to modify the surface charge. The resulting electrically charged coating may cause metal ions having an opposite charge to be attracted to and adsorbed on the surface of the material.

In one example, Pd ions that are positively charged can be attracted to a negatively charged coated surface by dipping the material in negatively charged polyelectrolyte. This process can help Pd ions to adsorb more uniformly on the surface, independent of surface roughness. These adsorbed Pd ions can be then reduced in reducer bath to form metal seeds on the surface that are required for subsequent electroless plating of the substrate surface.

In another example of this process, an Embedded Multi-die Interconnect Bridge

(EMIB) application may use electroless copper plating on top of solder resist. Dipping a solder resist panel in negative or charged polyelectrolyte may facilitate the adsorption of metal ion seeds necessary for electroless copper plating independent of roughening the surface.

FIG. 2 illustrates an example cross-sectional view of a substrate of a

semiconductor device at different process stages, in accordance with some embodiments. The substrate 230a, which may be similar to substrate 102a or the substrate comprising the package assembly 121, may go through different stages 230b-230d as described further below. In embodiments, the substrate 230a may be a surface of some other object, for example a dielectric, solder resist, or a polymer film, to which electroless plating may be applied.

In embodiments, substrate 230a may have a polyelectrolyte 232 applied to a surface of the substrate 230a. In embodiments, the polyelectrolyte 232 may include a polymer solution and may be positively charged or negatively charged. Examples of a negatively charged polyelectrolyte 232 may include poly(acrylic acid) (PAA) and poly(styrene sulfonate) (PSS). Examples of a positively charged polyelectrolyte 232 may include poly allyl amine hydrochloride (PAH).

The polyelectrolyte 232 may be applied by dipping the substrate 230a into the polyelectrolyte 232. The polyelectrolyte 232 may be applied using other processes, such as spraying, brushing, and the like. As a result, a coating with an electrical charge 23 Obi may adhere to the substrate 230b.

In embodiments, there may be multiple applications of polyelectrolyte 232 onto the substrate 230a. These may include multiple applications of the same polyelectrolyte 232, or may include multiple applications of a different polyelectrolyte that may have a different or opposite electrical charge. For example, coatings of positively charged and negatively charged polyelectrolytes may be interleaved (not shown) on the surface of the substrate 230b. Such interleaving of coatings may provide additional layers to which either positively charged or negatively charged ions may subsequently attach.

The coated substrate 230b may then be exposed to an ion solution 234. The ion solution 234 may also be referred to as a transition ion catalyst or an ion catalyst. The ion solution may include ions that are either positively charged or negatively charged. The ion solution 234 may be applied by dipping the substrate 230b into the solution. The ion solution 234 may be applied using other processes, such as spraying and the like. Ions 240 within the ion solution 234 may have either a positive charge or a negative charge. Ions 240 having a positive charge may be attracted to coatings of the substrate 230b that have a negative charge, and ions 240 having a negative charge may be attracted to coatings of the substrate 230 be that have a positive charge. The difference in charges between the ions and the coated substrate may enhance adsorption of the ions into the substrate surface, and result in an ion coated substrate 230c.

In embodiments, ion solution 234 may include palladium (Pd) ions 240 that have a positive charge. As a result of a coated substrate 230b of a negatively charged

polyelectrolyte 232, Pd ions 240 may be attracted to the coated substrate 230b resulting in the Pd ion coated substrate 230c.

The ion coated substrate 230c may then be exposed to a reducing agent 236. The reducing agent 236 may be applied by dipping the ion coated substrate 230c into the reducing agent 236. The reducing agent 236 may also be applied using other processes. As a result of exposure to the reducing agent 236, ions 240 may be converted to metal atoms 242 that are attached to the substrate 230d. For example, Pd ions, after exposure to a reducing agent, may be converted to Pd metal atoms.

The resulting metal atoms 242 attached to the substrate 230d may be used as a seed metal for subsequent electroless plating process on the surface of the substrate 230d. In embodiments, the electroless plating process may include plating copper metal onto the surface.

FIG. 3 is an example process flow diagram for provision of a substrate of a semiconductor device, in accordance with some embodiments. In embodiments, the semiconductor device may comprise a package, a PCB, or other semiconductor device using a polymer film, dielectric material, solder resist, or appropriate material that includes metal plating using an electroless plating process. The process 300 may comport with embodiments described in reference to FIG. 2. The actions described in the process 300 may occur in a different order or in parallel; the order provided below is for purposes of illustration and does not limit this disclosure.

The process 300 may begin at block 302 and include performing a polyelectrolyte solution (e.g. polyelectrolyte 232) treatment to a surface of a substrate (e.g. substrate 230a) to create a coating (e.g. 230bl) on the surface having an electrical charge. In

embodiments, the electrical charge may be a positive charge or a negative charge depending on the choice of polyelectrolyte 232. In embodiments as described above, the coating 230bl may include multiple coatings of one or more types of polyelectrolyte 232, where different types of polyelectrolyte 232 may have different types of electrical charge.

At block 304, the process may include applying a transition ion catalyst (e.g. ion solution 234) to the coated surface (e.g. 230b) based at least upon the electrical charge of the coating and an electrical charge of ions in the ion catalyst. As described above, the ion catalyst (e.g., Pd) may serve to enhance electroless plating of the surface.

At block 306, the process may include exposing the coated surface to a reducing agent (e.g. reducing agent 236) to cause the ions adsorbed into the surface to turn to metal. As described above, this metal may then form seeds to facilitate the electroless plating process.

At block 308, the process may include applying an electroless plating process to the surface. In embodiments as described above, the electroless plating process may be used to apply a copper plating to the coated surface using the metal seeds described above.

FIG. 4 illustrates an example computing device that may employ the apparatuses and/or methods described herein, according to various embodiments.

The motherboard 402 of the computing device 400 may include a number of components, including but not limited to a processor 404 and at least one communication chip 406. The processor 404 may be physically and electrically coupled to the motherboard 402. In some implementations, the communication chip 406 may also be physically and electrically coupled to the motherboard 402. In further implementations, the communication chip 406 may be part of the processor 404. In addition, the computing device 400 may further include an antenna 416.

Depending on its applications, the computing device 400 may include other components that may or may not be physically and electrically coupled to the motherboard 402. Some of these components are shown in FIG. 4 for purposes of explanation. These other components may include, but are not limited to, volatile memory (e.g., dynamic random-access memory (DRAM)) 408, static random access memory (SRAM) 409, nonvolatile memory (e.g., read-only memory (ROM)) 410, flash memory 411, a graphics central processing unit (CPU) 412, a digital signal processor 413, a chipset 414, a display (e.g., a touchscreen display) 418, a touchscreen controller 420, a battery 422, an audio codec, a video codec, a power amplifier (not shown), a global positioning system (GPS) device 426, a compass 428, a Geiger counter, an accelerometer, a gyroscope (not shown), a speaker 430, a camera 417, and a mass storage device 432. These components may be included in IC packages, some of which may be disposed on motherboard 402.

In embodiments, at least some of the computing device 400 components, for example, the motherboard 402, communication chip 406, processor 404, digital signal processor 413, or memory 410/411, may be provided with a substrate provided with a charged surface, in accordance with embodiments of FIGS. 1-3.

The communication chip 406 may enable wireless communications for the transfer of data to and from the computing device 400. The communication chip 406 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.7 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards.

The communication chip 406 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 406 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E- UTRAN). The communication chip 406 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 406 may operate in accordance with other wireless protocols in other embodiments.

The computing device 400 may include a plurality of communication chips 406. For instance, a first communication chip 406 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 406 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.

In various implementations, the computing device 400 may be a server, a mobile computing device, a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 400 may be any other electronic device that processes data.

The embodiments described herein may be further illustrated by the following examples.

EXAMPLES

Example 1 may be an apparatus, comprising: a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus, wherein the metal layer is provided in response to a treatment of the surface with a poly electrolyte solution having an electrical charge to provide adsorption of metal ions to the surface and subsequent electroless plating of the surface with a metal, wherein the adsorbed metal ions are to enhance electroless plating of the surface with the metal.

Example 2 may include the apparatus of example 1, wherein the treatment of the surface with a polyelectrolyte further includes a plurality of treatments of the surface respectively with a plurality of polyelectrolyte solutions, and wherein each of the polyelectrolyte solutions have a positive charge or a negative charge.

Example 3 may include the apparatus of example 1, wherein the metal includes copper.

Example 4 may include the apparatus of any one of examples 1-3, wherein the polyelectrolyte solution includes poly acrylic acid, polystyrene sulfonate, or poly allylamine hydrochloride.

Example 5 may include the apparatus of any one of examples 1-3, wherein the metal ions include palladium (Pd) ions.

Example 6 may include the apparatus of any one of examples 1-3, wherein the substrate includes a dielectric material, a polymer film, or solder resist. Example 7 may include the apparatus of any one of examples 1-3, wherein the adsorbtion of metal ions to the surface further includes adsorbtion of metal ions to the surface in response to exposure to a reducing agent.

Example 8 may include the apparatus of any one of examples 1-3, wherein the apparatus is an embedded multi-die interconnect bridge (EMIB).

Example 9 may be a method for plating, comprising: performing a polyelectrolyte solution treatment to a surface of a substrate to create a coating on the surface having an electrical charge; and applying a transition ion catalyst to the coated surface based at least upon the electrical charge of the coating and an electrical charge of ions in the ion catalyst.

Example 10 may include the method of example 9, further comprising conducting electroless plating of the surface with a metal, wherein the transition metal catalyst is to enhance electroless plating of the substrate surface.

Example 11 may include the method of example 9, wherein applying an ion catalyst to the coated surface further includes applying an ion solution to the coated surface to cause ions in the solution to be adsorbed to the coated surface based upon the electrical charge of the coating and an electrical charge of the ions.

Example 12 may include the method of example 11, wherein applying an ion solution to the coated surface further includes dipping the coated surface into the ion solution.

Example 13 may include the method of example 11, further including applying a reducing agent to the coated surface to attach the ions to the coated surface.

Example 14 may include the method of example 13, wherein applying a reducing agent to the coated surface further includes dipping the coated surface into the reducing agent.

Example 15 may include the method of example 9, wherein applying a

polyelectrolyte solution to a surface of the material further includes dipping the surface of the material into the polyelectrolyte solution.

Example 16 may include the method of example 9, wherein applying a

polyelectrolyte solution to a surface of the material to create a coating on the surface of the material further includes applying a plurality of polyelectrolyte solutions respectively to the surface of the material to create a plurality of coatings on the surface of the material.

Example 17 may include the method of example 16, wherein each of the plurality of coatings has a positive charge or a negative charge. Example 18 may include the method of any one of examples 9-17, wherein the polyelectrolyte solution includes poly acrylic acid, polystyrene sulfonate, or poly allylamine hydrochloride.

Example 19 may include the method of any one of examples 9-17, wherein the ion solution includes a palladium (Pd) ion solution.

Example 20 may include the method of any one of examples 9-17, wherein the substrate is a dielectric material, a polymer film, or solder resist.

Example 21 may be a computing device, comprising; a processor; a memory coupled with the processor; and wherein at least one of the processor or memory comprises an integrated circuit (IC), wherein the IC includes: a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus, wherein the metal layer is provided in response to a treatment of the surface with a polyelectrolyte solution having an electrical charge to provide adsorption of metal ions to the surface and subsequent electroless plating of the surface with a metal, wherein the adsorbed metal ions are to enhance electroless plating of the surface with the metal.

Example 22 may include the computing device of example 21 , wherein the treatment of the surface with a polyelectrolyte further includes a plurality of treatments of the surface respectively with a plurality of polyelectrolyte solutions, and wherein each of the polyelectrolyte solutions have a positive charge or a negative charge.

Example 23 may include the computing device of example 21 , wherein the metal includes copper.

Example 24 may include the computing device of any one of examples 21 -23, wherein the polyelectrolyte solution includes poly acrylic acid, polystyrene sulfonate, or poly allylamine hydrochloride.

Example 25 may include the computing device of any one of examples 21 -23, wherein the metal ions include palladium (Pd) ions.

Example 26 may include the computing device of any one of examples 21 -23, wherein the substrate includes a dielectric material, a polymer film, or solder resist.

Example 27 may include the computing device of any one of examples 21 -23, wherein the adsorbtion of metal ions to the surface further includes adsorbtion of metal ions to the surface in response to exposure to a reducing agent.

Example 28 may include the computing device of any one of examples 21 -23, wherein the apparatus is an embedded multi-die interconnect bridge (EMIB). Example 29 may be an apparatus, comprising: means for performing a polyelectrolyte solution treatment to a surface of a substrate to create a coating on the surface having an electrical charge; and applying a transition ion catalyst to the coated surface based at least upon the electrical charge of the coating and an electrical charge of ions in the ion catalyst.

Example 30 may include the apparatus of example 29, further comprising means for conducting electroless plating of the surface with a metal, wherein the transition metal catalyst is to enhance electroless plating of the substrate surface.

Example 31 may include the apparatus of example 29, wherein means for applying an ion catalyst to the coated surface further includes means for applying an ion solution to the coated surface to cause ions in the solution to be adsorbed to the coated surface based upon the electrical charge of the coating and an electrical charge of the ions.

Example 32 may include the apparatus of example 31, wherein means for applying an ion solution to the coated surface further includes means for dipping the coated surface into the ion solution.

Example 33 may include the apparatus of example 31, further including means for applying a reducing agent to the coated surface to attach the ions to the coated surface.

Example 34 may include the apparatus of example 33, wherein means for applying a reducing agent to the coated surface further includes means for dipping the coated surface into the reducing agent.

Example 35 may include the apparatus of example 29, wherein means for applying a polyelectrolyte solution to a surface of the material further includes means for dipping the surface of the material into the polyelectrolyte solution.

Example 36 may include the apparatus of example 29, wherein means for applying a polyelectrolyte solution to a surface of the material to create a coating on the surface of the material further includes means for applying a plurality of polyelectrolyte solutions respectively to the surface of the material to create a plurality of coatings on the surface of the material.

Example 37 may include the apparatus of example 36, wherein each of the plurality of coatings has a positive charge or a negative charge.

Example 38 may include the apparatus of any one of examples 29-37, wherein the polyelectrolyte solution includes poly acrylic acid, polystyrene sulfonate, or poly allylamine hydrochloride. Example 39 may include the apparatus of any one of examples 29-37, wherein the ion solution includes a palladium (Pd) ion solution.

Example 40 may include the apparatus of any one of examples 29-37, wherein the substrate is a dielectric material, a polymer film, or solder resist.

Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. Embodiments of the present disclosure may be implemented into a system using any suitable hardware and/or software to configure as desired.

Although certain embodiments have been illustrated and described herein for purposes of description, a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments described herein be limited only by the claims and the equivalents thereof.

Claims

Claims What is claimed is:

1. An apparatus, comprising:

a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus,

wherein the metal layer is provided in response to a treatment of the surface with a polyelectrolyte solution having an electrical charge to provide adsorption of metal ions to the surface and subsequent electroless plating of the surface with a metal, wherein the adsorbed metal ions are to enhance electroless plating of the surface with the metal.

2. The apparatus of claim 1, wherein the treatment of the surface with a polyelectrolyte further includes a plurality of treatments of the surface respectively with a plurality of polyelectrolyte solutions, and wherein each of the polyelectrolyte solutions have a positive charge or a negative charge.

3. The apparatus of claim 1, wherein the metal includes copper.

4. The apparatus of any one of claims 1-3, wherein the polyelectrolyte solution includes poly acrylic acid, polystyrene sulfonate, or poly allylamine hydrochloride.

5. The apparatus of any one of claims 1-3, wherein the metal ions include palladium (Pd) ions.

6. The apparatus of any one of claims 1-3, wherein the substrate includes a dielectric material, a polymer film, or solder resist.

7. The apparatus of any one of claims 1-3, wherein the adsorbtion of metal ions to the surface further includes adsorbtion of metal ions to the surface in response to exposure to a reducing agent.

8. The apparatus of any one of claims 1 -3, wherein the apparatus is an embedded multi-die interconnect bridge (EMIB).

9. A method for plating, comprising:

performing a polyelectrolyte solution treatment to a surface of a substrate to create a coating on the surface having an electrical charge; and

applying a transition ion catalyst to the coated surface based at least upon the electrical charge of the coating and an electrical charge of ions in the ion catalyst.

10. The method of claim 9, further comprising conducting electroless plating of the surface with a metal, wherein the transition metal catalyst is to enhance electroless plating of the substrate surface.

1 1. The method of claim 9, wherein applying an ion catalyst to the coated surface further includes applying an ion solution to the coated surface to cause ions in the solution to be adsorbed to the coated surface based upon the electrical charge of the coating and an electrical charge of the ions.

12. The method of claim 11 , wherein applying an ion solution to the coated surface further includes dipping the coated surface into the ion solution.

13. The method of claim 11 , further including applying a reducing agent to the coated surface to attach the ions to the coated surface.

14. The method of claim 13, wherein applying a reducing agent to the coated surface further includes dipping the coated surface into the reducing agent.

15. The method of claim 9, wherein applying a polyelectrolyte solution to a surface of the material further includes dipping the surface of the material into the polyelectrolyte solution.

16. The method of claim 9, wherein applying a polyelectrolyte solution to a surface of the material to create a coating on the surface of the material further includes applying a plurality of polyelectrolyte solutions respectively to the surface of the material to create a plurality of coatings on the surface of the material.

17. The method of claim 16, wherein each of the plurality of coatings has a positive charge or a negative charge.

18. The method of any one of claims 9-17, wherein the polyelectrolyte solution includes poly acrylic acid, polystyrene sulfonate, or poly allylamine hydrochloride.

19. The method of any one of claims 9-17, wherein the ion solution includes a palladium (Pd) ion solution.

20. The method of any one of claims 9-17, wherein the substrate is a dielectric material, a polymer film, or solder resist.

21. A computing device, comprising;

a processor;

a memory coupled with the processor; and

wherein at least one of the processor or memory comprises an integrated circuit (IC), wherein the IC includes:

22. The computing device of claim 21, wherein the treatment of the surface with a polyelectrolyte further includes a plurality of treatments of the surface respectively with a plurality of polyelectrolyte solutions, and wherein each of the polyelectrolyte solutions have a positive charge or a negative charge.

23. An apparatus, comprising:

means for performing a polyelectrolyte solution treatment to a surface of a substrate to create a coating on the surface having an electrical charge; and

24. The apparatus of claim 23, further comprising means for conducting electroless plating of the surface with a metal, wherein the transition metal catalyst is to enhance electroless plating of the substrate surface.

25. The apparatus of claim 23, wherein means for applying an ion catalyst to the coated surface further includes means for applying an ion solution to the coated surface to cause ions in the solution to be adsorbed to the coated surface based upon the electrical charge of the coating and an electrical charge of the ions.