WO2019066815A1

WO2019066815A1 - Substrate with integrated resistive circuit element and method of providing same

Info

Publication number: WO2019066815A1
Application number: PCT/US2017/053793
Authority: WO
Inventors: Veronica Strong; Aleksandar Aleksov
Original assignee: Intel Corporation
Priority date: 2017-09-27
Filing date: 2017-09-27
Publication date: 2019-04-04

Abstract

Techniques and mechanisms for providing an integrated resistive circuit element of a substrate which includes one or more organic dielectric layers. In an embodiment, the substrate includes dielectric layer portions, wherein conductors variously extend each in a respective one of the dielectric layer portions to a side region thereof. The resistive circuit element, integrated in or on the substrate, adjoins each of the dielectric layer portions. Seed layers are variously coupled each between a resistive material of the circuit element and a respective one of the conductors. An additional catalytic seed layer portion is disposed between the resistive material and at least one dielectric layer. In another embodiment, processing to form the resistive circuit element include an electroless deposition of the resistive material.

Description

SUBSTRATE WITH INTEGRATED RESISTIVE CIRCUIT ELEMENT AND METHOD OF PROVIDING SAME

BACKGROUND

1. Technical Field

[0001] Embodiments of the invention generally relate to integrated circuit (IC) package and printed circuit board (PCB) technologies and, more particularly but not exclusively, to an integrated resistor of a package substrate.

2. Background Art

[0002] Integrated circuits are usually manufactured on wafer substrates. A wafer substrate is then "diced" or "singulated" into individual dies, each die carrying a respective integrated circuit. The die is then mounted on a package substrate, often with an intermediate interposer substrate. The substrate or substrates provide structural rigidity to the resulting integrated circuit package. A package substrate usually provides x-y transformation from contacts of the die to contacts on a carrier substrate on which the integrated circuit package is mounted. Signals can be provided through conductors in the substrate or substrates to and from an integrated circuit in the die.

[0003] As semiconductor technology advances for higher processor performance, package-on-package (PoP) designs and other adaptations in package assembly architectures have arisen. These more complex architectures place a premium on space and other package assembly resources, and need to accommodate operational speeds, power use, signal integrity and other circuit performance characteristics. As successive generations of packaging technologies continue to scale in size and level of integration, there is expected to be an increasing demand for incremental improvements in the configuration of packaged circuit elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

[0005] FIG. 1 shows views illustrating elements of a substrate including an integrated circuit element according to an embodiment.

[0006] FIG. 2 is a flow diagram illustrating elements of a method for integrating a circuit element in a substrate according to an embodiment.

[0007] FIG. 3 shows cross-sectional diagrams each illustrating structures at a respective stage of a substrate manufacture process according to an embodiment.

[0008] FIG. 4 shows cross-sectional diagrams each illustrating structures at a respective stage of a substrate manufacture process according to an embodiment.

[0009] FIG. 5 shows cross-sectional diagrams each illustrating structures at a respective stage of a substrate manufacture process according to an embodiment.

[0010] FIG. 6 is a functional block diagram illustrating a computing device in accordance with one embodiment.

[0011] FIG. 7 is a cross-sectional view of an interposer implementing one or more embodiments.

DETAILED DESCRIPTION

[0012] Embodiments discussed herein variously provide techniques and mechanisms for integrating a resistive circuit element in a substrate. Some embodiments variously exploit electroless ("eless") chemistry during substrate manufacturing to deposit a resistive material on selected metal surfaces and/or organic dielectric surfaces. For example, palladium (Pd) catalysts may be selectively activated at one or more particular regions to define at least in part the shape of a circuit element that is to function as a resistor or, in some embodiments, as a fuse. Such processing may allow for a resistive circuit element to be integrated directly into a layer of a package substrate, or of a printed circuit board (PCB), during the manufacture thereof. Accordingly, some embodiments provide for integration of a resistor or fuse within an organic package substrate. In other embodiments, a resistive circuit element may be integrated with a substrate at an exterior surface thereof.

[0013] The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. Such devices may be portable or stationary. In some embodiments the technologies described herein may be employed in a desktop computer, laptop computer, smart phone, tablet computer, netbook computer, notebook computer, personal digital assistant, server, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including a package substrate, printed circuit board or other suitable substrate structure.

[0014] FIG. 1 illustrates features of a substrate 100 including an integrated resistive circuit element in accordance with an embodiment. FIG. 1 also includes a cross-sectional detail side view 104 illustrating structures such as those in a region 102 of substrate 100.

[0015] Substrate 100 is one example of an embodiment comprising metallization structures and one or more organic insulator materials which provide electrical isolation between various ones of said metallization structures. For example, substrate 100 may be a package substrate or a printed circuit board (PCB). In an embodiment, substrate 100 includes two dielectric layers and a resistive circuit element disposed therebetween, wherein seed layer portions variously couple the resistive circuit element each to a respective conductor disposed in one of the two dielectric layers.

[0016] In the example embodiment shown, metallization structures of substrate 100 include horizontal layers 120 of patterned conductive traces - e.g,. where layers 120 variously extend along respective xy planes of the xyz coordinate system shown. Such metallization structures may further include vias 124 which variously extend vertically (e.g., along the z-axis) to couple respective ones of layers 120 to each other. Layers 120 and vias 124 - e.g,. comprising copper, nickel, gold, silver and/or any of various other conductor materials - may facilitate electrical connectivity with one or each of two opposite sides 1 10, 1 12 of substrate 100. For example, connectivity with substrate 100 (e.g., through substrate 100) may be facilitated with conductive contacts (e.g., including the illustrative contacts 126 shown) which are variously disposed on one or each of opposite sides 1 10, 112.

[0017] One or more dielectric materials of insulator layers 122 may promote electrical isolation of various ones of layers 120 and/or various ones of vias 124. In an embodiment, insulator layers 122 include any of a variety of dielectric compounds used, for example, in conventional package substrates and/or PCBs. Such compounds may include, but are not limited to, polyimide (PI), polytetrafluoroethylene (PTFE), build-up film (or "BF", typically a ceramic or silica/glass filled epoxide matrix material), a liquid crystal polymer (LCP), and polyetheretherketone (PEEK). In some embodiments, insulator layers 122 include a laminate material such as FR4, FR5, bismaleimide triazine (BT) resin, etc. Substrate 100 may have a woven or reinforced core (not shown) or - alternatively - may be coreless, in various embodiments.

[0018] As shown in view 104, substrate 100 may include respective portions of one or more dielectric layers, wherein two conductors variously extend each in a different respective one of said portions. An integrated resistor of substrate 100 may be coupled to the two conductors each via a different respective seed layer portion. The term "dielectric layer portion" is used herein to refer to a portion of a dielectric layer - e.g., wherein another dielectric layer portion may be a different portion of the same dielectric layer or, alternatively, may be some or all of a different dielectric layer. The terms "dielectric layer" and "dielectric layer portion," as used herein, variously refer to a layer of dielectric material (or a portion of said layer), where one or more other materials, such as the conductor of an electrode, may extend at least partially in - e.g., through - the layer, or layer portion.

[0019] With respect to any one dielectric layer portion, "side region" refers herein to at least some part of a side of that dielectric layer portion. For example, "side regions" may refer herein to different regions at one side of the same dielectric layer or, alternatively, to respective side regions of two different dielectric layers (e.g., including adjoining dielectric layer or at least one dielectric layer at a metal-dielectric interface). [0020] In a similar respect, the term "seed layer portion" is used herein to refer to at least some portion of some seed layer - e.g., wherein another seed layer portion may be a different portion of the same seed layer or, alternatively, may be some or all of a different seed layer. Seed layer portions may be variously formed at respective side regions each of a different dielectric layer portion.

[0021] Although some embodiments are not limited in this regard, conductors which are each coupled to a resistive circuit element may variously extend in different respective portions of the same dielectric layer (e.g., in different portions of the same contiguous dielectric material). In such an embodiment, the two conductors may each extend to the same side of the dielectric layer (e.g., to different respective regions of the same side).

[0022] For example, in the embodiment shown by view 104, substrate 100 comprises a dielectric layer 130 including layer portion 132, 134. It is to be appreciated that dielectric layer 130 represents at least one dielectric layer which, for example, comprises multiple dielectric sub-layers and/or is disposed over other dielectric layers (not shown) of substrate 100. Layer portion 132 may include a side region 136, wherein a conductor 140 extends in layer portion 132 to side region 136. Alternatively or in addition, layer portion 134 may include a side region 138, wherein a conductor 142 extends in layer portion 134 to side region 138. Layer portions 132, 134 may each include a respective organic dielectric material such as a BF or any of various other organic polymers adapted, for example, from conventional package substrates or PCBs.

[0023] In another embodiment, layer portions 132, 134 may be respective portion of different dielectric layers - e.g., wherein one of the dielectric layers 130, 170 shown includes layer portion 132 and the other of dielectric layers 130, 170 includes layer portion 134. In such an embodiment, a side 172 of dielectric layers 170, for example, may comprise a side region which functionally corresponds to one of side region 136, 138. In other embodiments, substrate 100 omits dielectric layer 170 - e.g., wherein a resistive circuit element 160 is integrated on one of sides 1 10, 1 12.

[0024] Circuit element 160 may be integrated with substrate 100 - e.g., wherein circuit element 160 adjoins each of side region 136 and side region 138. For example a seed layer portion 150 may be disposed at side region 136 on an end of conductor 140, wherein seed layer portion 150 adjoins each of conductor 140 and circuit element 160. Similarly, another seed layer portion 152 disposed at side region 138, may adjoin each of conductor 142 and circuit element 160. Seed layer portions 150, 152 may include a metal which is different than that of conductor 140 and/or conductor 142 - e.g., wherein seed layer portions 150, 152 include palladium (Pd) and conductors 140, 142 include copper (Cu). Seed layer portions 150, 152 may be artifacts of an electroless deposition process which, according to some embodiments, enables electroless deposition of a resistive material of circuit element 160. Examples of such a resistive material include any of a variety of metals - such as, but not limited to, various compounds of nickel boron (NiB), nickel phosphorus (NiP), cobalt phosphide (CoP), cobalt boron (CoB), nickel boron molybdenum (NiBMo), nickel boron tin (NiBSn) or the like - produced by electroless deposition.

[0025] In an embodiment, circuit element 160 further includes another seed layer portion 162 at a side region 182 of another dielectric layer portion 180. In such an embodiment, seed layer portion 162 may adjoin a portion of the resistor material of circuit element 160 which extends across a region between side regions 136, 138. Seed layer portion 162 may comprise a catalytic metal - e.g., other than that of one or both of seed layer portions 150, 152 - that facilitates electroless deposition of the resistive material on a dielectric surface. In one example embodiment, respective (z-axis) thicknesses of seed layer portions 150, 152, 162 may each be equal to or less than 25 nm - e.g., wherein such thicknesses are each equal to or less than 10 nm. However, some embodiments are not limited to particular seed layer thicknesses. It will be appreciated that a seed layer portion being at given a dielectric side region may include the seed layer portion extending from that dielectric side region in one or each of two opposite directions (e.g., including an upward direction and a downward direction).

[0026] FIG. 2 shows features of a method 200 to integrate a circuit element with other structures of a substrate according to an embodiment. Method 200 may include processes to fabricate some or all of the structure of substrate 100, for example. The particular order of operations shown in the flow diagram of FIG. 2 is merely illustrative, and not limiting on some embodiments.

[0027] As shown in FIG. 2, method 200 may include, at 210, forming a first seed layer portion on a first side region of a first dielectric layer portion. The first seed layer portion may include palladium (Pd), platimum (Pt), gold (Au), silver (Ag), or any of various other metals suitable to provide a site for catalytic reaction. Forming of the first seed layer portion at 210 may include, for example, depositing a catalytic metal ionic precursor on the first side region, followed by selectively reducing a portion of the catalytic metal ionic precursor. Such a reduced portion may provide a catalytic site for a subsequent electroless deposition of a metal alloy that is to provide a resistive material of a circuit element. For example, method 200 may further comprise, at 220, forming a resistor, including performing an electroless deposition of a resistive material on the first seed layer portion. The resistive material may include an alloy of a metal such as one of nickel (Ni), copper (Cu), silver (Ag), gold (Au), or cobalt (Co), the alloy suitable to provide functionality of a resistor or of a fuse. Examples of such alloys include, but are not limited to, compounds of nickel boron (NiB), nickel phosphorus (NiP), cobalt phosphide (CoP), cobalt boron (CoB), nickel boron molybdenum (NiBMo), nickel boron tin (NiBSn) or the like.

[0028] In some embodiments, method 200 further comprises, at 230, forming a second seed layer portion on a second side region, wherein one of a second dielectric layer portion and the resistor includes the second side region. Method 200 may further include, at 240, forming a third seed layer portion on a third side region, wherein one of a third dielectric layer portion and the resistor includes the third side region. In such an embodiment, the first seed layer portion may - e.g., at a time after the resistor, the second seed layer portion and the third seed layer portion are formed - adjoin a portion of the resistive material which extends between the first surface region and the second surface region.

[0029] Forming of the second seed layer portion at 230 and/or forming of the third seed layer portion at 240 may include performing a metal exchange reaction and/or other suitable processing - e.g., adapted from any of a variety of conventional metal seeding techniques - to deposit copper, palladium or various other catalytic metals. In some embodiments, the forming at 230 and/or the forming at 240 includes depositing and subsequently reducing an catalytic metal ionic precursor - e.g., wherein two or more of the first seed layer portion, the second seed layer portion and the third seed layer portion have the same chemical composition and, in some embodiments, are different respective portions of the same contiguous seed layer. For example, one or each of the second seed layer portion and the third seed layer portion may include a metal (e.g., Pd) of the first seed layer portion. In other embodiments, the first seed layer portion has a different composition than that of one or both of the second seed layer portion and the third seed layer portion. [0030] The first dielectric layer portion, the second dielectric layer portion and the third dielectric layer portion may each include a respective organic dielectric - e.g.., wherein one or more build-up films (or other organic dielectric layers) each include a respective one of the three dielectric layer portions. For example, the first dielectric layer portion may adjoin (and be disposed between) both the second dielectric layer portion and the third dielectric layer portion in a common dielectric layer. In such an embodiment, the resistor may be formed at 220 on a single dielectric layer which comprises each of the first, second, and third dielectric layer portions. Alternatively, a first dielectric layer may include the first dielectric layer portion, wherein a second dielectric portion includes one or both of the second dielectric layer portion and the third dielectric layer portion.

[0031] Method 200 may further include forming a first conductor (at 250) which extends in the second dielectric layer portion to the second side region and (at 260) forming a second conductor which extends in the third dielectric layer portion to the third side region. One or both of the first and second conductors may be formed by resist, etch and metallization processes that, for example, are adapted from conventional techniques for building metallization structures of a package substrate or a PCB. Forming the first conductor at 250 and forming the second conductor at 260 may be performed concurrently or, for example, performed in sequence with each other and with the electroless deposition at 220.

[0032] At a time after a completion of performing the electroless deposition at 220, forming the second conductor at 250, and forming the third conductor at 260, the resistor may be coupled to the second conductor via the second seed layer portion and further coupled to the third conductor via the first third layer. In such a configuration, the resistor may be disposed between a first dielectric layer and a second dielectric layer which, for example, include the second dielectric layer portion and the third dielectric layer portion, respectively. Alternatively, the resistor may be disposed on a surface of a substrate - e.g., the surface including each of the first surface region, the second surface region and the third surface region.

[0033] FIG. 3 shows cross-sectional side views of structures at respective stages 300-305 of processing to fabricate an integrated circuit element of a substrate according to an embodiment. Processing such as that represented in stages 300-305 may fabricate some of all of the features of substrate 100 - e.g., where such processing includes features of method 200. [0034] At stage 300, an ionic precursor layer 320 may be disposed on a side 312 of a dielectric layer 310. Dielectric layer 310 may include a BF or any of a variety of other insulator materials. Prior to deposition of metallization layer 320, side 312 may be roughened by operations which, for example, are adapted from conventional desmear techniques. A roughening process may create ridges, pores and/or other structures within dielectric layer 310 at side 312, wherein the structures provide binding sites for catalytic metal ionic precursors of ionic precursor layer 320. After binding at side 312 - e.g., by chemisorption or other adsorption - such precursors may be reduced via subsequent chemical, thermal, ultra-violet and/or other reduction processes to produce noble transition metal nanoparticles which at (e.g., variously in or on) side 312.

[0035] Formation of ionic precursor layer 320 may include exposing side 312 to an aqueous solution or a non-aqueous solution - e.g., by immersion, spray coating, spin coating or other such deposition method - to an ionic bath solution which provides a source of palladium ions or other suitable metal ions. Such a metal ionic solution may comprise (for example) any of a variety of palladium salts including, but not limited to, palladium chloride, palladium bromide, palladium nitrate, palladium sulfate, palladium oxide and palladium hydroxide. Ionic precursor layer 320 may include coordinated metal ions (e.g., including palladium ions Pd⁺²) which, for example, accommodate ionic bonding to any of various salts (e.g., chlorides) or inclusion in a coordinated complex (e.g., porphyrins).

[0036] Side 312 of dielectric layer 310 may be functionalized with moieties that facilitate the adhesion of metal ionic precursors. Such moieties may comprise one or more

electronegative functional groups including, but not limited to, any of a variety of hydroxides, amines, ketones and carboxyl groups. A moiety may stabilize incoming transition metals (e.g., Pd⁺²) by providing surface binding sites for transition metal ions or for metal coordinated complexes.

[0037] At stage 301 , a patterned resist 314 (e.g., including a photoresist material, dielectric or other suitable material) to act as a mask may be formed on ionic precursor layer 320, the patterned resist 314 extending over only some of ionic precursor layer 320.

Subsequently, an exposed portion of ionic precursor layer 320 may be subjected to a reduction reaction - e.g., by introduction of a reduction agent 316 through patterned resist 314. Reducing agent 316 may include hydrazine, hypophosphite, amine borane or any of a variety of other compounds to reduce metal ions. Additionally or alternatively, light induced (e.g., by UV and/or laser) and/or heat induced reduction processes may be employed. A reduced portion 322 of ionic precursor layer 320 - e.g., resulting from reduction of Pd⁺² ions to Pd° - may form a seed layer portion (e.g., at 210 of method 200) to facilitate a subsequent growth of a resistive structure on dielectric layer 310.

[0038] For example, as shown at stage 302, a resistive material 330 may be grown (e.g., at 220 of method 200) on portion 322 via electroless deposition, wherein a reduced metal (e.g., Pd°) of portion 322 functions as a catalytic seed for such growth. Although some embodiments are not limited in this regard, electroless deposition of resistive material 330 may be performed after (or alternatively, before) patterned resist 314 has been stripped. Resistive material 330 may include a compound of nickel phosphorous (NiP), nickel boron (NiB), cobalt phosphide (CoP), cobalt boron (CoB), nickel boron molybdenum (NiBMo), nickel boron tin (NiBSn) or any of a variety of other materials suitable to provide functionality of a resistor or a fuse.

[0039] At stage 303, portions of ionic precursor layer 320 which were not exposed to reduction agent 316 - e.g., including portions other than portion 322 - may be etched or otherwise stripped from side 312. Subsequently, a seed metal 340 - e.g., comprising copper (Cu), silver (Ag), gold (Au), titanium (Ti), cobalt (Co) - may be deposited at least on a top side of resistive material 330. In some embodiments, seed metal 340 includes a combination of multiple constituent layers (e.g., including respective layers of titanium and copper, respective layers of tantalum and cobalt, or respective layers of tungsten and copper).

Different portions of seed metal 340 may ultimately function as distinct seed layer portions including, for example, the second seed layer portion formed at 230 and the third seed layer portion formed at 240.

[0040] Seed metal 340 may facilitate subsequent metallization to provide coupling of resistive material 330 to one or more conductors. For example, as shown at stage 304, a patterned resist 350 may be formed over resistive material 330 and seed metal 340, the patterned resist 350 leaving some portions of seed metal 340 exposed. Subsequently, an electrochemical or electroless deposition 352 of additional metal - e.g., including copper (Cu), silver (Ag), gold (Au), platinum (Pt), aluminum (Al) or the like - may be performed through patterned resist 350 onto the exposed portions of seed metal 340. [0041] As shown at stage 305, deposition 352 may result in the formation of conductors 360, 362 (e.g., at 250 and 260 of method 200) which are each coupled at a different respective location along a length of resistive material 330. Conductors 360, 362 may, for example, include the first conductor formed at 240 and the second conductor formed at 250. In such an embodiment, patterned resist 350 and portions of seed metal 340 may be subsequently etched or otherwise removed - and a layer 370 of dielectric material subsequently deposited - to provide at least some electrical isolation between conductors 360, 362. Resistive material 330 may thus be configured as a resistive circuit element which is coupled to each of conductors 360, 362 via a different respective two seed layer portions each formed from seed metal 340.

[0042] FIG. 4 shows cross-sectional side views of structures at respective stages 400-405 of processing to fabricate an integrated circuit element of a substrate according to an embodiment. Processing represented in stages 400-405 may fabricate some of all of the features of substrate 100, for example. Such processing may include features of method 200, for example.

[0043] At stage 400, seed layer portions 420, 422 may be selectively formed (e.g., at 230 and 240 of method 200) each at a respective side region of a side 412 of a dielectric layer 410. Seed layer portions 420, 422 may be selectively formed via metal exchange reaction over respective conductors 414, 416. Conductors 414, 416 may variously extend each in a respective dielectric layer portion of layer 410 - e.g., wherein seed layer portions 420, 422 are disposed on conductors 414, 416 (respectively) each at their corresponding side region. Metallization processing to form conductors 414, 416 (e.g., at 250 and 260 of method 200) may be adapted from conventional operations, which are not detailed herein to avoid obscuring features of various embodiments.

[0044] Formation of seed layer portions 420, 422 may result from a metal exchange reaction and/or other suitable processing - e.g., adapted from any of a variety of conventional metal seeding techniques - to deposit a catalytic metal (e.g., Pd°) on exposed surfaces of conductors 414, 416 at side 412. Prior to deposition of seed layer portions 420, 422, side 412 may be roughened by a desmear process.

[0045] As shown at stage 401 , ionic metal precursor portions 424, 426 may be subsequently deposited on side 412, and a patterned resist 430 formed at least on ionic metal precursor portions 426. Formation of ionic metal precursor portions 424, 426 may include processing such as that used to deposit ionic precursor layer 320. Similar to a portion of ionic precursor layer 320, ionic metal precursor portion 424 may be subsequently reduced to provide a site for growth of a resistive circuit element thereon. To facilitate such reduction, a patterned resist 430 may be formed on select portions of ionic metal precursor portions 424, 426 - e.g., wherein the patterned resist 430 leaves ionic metal precursor portion 424 (and, in some embodiments, seed layer portions 420, 422) exposed.

[0046] Subsequently, the exposed ionic metal precursor portion 424 may be subjected to a reduction reaction - e.g., by introduction of a reduction agent 432 through patterned resist 430. The reduction of ionic metal precursor portion 424 using reduction agent 432 may include one or more features of that provided with reduction agent 316, for example, and may result in a reduced portion 428 which forms a seed layer portion (e.g., at 210 of method 200) to facilitate a subsequent growth of a resistive structure on dielectric layer 410.

[0047] For example, as shown at stage 403, a resistive material 440 may be grown on portion 428 via electroless deposition (e.g., at 220 of method 200), wherein a reduced metal (e.g., Pd°) of portion 428 functions as a catalytic seed for such deposition. Seed layer portions 420, 422 may also provide sites for further growth of resistive material 440.

Although some embodiments are not limited in this regard, electroless deposition of resistive material 440 may be performed after (or alternatively, before) patterned resist 430 has been stripped. Resistive material 440 may include a compound of nickel phosphorous (NiP) any of a variety of other materials suitable to provide functionality of a resistor or a fuse.

Resistive material 440 may thus be configured as a resistive circuit element which is coupled to each of conductors 460, 462 via a different respective one of seed layer portions 420, 422.

[0048] Although some embodiments are not limited in this regard, additional processing may be performed for the resistive circuit element to be embedded in an interior region of the substrate. By way of illustration and not limitation, ionic metal precursor portions 426 which were not exposed to reduction agent 416 may be etched or otherwise stripped from side 412 (at stage 404). Subsequently, as shown at stage 405, a layer 450 of dielectric material may be subsequently deposited over resistive material 440.

[0049] FIG. 5 shows cross-sectional side views of structures at respective stages 500-505 of processing to fabricate an integrated circuit element of a substrate according to an embodiment. Processing such as that represented in stages 500-505 may fabricate structures of substrate 100 - e.g., according to method 200.

[0050] At stage 500, an ionic metal precursor layer 524 may be disposed on a side 512 of a dielectric layer 510 - e.g., after formation of a conductor 514 which extends in a dielectric layer portion of layer 510 and after growth of a seed layer portion 520 at a region of side 512. In such an embodiment, seed layer portion 520 may be disposed via metal exchange reaction on a surface of conductor 514 which is at the corresponding region of side 512. Dielectric layer 510 may include a BF or other such insulator material, and may be desmeared prior to deposition of a noble metal catalyst to form seed layer portion 520. Formation of seed layer portion 520 may include a metal exchange reaction by exposing side 512 - e.g., via immersion - to an ionic metal chemical bath solution, wherein a compound of seed layer portion 520 may include non-covalently bonded metal ions (e.g., including palladium ions Pd⁺²). Ionic metal precursor layer 524 and seed layer portion 520 may include respective features of ionic precursor layer 320 and seed layer portion 420, for example.

[0051] At stage 501 , a patterned resist 530 may be patterned on selective portions of ionic metal precursor layer 524 (and on seed layer portion 520, in some embodiments).

Subsequently, an exposed portion of ionic metal precursor layer 524 may be subjected to a reduction reaction by a reduction agent 532 introduced through patterned resist 530. Seed layer portion 520 may include a neutral metal (e.g., Pd°) prior to such reduction of ionic metal precursor layer 524 at stage 501 - e.g., wherein seed layer portion 520 is grown by a metal exchange reaction wherein palladium metal replaces copper metal at the surface of conductor 514.

[0052] A reduced portion 528 of ionic metal precursor layer 524 may facilitate a growth of a resistive structure thereon. For example, as shown at stage 502, patterned resist 530 and unreduced portions of ionic metal precursor layer 524 may be stripped, etched or otherwise removed, and a resistive material 540 grown (e.g., at 220 of method 200) on portion 528 and seed layer portion 520 via electroless deposition. Growth of resistive material 540 may be similar to that of resistive material 440 - e.g., wherein seed layer portion 520 and a reduced metal (e.g., Pd°) of portion 528 function as catalytic seeds for such growth.

[0053] At stage 503, a seed layer portion 550 - e.g., comprising copper (Cu), titanium (Ti) and/or any of various other metals - may be deposited at least on a top side of resistive material 540. Seed layer portion 550 may facilitate subsequent metallization to provide coupling of resistive material 540 to one or more conductors. For example, as shown at stage 504, a patterned resist 560 may be formed over resistive material 540 and seed layer portion 550, the patterned resist 560 leaving at least a portion of seed layer portion 550 exposed. Subsequently, a deposition 562 of additional metal - e.g., including copper (Cu), silver (Ag), gold (Au), platinum (Pt) or the like - may be performed through patterned resist 560 onto the exposed portions of seed layer portion 550.

[0054] As shown at stage 505, deposition 562 may result in the formation of another conductor 570 which is coupled to resistive material 540 via a seed layer portion formed by an only partial removal of seed layer portion 550. Conductor 570 may, for example, include one of the first conductor formed at 240 and the second conductor formed at 250. In such an embodiment, patterned resist 560 and portions of seed layer portion 550 may be subsequently stripped, etched or otherwise removed. Another layer 580 of dielectric material may be subsequently deposited on resistive material 540 and around conductor 570. Resistive material 540 may thus be configured as a resistive circuit element which is coupled to conductors 514, 570 via different respective seed layer portions.

[0055] FIG. 6 illustrates a computing device 600 in accordance with one embodiment. The computing device 600 houses a board 602. The board 602 may include a number of components, including but not limited to a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the board 602. In some implementations the at least one communication chip 606 is also physically and electrically coupled to the board 602. In further implementations, the communication chip 606 is part of the processor 604.

[0056] Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to the board 602. These other components include, but are not limited to, volatile memory (e.g., DRAM), nonvolatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). [0057] The communication chip 606 enables wireless communications for the transfer of data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 606 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 600 may include a plurality of communication chips 606. For instance, a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0058] The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communication chip 606 also includes an integrated circuit die packaged within the communication chip 606.

[0059] In various implementations, the computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other electronic device that processes data.

[0060] Some embodiments may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to an embodiment. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), etc.

[0061] FIG. 7 illustrates an interposer 700 that includes one or more embodiments. The interposer 700 is an intervening substrate used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 may be, for instance, an integrated circuit die. The second substrate 704 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 700 may couple an integrated circuit die to a ball grid array (BGA) 706 that can subsequently be coupled to the second substrate 704. In some embodiments, the first and second substrates 702, 704 are attached to opposing sides of the interposer 700. In other embodiments, the first and second substrates 702, 704 are attached to the same side of the interposer 700. And in further embodiments, three or more substrates are interconnected by way of the interposer 700.

[0062] The interposer 700 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

[0063] The interposer may include metal interconnects 708 and vias 710, including but not limited to through-silicon vias (TSVs) 712. The interposer 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 700. In accordance with some embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 700. [0064] In one implementation, a substrate comprises a first dielectric layer portion including a first side region, wherein a first conductor extends in the first dielectric layer portion to the first side region, a second dielectric layer portion including a second side region, wherein a second conductor extends in the second dielectric layer portion to the second side region, a first seed layer portion at the first side region, the first seed layer portion adjoining each of the first conductor and a resistive material of the resistor, a second seed layer portion at the second side region, the second seed layer portion adjoining each of the second conductor and the resistive material, and a resistor including a resistive material coupled to the first conductor and to the second conductor via the first seed layer portion and the second seed layer portion, respectively. The substrate further comprises a third dielectric layer portion including a third side region, wherein the first dielectric layer portion, the second dielectric layer portion and the third dielectric layer portion each include a respective organic dielectric, and a third seed layer portion, at the third side region, which adjoins a portion of the resistive material which extends between the first surface region and the second surface region.

[0065] In one embodiment, the third dielectric layer portion adjoins both the first dielectric layer portion and the second dielectric layer portion. In another embodiment, the resistor is disposed between a first dielectric layer including the first dielectric layer portion and a second dielectric layer including the second dielectric layer portion. In another embodiment, a packaged device includes the substrate. In another embodiment, a printed circuit board includes the substrate. In another embodiment, the third seed layer portion includes palladium (Pd). In another embodiment, one of the first seed layer portion and the second seed layer portion includes palladium (Pd). In another embodiment, the resistor includes nickel phosphorus (NiP).

[0066] In another implementation, a method comprises forming a first seed layer portion at a first side region of a first dielectric layer portion, forming a resistor, including performing an electroless deposition of a resistive material on the first seed layer portion, forming a second seed layer portion at a second side region, wherein one of a second dielectric layer portion and the resistor includes the second side region, and forming a third seed layer portion at a third side region. One of a third dielectric layer portion and the resistor includes the third side region, wherein the first dielectric layer portion, the second dielectric layer portion and the third dielectric layer portion each include a respective organic dielectric, wherein, after the resistor, the second seed layer portion and the third seed layer portion are formed, the first seed layer portion adjoins a portion of the resistive material which extends between the second surface region and the third surface region. The method further comprises forming a first conductor which extends in the second dielectric layer portion to the second side region, and forming a second conductor which extends in the third dielectric layer portion to the third side region.

[0067] In one embodiment, the third dielectric layer portion adjoins both the first dielectric layer portion and the second dielectric layer portion. In another embodiment, a first dielectric layer includes the first dielectric layer portion and a second dielectric layer includes the second dielectric layer portion. In another embodiment, forming the first seed layer portion includes depositing a catalytic metal ionic precursor on the first side region, and selectively reducing a portion of the catalytic metal ionic precursor on the first conductor. In another embodiment, the third seed layer portion includes palladium (Pd). In another embodiment, one of the first seed layer portion and the second seed layer portion includes palladium (Pd). In another embodiment, the resistor includes nickel phosphorus (NiP).

[0068] In another implementation, a system comprises a substrate comprising a first dielectric layer portion including a first side region, wherein a first conductor extends in the first dielectric layer portion to the first side region, a second dielectric layer portion including a second side region, wherein a second conductor extends in the second dielectric layer portion to the second side region, a first seed layer portion at the first side region, the first seed layer portion adjoining each of the first conductor and a resistive material of the resistor, a second seed layer portion at the second side region, the second seed layer portion adjoining each of the second conductor and the resistive material, and a resistor including a resistive material coupled to the first conductor and to the second conductor via the first seed layer portion and the second seed layer portion, respectively. The substrate further comprises a third dielectric layer portion including a third side region, wherein the first dielectric layer portion, the second dielectric layer portion and the third dielectric layer portion each include a respective organic dielectric, and a third seed layer portion, at the third side region, which adjoins a portion of the resistive material which extends between the first surface region and the second surface region. The system further comprises a display device coupled to the substrate, the display device to display an image based on a signal communicated with the substrate. [0069] In one embodiment, the third dielectric layer portion adjoins both the first dielectric layer portion and the second dielectric layer portion. In another embodiment, the resistor is disposed between a first dielectric layer including the first dielectric layer portion and a second dielectric layer including the second dielectric layer portion. In another embodiment, a packaged device of the system includes the substrate. In another embodiment, a printed circuit board of the system includes the substrate. In another embodiment, the third seed layer portion includes palladium (Pd). In another embodiment, one of the first seed layer portion and the second seed layer portion includes palladium (Pd). In another embodiment, the resistor includes nickel phosphorus (NiP).

[0070] Techniques and architectures for providing an integrated circuit element of a substrate are described herein. In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of certain embodiments. It will be apparent, however, to one skilled in the art that certain embodiments can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the description.

[0071] Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0072] Some portions of the detailed description herein are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the computing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. [0073] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the discussion herein, it is appreciated that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

[0074] Certain embodiments also relate to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs) such as dynamic RAM (DRAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.

[0075] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description herein. In addition, certain embodiments are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of such embodiments as described herein.

[0076] Besides what is described herein, various modifications may be made to the disclosed embodiments and implementations thereof without departing from their scope. Therefore, the illustrations and examples herein should be construed in an illustrative, and not a restrictive sense. The scope of the invention should be measured solely by reference to the claims that follow.

Claims

CLAIMS What is claimed is:

1. A substrate comprising: a resistor including a resistive material; a first dielectric layer portion including a first side region, wherein a first conductor extends in the first dielectric layer portion to the first side region; a second dielectric layer portion including a second side region, wherein a second conductor extends in the second dielectric layer portion to the second side region; a first seed layer portion at the first side region, the first seed layer portion adjoining each of the first conductor and the resistive material of the resistor; a second seed layer portion at the second side region, the second seed layer portion adjoining each of the second conductor and the resistive material, wherein the resistive material is coupled to the first conductor and to the second conductor via the first seed layer portion and the second seed layer portion, respectively; a third dielectric layer portion including a third side region, wherein the first dielectric layer portion, the second dielectric layer portion and the third dielectric layer portion each include a respective organic dielectric; and a third seed layer portion, at the third side region, which adjoins a portion of the resistive material which extends between the first surface region and the second surface region.

2. The substrate of claim 1, wherein the third dielectric layer portion adjoins both the first dielectric layer portion and the second dielectric layer portion.

3. The substrate of claim 1, wherein the resistor is disposed between a first dielectric layer including the first dielectric layer portion and a second dielectric layer including the second dielectric layer portion.

4. The substrate of claim 1, wherein a packaged device includes the substrate.

5. The substrate of claim 1, wherein a printed circuit board includes the substrate.

6. The substrate of claim 1, wherein the third seed layer portion includes palladium (Pd).

7. The substrate of claim 6, wherein one of the first seed layer portion and the second seed layer portion includes palladium (Pd).

8. The substrate of claim 1, wherein the resistor includes nickel phosphorus (NiP).

9. A method comprising: forming a first seed layer portion at a first side region of a first dielectric layer portion; forming a resistor, including performing an electroless deposition of a resistive material on the first seed layer portion; forming a second seed layer portion at a second side region, wherein one of a second dielectric layer portion and the resistor includes the second side region; forming a third seed layer portion at a third side region, wherein one of a third dielectric layer portion and the resistor includes the third side region, wherein the first dielectric layer portion, the second dielectric layer portion and the third dielectric layer portion each include a respective organic dielectric, wherein, after the resistor, the second seed layer portion and the third seed layer portion are formed, the first seed layer portion adjoins a portion of the resistive material which extends between the second surface region and the third surface region; forming a first conductor which extends in the second dielectric layer portion to the second side region; and forming a second conductor which extends in the third dielectric layer portion to the third side region.

10. The method of claim 9, wherein the third dielectric layer portion adjoins both the first dielectric layer portion and the second dielectric layer portion.

11. The method of claim 9, wherein a first dielectric layer includes the first dielectric layer portion and a second dielectric layer includes the second dielectric layer portion.

12. The method of claim 9, wherein forming the first seed layer portion includes: depositing a catalytic metal ionic precursor on the first side region; and selectively reducing a portion of the catalytic metal ionic precursor on the first conductor.

13. The method of claim 9, wherein the third seed layer portion includes palladium (Pd).

14. The method of claim 13, wherein one of the first seed layer portion and the second seed layer portion includes palladium (Pd).

15. The method of claim 9, wherein the resistor includes nickel phosphorus (NiP).

16. A system comprising: a substrate comprising: a resistor including a resistive material; a first dielectric layer portion including a first side region, wherein a first conductor extends in the first dielectric layer portion to the first side region; a second dielectric layer portion including a second side region, wherein a second conductor extends in the second dielectric layer portion to the second side region; a first seed layer portion at the first side region, the first seed layer portion adjoining each of the first conductor and the resistive material of the resistor; a second seed layer portion at the second side region, the second seed layer portion adjoining each of the second conductor and the resistive material, wherein the resistive material is coupled to the first conductor and to the second conductor via the first seed layer portion and the second seed layer portion, respectively; a third dielectric layer portion including a third side region, wherein the first dielectric layer portion, the second dielectric layer portion and the third dielectric layer portion each include a respective organic dielectric; and a third seed layer portion, at the third side region, which adjoins a portion of the resistive material which extends between the first surface region and the second surface region; and a display device coupled to the substrate, the display device to display an image based on a signal communicated with the substrate.

17. The system of claim 16, wherein the third dielectric layer portion adjoins both the first dielectric layer portion and the second dielectric layer portion.

18. The system of claim 16, wherein the resistor is disposed between a first dielectric layer including the first dielectric layer portion and a second dielectric layer including the second dielectric layer portion.

19. The system of claim 16, wherein a packaged device of the system includes the substrate.

20. The system of claim 16, wherein a printed circuit board of the system includes the substrate.

21. The system of claim 16, wherein the third seed layer portion includes palladium (Pd).

22. The system of claim 21, wherein one of the first seed layer portion and the second seed layer portion includes palladium (Pd).

23. The system of claim 16, wherein the resistor includes nickel phosphorus (NiP).