WO2019057064A1 - 阵列基板和显示面板 - Google Patents
阵列基板和显示面板 Download PDFInfo
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- WO2019057064A1 WO2019057064A1 PCT/CN2018/106447 CN2018106447W WO2019057064A1 WO 2019057064 A1 WO2019057064 A1 WO 2019057064A1 CN 2018106447 W CN2018106447 W CN 2018106447W WO 2019057064 A1 WO2019057064 A1 WO 2019057064A1
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- switching element
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- scan line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to an array substrate and a display panel.
- the liquid crystal display has the advantages of high image quality, small size, light weight, low voltage drive, low power consumption and wide application range, so it has been widely used in medium and small portable TVs, mobile phones, video recorders. Consumer electronics or computer products such as notebook computers, desktop monitors, and projection TVs have gradually replaced the cathode ray tube (CRT) display. However, how to improve the pixel aperture ratio of the liquid crystal display and reduce the leakage current, thereby achieving better display quality has always been one of the important research topics.
- Embodiments of the present disclosure provide an array substrate and a display panel to achieve a technical effect of reducing leakage current and achieving better display quality.
- an array substrate including: a data line; a scan line, the scan line is disposed to intersect with the data line; and a pixel electrode disposed at an intersection of the scan line and the data line
- the pixel electrode is provided with at least one slit, the length direction of the slit is inclined with respect to a vertical direction of the scan line; two active switching elements connected in series, and two active switching elements connected in series And connecting the scan line, the data line and the pixel electrode to form a switch circuit; and a common electrode layer disposed in the same layer as the pixel electrode, or stacked with the pixel electrode and separated by an insulating layer;
- the number of the slits is plural and arranged in parallel with each other, and the plurality of slits are a hollow structure in which both ends of the pixel electrode are closed or a hollow structure in which one end is closed and the other end is open.
- an array substrate including: a data line; a scan line, the scan line is disposed to intersect with the data line; and a pixel electrode, wherein the pixel electrode is disposed on the scan line and the data line At the intersection, the pixel electrode is provided with at least one slit, the length direction of the slit is inclined with respect to a vertical direction of the scanning line; and two active switching elements connected in series, the two actives in series A switching element is coupled to the scan line, the data line, and the pixel electrode to form a switching circuit.
- an angle at which the longitudinal direction of the slit is inclined with respect to a vertical direction of the scanning line ranges from 2° to 8°.
- a line width of the scan line is greater than a line width of the data line.
- the number of the slits is plural and disposed in parallel with each other, and the plurality of slits are hollow structures closed at both ends of the pixel electrode or hollowed out at one end and open at the other end structure.
- the array substrate further includes: a common electrode layer disposed in the same layer as the pixel electrode.
- the array substrate further includes: a common electrode layer, and the pixel electrode is stacked and spaced apart by an insulating layer.
- the two active switching elements include a first active switching element and a second active switching element, and a first electrode end of the first active switching element is connected to the data line a second electrode end of the first active switching element is connected from a side of the data line across the data line to a first electrode end of the second active switching element, the second A second electrode end of the source switching element is coupled to the pixel electrode, and a control electrode end of the first active switching element and a control electrode end of the second active switching element are coupled to the scan line.
- the pixel electrode is an ITO transparent electrode.
- the two active switching elements include a first active switching element and a second active switching element, a first electrode end and a second of the first active switching element a second electrode end of the active switching element is located at one side of the scan line, and a second electrode end of the first active switching element and a first electrode end of the second active switching element are located on the scan line On the other side, the control electrode terminal of the first active switching element and the control electrode terminal of the second active switching element are connected to the scan line.
- a display panel including: an array substrate, wherein the array substrate includes a data line, a scan line, a pixel electrode, and two active switching elements connected in series, wherein the scan line is disposed opposite to the data line
- the pixel electrode is disposed at an intersection of the scan line and the data line, and the pixel electrode is provided with at least one slit, and a length direction of the slit is inclined with respect to a vertical direction of the scan line.
- the two active switching elements connected in series are connected to the scan line, the data line and the pixel electrode to form a switch circuit; a color filter substrate, the color filter substrate is opposite to the array substrate and a plurality of liquid crystal molecules, the plurality of liquid crystal molecules being located between the array substrate and the color filter substrate; and a sealant, the sealant being located on the array substrate and the color filter An accommodating space is formed between the substrates and the array substrate and the color filter substrate to accommodate the plurality of liquid crystal molecules.
- an angle at which the longitudinal direction of the slit is inclined with respect to a vertical direction of the scanning line ranges from 2° to 8°.
- a line width of the scan line is greater than a line width of the data line.
- the number of the slits is plural and disposed in parallel with each other, and the plurality of slits are hollow structures closed at both ends of the pixel electrode or hollowed out at one end and open at the other end structure.
- the two active switching elements include a first active switching element and a second active switching element, and a first electrode end of the first active switching element is connected to the data line a second electrode end of the first active switching element is connected from a side of the data line across the data line to a first electrode end of the second active switching element, the second A second electrode end of the source switching element is coupled to the pixel electrode, and a control electrode end of the first active switching element and a control electrode end of the second active switching element are coupled to the scan line.
- the pixel electrode is an ITO transparent electrode.
- the two active switching elements include a first active switching element and a second active switching element, a first electrode end and a second of the first active switching element a second electrode end of the active switching element is located at one side of the scan line, and a second electrode end of the first active switching element and a first electrode end of the second active switching element are located on the scan line On the other side, the control electrode terminal of the first active switching element and the control electrode terminal of the second active switching element are connected to the scan line.
- the color filter substrate includes a plurality of color filters, and the plurality of color filters include a red filter, a green filter, and a blue filter.
- the display panel is an in-plane switching mode liquid crystal display panel or a fringe field switching mode liquid crystal display panel;
- the array substrate further includes: a common electrode layer; the common electrode layer and the pixel The electrodes are disposed in the same layer, or the common electrode layer is laminated with the pixel electrodes and spaced apart by an insulating layer.
- connection between the pixel electrode and the data line and the scan line is realized by two active switching elements connected in series, which can reduce the leakage current of the pixel structure and maintain the pixel electrode Voltage. Furthermore, by opening one or more slits inclined in the vertical direction with respect to the scanning line on the pixel electrode, it is possible to preset a certain inclination angle for the arrangement of the liquid crystal molecules, thereby significantly increasing the viewing angle of the display panel. .
- the common electrode disposed on the array substrate it can realize an in-plane switching mode liquid crystal display panel or a fringe field switching mode liquid crystal display panel.
- FIG. 1 is a schematic diagram of a layout of a pixel structure in an embodiment of the present disclosure.
- FIG. 2 is a schematic view showing the layout of an array substrate in still another embodiment of the present disclosure.
- FIG. 3 is a schematic structural diagram of an in-plane switching mode liquid crystal display panel according to another embodiment of the present disclosure.
- FIG. 4 is a schematic structural diagram of a fringe field switching mode liquid crystal display panel according to still another embodiment of the present disclosure.
- a pixel structure 110 provided in one embodiment of the present disclosure includes: adjacently disposed scan lines GL1 and scan lines GL2, adjacently disposed data lines DL1 and data lines DL2, and switching elements T1 ( A first active switching element), a switching element T2 (second active switching element), and a pixel electrode PE.
- the scan lines GL1 and GL2 are arranged to intersect with the data lines DL1 and DL2 to form a pixel area PA (shown by a broken line in FIG. 1), and the pixel electrode PE is located in the pixel area PA and connected to the scan line GL1 through the switching elements T1 and T2. And data line DL1.
- the pixel area PA is located at the intersection of the scanning line GL1 and the data line DL1 to which the pixel electrode PE is connected by the switching elements T1 and T2, so that the scanning line GL2 and the data line DL2 may not be used to some extent.
- a constituent part of the pixel structure 110 Furthermore, it can be seen from FIG.
- the scan line GL1 and the scan line GL2 are arranged substantially in parallel, and the data lines DL1 and DL2 are also arranged substantially in parallel, so that the scan line GL1, the scan line GL2, the data line DL1 and the data line DL2 are collectively arranged. It becomes a substantially quadrilateral pixel area PA.
- the source S1 of the switching element T1 is connected to the data line DL1
- the gate G1 of the switching element T1 is connected to the scanning line GL1
- the drain D1 of the switching element T1 is connected to the source S2 of the switching element T2
- the gate G2 of the switching element T2 The scan line GL1 is connected, and the drain D2 of the switching element T2 is connected to the pixel electrode PE.
- the switching element T1 and the switching element T2 are connected in series between the data line DL1 and the pixel electrode PE and the gates G1, G2 of both are connected to the same scanning line GL1; this embodiment passes the switching element T1 and The switching element T2 is connected in series to form a switching circuit, which can reduce the leakage current of the pixel structure 110 and maintain the voltage on the pixel electrode PE. Furthermore, it can be seen from the layout structure of the pixel structure 110 of FIG. 1 that the drain D1 of the switching element T1 extends from one side of the data line DL1 across the data line DL1 and is connected to the source S2 of the switching element T2.
- the source S1 of the switching element T1 and the drain D2 of the switching element T2 are located on the same side of the scanning line GL1 (for example, the upper side of the scanning line GL1 in FIG. 1), and the drain D1 of the switching element T1 and the switching element T2
- the source S2 is located on the other opposite side of the scan line GL1 (for example, the lower side of the scan line GL1 in FIG. 1), so that the overall layout structure of the switching element T1 and the switching element T2 is substantially U-shaped, and the layout manner can be greatly Increase the pixel aperture ratio.
- the switching elements T1, T2 may be NMOS transistors or PMOS transistors; of course, the switching elements T1, T2 may also be other three-terminal active switching elements, such as one of the source and the drain They may be collectively referred to as a first electrode terminal and the other as a second electrode terminal, and the gates are collectively referred to as a control electrode terminal.
- the source S1 of the switching element T1, the drain D2 of the switching element T2, the drain D1 of the switching element T1, and the source S2 of the switching element T2 may also be located on the same side of the scanning line GL1.
- the pixel electrode PE is provided with at least one slit ST extending from the scanning line GL1 toward the scanning line GL2, for example, two parallel narrow lines as shown in FIG.
- the slit ST has a length direction which is inclined with respect to the vertical direction of the scanning line GL1 (that is, the vertical direction in FIG. 1).
- the inclination angle ⁇ of the longitudinal direction of the slit ST relative to the vertical direction of the scanning line GL1 ranges from 2° to 8°, so that the liquid crystal molecules have a better pretilt angle, thereby achieving better display effect. Furthermore, it can be seen from FIG.
- each of the slits ST extends from the scanning line GL1 to the scanning line GL2 and penetrates through the pixel electrode PE, or in other words, the slit ST is hollowed out and closed at both ends.
- the pixel electrode PE is typically a transparent electrode such as an ITO (Indium Tin Oxide) electrode or the like.
- the pixel structure 110 realizes the connection between the pixel electrode PE and the data line DL1 and the scan line GL1 through the dual series switching element having a specific layout structure, which can reduce the leakage of the pixel structure 110.
- the current, the voltage on the pixel electrode PE, and the pixel aperture ratio are effectively increased.
- one or more slits ST extending from one of the adjacent two scanning lines, for example, GL1, GL2, to the other scanning line GL2 are opened on the pixel electrode PE, and the length of the slit ST is made.
- the direction is inclined with respect to the vertical direction of the scanning lines GL1/GL2, which can preset a certain inclination angle for the arrangement of the liquid crystal molecules, so that the viewing angle of the display device having the pixel structure 110 can be remarkably improved.
- an array substrate 10 provided in still another embodiment of the present disclosure includes: a transparent substrate 11, a plurality of scanning lines such as GL1, GL2, GL3, a plurality of data lines such as DL1, DL2, and a plurality of switches Elements such as T1 (first active switching element), T2 (second active switching element), T3 (first active switching element), T4 (second active switching element), and a plurality of pixel electrodes such as PE1, PE2 These scan lines GL1, GL2, GL3, these data lines DL1, DL2, these switching elements T1, T2, T3, T4 and these pixel electrodes PE1, PE2 are disposed on the transparent substrate 11.
- a transparent substrate 11 a plurality of scanning lines such as GL1, GL2, GL3, a plurality of data lines such as DL1, DL2, and a plurality of switches Elements such as T1 (first active switching element), T2 (second active switching element), T3 (first active switching element), T4 (second active switching element), and a plurality of pixel electrode
- the scan line GL1 and the scan line GL2 are disposed adjacent to each other, and the scan line GL2 is disposed adjacent to the scan line GL3, so that the scan line GL2 is located between the scan line GL1 and the scan line GL3.
- the data line DL1 and the data line DL2 are arranged adjacent to each other.
- the scanning lines GL1 and GL2 are disposed to intersect with the data lines DL1 and DL2 to form a pixel area PA1.
- the pixel electrode PE1 is disposed in the pixel area PA1 and is connected to the scanning line GL1 and the data line DL1 via the switching elements T1 and T2.
- the pixel area PA1 is located at the intersection of the scanning line GL1 and the data line DL1 to which the pixel electrode PE1 is connected by the switching elements T1 and T2. Furthermore, it can be seen from FIG.
- the scan line GL1 and the scan line GL2 are arranged substantially in parallel, and the data lines DL1 and DL2 are also arranged substantially in parallel, so that the scan line GL1, the scan line GL2, the data line DL1 and the data line DL2 are collectively arranged. It becomes a substantially quadrangular pixel area PA1.
- the source S1 of the switching element T1 is connected to the data line DL1
- the gate G1 of the switching element T1 is connected to the scanning line GL1
- the drain D1 of the switching element T1 is connected to the source S2 of the switching element T2
- the gate G2 of the switching element T2 The scan line GL1 is connected, and the drain D2 of the switching element T2 is connected to the pixel electrode PE1.
- the switching element T1 and the switching element T2 are connected in series between the data line DL1 and the pixel electrode PE1 and the gates G1, G2 of both are connected to the same scanning line GL1; this embodiment passes the switching element T1 and The switching element T2 is connected in series to form a switching circuit, which can reduce the leakage current of the pixel structure and maintain the voltage on the pixel electrode PE1. Furthermore, it can be seen from the layout structure shown in FIG. 2 that the drain D1 of the switching element T1 extends from one side of the data line DL1 across the data line DL1 and is connected to the source S2 of the switching element T2.
- the source S1 of the element T1 and the drain D2 of the switching element T2 are located on the same side of the scanning line GL1 (for example, the upper side of the scanning line GL1 in FIG. 2), and the drain D1 of the switching element T1 and the source of the switching element T2.
- S2 is located on the other opposite side of the scan line GL1 (for example, the lower side of the scan line GL1 in FIG. 2), so that the overall layout structure of the switching element T1 and the switching element T2 is substantially U-shaped, and the layout can be greatly improved. Pixel aperture ratio.
- the switching elements T1, T2 may be NMOS transistors or PMOS transistors; of course, the switching elements T1, T2 may also be other three-terminal active switching elements, such as one of the source and the drain They may be collectively referred to as a first electrode terminal and the other as a second electrode terminal, and the gates are collectively referred to as a control electrode terminal.
- the source S1 of the switching element T1, the drain D2 of the switching element T2, the drain D1 of the switching element T1, and the source S2 of the switching element T2 may also be located on the same side of the scanning line GL1.
- the pixel electrode PE1 is provided with at least one slit ST1 extending from the scanning line GL1 toward the scanning line GL2, for example, two parallel slits ST1 shown in FIG. 2, and the slit ST1
- the length direction is inclined with respect to the vertical direction of the scanning line GL2 (that is, the vertical direction in FIG. 2).
- the inclination angle ⁇ of the longitudinal direction of the slit ST1 with respect to the vertical direction of the scanning line GL2 ranges from 2° to 8°, so that the liquid crystal molecules have a better pretilt angle, thereby achieving better display effect. Furthermore, it can be seen from FIG.
- each of the slits ST1 extends from the scanning line GL1 to the scanning line GL2 and penetrates through the pixel electrode PE1, or in other words, the slit ST1 is hollowed out and closed at both ends.
- the pixel electrode PE1 is typically a transparent electrode such as an ITO electrode or the like.
- the scanning lines GL2 and GL3 are arranged to intersect with the data lines DL1 and DL2 to form a pixel area PA2 adjacent to the pixel area PA1.
- the pixel electrode PE2 is disposed in the pixel area PA2 and is connected to the scanning line GL2 and the data line DL1 through the switching elements T3, T4.
- the pixel area PA2 is located at the intersection of the scanning line GL2 and the data line DL1 to which the pixel electrode PE2 is connected by the switching elements T3 and T3. Furthermore, it can be seen from FIG.
- the source of the switching element T3 is connected to the data line DL1
- the gate of the switching element T3 is connected to the scanning line GL2
- the drain of the switching element T3 is connected to the source of the switching element T4
- the gate of the switching element T4 is connected to the scanning line GL2.
- the drain of the switching element T4 is connected to the pixel electrode PE2.
- the switching element T3 and the switching element T4 are connected in series between the data line DL1 and the pixel electrode PE2 and the gates of both are connected to the same scanning line GL2; this embodiment passes the switching element T3 and the switching element T4.
- the series connection can reduce the leakage current of the pixel structure and maintain the voltage on the pixel electrode PE2.
- the drain of the switching element T3 extends from one side of the data line DL1 across the data line DL1 and is connected to the source of the switching element T4, and the switching element T3
- the drain of the source and switching element T4 is located on the same side of the scan line GL2 (for example, the upper side of the scan line GL2 in FIG. 2), and the drain of the switching element T3 and the source of the switching element T4 are both located on the scan line GL2.
- the other opposite side for example, the lower side of the scanning line GL2 in FIG. 2), so that the overall layout structure of the switching element T3 and the switching element T3 is substantially U-shaped, this layout can greatly increase the pixel aperture ratio.
- the switching elements T3, T4 may be NMOS transistors or PMOS transistors; of course, the switching elements T3, T4 may also be other three-terminal active switching elements, such as one of the source and the drain. They may be collectively referred to as a first electrode terminal and the other as a second electrode terminal, and the gates are collectively referred to as a control electrode terminal.
- the source of the switching element T3, the drain of the switching element T4, the drain of the switching element T3, and the source of the switching element T4 may also be located on the same side of the scanning line GL2.
- the pixel electrode PE2 is provided with at least one slit ST2 extending from the scanning line GL2 toward the scanning line GL3, for example, two parallel slits ST2 shown in FIG. 2, and the slit ST2
- the length direction is inclined with respect to the vertical direction of the scanning line GL2 (that is, the vertical direction in FIG. 2).
- the inclination angle ⁇ of the longitudinal direction of the slit ST2 with respect to the vertical direction of the scanning line GL2 ranges from 2° to 8°, so that the liquid crystal molecules have a better pretilt angle, thereby achieving better display effect. Furthermore, it can be seen from FIG.
- each of the slits ST2 extends from the scanning line GL2 to the scanning line GL3 and penetrates through the pixel electrode PE2, or in other words, the slit ST2 has a hollow structure and is closed at both ends. Of course, it can also be a hollow structure with one end closed and the other end open.
- the pixel electrode PE2 is typically a transparent electrode such as an ITO electrode or the like.
- the slit ST1 is closer to the data line DL1 than the other end of the scanning line GL1 adjacent to the scanning line GL2, and the slit One end of the ST2 adjacent to the scanning line GL2 is closer to the data line DL1 with respect to the other end thereof adjacent to the scanning line GL3; in short, the slit ST1 and the slit ST2 in the adjacent two rows of pixel electrodes PE1, PE2 are inclined in opposite directions Settings.
- an IPS (In Plane Switching) mode liquid crystal display panel includes: an array substrate 20, a color filter substrate 30, a sealant 40, and a plurality of liquid crystal molecules. 50.
- the array substrate 20 and the color filter substrate 30 are opposite and spaced apart, and the sealant 40 is disposed between the array substrate 20 and the color filter substrate 30 to form an accommodation space together with the array substrate 20 and the color filter substrate 30.
- the display medium molecules such as these liquid crystal molecules 50 are accommodated.
- the array substrate 20 includes a transparent substrate 21, a pixel electrode PE, and a common electrode layer CE; the pixel electrode PE and the common electrode layer CE are disposed on the transparent substrate 21 in the same layer, thereby applying an appropriate voltage to the pixel electrode PE and the common electrode layer CE.
- a planar electric field (or transverse electric field) may be formed between the two to deflect the liquid crystal molecules 50. It is worth mentioning here that the structure of the array substrate 20 other than the common electrode layer CE can adopt the structure shown in FIG. 2, and details are not described herein again.
- a plurality of color filters such as a red color filter R, a green color filter G, and a blue color filter B are disposed on the color filter substrate 30.
- an FFS (Fringe Field Switching) mode liquid crystal display panel provided by another embodiment of the present disclosure includes: an array substrate 60, a color filter substrate 70, a sealant 80, and a plurality of liquid crystal molecules. 90.
- the array substrate 60 and the color filter substrate 70 are opposite and spaced apart, and the sealant 80 is disposed between the array substrate 60 and the color filter substrate 70 to form an accommodating space together with the array substrate 60 and the color filter substrate 70.
- These liquid crystal molecules 90 are accommodated.
- the array substrate 60 includes a transparent substrate 61 and a common electrode layer CE, an insulating layer 63, and a pixel electrode PE disposed on the transparent substrate 61.
- the pixel electrode PE and the common electrode layer CE are spaced apart by the insulating layer 63, so that the common electrode layer
- the CE is located between the transparent substrate 61 and the pixel electrode PE.
- a fringe electric field may be formed between the two when the appropriate voltage is applied to the pixel electrode PE and the common electrode layer CE to deflect the liquid crystal molecules 90.
- the structure of the array substrate 60 other than the common electrode layer CE can adopt the structure shown in FIG. 2, and details are not described herein again.
- a plurality of color filters such as a red color filter R, a green color filter G, and a blue color filter B are disposed on the color filter substrate 70.
- the disclosed systems, devices, and/or methods may be implemented in other ways.
- the device embodiments described above are merely illustrative.
- the division of the unit is only a logical function division.
- there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
- the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
- the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
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Abstract
一种阵列基板(10)以及采用所述阵列基板(10)的显示面板,所述阵列基板(10)包括数据线(DL1、DL2)、扫描线(GL1、GL2、GL3)、像素电极(PE)和串联的两个有源开关元件(T1、T2),所述扫描线(GL1、GL2、GL3)与所述数据线(DL1、DL2)交叉设置,所述像素电极(PE)设置在所述扫描线(GL1、GL2、GL3)与所述数据线(DL1、DL2)的交叉处,所述像素电极(PE)开设有至少一条狭缝(ST),所述狭缝(ST)的长度方向相对于所述扫描线(GL1、GL2、GL3)的垂直方向倾斜,所述串联的两个有源开关元件(T1、T2)与所述扫描线(GL1、GL2、GL3)、所述数据线(DL1、DL2)及所述像素电极相连接形成开关电路。
Description
本公开涉及显示技术领域,尤其涉及一种阵列基板以及一种显示面板。
液晶显示器具有高画质、体积小、重量轻、低电压驱动、低消耗功率及应用范围广等优点,因此已被广泛地应用于中、小型可携式电视、行动电话、摄录放影机、笔记型电脑、桌上型显示器以及投影电视等消费性电子或电脑产品,并且逐渐取代阴极射线管(Cathode Ray Tube,CRT)显示器而成为主流。然而,如何提升液晶显示器的像素开口率、减小漏电流,进而实现较佳显示品质一直以来都是重要研究课题之一。
发明内容
本公开的实施例提供一种阵列基板以及一种显示面板,以实现减小漏电流进而实现较佳显示品质的技术效果。
一方面,提供了一种阵列基板,包括:数据线;扫描线,所述扫描线与所述数据线交叉设置;像素电极,所述像素电极设置在所述扫描线与所述数据线的交叉处,所述像素电极开设有至少一条狭缝,所述狭缝的长度方向相对于所述扫描线的垂直方向倾斜;串联的两个有源开关元件,所述串联的两个有源开关元件与所述扫描线、所述数据线及所述像素电极相连接形成开关电路;以及公共电极层,与所述像素电极同层设置,或者与所 述像素电极层叠设置并间隔有绝缘层;其中,所述狭缝的数量为多个且相互平行设置,所述多个狭缝为所述像素电极上两端封闭的镂空结构或者一端封闭而另一端开口的镂空结构。
再一方面,提供了一种阵列基板,包括:数据线;扫描线,所述扫描线与所述数据线交叉设置;像素电极,所述像素电极设置在所述扫描线与所述数据线的交叉处,所述像素电极开设有至少一条狭缝,所述狭缝的长度方向相对于所述扫描线的垂直方向倾斜;以及串联的两个有源开关元件,所述串联的两个有源开关元件与所述扫描线、所述数据线及所述像素电极相连接形成开关电路。
在本公开的一个实施例中,所述狭缝的长度方向相对于所述扫描线的垂直方向倾斜的角度的取值范围为2°~8°。
在本公开的一个实施例中,所述扫描线的线宽大于所述数据线的线宽。
在本公开的一个实施例中,所述狭缝的数量为多个且相互平行设置,所述多个狭缝为所述像素电极上两端封闭的镂空结构或者一端封闭而另一端开口的镂空结构。
在本公开的一个实施例中,所述阵列基板还包括:公共电极层,与所述像素电极同层设置。
在本公开的一个实施例中,所述阵列基板还包括:公共电极层,与所述像素电极层叠设置并间隔有绝缘层。
在本公开的一个实施例中,所述两个有源开关元件包括第一有源开关元件和第二有源开关元件,所述第一有源开关元件的第一电极端连接所述 数据线,所述第一有源开关元件的第二电极端自所述数据线的一侧延伸跨越所述数据线后与所述第二有源开关元件的第一电极端相连,所述第二有源开关元件的第二电极端连接所述像素电极,所述第一有源开关元件的控制电极端和所述第二有源开关元件的控制电极端连接所述扫描线。
在本公开的一个实施例中,所述像素电极为ITO透明电极。
在本公开的一个实施例中,所述两个有源开关元件包括第一有源开关元件和第二有源开关元件,所述第一有源开关元件的第一电极端和所述第二有源开关元件的第二电极端位于所述扫描线的一侧,所述第一有源开关元件的第二电极端和所述第二有源开关元件的第一电极端位于所述扫描线的另一侧,所述第一有源开关元件的控制电极端和所述第二有源开关元件的控制电极端连接所述扫描线。
另一方面,提供了一种显示面板,包括:阵列基板,所述阵列基板包括数据线、扫描线、像素电极和串联的两个有源开关元件,所述扫描线与所述数据线交叉设置,所述像素电极设置在所述扫描线与所述数据线的交叉处,所述像素电极开设有至少一条狭缝,所述狭缝的长度方向相对于所述扫描线的垂直方向倾斜,所述串联的两个有源开关元件与所述扫描线、所述数据线及所述像素电极相连接形成开关电路;彩色滤光片基板,所述彩色滤光片基板与所述阵列基板相对且间隔设置;多个液晶分子,所述多个液晶分子位于所述阵列基板与所述彩色滤光片基板之间;以及框胶,所述框胶位于所述阵列基板与所述彩色滤光片基板之间与所述阵列基板及所述彩色滤光片基板共同形成容置空间以容纳所述多个液晶分子。
在本公开的一个实施例中,所述狭缝的长度方向相对于所述扫描线的垂直方向倾斜的角度的取值范围为2°~8°。
在本公开的一个实施例中,所述扫描线的线宽大于所述数据线的线宽。
在本公开的一个实施例中,所述狭缝的数量为多个且相互平行设置,所述多个狭缝为所述像素电极上两端封闭的镂空结构或者一端封闭而另一端开口的镂空结构。
在本公开的一个实施例中,所述两个有源开关元件包括第一有源开关元件和第二有源开关元件,所述第一有源开关元件的第一电极端连接所述数据线,所述第一有源开关元件的第二电极端自所述数据线的一侧延伸跨越所述数据线后与所述第二有源开关元件的第一电极端相连,所述第二有源开关元件的第二电极端连接所述像素电极,所述第一有源开关元件的控制电极端和所述第二有源开关元件的控制电极端连接所述扫描线。
在本公开的一个实施例中,所述像素电极为ITO透明电极。
在本公开的一个实施例中,所述两个有源开关元件包括第一有源开关元件和第二有源开关元件,所述第一有源开关元件的第一电极端和所述第二有源开关元件的第二电极端位于所述扫描线的一侧,所述第一有源开关元件的第二电极端和所述第二有源开关元件的第一电极端位于所述扫描线的另一侧,所述第一有源开关元件的控制电极端和所述第二有源开关元件的控制电极端连接所述扫描线。
在本公开的一个实施例中,所述彩色滤光片基板包括多个彩色滤光片,且所述多个彩色滤光片包括红色滤光片、绿色滤光片和蓝色滤光片。
在本公开的一个实施例中,所述显示面板为平面内切换模式液晶显示面板或边缘场切换模式液晶显示面板;所述阵列基板还包括:公共电极层;所述公共电极层与所述像素电极同层设置,或者所述公共电极层与所述像素电极层叠设置并间隔有绝缘层。
上述技术方案中的一个技术方案具有如下优点:通过串联的两个有源开关元件来实现像素电极和数据线及扫描线之间的连接,其能够减小像素结构的漏电流、保持像素电极上的电压。再者,通过在像素电极上开设一条或多条相对于扫描线的垂直方向倾斜的狭缝,其可以为液晶分子的排布预置一定的倾斜角度,从而能够显著提高显示面板的可视角度。另外,搭配阵列基板上设置的公共电极,其可以实现平面内切换模式液晶显示面板或边缘场切换模式液晶显示面板。
为了更清楚地说明本公开实施例的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本公开的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本公开一个实施例中的一种像素结构的布局示意图。
图2为本公开再一个实施例中的一种阵列基板的布局示意图。
图3为本公开另一个实施例中的一种平面内切换模式液晶显示面板的结构示意图。
图4为本公开又一个实施例中的一种边缘场切换模式液晶显示面板的 结构示意图。
下面将结合本公开实施例中的附图,对本公开实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本公开一部分实施例,而不是全部的实施例。基于本公开中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本公开保护的范围。
如图1所示,本公开一个实施例中提供的一种像素结构110,包括:相邻设置的扫描线GL1和扫描线GL2、相邻设置的数据线DL1和数据线DL2、开关元件T1(第一有源开关元件)、开关元件T2(第二有源开关元件)以及像素电极PE。
扫描线GL1及GL2与数据线DL1及DL2交叉设置共同围成一个像素区域PA(如图1中虚线框所示),像素电极PE位于像素区域PA内并通过开关元件T1及T2连接扫描线GL1和数据线DL1。换而言之,像素区域PA是位于像素电极PE通过开关元件T1及T2所连接的扫描线GL1和数据线DL1的交叉处,因此某种程度上也可以不将扫描线GL2和数据线DL2作为像素结构110的构成部分。再者,从图1中可以得知:扫描线GL1和扫描线GL2大致平行设置,数据线DL1和DL2也是大致平行设置,从而扫描线GL1、扫描线GL2、数据线DL1和数据线DL2共同围成了一个大致呈四边形的像素区域PA。
承上述,开关元件T1的源极S1连接数据线DL1,开关元件T1的栅 极G1连接扫描线GL1,开关元件T1的漏极D1连接开关元件T2的源极S2,开关元件T2的栅极G2连接扫描线GL1,以及开关元件T2的漏极D2连接像素电极PE。换而言之,开关元件T1和开关元件T2串联连接在数据线DL1和像素电极PE之间并且两者的栅极G1、G2连接至同一条扫描线GL1;本实施例通过将开关元件T1和开关元件T2串联形成开关电路,既能够减小像素结构110的漏电流,又能够保持像素电极PE上的电压。再者,从图1的像素结构110的布局(Layout)结构还可以得知:开关元件T1的漏极D1自数据线DL1的一侧延伸跨越数据线DL1后与开关元件T2的源极S2相连,开关元件T1的源极S1和开关元件T2的漏极D2位于扫描线GL1的同一侧(例如图1中的扫描线GL1的上侧),而开关元件T1的漏极D1和开关元件T2的源极S2均位于扫描线GL1的另一相对侧(例如图1中的扫描线GL1的下侧),从而使得开关元件T1和开关元件T2整体布局结构大致呈U型,该种布局方式可以大大提升像素开口率。此外,值得一提的是,开关元件T1、T2可以是NMOS晶体管,也可以是PMOS晶体管;当然,开关元件T1、T2也可以为其他三端有源开关元件,从而源极和漏极之一者可以统称为第一电极端且另一者统称为第二电极端,以及栅极统称为控制电极端。另外,在其他实施例中,开关元件T1的源极S1、开关元件T2的漏极D2、开关元件T1的漏极D1和开关元件T2的源极S2也可以均位于扫描线GL1的同一侧。
此外,为提供液晶分子一定的预倾角以达到增大视角的效果,像素电极PE上设有从扫描线GL1向扫描线GL2延伸的至少一条狭隙ST例如图 1所示的两条平行的狭缝ST,狭隙ST的长度方向相对于扫描线GL1的垂直方向(也即图1中的竖直方向)倾斜。可选地,狭缝ST的长度方向相对于扫描线GL1的垂直方向的倾斜夹角α的取值范围为2°~8°,以使得液晶分子具有较佳的预倾角,进而达成较佳的显示效果。再者,从图1中还可以得知:每一条狭隙ST是从扫描线GL1向扫描线GL2延伸并贯穿像素电极PE,或换而言之,狭缝ST为镂空结构且两端封闭,当然也可以是一端封闭而另一端开口的镂空结构。另外,像素电极PE典型地为透明电极例如ITO(Indium Tin Oxide,铟锡氧化物)电极等。
综上所述,本实施例提供的像素结构110通过具有特定布局结构的双串联开关元件来实现像素电极PE和数据线DL1及扫描线GL1之间的连接,其能够减小像素结构110的漏电流、保持像素电极PE上的电压以及有效提升像素开口率。再者,通过在像素电极PE上开设一条或多条从相邻两条扫描线例如GL1、GL2中的一条扫描线GL1向另一条扫描线GL2延伸的狭隙ST,且使狭隙ST的长度方向相对于扫描线GL1/GL2的垂直方向倾斜,其可以为液晶分子的排布预置一定的倾斜角度,从而能够显著提高具有像素结构110的显示设备的可视角度。
如图2所示,本公开再一个实施例中提供的一种阵列基板10,包括:透明基底11,多条扫描线例如GL1、GL2、GL3,多条数据线例如DL1、DL2,多个开关元件例如T1(第一有源开关元件)、T2(第二有源开关元件)、T3(第一有源开关元件)、T4(第二有源开关元件)和多个像素电极例如PE1、PE2;这些扫描线GL1、GL2、GL3,这些数据线DL1、DL2,这些开关元 件T1、T2、T3、T4和这些像素电极PE1、PE2设置在所述透明基底11上。扫描线GL1和扫描线GL2相邻设置,扫描线GL2又和扫描线GL3相邻设置,从而扫描线GL2位于扫描线GL1和扫描线GL3之间。数据线DL1和数据线DL2相邻设置。
扫描线GL1及GL2与数据线DL1及DL2交叉设置共同围成一个像素区域PA1,像素电极PE1设置在像素区域PA1内且通过开关元件T1、T2连接扫描线GL1和数据线DL1。换而言之,像素区域PA1是位于像素电极PE1通过开关元件T1及T2所连接的扫描线GL1和数据线DL1的交叉处。再者,从图2中可以得知:扫描线GL1和扫描线GL2大致平行设置,数据线DL1和DL2也是大致平行设置,从而扫描线GL1、扫描线GL2、数据线DL1和数据线DL2共同围成了一个大致呈四边形的像素区域PA1。
承上述,开关元件T1的源极S1连接数据线DL1,开关元件T1的栅极G1连接扫描线GL1,开关元件T1的漏极D1连接开关元件T2的源极S2,开关元件T2的栅极G2连接扫描线GL1,以及开关元件T2的漏极D2连接像素电极PE1。换而言之,开关元件T1和开关元件T2串联连接在数据线DL1和像素电极PE1之间并且两者的栅极G1、G2连接至同一条扫描线GL1;本实施例通过将开关元件T1和开关元件T2串联形成开关电路,既能够减小像素结构的漏电流,又能够保持像素电极PE1上的电压。再者,从图2所示的布局(Layout)结构还可以得知:开关元件T1的漏极D1自数据线DL1的一侧延伸跨越数据线DL1后与开关元件T2的源极S2相连,开关元件T1的源极S1和开关元件T2的漏极D2位于扫描线GL1 的同一侧(例如图2中的扫描线GL1的上侧),而开关元件T1的漏极D1和开关元件T2的源极S2均位于扫描线GL1的另一相对侧(例如图2中的扫描线GL1的下侧),从而使得开关元件T1和开关元件T2的整体布局结构大致呈U型,该种布局方式可以大大提升像素开口率。此外,值得一提的是,开关元件T1、T2可以是NMOS晶体管,也可以是PMOS晶体管;当然,开关元件T1、T2也可以为其他三端有源开关元件,从而源极和漏极之一者可以统称为第一电极端且另一者统称为第二电极端,以及栅极统称为控制电极端。另外,在其他实施例中,开关元件T1的源极S1、开关元件T2的漏极D2、开关元件T1的漏极D1和开关元件T2的源极S2也可以均位于扫描线GL1的同一侧。
此外,为提供液晶分子一定的预倾角,像素电极PE1上设有从扫描线GL1向扫描线GL2延伸的至少一条狭隙ST1例如图2所示的两条平行的狭缝ST1,狭隙ST1的长度方向相对于扫描线GL2的垂直方向(也即图2中的竖直方向)倾斜。可选地,狭缝ST1的长度方向相对于扫描线GL2的垂直方向的倾斜夹角α的取值范围为2°~8°,以使得液晶分子具有较佳的预倾角,进而达成较佳的显示效果。再者,从图2中还可以得知:每一条狭隙ST1是从扫描线GL1向扫描线GL2延伸并贯穿像素电极PE1,或换而言之,狭缝ST1为镂空结构且两端封闭,当然也可以是一端封闭而另一端开口的镂空结构。另外,像素电极PE1典型地为透明电极例如ITO电极等。
类似地,扫描线GL2及GL3与数据线DL1及DL2交叉设置共同围成 一个像素区域PA2,像素区域PA2与像素区域PA1相邻。像素电极PE2设置在像素区域PA2内且通过开关元件T3、T4连接扫描线GL2和数据线DL1。换而言之,像素区域PA2是位于像素电极PE2通过开关元件T3及T3所连接的扫描线GL2和数据线DL1的交叉处。再者,从图2中可以得知:扫描线GL2和扫描线GL3大致平行设置,数据线DL1和DL2也是大致平行设置,从而扫描线GL2、扫描线GL3、数据线DL1和数据线DL2共同围成了一个大致呈四边形的像素区域PA2。
承上述,开关元件T3的源极连接数据线DL1,开关元件T3的栅极连接扫描线GL2,开关元件T3的漏极连接开关元件T4的源极,开关元件T4的栅极连接扫描线GL2,以及开关元件T4的漏极连接像素电极PE2。换而言之,开关元件T3和开关元件T4串联连接在数据线DL1和像素电极PE2之间并且两者的栅极连接至同一条扫描线GL2;本实施例通过将开关元件T3和开关元件T4串联,既能够减小像素结构的漏电流,又能够保持像素电极PE2上的电压。再者,从图2所示的布局(Layout)结构还可以得知:开关元件T3的漏极自数据线DL1的一侧延伸跨越数据线DL1后与开关元件T4的源极相连,开关元件T3的源极和开关元件T4的漏极位于扫描线GL2的同一侧(例如图2中的扫描线GL2的上侧),而开关元件T3的漏极和开关元件T4的源极均位于扫描线GL2的另一相对侧(例如图2中的扫描线GL2的下侧),从而使得开关元件T3和开关元件T3的整体布局结构大致呈U型,该种布局方式可以大大提升像素开口率。此外,值得一提的是,开关元件T3、T4可以是NMOS晶体管,也可以是PMOS晶体管; 当然,开关元件T3、T4也可以为其他三端有源开关元件,从而源极和漏极之一者可以统称为第一电极端且另一者统称为第二电极端,以及栅极统称为控制电极端。另外,在其他实施例中,开关元件T3的源极、开关元件T4的漏极、开关元件T3的漏极和开关元件T4的源极也可以均位于扫描线GL2的同一侧。
此外,为提供液晶分子一定的预倾角,像素电极PE2上设有从扫描线GL2向扫描线GL3延伸的至少一条狭隙ST2例如图2所示的两条平行的狭缝ST2,狭隙ST2的长度方向相对于扫描线GL2的垂直方向(也即图2中的竖直方向)倾斜。可选地,狭缝ST2的长度方向相对于扫描线GL2的垂直方向的倾斜夹角β的取值范围为2°~8°,以使得液晶分子具有较佳的预倾角,进而达成较佳的显示效果。再者,从图2中还可以得知:每一条狭隙ST2是从扫描线GL2向扫描线GL3延伸并贯穿像素电极PE2,或换而言之,狭缝ST2为镂空结构且两端封闭,当然也可以是一端封闭而另一端开口的镂空结构。另外,像素电极PE2典型地为透明电极例如ITO电极等。
此外,比较图2中的狭缝ST1和狭缝ST2的倾斜方向,还可以得知:狭缝ST1邻近扫描线GL2的一端相对于其邻近扫描线GL1的另一端更靠近数据线DL1,狭缝ST2邻近扫描线GL2的一端相对于其邻近扫描线GL3的另一端更靠近数据线DL1;简而言之,相邻两行像素电极PE1、PE2中的狭缝ST1与狭缝ST2沿相反方向倾斜设置。
另外,在图2中,因为扫描线GL1、GL2是直接跨越相对应的开关元 件T1、T2、T3及T4的栅极,因此可选为设置宽度W1较大的扫描线,其大于数据线的线宽W2。
参见图3,本公开另一个实施例提供的一种IPS(In Plane Switching,平面内切换)模式液晶显示面板,包括:阵列基板20、彩色滤光片基板30、框胶40和多个液晶分子50。阵列基板20和彩色滤光片基板30相对且间隔设置,框胶40位于阵列基板20和彩色滤光片基板30之间以与阵列基板20及彩色滤光片基板30共同形成一个容置空间以容纳这些液晶分子50等显示介质分子。
承上述,阵列基板20包括透明基底21、像素电极PE以及公共电极层CE;像素电极PE和公共电极层CE同层设置在透明基底21上,从而施加适当电压于像素电极PE和公共电极层CE上时可以在两者之间形成平面电场(或称横向电场)以使液晶分子50偏转。此处值得一提的是,阵列基板20除公共电极层CE之外的结构可以采用图2所示结构,具体细节不再赘述。彩色滤光片基板30上设置有多个彩色滤光片例如红色滤光片R、绿色滤光片G和蓝色滤光片B。
参见图4,本公开又一个实施例提供的一种FFS(Fringe Field Switching,边缘场切换)模式液晶显示面板,包括:阵列基板60、彩色滤光片基板70、框胶80和多个液晶分子90。阵列基板60和彩色滤光片基板70相对且间隔设置,框胶80位于阵列基板60和彩色滤光片基板70之间以与阵列基板60及彩色滤光片基板70共同形成一个容置空间以容纳这些液晶分子90。
承上述,阵列基板60包括透明基底61和设置在透明基底61上的公共电极层CE、绝缘层63以及像素电极PE;像素电极PE和公共电极层CE通过绝缘层63间隔设置,从而公共电极层CE位于透明基底61和像素电极PE之间。当施加适当电压于像素电极PE和公共电极层CE上时可以在两者之间形成边缘电场以使液晶分子90偏转。此处值得一提的是,阵列基板60除公共电极层CE之外的结构可以采用图2所示结构,具体细节不再赘述。彩色滤光片基板70上设置有多个彩色滤光片例如红色滤光片R、绿色滤光片G和蓝色滤光片B。
在本申请所提供的几个实施例中,应该理解到,所揭露的***,装置和/或方法,可以通过其它的方式实现。例如,以上所描述的装置实施例仅仅是示意性的,例如,所述单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,例如多路单元或组件可以结合或者可以集成到另一个***,或一些特征可以忽略,或不执行。另一点,所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口,装置或单元的间接耦合或通信连接,可以是电性,机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的,作为单元显示的部件可以是或者也可以不是物理单元,即可以位于一个地方,或者也可以分布到多路网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
最后应说明的是:以上实施例仅用以说明本公开的技术方案,而非 对其限制;尽管参照前述实施例对本公开进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。
Claims (20)
- 一种阵列基板,包括:数据线;扫描线,所述扫描线与所述数据线交叉设置;像素电极,所述像素电极设置在所述扫描线与所述数据线的交叉处,所述像素电极开设有至少一条狭缝,所述狭缝的长度方向相对于所述扫描线的垂直方向倾斜;串联的两个有源开关元件,所述串联的两个有源开关元件与所述扫描线、所述数据线及所述像素电极相连接形成开关电路;以及公共电极层,与所述像素电极同层设置,或者与所述像素电极层叠设置并间隔有绝缘层;其中,所述狭缝的数量为多个且相互平行设置,所述多个狭缝为所述像素电极上两端封闭的镂空结构或者一端封闭而另一端开口的镂空结构。
- 一种阵列基板,包括:数据线;扫描线,所述扫描线与所述数据线交叉设置;像素电极,所述像素电极设置在所述扫描线与所述数据线的交叉处,所述像素电极开设有至少一条狭缝,所述狭缝的长度方向相对于所述扫描线的垂直方向倾斜;以及串联的两个有源开关元件,所述串联的两个有源开关元件与所述扫描线、所述数据线及所述像素电极相连接形成开关电路。
- 根据权利要求2所述的阵列基板,其中,所述狭缝的长度方向相对于所述扫描线的垂直方向倾斜的角度的取值范围为2°~8°。
- 根据权利要求2所述的阵列基板,其中,所述扫描线的线宽大于所述数据线的线宽。
- 根据权利要求2所述的阵列基板,其中,所述狭缝的数量为多个且相互平行设置,所述多个狭缝为所述像素电极上两端封闭的镂空结构或者一端封闭而另一端开口的镂空结构。
- 根据权利要求2所述的阵列基板,还包括:公共电极层,与所述像素电极同层设置。
- 根据权利要求2所述的阵列基板,还包括:公共电极层,与所述像素电极层叠设置并间隔有绝缘层。
- 根据权利要求2所述的阵列基板,其中,所述两个有源开关元件包括第一有源开关元件和第二有源开关元件,所述第一有源开关元件的第一电极端连接所述数据线,所述第一有源开关元件的第二电极端自所述数据线的一侧延伸跨越所述数据线后与所述第二有源开关元件的第一电极端相连,所述第二有源开关元件的第二电极端连接所述像素电极,所述第一有源开关元件的控制电极端和所述第二有源开关元件的控制电极端连接所述扫描线。
- 根据权利要求2所述的阵列基板,其中,所述像素电极为ITO透明电极。
- 根据权利要求2所述的阵列基板,其中,所述两个有源开关元件包 括第一有源开关元件和第二有源开关元件,所述第一有源开关元件的第一电极端和所述第二有源开关元件的第二电极端位于所述扫描线的一侧,所述第一有源开关元件的第二电极端和所述第二有源开关元件的第一电极端位于所述扫描线的另一侧,所述第一有源开关元件的控制电极端和所述第二有源开关元件的控制电极端连接所述扫描线。
- 一种显示面板,包括:阵列基板,所述阵列基板包括数据线、扫描线、像素电极和串联的两个有源开关元件,所述扫描线与所述数据线交叉设置,所述像素电极设置在所述扫描线与所述数据线的交叉处,所述像素电极开设有至少一条狭缝,所述狭缝的长度方向相对于所述扫描线的垂直方向倾斜,所述串联的两个有源开关元件与所述扫描线、所述数据线及所述像素电极相连接形成开关电路;彩色滤光片基板,所述彩色滤光片基板与所述阵列基板相对且间隔设置;多个液晶分子,所述多个液晶分子位于所述阵列基板与所述彩色滤光片基板之间;以及框胶,所述框胶位于所述阵列基板与所述彩色滤光片基板之间与所述阵列基板及所述彩色滤光片基板共同形成容置空间以容纳所述多个液晶分子。
- 根据权利要求11所述的显示面板,其中,所述狭缝的长度方向相对于所述扫描线的垂直方向倾斜的角度的取值范围为2°~8°。
- 根据权利要求11所述的显示面板,其中,所述扫描线的线宽大于所述数据线的线宽。
- 根据权利要求11所述的显示面板,其中,所述狭缝的数量为多个且相互平行设置,所述多个狭缝为所述像素电极上两端封闭的镂空结构或者一端封闭而另一端开口的镂空结构。
- 根据权利要求11所述的显示面板,其中,所述两个有源开关元件包括第一有源开关元件和第二有源开关元件,所述第一有源开关元件的第一电极端连接所述数据线,所述第一有源开关元件的第二电极端自所述数据线的一侧延伸跨越所述数据线后与所述第二有源开关元件的第一电极端相连,所述第二有源开关元件的第二电极端连接所述像素电极,所述第一有源开关元件的控制电极端和所述第二有源开关元件的控制电极端连接所述扫描线。
- 根据权利要求11所述的显示面板,其中,所述像素电极为ITO透明电极。
- 根据权利要求11所述的显示面板,其中,所述两个有源开关元件包括第一有源开关元件和第二有源开关元件,所述第一有源开关元件的第一电极端和所述第二有源开关元件的第二电极端位于所述扫描线的一侧,所述第一有源开关元件的第二电极端和所述第二有源开关元件的第一电极端位于所述扫描线的另一侧,所述第一有源开关元件的控制电极端和所述第二有源开关元件的控制电极端连接所述扫描线。
- 根据权利要求11所述的显示面板,其中,所述彩色滤光片基板包 括多个彩色滤光片,且所述多个彩色滤光片包括红色滤光片、绿色滤光片和蓝色滤光片。
- 根据权利要求11所述的显示面板,其中,所述显示面板为平面内切换模式液晶显示面板;所述阵列基板还包括:公共电极层,与所述像素电极同层设置。
- 根据权利要求11所述的显示面板,其中,所述显示面板为边缘场切换模式液晶显示面板;所述阵列基板还包括:公共电极层,与所述像素电极层叠设置并间隔有绝缘层。
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CN107436519A (zh) * | 2017-09-22 | 2017-12-05 | 惠科股份有限公司 | 阵列基板和显示面板 |
CN107450247A (zh) * | 2017-09-22 | 2017-12-08 | 惠科股份有限公司 | 像素结构和阵列基板 |
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