WO2019052435A1 - 像素驱动电路及方法、显示装置 - Google Patents

像素驱动电路及方法、显示装置 Download PDF

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Publication number
WO2019052435A1
WO2019052435A1 PCT/CN2018/104937 CN2018104937W WO2019052435A1 WO 2019052435 A1 WO2019052435 A1 WO 2019052435A1 CN 2018104937 W CN2018104937 W CN 2018104937W WO 2019052435 A1 WO2019052435 A1 WO 2019052435A1
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Prior art keywords
signal
switching element
node
scan signal
thin film
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PCT/CN2018/104937
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English (en)
French (fr)
Inventor
胡双
闵泰烨
张智
陈帅
钱谦
唐秀珠
田振国
赵敬鹏
董兴
唐滔良
熊丽军
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18852768.3A priority Critical patent/EP3693953A4/en
Priority to US16/332,449 priority patent/US11322082B2/en
Publication of WO2019052435A1 publication Critical patent/WO2019052435A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, a pixel driving method, and a display device.
  • OLED Organic Light Emitting Diode
  • PMOLED Passive Matrix Driving OLED
  • AMOLED Active Matrix Driving OLED
  • each illuminating pixel has an independent pixel driving circuit for supplying a driving current thereto.
  • the uniformity of OLED illumination in each pixel in the AMOLED display panel needs to be improved.
  • An object of the present disclosure is to provide a pixel driving circuit, a pixel driving method, and a display device, and at least to some extent overcome one or more problems due to limitations and disadvantages of the related art.
  • a pixel driving circuit comprising:
  • control end receives the first scan signal, the first end is connected to the first node, and the second end receives the data signal;
  • a second switching element the control end of which receives the second scan signal, the first end is connected to the second node, and the second end receives the data signal;
  • control end is connected to the second node, and the second end receives the first power signal
  • a driving transistor having a control end connected to the first node, a first end connected to the first pole of the electroluminescent element, and a second end receiving the first power signal;
  • a capacitor having a first end connected to the control end of the driving transistor and a second end connected to the first end of the driving transistor;
  • a third switching element the control end thereof receives a third scan signal, the first end is connected to the second pole of the electroluminescent element and receives the second power signal, and the second end is connected to the first end of the driving transistor; among them;
  • the conduction levels of the first compensation element and the second compensation element are opposite to the conduction levels of the first switching element, the second switching element, the driving transistor, and the third switching element .
  • the pixel driving circuit is connected to the Nth row and the N+1th row scanning signal line; wherein the Nth row scanning signal line is used to output the second scan signal, The (N+1)th scanning signal line is for outputting the third scanning signal; N is a positive integer.
  • the switching element and the driving transistor are both N-type thin film transistors, and the compensating elements are all P-type thin film transistors.
  • the switching element and the driving transistor are both P-type thin film transistors, and the compensating elements are all N-type thin film transistors.
  • the thin film transistor is one of an amorphous silicon thin film transistor, a polysilicon thin film transistor, and an amorphous-indium gallium zinc oxide thin film transistor.
  • a pixel driving method for driving the pixel driving circuit includes:
  • the first scan signal and the third scan signal are both at a first level, and the second scan signal, the data signal, and the first power signal are both at a second level, and the first scan signal is turned on.
  • a switching element for transmitting the data signal to the first node such that the second compensating element is turned on by the data signal, and the third switching element is turned on by the third scanning signal to enable Transmitting the second power signal to the second node, so that the first compensation component is turned on by the second power signal;
  • the first scan signal, the third scan signal, the data signal, and the first power signal are all at the first level, and the second scan signal is the second Leveling
  • the first switching element is turned on by the first scan signal to transmit the data signal to the first node to charge a capacitor
  • the second compensation component is in the data signal Turning off, using the third scan signal to turn on the third switching element to transmit the second power signal to the second node, so that the first compensation component is in the second Conducted by the power signal
  • the first scan signal, the second scan signal, and the data signal are all at the second level, and the third scan signal and the first power signal are both a third level, the third switching element is turned on by the third scan signal to transmit the second power signal to the second node, so that the first compensation element is at the second power source
  • the driving transistor is turned on by the data signal stored in the capacitor, so that a data signal stored in the capacitor is dropped to a threshold of the driving transistor through the driving transistor Voltage;
  • the second scan signal, the data signal, and the first power signal are all at the first level, and the first scan signal and the third scan signal are both second.
  • first switching element to the third switching element and the driving transistor are turned on by the first level, and the first compensating element and the second compensating element are in the first electric Turning off under the action of the flat, the first switching element to the third switching element and the driving transistor are turned off by the second level, the first compensating element and the second compensating element being The second level is turned on.
  • the switching element and the driving transistor are both N-type thin film transistors
  • the compensating elements are all P-type thin film transistors
  • the first level is a high level
  • the second level is a low level.
  • the switching element and the driving transistor are both P-type thin film transistors
  • the compensating elements are all N-type thin film transistors
  • the first level is a low level.
  • the second level is a high level.
  • the thin film transistor is one of an amorphous silicon thin film transistor, a polysilicon thin film transistor, and an amorphous-indium gallium zinc oxide thin film transistor.
  • a display device comprising the pixel driving circuit of any of the above.
  • FIG. 1 is a schematic diagram of a pixel driving circuit of a conventional 2T1C structure
  • FIG. 2 is a schematic diagram of a pixel driving circuit provided in an exemplary embodiment of the present disclosure
  • FIG. 3 is a timing chart showing the operation of a pixel driving circuit provided in an exemplary embodiment of the present disclosure
  • FIG. 4 is an equivalent circuit diagram of a pixel driving circuit provided in a reset phase according to an exemplary embodiment of the present disclosure
  • FIG. 5 is an equivalent circuit diagram of a pixel driving circuit provided in a precharge phase according to an exemplary embodiment of the present disclosure
  • FIG. 6 is an equivalent circuit diagram of a pixel driving circuit provided in a writing phase according to an exemplary embodiment of the present disclosure
  • FIG. 7 is an equivalent circuit diagram of a pixel driving circuit provided in a bootstrap illumination phase according to an exemplary embodiment of the present disclosure.
  • the conventional pixel driving circuit includes a transistor T0, a transistor T0', and a capacitor C0, that is, a 2T1C structure, wherein the transistor T0 is for receiving the scan signal Scan and the data signal Data, and the transistor T0' is used as a driving transistor.
  • the threshold voltage Vth of the transistor is caused to drift and inconsistency.
  • the drift and inconsistency of the transistor threshold voltage Vth can cause the driving current to be inconsistent, resulting in low uniformity of OLED illumination in each pixel in the AMOLED display panel using the conventional pixel driving circuit.
  • a pixel driving circuit which can be used to drive an electroluminescent element.
  • the pixel driving circuit can include: a first switching element T1, a second switching element T2, and a first compensation.
  • the first switching element T1 receives the first scan signal Scan1, the first end is connected to the first node 1, and the second end receives the data signal Data;
  • the second switching element T2 the control end thereof receives the second scan signal Scan2, the first end is connected to the second node 2, and the second end receives the data signal Data;
  • a first compensating element T4 the control end of which is connected to the second node 2, the second end receives the first power signal VDD;
  • a second compensating element T5 having a control end and a first end connected to the first node 1 and a second end connected to the first end of the first compensating element T4;
  • the driving transistor DT has a control terminal connected to the first node 1, a first end connected to the first electrode of the electroluminescent element L, and a second end receiving the first power signal VDD;
  • a capacitor C having a first end connected to the control end of the driving transistor DT and a second end connected to the first end of the driving transistor DT;
  • a third switching element T3 the control end thereof receives a third scan signal Scan3, the first end is connected to the second electrode of the electroluminescent element L and receives the second power signal VSS, and the second end is opposite to the driving transistor DT First end connection;
  • the electroluminescence element L is a current-driven electroluminescence element which is controlled to emit light by a current flowing through the driving transistor DT, for example, an OLED, but electroluminescence in the present exemplary embodiment
  • the element L is not limited to this.
  • the electroluminescent element L has a first pole and a second pole.
  • the first pole of the electroluminescent element L can be an anode and the second pole of the electroluminescent element L can be a cathode.
  • the first pole of the electroluminescent element L can be a cathode
  • the second pole of the electroluminescent element L can be an anode.
  • the first to third switching elements T1 to T3 may respectively correspond to the first to third switching transistors, and each of the switching transistors has a control end, a first end, and a second end.
  • the control terminal of each switching transistor may be a gate
  • the first end of each switching transistor may be a source
  • the second end of each switching transistor may be a drain.
  • the control terminal of each switching transistor may be a gate
  • the first end of each switching transistor may be a drain
  • the second end of each switching transistor may be a source.
  • each of the switching transistors may be an enhancement transistor or a depletion transistor, which is not specifically limited in this exemplary embodiment. It should be noted that since the source and the drain of the switching transistor are symmetrical, the source and the drain of the first to third switching transistors T1 to T3 can be interchanged.
  • the first compensating element T4 and the second compensating element T5 may respectively correspond to the first compensating transistor and the second compensating transistor, and each compensating transistor has a control end, a first end and a second end.
  • the control terminal of each compensation transistor may be a gate
  • the first end of each compensation transistor may be a source
  • the second end of each compensation transistor may be a drain.
  • the control terminal of each compensation transistor may be a gate
  • the first end of each compensation transistor may be a drain
  • the second end of each compensation transistor may be a source.
  • each of the compensation transistors may be an enhancement compensation transistor or a depletion compensation transistor, which is not specifically limited in this exemplary embodiment. It should be noted that since the source and the drain of the compensation transistor are symmetric, the source and the drain of the first compensation transistor T4 and the second compensation transistor T5 may be interchanged.
  • the driving transistor DT has a control end, a first end, and a second end.
  • the control terminal of the driving transistor DT may be a gate
  • the first end of the driving transistor DT may be a source
  • the second end of the driving transistor DT may be a drain.
  • the control terminal of the driving transistor DT may be a gate
  • the first end of the driving transistor DT may be a drain
  • the second end of the driving transistor DT may be a source.
  • the driving transistor DT may be an enhancement driving transistor or a depletion driving transistor, which is not particularly limited in this exemplary embodiment.
  • the type of the capacitor C can be selected according to a specific circuit.
  • the capacitor C may be a MOS capacitor, a metal capacitor, or a double poly capacitor, etc., which is not specifically limited in this exemplary embodiment.
  • the conduction levels of the first compensation component T4 and the second compensation component T5 and the conduction of the first switching component T1, the second switching component T2, the driving transistor DT, and the third switching component T3 In other words, when the on-levels of the first compensating element T4 and the second compensating element T5 are at a high level, the first switching element T1, the second switching element T2, the third switching element T3, and the driving transistor DT are turned on.
  • the level is a low level; when the on-level of the first compensating element T4 and the second compensating element T5 is a low level, the first switching element T1, the second switching element T2, the third switching element T3, and the driving transistor DT
  • the turn-on level is high.
  • the compensating elements are all P-type thin film transistors, that is, in the first switching element T1, the second switching element T2, and the third switch.
  • the first compensating element T4 and the second compensating element T5 are both P-type thin film transistors; or both the switching element and the driving transistor DT are P-type thin film transistors
  • the compensation component is an N-type thin film transistor, that is, when the first switching element T1, the second switching element T2, the third switching element T3, and the driving transistor DT are P-type thin film transistors, the first compensation element T4 and The second compensating element T5 is an N-type thin film transistor.
  • the type of the above thin film transistor can be selected according to the specific requirements of the circuit.
  • the thin film transistor may be one of an amorphous silicon thin film transistor, a polycrystalline silicon thin film transistor, and an amorphous-indium gallium zinc oxide thin film transistor, which is not particularly limited in the exemplary embodiment.
  • the pixel driving circuit provided in the exemplary embodiment of the present disclosure includes a first switching element T1, a second switching element T2, a first compensation element T4, a second compensation element T5, a driving transistor DT, a capacitor C, and a third switching element T3. .
  • the capacitor C is charged by the data signal Data
  • the driving transistor DT is turned on by the data signal Data stored in the capacitor C, so that the capacitor C is The stored data signal Data is dropped by the driving transistor DT to the threshold voltage Vth of the driving transistor DT to write the threshold voltage Vth of the driving transistor DT to the first node 1, thereby eliminating the influence of the threshold voltage Vth of the driving transistor DT on the driving current, The uniformity of the brightness of each pixel display is ensured; on the other hand, in the reset phase, the first switching element T1 and the third switching element T3 are turned on by the first scan signal Scan1 and the third scan signal Scan3 to turn the data signal Data is transmitted to the first node 1, and the second power signal VSS is transmitted to the second node 2 to reset the first node 1 by the data signal Data (ie, discharge the capacitor C), and pass the second power signal VSS to The two nodes 2 are reset, thereby eliminating the
  • the circuit structure of the plurality of pixel driving circuits arranged in the array is simplified and realized.
  • the pixel driving circuit is connected to the Nth row and the N+1th row scanning signal line; wherein, the Nth row scanning signal line is for outputting the second scanning signal Scan2, and the N+1th row scanning signal line is for outputting The third scan signal Scan3; N is a positive integer.
  • the control end of the second switching element T2 in the pixel driving circuit is connected to the Nth scanning signal line
  • the control end of the third switching element T3 in the pixel driving circuit is connected to the N+1th scanning signal line.
  • the pixel driving method can include the following four stages, wherein:
  • the first scan signal Scan1 and the third scan signal Scan3 are both at a first level, and the second scan signal Scan2, the data signal Data, and the first power signal VDD are both at a second level, using the first Scanning signal Scan1 turns on first switching element T1 to transmit said data signal Data to first node 1 to cause second compensating element T5 to be turned on by said data signal Data, using said third scan
  • the signal Scan3 turns on the third switching element T3 to transmit the second power signal VSS to the second node 2, so that the first compensation element T4 is turned on by the second power signal VSS;
  • the first scan signal Scan1, the third scan signal Scan3, the data signal Data, and the first power signal VDD are all at the first level
  • the second scan signal Scan2 For the second level, the first switching element T1 is turned on by the first scan signal Scan1 to transmit the data signal Data to the first node 1 to charge the capacitor C, and The second compensating element T5 is turned off by the data signal Data, and the third switching element T3 is turned on by the third scan signal Scan3 to transmit the second power signal VSS to the second Node 2, such that the first compensation component T4 is turned on by the second power signal VSS;
  • the first scan signal Scan1, the second scan signal Scan2, and the data signal Data are all the second level
  • the third switching element T3 is turned on by the third scan signal Scan3, so that the second power signal VSS is transmitted to the second node 2, so that the first a compensating element T4 is turned on by the second power signal VSS
  • the driving transistor DT is turned on by the data signal Data stored in the capacitor C, so that the capacitor C is stored.
  • the data signal Data is dropped by the driving transistor DT to the threshold voltage Vth of the driving transistor DT;
  • the second scan signal Scan2 In the bootstrap illumination phase, the second scan signal Scan2, the data signal Data, and the first power signal VDD are all at the first level, the first scan signal Scan1 and the third scan signal Scan3 is at a second level, and the second switching element T2 is turned on by the second scan signal Scan2, so that the data signal Data is transmitted to the second node 2 due to the bootstrap function of the capacitor C.
  • the signal of the first node 1 is bootstrapped from a threshold voltage Vth of the driving transistor DT to a sum of a threshold voltage Vth of the driving transistor DT and the data signal Data, and the driving transistor DT is at the first
  • the signal of the node 1 is turned on, and the driving current is outputted by the first power signal VDD to drive the electroluminescent element L to emit light;
  • the first to third switching elements (T1 to T3) and the driving transistor DT are turned on by the first level
  • the element T5 is turned off by the first level
  • the first to third switching elements (T1 to T3) and the driving transistor DT are turned off by the second level.
  • the first compensating element T4 and the second compensating element T5 are turned on by the second level.
  • the switching elements (ie, the first to third switching elements T1 to T3) and the driving transistor DT are both N-type thin film transistors
  • the compensating elements (ie, the first compensating element T4 and The second compensating element T5) is a P-type thin film transistor, the first level is a high level, the second level is a low level; or the switching element (ie, the first to third switches)
  • the elements T1 to T3) and the driving transistor DT are both P-type thin film transistors
  • the compensating elements (ie, the first compensating element T4 and the second compensating element T5) are N-type thin film transistors, and the first level is low.
  • the second level is high.
  • the thin film transistor may be one of an amorphous silicon thin film transistor, a polycrystalline silicon thin film transistor, and an amorphous-indium gallium zinc oxide thin film transistor, which is not particularly limited in the exemplary embodiment.
  • the driving transistors DT are all N-type thin film transistors
  • the first compensating element T4 and the second compensating element T5 are both P-type thin film transistors
  • the first level is a high level and the second level is a low level.
  • the conduction current of the DT is on a high level. Since the first compensation element T4 and the second compensation element T5 are both P-type thin film transistors, the conduction of the first compensation element T4 and the second compensation element T5 is low. level.
  • the driving timing chart shows the first scan signal Scan1, the second scan signal Scan2, the third scan signal Scan3, the first power signal VDD, and the data signal Data. It should be noted that the second power signal VSS is always at a low level.
  • the first scan signal Scan1 and the third scan signal Scan3 are both at a first level
  • the second scan signal Scan2 the data signal Data
  • the first power signal VDD are both at a second level.
  • the first scan signal Scan1 and the third scan signal Scan3 are both at a high level, and the second scan signal Scan2, the data signal Data, and the first power signal VDD are both at a low level, as shown in FIG.
  • the first switching element T1 is turned on by the first scanning signal Scan1, and the data signal Data is transmitted to the first node 1 through the first switching element T1 to reset the first node 1, that is, to perform the capacitance C.
  • the second compensating element T5 is turned on by the data signal Data transmitted to the first node 1, and the data signal Data transmitted by the driving transistor DT to the first node 1 is Turning off, the third switching element T3 is turned on by the third scanning signal Scan3, and the second power signal VSS is transmitted to the second node 2 through the third switching element T3 to reset the second node 2. That is, resetting the first pole of the electroluminescent element L, the first compensating element T4 is turned on by the second power signal VSS transmitted to the second node 2, and the second switching element T2 is in the second scanning signal Turn off under the influence of Scan2. It can be seen from the above process that both the capacitor C and the first pole of the electroluminescent element L are reset during the reset phase (ie, the t1 phase), eliminating the influence of the previous frame signal on the display brightness.
  • the first scan signal Scan1, the third scan signal Scan3, the data signal Data, and the first power signal VDD are all at the first level
  • the level of the second scan signal Scan2 is the second level
  • the first switching element T1 is turned on by the first scan signal Scan1 to transmit the data signal Data to the first node 1, Charging the capacitor C, and turning off the second compensating element T5 under the action of the data signal Data, and turning on the third switching element T3 by using the third scan signal Scan3 to make the second power source
  • the signal VSS is transmitted to the second node 2 such that the first compensation element T4 is turned on by the second power signal VSS.
  • the first scan signal Scan1 and the third scan signal Scan3, the data signal Data, and the first power supply signal VDD are both at a high level, and the second scan signal Scan2 is at a low level.
  • the second switching element T2 is turned off by the second scanning signal Scan2
  • the third switching element T3 is turned on by the third scanning signal Scan3 to transmit the second power signal VSS to the second.
  • the first compensation component T4 is turned on by the second power signal VSS transmitted to the second node 2
  • the first switching element T1 is at the first scan signal Scan1.
  • the data signal Data is transmitted to the first node 1 to charge the first end of the capacitor C, so that the signal of the first end of the storage capacitor C becomes the data signal Data, that is, the signal of the first node As the data signal Data, since the data signal Data is a high level signal, the second compensating element T5 is turned off by the data signal Data transmitted to the first node 1, and the driving transistor DT is transmitted to the first node 1. The data signal Data is turned on.
  • the first scan signal Scan1, the second scan signal Scan2, and the data signal Data are all the second level
  • the third scan signal Scan3 and the The first power signal VDD is at a first level
  • the third switching element T3 is turned on by the third scan signal Scan3 to transmit the second power signal VSS to the second node 2, so that The first compensating element T4 is turned on by the second power signal VSS, and the driving transistor DT is turned on by the data signal Data stored in the capacitor C, so that the capacitor C
  • the data signal Data stored therein is dropped by the drive transistor DT to the threshold voltage Vth of the drive transistor DT.
  • the first scan signal Scan1, the second scan signal Scan2, and the data signal Data are all at a low level
  • the third scan signal Scan3 and the first power signal VDD are both at a high level, as shown in FIG. It is shown that the first switching element T1 is turned off by the first scanning signal Scan1, the second switching element T2 is turned off by the second scanning signal Scan2, and the third switching element T3 is under the action of the third scanning signal Scan3.
  • the second power signal VSS is transmitted to the second node 2 through the third switching element T3, and the first compensation element T4 is turned on by the second power signal VSS transmitted to the second node 2, since the capacitor C is in advance
  • the data phase Data is stored in the charging phase (ie, the t2 phase), so the driving transistor DT is turned on by the data signal Data stored in the capacitor C.
  • the data signal Data stored in the capacitor C is lowered to the driving by the driving transistor DT.
  • the threshold voltage Vth of the transistor DT that is, the signal of the first node 1 falls from the data signal Data to the threshold voltage Vth of the driving transistor DT. It should be noted that when the signal of the first node 1 falls to the threshold voltage Vth of the driving transistor DT, the driving transistor DT is turned off.
  • the second scan signal Scan2 the data signal Data, and the first power signal VDD are all at the first level
  • the first scan signal Scan1 and the The level of the third scan signal Scan3 is a second level
  • the second switching element T2 is turned on by the second scan signal Scan2, so that the data signal Data is transmitted to the second node 2 and passed
  • the bootstrap action of the capacitor C bootstraps the signal of the first node 1 from the threshold voltage Vth of the driving transistor DT to the sum of the threshold voltage Vth of the driving transistor DT and the data signal Data
  • the driving transistor DT is turned on by the signal of the first node 1, and outputs a driving current under the action of the first power signal VDD to drive the electroluminescent element L to emit light.
  • the first scan signal Scan1 and the third scan signal Scan3 are at a low level, and the second scan signal Scan2, the data signal Data, and the first power signal VDD are both at a high level, as shown in FIG.
  • the first switching element T1 is turned off by the first scanning signal Scan1
  • the third switching element T3 is turned off by the third scanning signal Scan3
  • the second switching element T2 is guided by the second scanning signal Scan2.
  • the data signal Data is transmitted to the second node 2 through the second switching element T2.
  • the signal of the second node 2 is the data signal Data.
  • the signal of the first node 1 is driven from the driving transistor DT.
  • the threshold voltage Vth is bootstrapped to the sum of the threshold voltage Vth of the driving transistor DT and the data signal Data. Since the signals of the first node 1 and the second node 2 are both high level signals, the first compensating element T4 and The second compensating element T5 is turned off.
  • the driving transistor DT is turned on by the signal of the first node 1 (ie, the threshold voltage Vth of the driving transistor DT and the data signal Data), and outputs a driving current under the action of the first power supply signal VDD, since the driving transistor DT is guided. When it is over, the voltage at the first end of the drive transistor DT becomes VDD.
  • Vgs is the voltage difference between the gate and the source of the drive transistor DT
  • Vg is the gate voltage of the drive transistor DT
  • Vs is the source voltage of the drive transistor DT.
  • the driving current of the driving transistor DT is independent of the threshold voltage Vth of the driving transistor DT, thereby eliminating the influence of the threshold voltage Vth of the driving transistor DT on the driving current, and ensuring the display brightness of each pixel. Uniformity.
  • the capacitor C is charged by the data signal Data, and in the writing phase (ie, the t3 phase), the driving transistor DT is turned on by the data signal Data stored in the capacitor C, so that the data signal Data stored in the capacitor C is
  • the threshold voltage Vth of the driving transistor DT is written to the first node 1 by the driving transistor DT to the threshold voltage Vth of the driving transistor DT, thereby eliminating the influence of the threshold voltage Vth of the driving transistor DT on the driving current, thereby ensuring display of each pixel.
  • the first switching element T1 and the third switching element T3 are turned on by the first scan signal Scan1 and the third scan signal Scan3 to transmit the data signal Data is transmitted to the first node 1, and the second power signal VSS is transmitted to the second node 2 to reset the first node 1 by the data signal Data (ie, discharge the capacitor C), and pass the second power signal VSS to The two nodes 2 are reset to eliminate the influence of the previous frame signal on the display brightness.
  • all the switching elements and the driving transistors are N-type thin film transistors, and all of the compensating elements are P-type thin film transistors; however, those skilled in the art can easily provide the pixel driving circuit according to the present disclosure. It is obtained that all switching elements and driving transistors are P-type thin film transistors, and all compensating elements are pixel driving circuits of N-type thin film transistors.
  • the use of a P-type thin film transistor has the following advantages: for example, strong noise suppression; for example, low level conduction, and low level in charge management is easy to implement; for example, a P-type thin film transistor is simple in process and relatively low in price; for example, P The stability of the thin film transistor is better and the like.
  • CMOS Complementary Metal Oxide Semiconductor
  • the example embodiment also provides a display device including the above-described pixel driving circuit.
  • the display device includes: a plurality of scan lines for providing scan signals; a plurality of data lines for providing data signals; and a plurality of pixel drive circuits electrically connected to the scan lines and the data lines; at least one of the pixels
  • the driving circuit includes any of the above-described pixel driving circuits in the present exemplary embodiment.
  • the pixel driving power charges the capacitor through the data signal, and in the writing phase, the driving transistor is turned on by the data signal stored in the capacitor, so that the data signal stored in the capacitor is dropped to the threshold voltage of the driving transistor through the driving transistor, Writing the threshold voltage of the driving transistor to the first node, thereby eliminating the influence of the threshold voltage of the driving transistor on the driving current, ensuring uniformity of brightness of each pixel display; and, in the reset phase, passing the first scanning signal and the third
  • the scan signal turns on the first switching element and the third switching element to transmit the data signal to the first node, and the second power signal is transmitted to the second node, thereby resetting the first node by the data signal (ie, the capacitance Performing a discharge), resetting the second node by the second power signal to eliminate the influence of the previous frame signal on the display brightness.
  • the display device may include, for example, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, or the like
  • modules or units of equipment for action execution are mentioned in the detailed description above, such division is not mandatory. Indeed, in accordance with embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one of the modules or units described above may be further divided into multiple modules or units.

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Abstract

一种像素驱动电路及像素驱动方法、显示装置。该像素驱动电路包括第一开关元件(T1)、第二开关元件(T2)、第一补偿元件(T4)、第二补偿元件(T5)、驱动晶体管(DT)、电容(C)以及第三开关元件(T3)。可以消除驱动晶体管的阈值电压对驱动电流的影响，保证了各个像素显示亮度的均匀性，此外还可以消除上一帧信号对显示亮度的影响。

Description

像素驱动电路及方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及像素驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点越来越多地被应用于高性能显示领域当中。OLED显示装置按照驱动方式的不同可分为PMOLED(Passive Matrix Driving OLED，无源矩阵驱动有机发光二极管)和AMOLED(Active Matrix Driving OLED，有源矩阵驱动有机发光二极管)两种。由于AMOLED显示器具有低制造成本、高应答速度、省电、可用于便携式设备的直流驱动、工作温度范围大等优点，AMOLED得到了显示技术开发商日益广泛的关注。
在现有的AMOLED显示面板中，每个发光像素都有独立的像素驱动电路为其提供驱动电流。然而，在传统的像素驱动电路的驱动作用下，AMOLED显示面板中各像素中的OLED发光均匀性有待提高。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的相关技术的信息。
发明内容
本公开的目的在于提供一种像素驱动电路及像素驱动方法、显示装置，进而至少在一定程度上克服由于相关技术的限制和缺陷而导致的一个或者多个问题。
根据本公开的一个方面，提供一种像素驱动电路，所述像素驱动电路包括：
第一开关元件，其控制端接收第一扫描信号，第一端与第一节点连接，第二端接收数据信号；
第二开关元件，其控制端接收第二扫描信号，第一端与第二节点连接，第二端接收所述数据信号；
第一补偿元件，其控制端与所述第二节点连接，第二端接收第一电源信号；
第二补偿元件，其控制端和第一端均与所述第一节点连接，第二端与所述第一补偿元件的第一端连接；
驱动晶体管，其控制端与所述第一节点连接，第一端与电致发光元件的第一极连接，第二端接收所述第一电源信号；
电容，其第一端与所述驱动晶体管的控制端连接，第二端与所述驱动晶体管的第一端连接；
第三开关元件，其控制端接收第三扫描信号，第一端与所述电致发光元件的第二极连接并接收第二电源信号，第二端与所述驱动晶体管的第一端连接；其中；
所述第一补偿元件和所述第二补偿元件的导通电平与所述第一开关元件、所述第二开关元件、所述驱动晶体管和所述第三开关元件的导通电平相反。
在本公开的一种示例性实施例中，所述像素驱动电路与第N行以及第N+1行扫描信号线连接；其中，第N行扫描信号线用于输出所述第二扫描信号，第N+1行扫描信号线用于输出所述第三扫描信号；N为正整数。
在本公开的一种示例性实施例中，所述开关元件和所述驱动晶体管均为N型薄膜晶体管，所述补偿元件均为P型薄膜晶体管。
在本公开的一种示例性实施例中，所述开关元件和所述驱动晶体管均为P型薄膜晶体管，所述补偿元件均为N型薄膜晶体管。
在本公开的一种示例性实施例中，所述薄膜晶体管为非晶硅薄膜晶体管、多晶硅薄膜晶体管以及非晶-氧化铟镓锌薄膜晶体管中的一种。
根据本公开的一个方面，提供一种像素驱动方法，用于驱动上述任意一项所述的像素驱动电路，所述像素驱动方法包括：
在重置阶段，第一扫描信号和第三扫描信号均为第一电平，第二扫描信号、数据信号以及第一电源信号均为第二电平，利用所述第一扫描信号导通第一开关元件，以使所述数据信号传输至第一节点，以使第二补偿元件在所述数据信号的作用下导通，利用所述第三扫描信号导通第三开关元件，以使第二电源信号传输至第二节点，以使第一补偿元件在所述第二电源信号的作用下导通；
在预充电阶段，所述第一扫描信号、所述第三扫描信号、所述数据信号以及所述第一电源信号均为所述第一电平，所述第二扫描信号为所述第二电平，利用所述第一扫描信号导通所述第一开关元件，以使所述数据信号传输至所述第一节点，以对电容充电，并使第二补偿元件在所述数据信号的作用下关断，利用所述第三扫描信号导通所述第三开关元件，以使所述第二电源信号传输至所述第二节点，以使所述第一补偿元件在所述第二电源信号的作用下导通；
在写入阶段，所述第一扫描信号、所述第二扫描信号以及所述数据信号均为所述第二电平，所述第三扫描信号和所述第一电源信号均为所述第一电平，利用所述第三扫描信号导通所述第三开关元件，以使所述第二电源信号传输至所述第二节点，以使所述第一补偿元件在所述第二电源信号的作用下导通，所述驱动晶体管在所述电容中存储的所 述数据信号的作用下导通，使得所述电容中存储的数据信号通过所述驱动晶体管下降至所述驱动晶体管的阈值电压；
在自举发光阶段，所述第二扫描信号、所述数据信号以及所述第一电源信号均为所述第一电平，所述第一扫描信号和所述第三扫描信号均为第二电平，利用所述第二扫描信号导通所述第二开关元件，使得所述数据信号传输至所述第二节点，并通过所述电容的自举作用将所述第一节点的信号从所述驱动晶体管的阈值电压自举至所述驱动晶体管的阈值电压与所述数据信号之和，所述驱动晶体管在所述第一节点的信号的作用下导通，并在所述第一电源信号的作用下输出驱动电流以驱动电致发光元件发光；
其中，所述第一开关元件至所述第三开关元件以及所述驱动晶体管在所述第一电平的作用下导通，所述第一补偿元件和第二补偿元件在所述第一电平的作用下关断，所述第一开关元件至所述第三开关元件以及驱动晶体管在所述第二电平的作用下关断，所述第一补偿元件和第二补偿元件在所述第二电平的作用下导通。
在本公开的一种示例性实施例中，所述开关元件和所述驱动晶体管均为N型薄膜晶体管，所述补偿元件均为P型薄膜晶体管，所述第一电平为高电平、所述第二电平为低电平。
在本公开的一种示例性实施例中，所述开关元件和所述驱动晶体管均为P型薄膜晶体管，所述补偿元件均为N型薄膜晶体管，所述第一电平为低电平，所述第二电平为高电平。
在本公开的一种示例性实施例中，所述薄膜晶体管为非晶硅薄膜晶体管、多晶硅薄膜晶体管以及非晶-氧化铟镓锌薄膜晶体管中的一种。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的像素驱动电路。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的相关技术的信息。
附图说明
通过参照附图来详细描述其示例性实施例，本公开的上述和其它特征及优点将变得更加明显。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1为传统2T1C结构的像素驱动电路的示意图；
图2为本公开一示例性实施例中提供的像素驱动电路的示意图；
图3为本公开一示例性实施例中提供的像素驱动电路的工作时序图；
图4为本公开一示例性实施例中提供的像素驱动电路在重置阶段的等效电路图；
图5为本公开一示例性实施例中提供的像素驱动电路在预充电阶段的等效电路图；
图6为本公开一示例性实施例中提供的像素驱动电路在写入阶段的等效电路图；
图7为本公开一示例性实施例中提供的像素驱动电路在自举发光阶段的等效电路图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施例；相反，提供这些实施例使得本公开将全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免模糊本公开的各方面。
此外，附图仅为本公开的示意性图解，并非一定是按照比例绘制。图中相同的附图标记标识相同或相似的部分，因而将省略对它们的重复描述。
如图1所示，传统的像素驱动电路包括晶体管T0、晶体管T0’和一个电容C0，即2T1C结构，其中晶体管T0用于接收扫描信号Scan和数据信号Data，晶体管T0’用作驱动晶体管。该像素驱动电路驱动电流的计算公式为：Ion＝K×(Vgs-Vth) 2＝K×(Vg-Vs-Vth)2＝K×(Data-VDD-Vth) 2。由上述驱动电流的计算公式可知，传统的像素驱动电路中驱动电流Ion的大小与驱动晶体管的阈值电压Vth有关。然而，由于晶体管的工艺差异以及长时间工作的原因，致使晶体管的阈值电压Vth出现漂移和不一致的问题。结合上述驱动电流的计算公式可知，晶体管阈值电压Vth的漂移和不一致的问题可以导致驱动电流不一致，从而导致使用传统的像素驱动电路的AMOLED显示面板中各像素中的OLED发光均匀性较低。
本示例实施方式中提供了一种像素驱动电路，可以用于驱动电致发光元件，参照图2所示，该像素驱动电路可以包括：第一开关元件T1、第二开关元件T2、第一补偿元件T4、第二补偿元件T5、驱动晶体管DT、电容C以及第三开关元件T3。其中：
第一开关元件T1，其控制端接收第一扫描信号Scan1，第一端与第一节点1连接，第二端接收数据信号Data；
第二开关元件T2，其控制端接收第二扫描信号Scan2，第一端与第二节点2连接，第二端接收所述数据信号Data；
第一补偿元件T4，其控制端与所述第二节点2连接，第二端接收第一电源信号VDD；
第二补偿元件T5，其控制端和第一端均与所述第一节点1连接，第二端与所述第一补偿元件T4的第一端连接；
驱动晶体管DT，其控制端与所述第一节点1连接，第一端与电致发光元件L的第一极连接，第二端接收所述第一电源信号VDD；
电容C，其第一端与所述驱动晶体管DT的控制端连接，第二端与所述驱动晶体管DT的第一端连接；
第三开关元件T3，其控制端接收第三扫描信号Scan3，第一端与所述电致发光元件L的第二极连接并接收第二电源信号VSS，第二端与所述驱动晶体管DT的第一端连接；其中；
所述第一补偿元件T4和所述第二补偿元件T5的导通电平与所述第一开关元件T1、所述第二开关元件T2、驱动晶体管DT和第三开关元件T3的导通电平相反。
在本示例性实施例中，电致发光元件L为电流驱动型电致发光元件，由流经驱动晶体管DT的电流控制其进行发光，例如，OLED，但本示例性实施例中的电致发光元件L不限于此。此外，电致发光元件L具有第一极和第二极。例如，电致发光元件L的第一极可以为阳极，电致发光元件L的第二极可以为阴极。再例如，电致发光元件L的第一极可以为阴极，电致发光元件L的第二极可以为阳极。
所述第一开关元件至第三开关元件T1～T3可以分别对应第一开关晶体管至第三开关晶体管，每一个开关晶体管均具有控制端、第一端以及第二端。例如，各开关晶体管的控制端可以为栅极，各开关晶体管的第一端可以为源极，各开关晶体管的第二端可以为漏极。再例如，各开关晶体管的控制端可以为栅极，各开关晶体管的第一端可以为漏极，各开关晶体管的第二端可以为源极。此外，各个开关晶体管可以为增强型晶体管或者耗尽型晶体管，本示例性实施例对此不作特殊限定。需要说明的是，由于开关晶体管的源极和漏极对称，因此，第一开关晶体管至第三开关晶体管T1～T3的源极、漏极可以互换。
所述第一补偿元件T4和第二补偿元件T5可以分别对应第一补偿晶体管和第二补偿晶体管，各补偿晶体管均具有控制端、第一端以及第二端。例如，各补偿晶体管的控制端可以为栅极，各补偿晶体管的第一端可以为源极，各补偿晶体管的第二端可以为漏极。再例如，各补偿晶体管的控制端可以为栅极，各补偿晶体管的第一端可以为漏极，各补偿晶体管的第二端可以为源极。此外，各补偿晶体管可以为增强型补偿晶体管或者耗尽型补偿晶体管，本示例性实施例对此不作特殊限定。需要说明的是，由于补偿晶体管的 源极和漏极对称，因此，第一补偿晶体管T4和第二补偿晶体管T5的源极、漏极可以互换。
所述驱动晶体管DT具有控制端、第一端以及第二端。例如，驱动晶体管DT的控制端可以为栅极，驱动晶体管DT的第一端可以为源极、驱动晶体管DT的第二端可以为漏极。再例如，驱动晶体管DT的控制端可以为栅极，驱动晶体管DT的第一端可以为漏极，驱动晶体管DT的第二端可以为源极。此外，驱动晶体管DT可以为增强型驱动晶体管或耗尽型驱动晶体管，本示例性实施例对此不作特殊限定。
所述电容C的类型可以根据具体的电路进行选择。例如，所述电容C可以为MOS电容、金属电容或双多晶电容等，本示例性实施例对此不作特殊限定。
所述第一补偿元件T4和所述第二补偿元件T5的导通电平与所述第一开关元件T1、所述第二开关元件T2、驱动晶体管DT和第三开关元件T3的导通电平相反，即在第一补偿元件T4和第二补偿元件T5的导通电平为高电平时，第一开关元件T1、第二开关元件T2、第三开关元件T3以及驱动晶体管DT的导通电平为低电平；在第一补偿元件T4和第二补偿元件T5的导通电平为低电平时，第一开关元件T1、第二开关元件T2、第三开关元件T3以及驱动晶体管DT的导通电平为高电平。基于此，在所述开关元件和所述驱动晶体管DT均为N型薄膜晶体管时，所述补偿元件均为P型薄膜晶体管，即在第一开关元件T1、第二开关元件T2、第三开关元件T3以及驱动晶体管DT均为N型薄膜晶体管时，第一补偿元件T4和第二补偿元件T5均为P型薄膜晶体管；或者在所述开关元件和所述驱动晶体管DT均为P型薄膜晶体管时，所述补偿元件均为N型薄膜晶体管，即在第一开关元件T1、第二开关元件T2、第三开关元件T3以及驱动晶体管DT均为P型薄膜晶体管时，第一补偿元件T4和第二补偿元件T5均为N型薄膜晶体管。进一步的，上述薄膜晶体管的类型可以根据电路的具体要求进行选择。例如，薄膜晶体管可以为非晶硅薄膜晶体管、多晶硅薄膜晶体管以及非晶-氧化铟镓锌薄膜晶体管中的一种，本示例性实施例对此不作特殊限定。
本公开示例性实施例中所提供的像素驱动电路包括第一开关元件T1、第二开关元件T2、第一补偿元件T4、第二补偿元件T5、驱动晶体管DT、电容C以及第三开关元件T3。在该像素驱动电路的工作过程中，在预充电阶段，通过数据信号Data对电容C充电，并在写入阶段，通过电容C中存储的数据信号Data将驱动晶体管DT导通，使得电容C中存储的数据信号Data通过驱动晶体管DT下降至驱动晶体管DT的阈值电压Vth，以将驱动晶体管DT的阈值电压Vth写入第一节点1，从而消除驱动晶体管DT的阈值电压Vth对驱动电流的影响，保证了各个像素显示亮度的均一性；另一方面，在重置阶段，通过第一扫描信号Scan1和第三扫描信号Scan3将第一开关元件T1和第三开关元件T3 导通，以将数据信号Data传输至第一节点1、第二电源信号VSS传输至第二节点2，以通过数据信号Data对第一节点1进行重置(即对电容C进行放电)，通过第二电源信号VSS对第二节点2进行重置，从而消除上一帧信号对显示亮度的影响。
在阵列排布的多个像素驱动电路中，为了复用各像素驱动电路中的第二扫描信号Scan2和第三扫描信号Scan3，以简化阵列排布的多个像素驱动电路的电路结构以及实现逐行扫描。所述像素驱动电路与第N行以及第N+1行扫描信号线连接；其中，第N行扫描信号线用于输出所述第二扫描信号Scan2，第N+1行扫描信号线用于输出所述第三扫描信号Scan3；N为正整数。具体的，像素驱动电路中的第二开关元件T2的控制端均连接第N行扫描信号线，像素驱动电路中的第三开关元件T3的控制端连接第N+1行扫描信号线。
在本公开的示例性实施例中，还提供了一种像素驱动方法，用于驱动如图2所述的像素驱动电路。该像素驱动方法可以包括以下四个阶段，其中：
在重置阶段，第一扫描信号Scan1和第三扫描信号Scan3均为第一电平，第二扫描信号Scan2、数据信号Data以及第一电源信号VDD均为第二电平，利用所述第一扫描信号Scan1导通第一开关元件T1，以使所述数据信号Data传输至第一节点1，以使第二补偿元件T5在所述数据信号Data的作用下导通，利用所述第三扫描信号Scan3导通第三开关元件T3，以使第二电源信号VSS传输至第二节点2，以使第一补偿元件T4在所述第二电源信号VSS的作用下导通；
在预充电阶段，所述第一扫描信号Scan1、所述第三扫描信号Scan3、所述数据信号Data以及所述第一电源信号VDD均为所述第一电平，所述第二扫描信号Scan2为所述第二电平，利用所述第一扫描信号Scan1导通所述第一开关元件T1，以使所述数据信号Data传输至所述第一节点1，以对电容C充电，并使第二补偿元件T5在所述数据信号Data的作用下关断，利用所述第三扫描信号Scan3导通所述第三开关元件T3，以使所述第二电源信号VSS传输至所述第二节点2，以使所述第一补偿元件T4在所述第二电源信号VSS的作用下导通；
在写入阶段，所述第一扫描信号Scan1、所述第二扫描信号Scan2以及所述数据信号Data均为所述第二电平，所述第三扫描信号Scan3和所述第一电源信号VDD均为所述第一电平，利用所述第三扫描信号Scan3导通所述第三开关元件T3，以使所述第二电源信号VSS传输至所述第二节点2，以使所述第一补偿元件T4在所述第二电源信号VSS的作用下导通，所述驱动晶体管DT在所述电容C中存储的所述数据信号Data的作用下导通，使得所述电容C中存储的数据信号Data通过所述驱动晶体管DT下降至所述驱动晶体管DT的阈值电压Vth；
在自举发光阶段，所述第二扫描信号Scan2、所述数据信号Data以及所述第一电源信号VDD均为所述第一电平，所述第一扫描信号Scan1和所述第三扫描信号Scan3均为第二电平，利用所述第二扫描信号Scan2导通所述第二开关元件T2，使得所述数据信号Data传输至所述第二节点2，由于所述电容C的自举作用将所述第一节点1的信号从所述驱动晶体管DT的阈值电压Vth自举至所述驱动晶体管DT的阈值电压Vth与所述数据信号Data之和，所述驱动晶体管DT在所述第一节点1的信号的作用下导通，并在所述第一电源信号VDD的作用下输出驱动电流以驱动电致发光元件L发光；
其中，所述第一开关元件至所述第三开关元件(T1～T3)以及所述驱动晶体管DT在所述第一电平的作用下导通，所述第一补偿元件T4和第二补偿元件T5在所述第一电平的作用下关断，所述第一开关元件至所述第三开关元件(T1～T3)以及驱动晶体管DT在所述第二电平的作用下关断，所述第一补偿元件T4和第二补偿元件T5在所述第二电平的作用下导通。
在本示例性实施例中，所述开关元件(即第一开关元件至第三开关元件T1～T3)和驱动晶体管DT均为N型薄膜晶体管，所述补偿元件(即第一补偿元件T4和第二补偿元件T5)均为P型薄膜晶体管，所述第一电平为高电平、所述第二电平为低电平；或者所述开关元件(即第一开关元件至第三开关元件T1～T3)和驱动晶体管DT均为P型薄膜晶体管，所述补偿元件(即第一补偿元件T4和第二补偿元件T5)均为N型薄膜晶体管，所述第一电平为低电平，所述第二电平为高电平。上述薄膜晶体管可以为非晶硅薄膜晶体管、多晶硅薄膜晶体管以及非晶-氧化铟镓锌薄膜晶体管中的一种，本示例性实施例对此不作特殊限定。
下面，结合图3所示的像素驱动电路的工作时序图对图2中的像素驱动电路的工作过程加以详细的说明，以第一开关元件T1、第二开关元件T2、第三开关元件T3以及驱动晶体管DT均为N型薄膜晶体管，第一补偿元件T4和第二补偿元件T5均为P型薄膜晶体管，第一电平为高电平，第二电平为低电平为例。由于第一开关元件T1、第二开关元件T2、第三开关元件T3以及驱动晶体管DT均为N型薄膜晶体管，因此第一开关元件T1、第二开关元件T2、第三开关元件T3以及驱动晶体管DT的导通电平均为高电平，由于第一补偿元件T4和第二补偿元件T5均为P型薄膜晶体管，因此第一补偿元件T4和第二补偿元件T5的导通电平均为低电平。该驱动时序图绘示了第一扫描信Scan1，第二扫描信号Scan2，第三扫描信号Scan3，第一电源信号VDD，数据信号Data。需要说明的是，第二电源信号VSS始终为低电平。
在重置阶段(即t1阶段)，第一扫描信号Scan1和第三扫描信号Scan3均为第一电平，第二扫描信号Scan2、数据信号Data以及第一电源信号VDD均为第二电平，利用 所述第一扫描信号Scan1导通第一开关元件T1，以使所述数据信号Data传输至第一节点1，以使第二补偿元件T5在所述数据信号Data的作用下导通，利用所述第三扫描信号Scan3导通第三开关元件T3，以使第二电源信号VSS传输至第二节点2，以使第一补偿元件T4在所述第二电源信号VSS的作用下导通。在本示例性实施例中，第一扫描信号Scan1和第三扫描信号Scan3均为高电平，第二扫描信号Scan2、数据信号Data以及第一电源信号VDD均为低电平，如图4所述，第一开关元件T1在第一扫描信号Scan1的作用下导通，数据信号Data通过第一开关元件T1传输至第一节点1，以对第一节点1进行重置，即对电容C进行放电，由于此时数据信号Data为低电平，因此第二补偿元件T5在传输至第一节点1的数据信号Data的作用下导通，驱动晶体管DT在传输至第一节点1的数据信号Data的作用下关断，第三开关元件T3在第三扫描信号Scan3的作用下导通，第二电源信号VSS通过第三开关元件T3传输至第二节点2，以对第二节点2进行重置，即对电致发光元件L的第一极进行重置，第一补偿元件T4在传输至第二节点2的第二电源信号VSS的作用下导通，第二开关元件T2在第二扫描信号Scan2的作用下关断。由上述过程可知，在重置阶段(即t1阶段)对电容C和电致发光元件L的第一极均进行了重置，消除了上一帧信号对显示亮度的影响。
在预充电阶段(即t2阶段)，所述第一扫描信号Scan1、所述第三扫描信号Scan3、所述数据信号Data以及所述第一电源信号VDD均为所述第一电平，所述第二扫描信号Scan2的电平为所述第二电平，利用所述第一扫描信号Scan1导通所述第一开关元件T1，以使所述数据信号Data传输至所述第一节点1，以对电容C充电，并使第二补偿元件T5在所述数据信号Data的作用下关断，利用所述第三扫描信号Scan3导通所述第三开关元件T3，以使所述第二电源信号VSS传输至所述第二节点2，以使所述第一补偿元件T4在所述第二电源信号VSS的作用下导通。在本示例性实施例中，第一扫描信号Scan1和第三扫描信号Scan3、数据信号Data以及第一电源信号VDD均为高电平，第二扫描信号Scan2为低电平。如图5所示，第二开关元件T2在第二扫描信号Scan2的作用下关断，第三开关元件T3在第三扫描信号Scan3的作用下导通，将第二电源信号VSS传输至第二节点2，由于第二电源信号VSS为低电平，因此第一补偿元件T4在传输至第二节点2的第二电源信号VSS的作用下导通，第一开关元件T1在第一扫描信号Scan1的作用下导通，将数据信号Data传输至第一节点1，以对电容C的第一端进行充电，使得存储电容C的第一端的信号变为数据信号Data，即第一节点的信号变为数据信号Data，由于数据信号Data为高电平信号，因此第二补偿元件T5在传输至第一节点1的数据信号Data的作用下关断，驱动晶体管DT在传输至第一节点1的数据信号Data的作用下导通。
在写入阶段(即t3阶段)，所述第一扫描信号Scan1、所述第二扫描信号Scan2以 及所述数据信号Data均为所述第二电平，所述第三扫描信号Scan3和所述第一电源信号VDD均为第一电平，利用所述第三扫描信号Scan3导通所述第三开关元件T3，以使所述第二电源信号VSS传输至所述第二节点2，以使所述第一补偿元件T4在所述第二电源信号VSS的作用下导通，所述驱动晶体管DT在所述电容C中存储的所述数据信号Data的作用下导通，使得所述电容C中存储的数据信号Data通过所述驱动晶体管DT下降至所述驱动晶体管DT的阈值电压Vth。在本示例性实施例中，第一扫描信号Scan1、第二扫描信号Scan2、数据信号Data均为低电平，第三扫描信号Scan3以及第一电源信号VDD均为高电平，如图6所示，第一开关元件T1在第一扫描信号Scan1的作用下关断，第二开关元件T2在第二扫描信号Scan2的作用下关断，第三开关元件T3在第三扫描信号Scan3的作用下导通，第二电源信号VSS通过第三开关元件T3传输至第二节点2，第一补偿元件T4在传输至第二节点2的第二电源信号VSS的作用下导通，由于电容C在预充电阶段(即t2阶段)存储了数据信号Data，因此驱动晶体管DT在存储在电容C中的数据信号Data的作用下导通，此时电容C中存储的数据信号Data通过驱动晶体管DT下降至驱动晶体管DT的阈值电压Vth，即第一节点1的信号从数据信号Data下降至驱动晶体管DT的阈值电压Vth。需要说明的是，在第一节点1的信号下降至驱动晶体管DT的阈值电压Vth时，驱动晶体管DT关断。
在自举发光阶段(即t4阶段)，所述第二扫描信号Scan2、所述数据信号Data以及所述第一电源信号VDD均为所述第一电平，所述第一扫描信号Scan1和所述第三扫描信号Scan3的电平均为第二电平，利用所述第二扫描信号Scan2导通所述第二开关元件T2，使得所述数据信号Data传输至所述第二节点2，并通过所述电容C的自举作用将所述第一节点1的信号从所述驱动晶体管DT的阈值电压Vth自举至所述驱动晶体管DT的阈值电压Vth与所述数据信号Data之和，所述驱动晶体管DT在所述第一节点1的信号的作用下导通，并在所述第一电源信号VDD的作用下输出驱动电流以驱动电致发光元件L发光。在本示例性实施例中，第一扫描信号Scan1、第三扫描信号Scan3为低电平，第二扫描信号Scan2、数据信号Data以及第一电源信号VDD均为高电平，如图7所示，第一开关元件T1在第一扫描信号Scan1的作用下关断，第三开关元件T3在第三扫描信号Scan3的作用下关断，第二开关元件T2在第二扫描信号Scan2的作用下导通，数据信号Data通过第二开关元件T2传输至第二节点2，此时第二节点2的信号为数据信号Data，在电容C的自举作用下，第一节点1的信号从驱动晶体管DT的阈值电压Vth自举至驱动晶体管DT的阈值电压Vth与数据信号Data之和，由于此时第一节点1和第二节点2的信号均为高电平信号，因此，第一补偿元件T4和第二补偿元件T5均关断。驱动晶体管DT在第一节点1的信号(即驱动晶体管DT的阈值电压Vth与数据信号Data)的作 用下导通，并在第一电源信号VDD的作用下输出驱动电流，由于在驱动晶体管DT导通时，驱动晶体管DT第一端的电压变为VDD。
在此基础上，根据驱动晶体管DT的驱动电流的计算公式：
Ion＝K×(Vgs-Vth)2＝K×(Vg-Vs-Vth)2
＝K×(Data+Vth-VDD-Vth)2
＝K×(Data-VDD)2
其中，Vgs为驱动晶体管DT的栅极和源极之间的电压差、Vg为驱动晶体管DT的栅极电压、Vs为驱动晶体管DT的源极电压。
由上述驱动晶体管DT驱动电流的计算公式可知，驱动晶体管DT的驱动电流与驱动晶体管DT的阈值电压Vth无关，从而消除了驱动晶体管DT的阈值电压Vth对驱动电流的影响，保证了各个像素显示亮度的均一性。
综上所述，通过数据信号Data对电容C充电，并在写入阶段(即t3阶段)，通过电容C中存储的数据信号Data将驱动晶体管DT导通，使得电容C中存储的数据信号Data通过驱动晶体管DT下降至驱动晶体管DT的阈值电压Vth，以将驱动晶体管DT的阈值电压Vth写入第一节点1，从而消除驱动晶体管DT的阈值电压Vth对驱动电流的影响，保证了各个像素显示亮度的均一性；另一方面，在重置阶段(即t1阶段)，通过第一扫描信号Scan1和第三扫描信号Scan3将第一开关元件T1和第三开关元件T3导通，以将数据信号Data传输至第一节点1、第二电源信号VSS传输至第二节点2，以通过数据信号Data对第一节点1进行重置(即对电容C进行放电)，通过第二电源信号VSS对第二节点2进行重置，以消除上一帧信号对显示亮度的影响。
需要说明的是，在上述实施例中，所有开关元件和驱动晶体管均为N型薄膜晶体管，所有补偿元件均为P型薄膜晶体管；但本领域的技术人员容易根据本公开所提供的像素驱动电路得到所有开关元件和驱动晶体管均为P型薄膜晶体管，所有补偿元件均为N型薄膜晶体管的像素驱动电路。采用P型薄膜晶体管具有以下优点：例如对噪声抑制力强；例如由于是低电平导通，而充电管理中低电平容易实现；例如P型薄膜晶体管制程简单，相对价格较低；例如P型薄膜晶体管的稳定性更好等等。
当然，本公开所提供的像素驱动电路也可以改为CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)电路等，并不局限于本实施例中所提供的像素驱动电路，这里不再赘述。
本示例实施方式还提供一种显示装置，包括上述的像素驱动电路。该显示装置包括：多条扫描线，用于提供扫描信号；多条数据线，用于提供数据信号；多个像素驱动电路，电连接于上述的扫描线和数据线；其中至少之一的像素驱动电路包括为本示例实施方式 中的上述任一像素驱动电路。在该像素驱动电通过数据信号对电容充电，并在写入阶段，通过电容中存储的数据信号将驱动晶体管导通，使得电容中存储的数据信号通过驱动晶体管下降至驱动晶体管的阈值电压，以将驱动晶体管的阈值电压写入第一节点，从而消除驱动晶体管的阈值电压对驱动电流的影响，保证了各个像素显示亮度的均一性；此外，在重置阶段，通过第一扫描信号和第三扫描信号将第一开关元件和第三开关元件导通，以将数据信号传输至第一节点、第二电源信号传输至第二节点，从而通过数据信号对第一节点进行重置(即对电容进行放电)，通过第二电源信号对第二节点进行重置，以消除上一帧信号对显示亮度的影响。所述显示装置例如可以包括手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要说明的是：所述显示装置中各模块单元的具体细节已经在对应的像素驱动电路中进行了详细的描述，因此这里不再赘述。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
此外，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (10)

  1. 一种像素驱动电路，其特征在于，所述像素驱动电路包括：
    第一开关元件，其控制端接收第一扫描信号，第一端与第一节点连接，第二端接收数据信号；
    第二开关元件，其控制端接收第二扫描信号，第一端与第二节点连接，第二端接收所述数据信号；
    第一补偿元件，其控制端与所述第二节点连接，第二端接收第一电源信号；
    第二补偿元件，其控制端和第一端均与所述第一节点连接，第二端与所述第一补偿元件的第一端连接；
    驱动晶体管，其控制端与所述第一节点连接，第一端与电致发光元件的第一极连接，第二端接收所述第一电源信号；
    电容，其第一端与所述驱动晶体管的控制端连接，第二端与所述驱动晶体管的第一端连接；
    第三开关元件，其控制端接收第三扫描信号，第一端与所述电致发光元件的第二极连接并接收第二电源信号，第二端与所述驱动晶体管的第一端连接；其中；
    所述第一补偿元件和所述第二补偿元件的导通电平与所述第一开关元件、所述第二开关元件、所述驱动晶体管和所述第三开关元件的导通电平相反。
  2. 根据权利要求1所述的像素驱动电路，其特征在于，所述像素驱动电路与第N行以及第N+1行扫描信号线连接；其中，第N行扫描信号线用于输出所述第二扫描信号，第N+1行扫描信号线用于输出所述第三扫描信号；N为正整数。
  3. 根据权利要求1所述的像素驱动电路，其特征在于，所述开关元件和所述驱动晶体管均为N型薄膜晶体管，所述补偿元件均为P型薄膜晶体管。
  4. 根据权利要求1所述的像素驱动电路，其特征在于，所述开关元件和所述驱动晶体管均为P型薄膜晶体管，所述补偿元件均为N型薄膜晶体管。
  5. 根据权利要求3或4所述的像素驱动电路，其特征在于，所述薄膜晶体管为非晶硅薄膜晶体管、多晶硅薄膜晶体管以及非晶-氧化铟镓锌薄膜晶体管中的一种。
  6. 一种像素驱动方法，用于驱动权利要求1所述的像素驱动电路，其特征在于，所述像素驱动方法包括：
    在重置阶段，第一扫描信号和第三扫描信号均为第一电平，第二扫描信号、数据信号以及第一电源信号均为第二电平，利用所述第一扫描信号导通第一开关元件，以使所述数据信号传输至第一节点，以使第二补偿元件在所述数据信号的 作用下导通，利用所述第三扫描信号导通第三开关元件，以使第二电源信号传输至第二节点，以使第一补偿元件在所述第二电源信号的作用下导通；
    在预充电阶段，所述第一扫描信号、所述第三扫描信号、所述数据信号以及所述第一电源信号均为所述第一电平，所述第二扫描信号为所述第二电平，利用所述第一扫描信号导通所述第一开关元件，以使所述数据信号传输至所述第一节点，以对电容充电，并使第二补偿元件在所述数据信号的作用下关断，利用所述第三扫描信号导通所述第三开关元件，以使所述第二电源信号传输至所述第二节点，以使所述第一补偿元件在所述第二电源信号的作用下导通；
    在写入阶段，所述第一扫描信号、所述第二扫描信号以及所述数据信号均为所述第二电平，所述第三扫描信号和所述第一电源信号均为所述第一电平，利用所述第三扫描信号导通所述第三开关元件，以使所述第二电源信号传输至所述第二节点，以使所述第一补偿元件在所述第二电源信号的作用下导通，所述驱动晶体管在所述电容中存储的所述数据信号的作用下导通，使得所述电容中存储的数据信号通过所述驱动晶体管下降至所述驱动晶体管的阈值电压；
    在自举发光阶段，所述第二扫描信号、所述数据信号以及所述第一电源信号均为所述第一电平，所述第一扫描信号和所述第三扫描信号均为第二电平，利用所述第二扫描信号导通所述第二开关元件，使得所述数据信号传输至所述第二节点，并通过所述电容的自举作用将所述第一节点的信号从所述驱动晶体管的阈值电压自举至所述驱动晶体管的阈值电压与所述数据信号之和，所述驱动晶体管在所述第一节点的信号的作用下导通，并在所述第一电源信号的作用下输出驱动电流以驱动电致发光元件发光；
    其中，所述第一开关元件至所述第三开关元件以及所述驱动晶体管在所述第一电平的作用下导通，所述第一补偿元件和第二补偿元件在所述第一电平的作用下关断，所述第一开关元件至所述第三开关元件以及驱动晶体管在所述第二电平的作用下关断，所述第一补偿元件和第二补偿元件在所述第二电平的作用下导通。
  7. 根据权利要求6所述的像素驱动方法，其特征在于，所述开关元件和所述驱动晶体管均为N型薄膜晶体管，所述补偿元件均为P型薄膜晶体管，所述第一电平为高电平、所述第二电平为低电平。
  8. 根据权利要求6所述的像素驱动方法，其特征在于，所述开关元件和所述驱动晶体管均为P型薄膜晶体管，所述补偿元件均为N型薄膜晶体管，所述第一电平为低电平，所述第二电平为高电平。
  9. 根据权利要求7或8所述的像素驱动方法，其特征在于，所述薄膜晶体管 为非晶硅薄膜晶体管、多晶硅薄膜晶体管以及非晶-氧化铟镓锌薄膜晶体管中的一种。
  10. 一种显示装置，其特征在于，包括权利要求1～5中任意一项所述的像素驱动电路。
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US11322082B2 (en) 2022-05-03
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