WO2019052008A1 - 一种阵列基板及其制备方法、显示装置 - Google Patents

一种阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2019052008A1
WO2019052008A1 PCT/CN2017/112628 CN2017112628W WO2019052008A1 WO 2019052008 A1 WO2019052008 A1 WO 2019052008A1 CN 2017112628 W CN2017112628 W CN 2017112628W WO 2019052008 A1 WO2019052008 A1 WO 2019052008A1
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Prior art keywords
layer
pattern layer
metal pattern
line pattern
buffer
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PCT/CN2017/112628
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English (en)
French (fr)
Inventor
石龙强
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/740,008 priority Critical patent/US10700102B2/en
Publication of WO2019052008A1 publication Critical patent/WO2019052008A1/zh

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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array, a method for fabricating the same, and a display device.
  • the size of the display is getting larger and larger, while the data line and the scan line of the large-sized display have a large resistance and capacitance load, and the excessive resistance and capacitance load will cause delay of the output waveform, resulting in abnormal display. .
  • the invention mainly provides an array substrate, a preparation method thereof and a display device, aiming at solving the problem that the resistance of the data line or the scan line is too large and the display is abnormal.
  • a technical solution adopted by the present invention is to provide an array substrate, wherein the array substrate includes a base substrate, a metal pattern layer, a data line pattern layer, and a scan line pattern layer; a metal pattern layer is disposed on the base substrate, the data line pattern layer is disposed in a different layer from the metal pattern layer and electrically connected to the metal pattern layer or the scan line pattern layer and the metal pattern layer are different A layer is disposed and electrically connected to the metal pattern layer.
  • another technical solution adopted by the present invention is to provide a display device, wherein the display device includes an array substrate, and the array substrate includes a base substrate, a metal pattern layer, a data line pattern layer, and a scan line pattern layer; wherein the metal pattern layer is disposed on the base substrate, the data line pattern layer is disposed in a different layer from the metal pattern layer and electrically connected to the metal pattern layer or the scan line.
  • the pattern layer and the metal pattern layer are disposed in different layers and are electrically connected to the metal pattern layer.
  • another technical solution adopted by the present invention is to provide a method for preparing an array substrate, the method comprising: depositing a metal on a substrate to form a metal pattern layer and a light shielding layer disposed at intervals; forming Covering a buffer layer of the metal pattern layer and opening a first via hole penetrating the buffer layer and communicating the metal pattern layer; forming an active layer and a first insulating layer stacked in a layer on the buffer layer; a gate lithography process respectively forming a gate pattern layer and a scan line pattern layer on the first insulating layer and the buffer layer, wherein the scan line pattern layer is electrically connected to the metal pattern layer through the first via hole Forming a second insulating layer on the buffer layer; forming a source pattern layer, a drain pattern layer, and a data line pattern layer on the second insulating layer.
  • the present invention provides a metal pattern layer on the substrate, the data line pattern layer and the metal pattern layer are disposed in different layers and electrically connected to the metal pattern layer or the scan line pattern layer and The metal pattern layer is disposed in a different layer and electrically connected to the metal pattern layer, such that the data line pattern layer or the scan line pattern layer and the metal pattern layer form a parallel structure, since the parallel structure has a resistance smaller than the data line pattern layer or the scan line pattern.
  • the layer resistance makes the resistance of the parallel structure used as a data line or a scan line small, thereby improving the display effect.
  • FIG. 1 is a schematic structural view of a first embodiment of an array substrate provided by the present invention.
  • FIG. 2 is a schematic structural view of a second embodiment of an array substrate provided by the present invention.
  • FIG. 3 is a schematic structural view of a third embodiment of an array substrate provided by the present invention.
  • FIG. 4 is a schematic structural view of a fourth embodiment of an array substrate provided by the present invention.
  • FIG. 5 is a schematic structural view of a fifth embodiment of an array substrate provided by the present invention.
  • FIG. 6 is a schematic structural diagram of an embodiment of a display device provided by the present invention.
  • FIG. 7 is a schematic flow chart of an embodiment of a method for preparing an array substrate provided by the present invention.
  • a first embodiment of an array substrate provided by the present invention includes a base substrate 101 , a metal pattern layer 102 , a scan line pattern layer 103 , and a data line pattern layer 104 .
  • the metal pattern layer 102 is disposed on the base substrate 101. Further, the base substrate 101 is further provided with a light shielding layer 105. The light shielding layer 105 is disposed in the same layer as the metal pattern layer 102 and formed by the same photolithography process.
  • a metal material layer may be deposited on the base substrate 101 by physical vapor deposition or plasma vapor deposition, and then a metal pattern layer is simultaneously formed on the base substrate 101 by a photolithography process of exposure, development, etching, and lift-off. 102 and a light shielding layer 105.
  • the metal material of the metal material layer is a metal material including, but not limited to, aluminum or molybdenum.
  • the scan line pattern layer 103 is electrically connected to the metal pattern layer 102.
  • the buffer layer 106 covering the metal pattern layer 102 is further disposed on the base substrate 101.
  • the buffer layer 106 is provided with a first via 1061 that penetrates the buffer layer 106 and communicates with the metal pattern layer 102.
  • the physical vapor phase can be used.
  • a silicon oxide layer covering the metal pattern layer 102 is deposited on the base substrate 101 by a deposition method or a plasma vapor deposition method to form a buffer layer 106.
  • a photolithography process by exposure, development, etching, and lift-off is performed.
  • the buffer layer 106 etches the first via 1061 that communicates with the metal pattern layer 102.
  • the scan line pattern layer 103 is disposed on the buffer layer 102 to be electrically connected to the metal pattern layer 102 through the first via 1061.
  • the buffer layer 106 is provided with an active layer 107, a first insulating layer 108 and a gate pattern layer 109 which are sequentially stacked, wherein the scan line pattern layer 103 and the gate pattern layer 109 are formed by the same photolithography process. .
  • IGZO is deposited on the buffer layer 106 at a position opposite to the light shielding layer 105 by physical vapor deposition, and then an IGZO pattern is formed on the buffer layer 106 by a photolithography process of exposure, development, etching, and lift-off.
  • a source layer 107 further, a silicon oxide is deposited on the active layer 107 by physical vapor deposition, and then a first insulating layer 108 is formed by a photolithography process of exposure, development, etching, and lift-off; on the first insulating layer 108, a buffer layer A metal material is deposited on the first via 1061, and then a gate pattern layer 109 and a scan line pattern layer 103 are formed on the first insulating layer 108 and the buffer layer 106 by photolithography processes of exposure, development, etching, and lift-off, respectively. At this time, the scan line pattern layer 103 formed on the buffer layer 106 can be electrically connected to the metal pattern layer 102 through the metal material in the first via 1061.
  • the metallic material is a metallic material including, but not limited to, aluminum or molybdenum.
  • the buffer layer 106 is further provided with a second insulating layer 110 covering the gate pattern layer 109.
  • the second insulating layer 110 is provided with a source pattern layer 111 and a drain pattern layer 112.
  • the data line pattern layer 104 is disposed on the buffer layer 106.
  • the source pattern layer 111 and the drain pattern layer 112 are formed by the same photolithography process.
  • silicon oxide may be deposited on the buffer layer 106 by physical vapor deposition, and a second insulating layer 110 covering the gate pattern layer 109 is formed on the buffer layer 106 by a photolithography process of exposure, development, etching, and lift-off, and then The source via 1101 and the drain via 1102 of the active layer 107 are opened in the photolithography process of the second insulating layer 110 by exposure, development, etching, and stripping, and finally by physical vapor deposition or plasma vapor deposition.
  • a metal material is deposited on the second insulating layer 110, the source via 1101 and the drain via 1102, and the source pattern layer 111 and the drain pattern layer 112 are simultaneously formed by a photolithography process of exposure, development, etching, and lift-off. And a data line pattern layer 104.
  • the scan line pattern layer 103 in this embodiment is electrically connected to the metal pattern layer 102 through the first via 1061 on the buffer layer 106 to form a parallel structure with the metal pattern layer 102, thereby causing the scan line pattern layer 103 and the metal pattern.
  • the parallel structure formed by the layers 102 has a resistance smaller than that of the scan line pattern layer 103.
  • a second embodiment of the array substrate provided by the present invention further includes a first conductive layer 213, which is disposed in the same layer as the active layer 207 and formed by the same photolithography process, and passes through the first The via 2061 is electrically connected to the metal pattern layer 202.
  • IGZO is deposited on the buffer layer 206 and in the first via 2061 by physical vapor deposition, and then subjected to photolithography by exposure, development, etching, and lift-off.
  • the process forms two IGZO patterns on the buffer layer 206, wherein the active layer 207 is located opposite to the light shielding layer 205, and the first conductive layer 213 is located at the first via 2061, and the first conductive layer 213 is
  • the metal pattern layer 202 can be electrically connected through the IGZO in the first via 2061.
  • the scan line pattern layer 203 in this embodiment is disposed on the first conductive layer 213 such that the scan line pattern layer 203 is electrically connected to the metal pattern layer 202 through the first conductive layer 213 to interact with the first conductive layer 213 and
  • the metal pattern layers 202 collectively form a parallel structure having a resistance smaller than that of the scan line pattern layer 203.
  • a third embodiment of the array substrate provided by the present invention includes a base substrate 301, a metal pattern layer 302, a scan line pattern layer 303, and a data line pattern layer 304.
  • the metal pattern layer 302 is disposed on the base substrate 301. Further, the base substrate 301 is further provided with a light shielding layer 305. The light shielding layer 305 is disposed in the same layer as the metal pattern layer 302 and formed by the same photolithography process.
  • a metal material layer may be deposited on the base substrate 301 by physical vapor deposition or plasma vapor deposition, and then a metal pattern layer is simultaneously formed on the base substrate 301 by a photolithography process of exposure, development, etching, and lift-off. 302 and a light shielding layer 305.
  • the metal material of the metal material layer is a metal material including, but not limited to, aluminum or molybdenum.
  • the light shielding layer 305 is provided with an active layer 306, a first insulating layer 307 and a gate pattern layer 308 which are sequentially stacked.
  • the scanning line pattern layer 303 is disposed on the base substrate 301 and is identical to the gate pattern layer 308. A lithography process is formed.
  • the active layer 306 can be formed by depositing IGZO on the light shielding layer by physical vapor deposition, and then forming an IGZO pattern by a photolithography process of exposure, development, etching, and lift-off; and further active by physical vapor deposition.
  • a silicon oxide is deposited on the layer 306, and then a first insulating layer 307 is formed by a photolithography process of exposure, development, etching, and lift-off; a metal material is deposited on the first insulating layer 307 and the base substrate 301, and then exposed, developed, and etched.
  • a lift-off photolithography process forms a gate pattern layer 308 and a scan line pattern layer 303 on the first insulating layer 307 and the base substrate 301, respectively.
  • the array substrate of the present embodiment further includes a second insulating layer 309 and a source pattern layer 310 and a drain pattern layer 311 disposed on the second insulating layer 309.
  • the data pattern layer 304 is disposed on the second insulating layer 309.
  • the source pattern layer 310 and the drain pattern layer 311 are formed by the same photolithography process, wherein the second insulating layer 309 is provided with a second via hole 3091 extending through the second insulating layer 309 and communicating with the metal pattern layer 302.
  • the data line pattern layer 304 is electrically connected to the metal pattern layer 302 through the second via hole 3091.
  • silicon nitride covering the gate pattern layer 308 may be formed on the base substrate 301 by physical vapor deposition, and the second insulating layer 309 may be formed by a photolithography process of exposure, development, etching, and lift-off, and then exposed. a lithography process of developing, etching, and stripping, opening a second via 3091 that communicates with the metal pattern layer 302 through the second insulating layer 309, and a source via 3092 and a drain via 3093 that communicate with the active layer 306.
  • a metal is deposited on the second insulating layer 309, the second via 3091, the source via 3092 and the drain via 3093, and is exposed to the second insulating layer by a photolithography process of exposure, development, etching and stripping.
  • the source pattern layer 310, the drain pattern layer 311 and the data line pattern layer 304 are simultaneously formed on the 309, and the data line pattern layer 304 can be electrically connected to the metal pattern layer 302 through the metal material in the second via 3091 to
  • the metal pattern layer 302 forms a parallel structure having a resistance smaller than that of the data line pattern layer 304.
  • the fourth embodiment of the array substrate provided by the present invention further includes a buffer layer 412 disposed on the base substrate 401 and covering the metal pattern layer 402 .
  • the buffer layer 412 is provided with a third via 4121 extending through the buffer layer 412 and communicating with the metal pattern layer 402. Further, the second insulating layer 409 is disposed on the buffer layer 412, and the second via 4091 and the third via The holes 4121 are in communication such that the data line pattern layer 404 is electrically connected to the metal pattern layer 402 through the second vias 4091 and the third vias 4121.
  • the metal material is deposited in the second via hole 4091 and the third via hole 4121 at the same time, that is, when the data line pattern layer 404 is formed,
  • the metal material in the second via 4091 and the third via 4121 is electrically connected to the metal pattern layer 402.
  • the fifth embodiment of the array substrate provided by the present invention further includes a second conductive layer 513 disposed in the same layer as the active layer 506 and formed by the same photolithography process, and located in the second The via hole 5091 and the third via hole 5121 are connected such that the data line pattern layer 504 is electrically connected to the metal pattern layer 502 through the second conductive layer 513.
  • IGZO is simultaneously deposited in the third via 5121, and then the active layer 506 can be simultaneously formed by photolithography processes of exposure, development, etching, and lift-off.
  • the second conductive layer 513 the second conductive layer 513 can be electrically connected to the metal pattern layer 502 through the IGZO in the third via 521.
  • the data line pattern layer 504 passes.
  • the second via 5091 is electrically connected to the second conductive layer 513, and the data line pattern layer 504 is electrically connected to the metal pattern layer 502 through the second conductive layer 513.
  • the data line pattern layer 504 in this embodiment is electrically connected to the metal pattern layer 502 through the second conductive layer 513 to electrically connect with the second conductive layer 513 and the metal pattern layer 502 to form a parallel structure, and the resistance of the parallel structure is smaller than The resistance of the data line pattern layer 504.
  • the display device embodiment provided by the present invention includes a backlight module 100 and the array substrate 200 in any of the above embodiments.
  • an embodiment of a method for fabricating an array substrate provided by the present invention includes:
  • S11 depositing a metal on the base substrate 101 to form a spaced-apart metal pattern layer 102 and a light shielding layer 105;
  • the present invention provides a metal pattern layer on a substrate, the data line pattern layer and the metal pattern layer are disposed in different layers and electrically connected to the metal pattern layer or the scan line pattern layer and the metal pattern layer are disposed in different layers and
  • the method of electrically connecting to the metal pattern layer is such that the data line pattern layer or the scan line pattern layer and the metal pattern layer form a parallel structure, and the parallel structure is made because the resistance of the parallel structure is smaller than the data line pattern layer or the scan line pattern layer resistance.

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Abstract

本发明提供一种阵列基板及其制备方法、显示装置，该阵列基板包括包括衬底基板、金属图案层、数据线图案层及扫描线图案层，金属图案层设置于衬底基板上，数据线图案层与金属图案层异层设置且与金属图案层电连接或扫描线图案层与金属图案层异层设置且与金属图案层电连接，使得数据线图案层或扫描线图案层与金属图案层形成一个并联结构，由于该并联结构的电阻小于数据线图案层或扫描线图案层电阻，使得该并联结构作为数据线或扫描线使用时的电阻变小，提高显示效果。

Description

一种阵列基板及其制备方法、显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列及其制备方法、显示装置。
【背景技术】
随着科技的发展，显示器的尺寸越来越大，而大尺寸的显示器中数据线及扫描线有着很大的电阻电容负载，过大的电阻电容负载会造成输出波形的延迟，导致显示的异常。
【发明内容】
本发明主要提供一种阵列基板及其制备方法、显示装置，旨在解决数据线或扫描线的电阻过大而导致显示异常的问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，其中，所述阵列基板包括衬底基板、金属图案层、数据线图案层及扫描线图案层；其中，所述金属图案层设置于所述衬底基板上，所述数据线图案层与所述金属图案层异层设置且与所述金属图案层电连接或所述扫描线图案层与所述金属图案层异层设置且与所述金属图案层电连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示装置，其中，所述显示装置包括阵列基板，所述阵列基板包括衬底基板、金属图案层、数据线图案层及扫描线图案层；其中，所述金属图案层设置于所述衬底基板上，所述数据线图案层与所述金属图案层异层设置且与所述金属图案层电连接或所述扫描线图案层与所述金属图案层异层设置且与所述金属图案层电连接。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种阵列基板的制备方法，所述方法包括：在衬底基板上沉积金属以形成间隔设置的金属图案层与遮光层；形成覆盖所述金属图案层的缓冲层并开设贯穿所述缓冲层且连通所述金属图案层的第一过孔；在所述缓冲层依次形成层叠设置的有源层及第一绝缘层；通过同一道光刻工艺分别在所述第一绝缘层与所述缓冲层上形成栅极图案层和扫描线图案层，所述扫描线图案层通过所述第一过孔与所述金属图案层电连接；在所述缓冲层上形成第二绝缘层；在所述第二绝缘层上形成源极图案层、漏极图案层和数据线图案层。
本发明的有益效果是：区别于现有技术的情况，本发明通过在基板上设置金属图案层，数据线图案层与金属图案层异层设置且与金属图案层电连接或扫描线图案层与金属图案层异层设置且与金属图案层电连接的方法，使得数据线图案层或扫描线图案层与金属图案层形成一个并联结构，由于该并联结构的电阻小于数据线图案层或扫描线图案层电阻，使得该并联结构作为数据线或扫描线使用时的电阻变小，提高显示效果。
【附图说明】
图1是本发明提供的阵列基板第一实施例的结构示意图；
图2是本发明提供的阵列基板第二实施例的结构示意图；
图3是本发明提供的阵列基板第三实施例的结构示意图；
图4是本发明提供的阵列基板第四实施例的结构示意图；
图5是本发明提供的阵列基板第五实施例的结构示意图
图6是本发明提供的显示装置实施例的结构示意图；
图7是本发明提供的阵列基板的制备方法实施例的流程示意图。
【具体实施方式】
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所提供的一种阵列基板及其制备方法、显示装置做进一步详细描述。
参阅图1，本发明提供的阵列基板第一实施例包括衬底基板101、金属图案层102、扫描线图案层103及数据线图案层104。
其中，金属图案层102设置于衬底基板101上，进一步的，衬底基板101上还设有遮光层105，遮光层105与金属图案层102同层间隔设置且通过同一道光刻工艺形成。
具体的，可通过物理气相沉积法或等离子体气相沉积法在衬底基板101上沉积金属材料层，然后通过曝光、显影、蚀刻及剥离的光刻工艺在衬底基板101上同时形成金属图案层102以及遮光层105。
可选的，金属材料层的金属材料为包括但不限于铝或钼的金属材料。
进一步的，扫描线图案层103与金属图案层102电连接。
具体的，衬底基板101上还设有覆盖金属图案层102的缓冲层106，缓冲层106设有贯穿缓冲层106且连通金属图案层102的第一过孔1061，具体的，可使用物理气相沉积法或等离子体气相沉积法在衬底基板101上沉积覆盖金属图案层102的氧化硅层以形成缓冲层106，在形成缓冲层106之后，通过曝光、显影、蚀刻及剥离的光刻工艺在缓冲层106蚀刻出连通金属图案层102的第一过孔1061，扫描线图案层103设置于缓冲层102上以通过第一过孔1061与金属图案层102电连接。
进一步的，缓冲层106上设有依次层叠设置的有源层107、第一绝缘层108及栅极图案层109，其中，扫描线图案层103与栅极图案层109通过同一道光刻工艺形成。
具体的，在缓冲层106上且与遮光层105相对的位置通过物理气相沉积法沉积IGZO，然后通过曝光、显影、蚀刻及剥离的光刻工艺在缓冲层106上形成IGZO图案，即可形成有源层107；进而通过物理气相沉积法在有源层107上沉积氧化硅，然后通过曝光、显影、蚀刻及剥离的光刻工艺形成第一绝缘层108；在第一绝缘层108上、缓冲层106上以及第一过孔1061中沉积金属材料，然后通过曝光、显影、蚀刻及剥离的光刻工艺分别在第一绝缘层108和缓冲层106上形成栅极图案层109以及扫描线图案层103，此时，在缓冲层106上形成的扫描线图案层103即可通过第一过孔1061中的金属材料与金属图案层102电连接。
可选的，金属材料为包括但不限于铝或钼的金属材料。
进一步的，缓冲层106上还设有覆盖栅极图案层109的第二绝缘层110，第二绝缘层110上设有源极图案层111和漏极图案层112，其中，数据线图案层104与源极图案层111和漏极图案层112通过同一道光刻工艺形成。
具体的，可通过物理气相沉积法在缓冲层106上沉积氧化硅，通过曝光、显影、蚀刻及剥离的光刻工艺在缓冲层106上形成覆盖栅极图案层109的第二绝缘层110，然后在第二绝缘层110通过曝光、显影、蚀刻及剥离的光刻工艺开设连通有源层107的源极过孔1101及漏极过孔1102，最后可通过物理气相沉积法或等离子体气相沉积法在第二绝缘层110上、源极过孔1101及漏极过孔1102中沉积金属材料，并通过曝光、显影、蚀刻及剥离的光刻工艺同时形成源极图案层111、漏极图案层112以及数据线图案层104。
本实施例中的扫描线图案层103在缓冲层106上通过第一过孔1061与金属图案层102电连接，以与金属图案层102形成一个并联结构，进而使得扫描线图案层103与金属图案层102共同形成的并联结构的电阻小于扫描线图案层103的电阻。
参阅图2，本发明提供的阵列基板第二实施例进一步包括第一导电层213，该第一导电层213与有源层207同层间隔设置且通过同一道光刻工艺形成，并通过第一过孔2061与金属图案层202电连接。
具体的，在如上述第一实施例中形成有源层207时，通过物理气相沉积法在缓冲层206上以及第一过孔2061中沉积IGZO，然后通过曝光、显影、蚀刻及剥离的光刻工艺在缓冲层206上形成两个IGZO图案，其中与遮光层205相对位置的即为有源层207，位于第一过孔2061处的即为第一导电层213，该第一导电层213即可通过第一过孔2061中的IGZO与金属图案层202电连接。
进一步的，本实施例中的扫描线图案层203设置于第一导电层213上，使得扫描线图案层203通过第一导电层213与金属图案层202电连接，以与第一导电层213和金属图案层202共同形成一个并联结构，该并联结构的电阻小于扫描线图案层203的电阻。
本实施例中的其他结构与上述第一实施例相同，在此不再赘述。
参阅图3，本发明提供的阵列基板第三实施例包括衬底基板301、金属图案层302、扫描线图案层303及数据线图案层304。
其中，金属图案层302设置于衬底基板301上，进一步的，衬底基板301上还设有遮光层305，遮光层305与金属图案层302同层间隔设置且通过同一道光刻工艺形成。
具体的，可通过物理气相沉积法或等离子体气相沉积法在衬底基板301上沉积金属材料层，然后通过曝光、显影、蚀刻及剥离的光刻工艺在衬底基板301上同时形成金属图案层302以及遮光层305。
可选的，金属材料层的金属材料为包括但不限于铝或钼的金属材料。
进一步的，遮光层305上设有依次层叠的有源层306、第一绝缘层307以及栅极图案层308，扫描线图案层303设置于衬底基板301上且与栅极图案层308通过同一道光刻工艺形成。
具体的，可通过物理气相沉积法在遮光层上沉积IGZO，然后通过曝光、显影、蚀刻及剥离的光刻工艺形成IGZO图案，即可形成有源层306；进而通过物理气相沉积法在有源层306上沉积氧化硅，然后通过曝光、显影、蚀刻及剥离的光刻工艺形成第一绝缘层307；在第一绝缘层307以及衬底基板301上沉积金属材料，然后通过曝光、显影、蚀刻及剥离的光刻工艺分别在第一绝缘层307和衬底基板301上形成栅极图案层308以及扫描线图案层303。
进一步的，本实施例的阵列基板还包括第二绝缘层309以及设置于第二绝缘层309上的源极图案层310和漏极图案层311，数据图案层304设置于第二绝缘层309上且与源极图案层310和漏极图案层311通过同一道光刻工艺形成，其中，第二绝缘层309上设有贯穿第二绝缘层309且连通金属图案层302的第二过孔3091，数据线图案层304通过该第二过孔3091与金属图案层302电连接。
具体的，可通过物理气相沉积法在衬底基板301上形成覆盖栅极图案层308的氮化硅，并通过曝光、显影、蚀刻及剥离的光刻工艺形成第二绝缘层309，然后通过曝光、显影、蚀刻及剥离的光刻工艺开设贯穿第二绝缘层309且与金属图案层302连通的第二过孔3091、与有源层306连通的源极过孔3092和漏极过孔3093，最后在第二绝缘层309上、第二过孔3091、源极过孔3092和漏极过孔3093中沉积金属，并通过曝光、显影、蚀刻及剥离的光刻工艺即可在第二绝缘层309上同时形成源极图案层310、漏极图案层311和数据线图案层304，该数据线图案层304即可通过第二过孔3091中的金属材料与金属图案层302电连接，以与金属图案层302形成一个并联结构，该并联结构的电阻小于数据线图案层304的电阻。
参阅图4，本发明提供的阵列基板第四实施例进一步包括缓冲层412，缓冲层412设置于衬底基板401上且覆盖金属图案层402。
其中，缓冲层412设有贯穿缓冲层412且与金属图案层402连通的第三过孔4121，进一步的，第二绝缘层409设置于缓冲层412上，且第二过孔4091与第三过孔4121连通，以使得数据线图案层404通过第二过孔4091与第三过孔4121与金属图案层402电连接。
具体的，在如上述第三实施例中形成数据线图案层404时，同时在第二过孔4091和第三过孔4121中沉积金属材料，即可在形成数据线图案层404时，通过第二过孔4091和第三过孔4121中的金属材料与金属图案层402电连接。
本实施例中的其他结构与上述第三实施例相同，在此不再赘述。
参阅图5，本发明提供的阵列基板第五实施例进一步包括第二导电层513，该第二导电层513与有源层506同层间隔设置且通过同一道光刻工艺形成，并位于第二过孔5091和第三过孔5121之间，以使得数据线图案层504通过第二导电层513与金属图案层502电连接。
具体的，在如上述第三实施例中形成有源层506时，在第三过孔5121中同时沉积IGZO，然后通过曝光、显影、蚀刻及剥离的光刻工艺即可同时形成有源层506和第二导电层513，该第二导电层513即可通过第三过孔5121中的IGZO与金属图案层502电连接，同理，在形成数据线图案层504时，数据线图案层504通过第二过孔5091与第二导电层513电连接，进而数据线图案层504通过第二导电层513与金属图案层502电连接。
本实施例中的数据线图案层504通过第二导电层513与金属图案层502电连接，以与第二导电层513与金属图案层502电连接共同形成一个并联结构，该并联结构的电阻小于数据线图案层504的电阻。
本实施例中的其他结构与上述第四实施例相同，在此不再赘述。
参阅图6，本发明提供的显示装置实施例包括背光模组100及上述任一实施例中的阵列基板200。
共同参阅图1和图7，本发明提供的阵列基板的制备方法实施例包括：
S11：在衬底基板101上沉积金属以形成间隔设置的金属图案层102与遮光层105；
S12：形成覆盖金属图案层102的缓冲层106并开设贯穿缓冲层106且连通金属图案层102的第一过孔1061；
S13：在缓冲层106上依次形成层叠设置的有源层107及第一绝缘层108；
S14：通过同一道光刻工艺分别在第一绝缘层108与缓冲层106上形成栅极图案层109和扫描线图案层103，扫描线图案层103通过第一过孔1061与金属图案层102电连接；
S15：在缓冲层106上形成覆盖栅极图案层109的第二绝缘层110；
S16：在第二绝缘层110上形成源极图案层111、漏极图案层112及数据线图案层104。
本实施例中各步骤的详细实施方法可参阅上述阵列基板第一实施例中的描述，在此不再赘述。
区别于现有技术的情况，本发明通过在基板上设置金属图案层，数据线图案层与金属图案层异层设置且与金属图案层电连接或扫描线图案层与金属图案层异层设置且与金属图案层电连接的方法，使得数据线图案层或扫描线图案层与金属图案层形成一个并联结构，由于该并联结构的电阻小于数据线图案层或扫描线图案层电阻，使得该并联结构作为数据线或扫描线使用时的电阻变小，提高显示效果。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (17)

  1. 一种阵列基板，其中，所述阵列基板包括衬底基板、金属图案层、数据线图案层及扫描线图案层；
    其中，所述金属图案层设置于所述衬底基板上，所述数据线图案层与所述金属图案层异层设置且与所述金属图案层电连接或所述扫描线图案层与所述金属图案层异层设置且与所述金属图案层电连接。
  2. 根据权利要求1所述的基板，其特征在于，所述衬底基板上设有遮光层，所述金属图案层与所述遮光层同层间隔设置且通过同一道光刻工艺形成。
  3. 根据权利要求2所述的基板，其特征在于，所述衬底基板上设有覆盖所述金属图案层的缓冲层，所述缓冲层上设有依次层叠的有源层、第一绝缘层及栅极图案层，所述扫描线图案层与所述栅极图案层通过同一道光刻工艺形成。
  4. 根据权利要求3所述的阵列基板，其中，所述缓冲层设有贯穿所述缓冲层且连通所述金属图案层的第一过孔，所述扫描线图案层通过所述第一过孔与所述金属图案层电连接。
  5. 根据权利要求4所述的阵列基板，其中，所述缓冲层上还设有与所述有源层间隔设置且通过同一道光刻工艺形成的第一导电层，所述第一导电层通过所述第一过孔与所述金属图案层电连接，所述扫描线图案层设置于所述第一导电层上。
  6. 根据权利要求2所述的阵列基板，其中，所述阵列基板进一步包括第二绝缘层以及设置于所述第二绝缘层上的源极图案层和漏极图案层，所述数据线图案层设置于所述第二绝缘层上且与所述源极图案层和漏极图案层通过同一道光刻工艺形成，所述第二绝缘层设有贯穿所述第二绝缘层且与所述金属图案层连通的第二过孔，所述数据线图案层通过所述第二过孔与所述金属图案层电连接。
  7. 根据权利要求6所述的阵列基板，其中，所述第二绝缘层设置于所述缓冲层上，所述缓冲层设有贯穿所述缓冲层且与所述金属图案层连通的第三过孔，所述第三过孔与所述第二过孔连通，以使得所述数据线图案层通过所述第三过孔与所述第二过孔与所述金属图案层电连接。
  8. 根据权利要求7所述的阵列基板，其中，所述缓冲层上设有第二导电层，所述第二导电层与所述有源层间隔设置且通过同一道光刻工艺形成，所述第二导电层位于所述第二过孔和所述第三过孔之间，以使得所述数据线图案层通过所述第二导电层与所述金属图案层电连接。
  9. 一种显示装置，其中，所述显示装置包括阵列基板，所述阵列基板包括衬底基板、金属图案层、数据线图案层及扫描线图案层；
    其中，所述金属图案层设置于所述衬底基板上，所述数据线图案层与所述金属图案层异层设置且与所述金属图案层电连接或所述扫描线图案层与所述金属图案层异层设置且与所述金属图案层电连接。
  10. 根据权利要求9所述的显示装置，其中，所述衬底基板上设有遮光层，所述金属图案层与所述遮光层同层间隔设置且通过同一道光刻工艺形成。
  11. 根据权利要求10所述的显示装置，其中，所述衬底基板上设有覆盖所述金属图案层的缓冲层，所述缓冲层上设有依次层叠的有源层、第一绝缘层及栅极图案层，所述扫描线图案层与所述栅极图案层通过同一道光刻工艺形成。
  12. 根据权利要求11所述的显示装置，其中，所述缓冲层设有贯穿所述缓冲层且连通所述金属图案层的第一过孔，所述扫描线图案层通过所述第一过孔与所述金属图案层电连接。
  13. 根据权利要求12所述的显示装置，其中，所述缓冲层上还设有与所述有源层间隔设置且通过同一道光刻工艺形成的第一导电层，所述第一导电层通过所述第一过孔与所述金属图案层电连接，所述扫描线图案层设置于所述第一导电层上。
  14. 根据权利要求10所述的显示装置，其中，所述阵列基板进一步包括第二绝缘层以及设置于所述第二绝缘层上的源极图案层和漏极图案层，所述数据线图案层设置于所述第二绝缘层上且与所述源极图案层和漏极图案层通过同一道光刻工艺形成，所述第二绝缘层设有贯穿所述第二绝缘层且与所述金属图案层连通的第二过孔，所述数据线图案层通过所述第二过孔与所述金属图案层电连接。
  15. 根据权利要求14所述的显示装置，其中，所述衬底基板上还设有覆盖所述金属图案层的缓冲层，所述第二绝缘层设置于所述缓冲层上，所述缓冲层设有贯穿所述缓冲层且与所述金属图案层连通的第三过孔，所述第三过孔与所述第二过孔连通，以使得所述数据线图案层通过所述第三过孔与所述第二过孔与所述金属图案层电连接。
  16. 根据权利要求15所述的显示装置，其中，所述缓冲层上设有有源层及第二导电层，所述第二导电层与所述有源层间隔设置且通过同一道光刻工艺形成，所述第二导电层位于所述第二过孔和所述第三过孔之间，以使得所述数据线图案层通过所述第二导电层与所述金属图案层电连接。
  17. 一种阵列基板的制备方法，其中，所述方法包括：
    在衬底基板上沉积金属以形成间隔设置的金属图案层与遮光层；
    形成覆盖所述金属图案层的缓冲层并开设贯穿所述缓冲层且连通所述金属图案层的第一过孔；
    在所述缓冲层依次形成层叠设置的有源层及第一绝缘层；
    通过同一道光刻工艺分别在所述第一绝缘层与所述缓冲层上形成栅极图案层和扫描线图案层，所述扫描线图案层通过所述第一过孔与所述金属图案层电连接；
    在所述缓冲层上形成第二绝缘层；
    在所述第二绝缘层上形成源极图案层、漏极图案层和数据线图案层。
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