WO2019042429A1 - 集成电路芯片及其制作方法、栅驱动电路 - Google Patents

集成电路芯片及其制作方法、栅驱动电路 Download PDF

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WO2019042429A1
WO2019042429A1 PCT/CN2018/103620 CN2018103620W WO2019042429A1 WO 2019042429 A1 WO2019042429 A1 WO 2019042429A1 CN 2018103620 W CN2018103620 W CN 2018103620W WO 2019042429 A1 WO2019042429 A1 WO 2019042429A1
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conductivity type
high voltage
integrated circuit
circuit chip
drain
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PCT/CN2018/103620
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English (en)
French (fr)
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顾力晖
张森
齐从明
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无锡华润上华科技有限公司
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Priority to US16/643,170 priority Critical patent/US11056402B2/en
Priority to JP2020512468A priority patent/JP6966635B2/ja
Publication of WO2019042429A1 publication Critical patent/WO2019042429A1/zh

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    • H—ELECTRICITY
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to an integrated circuit chip, a method for fabricating the same, and a gate driving circuit.
  • FIG. 1A shows a gate driving circuit 100a formed using a high voltage integrated circuit chip (HVIC) including a high voltage integrated circuit chip 10a, a resistor R1, a bootstrap diode D1, a bootstrap capacitor C1, a first power transistor P1, and a second Power tube P2.
  • the high voltage integrated circuit chip 10a has a low side power supply terminal VCC, a high side power supply terminal VB, a floating power supply terminal VS, a high side output HO, a low side output LO, and a ground terminal COM, and each device is connected as shown in FIG. 1A.
  • the voltage of VS is periodically floating between low voltage and high voltage.
  • the low side power supply terminal VCC charges the bootstrap capacitor C1 through the bootstrap diode D1 to make its potential close to VCC.
  • Supply power to the high-side power supply VB when the VS terminal voltage floats to high voltage, the charge stored by the bootstrap capacitor acts as the VS voltage exceeds the VCC voltage, and the diode enters the reverse-off state.
  • the VB of both ends of the bootstrap capacitor C1 is passed.
  • the voltage difference between VSs is still approximately equal to VCC, thereby powering the high side control circuitry. Therefore, bootstrap diodes need to withstand high voltages, usually by means of external discrete devices.
  • An integrated circuit chip comprising:
  • the depletion type a source of the MOS device is connected to a high side power terminal of the integrated circuit chip
  • a bipolar transistor having a collector and a base shorted and connected to a power supply terminal of the integrated circuit chip, the emitter of the bipolar transistor being coupled to a gate of the depletion MOS device.
  • a method of fabricating an integrated circuit chip including:
  • a high voltage junction terminal in the semiconductor substrate Forming a high voltage junction terminal in the semiconductor substrate, the high voltage junction terminal surrounding the high voltage island, forming a depletion mode MOS device in the high voltage junction terminal, a gate and a drain of the depletion mode MOS device Shorting, a source of the depletion MOS device is connected to a high side power terminal of the integrated circuit chip;
  • a gate driving circuit comprising the integrated circuit chip as described above, and a resistor, a bootstrap capacitor, a first power tube and a second power tube, wherein the power terminal of the integrated circuit chip passes through a resistor a working power connection, a first end of the bootstrap capacitor is connected to a high side power terminal of the integrated circuit chip, and a second end of the bootstrap capacitor is connected to a floating power end of the integrated circuit chip, where the a gate of a power tube is connected to a high-end output of the integrated circuit chip, a source of the first power tube is connected to the working power source, a drain of the first power tube is connected to the integrated circuit chip a floating power supply terminal and a drain connection of the second power tube, a gate of the second power tube is connected to a low end output of the integrated circuit chip, and a source of the second power tube is integrated with the The ground terminal of the circuit chip is connected.
  • FIG. 1A shows a schematic circuit diagram of a gate drive circuit in the conventional art
  • FIG. 1B shows a schematic circuit diagram of a gate drive circuit in accordance with an embodiment of the present invention
  • 2A is a schematic plan view showing a high voltage island and a high voltage junction terminal of an integrated circuit chip in the conventional art
  • FIG. 2B shows a schematic plan view of a high voltage island and a high voltage junction terminal in accordance with an embodiment of the present invention
  • 3A is a cross-sectional view of the high voltage junction terminal of the integrated circuit chip shown in FIG. 2A taken along the A-A direction;
  • 3B is a cross-sectional view of the high voltage junction terminal of the integrated circuit chip shown in FIG. 2B taken along line B-B;
  • FIG. 4 is a flow chart showing schematic steps of a method of fabricating an integrated circuit chip in accordance with an embodiment of the present invention.
  • Spatial relationship terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., may be used herein for convenience of description. The relationship of one element or feature shown in the figures to the other elements or features is thus described. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned “on” or “below” or “below” or “under” the element or feature is to be “on” the other element or feature.
  • the exemplary terms “below” and “include” can include both the above and the The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein interpreted accordingly.
  • composition and/or “comprising”, when used in the specification, is used to determine the presence of the features, integers, steps, operations, components and/or components, but does not exclude one or more The presence or addition of features, integers, steps, operations, components, components, and/or groups.
  • the term “and/or” includes any and all combinations of the associated listed items.
  • the present embodiment provides an integrated circuit chip and a gate driving circuit formed using the integrated circuit chip.
  • the integrated circuit chip has a bootstrap device formed therein, thereby eliminating the need to use an external bootstrap diode, thereby avoiding the use of the bootstrap diode.
  • the external bootstrap diode causes the design of the application system circuit to be complicated and difficult to debug, and the cost is high.
  • the purpose of this embodiment is achieved by designing a high-voltage-resistant depletion NMOS device, which is integrated with the high-voltage island of the high-voltage integrated circuit, substantially without increasing the layout area of the chip, and providing a Use the circuit structure of the device.
  • FIGS. 1B to 3B An integrated circuit chip according to an embodiment of the present invention and a bootstrap circuit formed using the integrated circuit chip will be described below with reference to FIGS. 1B to 3B.
  • the present embodiment discloses a bootstrap circuit 100b in which an integrated circuit chip 10b is used to form a bipolar transistor Q1 and a high voltage-resistant depletion NMOS device N1.
  • the connection relationship of the gate driving circuit shown in FIG. 1B is that the collector and the base of the bipolar transistor Q1 are short-circuited and connected to the low-side power supply terminal VCC of the integrated circuit chip 10b, and the bipolar transistor Q1 is An emitter is connected to a gate of the depletion mode MOS device N1, a gate and a drain of the depletion mode MOS device N1 are shorted, a source of the depletion mode MOS device and the integrated circuit chip 10b
  • the high side power supply terminal VB is connected.
  • the low-side power supply terminal VCC of the integrated circuit chip 10b is connected to an operating power source (for example, an external working power supply of 600V voltage) through a resistor R1, and the high-side power supply terminal VB of the integrated circuit chip 10b and the first end of the bootstrap capacitor C1.
  • an operating power source for example, an external working power supply of 600V voltage
  • the floating power terminal VS of the integrated circuit chip 10b is connected to the second end of the bootstrap capacitor C1
  • the high-end output HO of the integrated circuit chip 10b is connected to the gate of the first power tube P1.
  • a source of the power tube P1 is connected to the working power source, and a drain of the first power tube P is connected to the floating power terminal VS of the integrated circuit chip 10b and the drain of the second power tube P2.
  • the low-side output LO of the integrated circuit chip 10b is connected to the gate of the second power transistor P2, and the source of the second power transistor P2 is connected to the ground terminal COM of the integrated circuit chip 10b
  • the principle of the bootstrap circuit 100b shown in FIG. 1B is that the VS terminal level of the integrated circuit chip 10b periodically floats between a low level and a high voltage, and when the VS terminal is at a low level, the bipolar transistor Q1 In the forward conduction state, the depletion-type high-voltage NMOS device N1 is turned on, so that the operating power supply charges the bootstrap capacitor C1 connected between both ends of VB and VS. When the VS terminal floats to the high voltage, the voltage of the VB terminal is increased synchronously under the action of the bootstrap capacitor C1.
  • the bipolar transistor Q1 When the potential of the VS terminal exceeds the VCC terminal, the bipolar transistor Q1 enters the reverse bias cutoff, and the VS terminal voltage further rises, and the depletion high voltage
  • the NMOS device N1 is turned off due to the shimming action, so that the device (i.e., the integrated circuit chip 10b) provided by the present invention can constitute the gate driving circuit of Fig. 1B, thereby eliminating the external discrete bootstrap diode.
  • the integrated circuit chip 10b typically includes a control circuit, a low side drive circuit, a high side drive circuit, and a level shift circuit that passes the low side control signal of the control circuit to the high side drive circuit.
  • the high side driving circuit is formed in the high voltage island of the chip or the semiconductor substrate, and the potential is a floating potential, which is usually surrounded by a high voltage junction terminal to withstand high voltage, and functions to isolate the high side driving circuit and the low side driving circuit.
  • the bipolar transistor Q1 of the high voltage integrated circuit chip 10b is fabricated in a low voltage region of the integrated circuit chip, and the high voltage depletion NMOS device N1 is simultaneously used as a high voltage junction terminal of the high voltage island of the integrated circuit chip, thereby substantially not increasing. Layout area.
  • the bipolar transistor Q1 can be implemented by a standard bipolar transistor of the BCD process platform, and will not be described here.
  • the high voltage island and the high voltage junction terminal of the integrated circuit chip 10b of the present embodiment will be described below with reference to FIGS. 2A to 3B, and the difference between the high voltage island and the high voltage junction terminal of the current high voltage integrated circuit chip 10a will be described.
  • Figure 2A is a schematic top view of a conventional high voltage island and high voltage junction terminal
  • Figure 2B is a schematic top view of a high voltage island and high voltage junction terminal proposed in the present embodiment.
  • the conventional high voltage island (exemplarily quadrangular) 101a shown in Fig. 2A is surrounded by a high voltage junction terminal (exemplarily quadrangular) 102a, typically integrated on one side of the high voltage junction terminal 102a, such as part 103a of Fig. 2A.
  • the flat shifting device such as the LDMOS device, and the other three sides of the high voltage junction terminal 102a, such as 104a in Fig.
  • 2A are conventional withstand voltage junction terminals, ensuring the withstand voltage of the high voltage island.
  • 2B shows the high voltage island 101b proposed in the embodiment, which integrates a depletion type high voltage NMOS device on three sides 104b of the high voltage junction terminal 102b, and also integrates two high voltage electric translations on the other side of the high voltage junction terminal.
  • the bit device 103b as can be seen from FIG. 2B, the present embodiment utilizes a 3-side high-voltage junction terminal of a conventional high-voltage island without a device, and a high-voltage-resistant depletion NMOS device is disposed on the 3-side high-voltage junction terminal without additional Area.
  • FIG. 3A is a schematic diagram of a conventional high-voltage junction terminal structure corresponding to the cross-sectional position AA of FIG. 2A, the basic structure of which includes a p-type substrate 103, which is located in the P-type substrate 103.
  • the high voltage N well 107 is used as a drift region, and a low voltage N well 108 is formed therein, and a P+ active region 110a is formed in the P well 106 for extracting the P well and connecting to the P substrate to be formed in the low voltage N well 108.
  • the N+ active region 110b is used to extract an N well, that is, a high voltage island potential VB terminal, and a field such as a field is formed between the P+ active region 11a and the N+ active region 110b and with other adjacent regions (not shown).
  • the isolation structure 109 of the oxide layer is formed with a polysilicon field plate 111 on the isolation structure 109 between the P+ active region 110a and the N+ active region 110b.
  • 112a is a metal extraction that leads to the P+ active region end and simultaneously extracts the polysilicon field plate 111.
  • 112b is a metal extraction for connecting the high-voltage island potential (ie, the high-side power supply terminal VB) to the N+ active region.
  • a dielectric layer and a via filled with a conductive material are formed between the metal extraction and the substrate to connect the metal extraction and corresponding regions.
  • 3B is a structure of the high voltage depletion NMOS device disclosed in the embodiment, which corresponds to the cross-sectional position BB of FIG. 2B, and the basic structure thereof includes: a p-type substrate 103, and a P-type buried layer is formed in the P-type substrate 103. 104 and deep N buried layer 105. A P well 106 and a high voltage N well 107 are formed over the P type buried layer 104 and the deep N buried layer 105, and the high voltage N well 107 is used as a drift region, and a low voltage N well 108 is formed therein. A P+ active region 110a is formed in the P well 106 for extracting the P well and connecting to the P substrate.
  • An N+ source region 110b is formed in the low voltage N-well 108 for extracting the N-well.
  • An N+ drain 110c is also formed in the high voltage N-well for drawing a high voltage N-well to form the drain of the depletion mode NMOS device.
  • An isolation structure 109 such as a field oxide layer is formed between the P+ active region 110a, the N+ source region 110b, and the N+ drain electrode 110c and between other adjacent regions (not shown).
  • a polysilicon field plate 111 is formed on the isolation structure 109 between the N+ drain 110c and the N+ source region 110b.
  • the metal extraction 112a is electrically connected to the P+ active region through a via, and the metal extraction 112b is electrically connected to the N+ source region 110b for electrical connection with the high side power terminal VB.
  • the metal extraction 112c is a metal extraction of the drain and gate of the high voltage depletion NMOS device, and the drain and gate are shorted to increase the charging current.
  • the high-voltage-resistant depletion NMOS device N1 of the present embodiment only increases the implantation of the drain and changes the connection mode of the part of the metal extraction, which can completely adopt the standard process platform. Existing level production, no additional cost.
  • the cross-section thereof is the structure shown in FIG. 3B, that is, for a high-voltage island, a depletion type MOS device is formed on the high-voltage junction terminal, and the depletion mode MOS is formed.
  • the width of the device is the sum of the lengths of the three sides 104b of the high voltage junction terminal.
  • the depletion type MOS device since the depletion type MOS device is formed at the high-voltage junction terminal inside the chip, it can withstand high voltage, and thus can be used as a bootstrap device. This makes it unnecessary to use an external bootstrap diode when forming the bootstrap circuit, which improves the integration of the chip and simplifies the peripheral circuit, thereby reducing the cost and improving the reliability. And the integrated bootstrap device does not require additional processing and is compatible with standard processes.
  • This embodiment provides a method for fabricating an integrated circuit chip, as shown in FIG. 4, including:
  • Step 401 providing a semiconductor substrate in which a high voltage island for fabricating a high voltage gate drive circuit is formed.
  • the semiconductor substrate may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductor, and further comprising a plurality of layers of these semiconductors
  • the structure or the like may be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI).
  • Devices such as NMOS and/or PMOS may be formed on the semiconductor substrate.
  • a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source or a drain of the transistor, or a metal interconnection structure electrically connected to the transistor.
  • the high-voltage islands and the high-voltage gate driving circuit can be fabricated according to specific circuit layouts and designs by methods such as photolithography, implantation, etching, etc., which are commonly used in the art, and will not be described herein.
  • Step 402 forming a depletion mode MOS device surrounding the high voltage island in the semiconductor substrate, the depletion mode MOS device serving as a high voltage junction terminal of the high voltage island, and the depletion mode MOS device
  • the gate and the drain are shorted, and a source of the depletion mode MOS device is connected to a high side power terminal of the integrated circuit chip.
  • the layout of the high voltage junction termination/depletion MOS device and the high voltage island is as shown in FIG. 2B, and the high voltage island and the high voltage junction terminal are quadrangular, on three consecutive sides of the high voltage island.
  • the depletion mode MOS device is formed.
  • a high voltage level shifting device such as an LDMOS device, is formed on the remaining side of the high voltage island.
  • the depletion mode MOS device can be completed by the following steps:
  • an adjacent first well region having a first conductivity type and a second well region having a second conductivity type, the first conductivity type such as a P type, and the second conductive region are formed on the semiconductor substrate Type such as N type;
  • a first buried layer having a first conductivity type and a second buried layer having a second conductivity type are formed on the semiconductor substrate;
  • an epitaxial layer is formed on the semiconductor substrate, and a first well region having a first conductivity type and a second high voltage well region having a second conductivity type are fabricated in the epitaxial layer, and in the second Forming a third low voltage well region having a second conductivity type in the high voltage well region;
  • an isolation structure such as field oxygen is formed in the epitaxial layer to define an active region
  • an active region having a first conductivity type is formed in the first well region, a drain having a second conductivity type is formed in the second well region, and a drain is formed in the third well region a source region having a second conductivity type;
  • a polysilicon field plate is formed on the isolation structure between the drain having the second conductivity type and the source region having the second conductivity type;
  • Step 403 forming a bipolar transistor in the semiconductor substrate, the collector and the base of the bipolar transistor being shorted and connected to a low side power terminal of the integrated circuit chip, the emitter of the bipolar transistor Connected to the gate of the depletion mode NMOS device.
  • the bipolar transistor is formed in a region of the semiconductor substrate that is outside the termination of the high voltage junction.
  • the process steps of the method for fabricating the integrated circuit chip according to the embodiment of the present invention are completed. It can be understood that the method for fabricating the integrated circuit chip of the embodiment includes not only the above steps, but also before, during or after the above steps. It includes other required steps, such as the steps of making a bipolar transistor and a low voltage driving circuit and a control circuit.
  • the depletion type MOS device since the depletion type MOS device is formed at the high-voltage junction terminal inside the chip, it can withstand high voltage, and thus can be used as a bootstrap device, so that the bootstrap circuit is formed without using an external connection.
  • the bootstrap diodes increase chip integration and simplify peripheral circuitry, reducing cost and reliability, and the integrated bootstrap device requires no additional processing and is compatible with standard processes.

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Abstract

一种集成电路芯片及其制作方法、栅驱动电路，该集成电路芯片包括：半导体衬底(103)，在半导体衬底(103)中形成有高压岛(101a)；高压结终端(102a)，所述高压结终端(102a)包围所述高压岛(101a)，在所述高压结终端(102a)形成有耗尽型MOS器件(N1)，所述耗尽型MOS器件(N1)的栅极和漏极短接，所述耗尽型MOS器件(N1)的源极与所述集成电路芯片的高侧电源端(VB)连接；双极晶体管(Q1)，所述双极晶体管(Q1)的集电极和基极短接并与所述集成电路芯片的低侧电源端(VCC)连接，所述双极晶体管(Q1)的发射极与所述耗尽型MOS器件(N1)的栅极连接。

Description

集成电路芯片及其制作方法、栅驱动电路 技术领域
本发明涉及半导体技术领域，具体而言涉及一种集成电路芯片及其制作方法、栅驱动电路。
背景技术
图1A示出一种采用高压集成电路芯片(HVIC)形成的栅驱动电路100a，其包括高压集成电路芯片10a、电阻R1、自举二极管D1、自举电容C1、第一功率管P1和第二功率管P2。高压集成电路芯片10a具有低侧电源端VCC、高侧电源端VB、浮动电源端VS、高侧输出HO、低侧输出LO以及接地端COM，各器件连接如图1A所示。在电路工作时VS的电压是周期性浮动于低压和高压之间，当浮动电源端VS为低电平时，低侧电源端VCC通过自举二极管D1对自举电容C1充电使其电位接近VCC，向高侧电源VB供电；当VS端电压浮动到高压时，通过自举电容储存的电荷的作用VS电压超过VCC电压，二极管进入反向截止状态，这时，通过自举电容C1两端的VB和VS之间的电压差仍为约等于VCC，从而对高侧控制电路供电。因此，自举(bootstrap)二极管需要承受高压，通常采用外置分立器件的方式来实现。
传统的高压集成电路采用外置的方式来实现电压自举来给高侧电路供电，给应用***电路的设计增加了复杂性和调试的困难和成本。而通常集成工艺平台难以提供集成的合适的自举二极管，因而无法使用集成的标准器件用作HVIC的自举二极管。
发明内容
基于此，有必要提供一种集成电路芯片及其制作方法、栅驱动电路。
一种集成电路芯片，包括：
半导体衬底，在所述半导体衬底中形成有用于制作高压栅驱动电路的高压岛；
高压结终端，所述高压结终端包围所述高压岛，在所述高压结终端形成有耗尽型MOS器件，所述耗尽型MOS器件的栅极和漏极短接，所述耗尽型MOS器件的源极与所述集成电路芯片的高侧电源端连接；及
双极晶体管，所述双极晶体管的集电极和基极短接并与所述集成电路芯片的电源端连接，所述双极晶体管的发射极与所述耗尽型MOS器件的栅极连接。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
另一方面，还提供一种集成电路芯片的制作方法，包括：
提供半导体衬底，在所述半导体衬底中形成用于制作高压栅驱动电路的高压岛；
在所述半导体衬底中形成高压结终端，所述高压结终端包围所述高压岛，在所述高压结终端中形成耗尽型MOS器件，所述耗尽型MOS器件的栅极和漏极短接，所述耗尽型MOS器件的源极与所述集成电路芯片的高侧电源端连接；及
在所述半导体衬底中形成双极晶体管，所述双极晶体管的集电极和基极短接并与所述集成电路芯片的电源端连接，所述双极晶体管的发射极与所述耗尽型NMOS器件的栅极连接。
再一方面，还提供一种栅驱动电路，其包括如上所述的集成电路芯片，以及电阻、自举电容、第一功率管和第二功率管，所述集成电路芯片的电源端通过电阻与工作电源连接，所述自举电容的第一端与所述集成电路芯片的高侧电源端连接，所述自举电容的第二端与所述集成电路芯片的浮动电源端连接，所述第一功率管的栅极与所述集成电路芯片的高端输出连接，所述第一功率管的源极与所述工作电源连接，所述第一功率管的漏极与所述集成电路芯片的所述浮动电源端以及所述第二功率管的漏极连接，所述第二功率管的栅极与所述集成电路芯片的低端输出连接，所述第二功率管的源极与所述集成电路芯片的接地端连接。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
附图中：
图1A示出传统技术中一种栅驱动电路的示意性电路图示；
图1B示出根据本发明一实施方式的栅驱动电路的示意性电路图示；
图2A示出传统技术中一种集成电路芯片的高压岛和高压结终端的示意俯视图；
图2B示出根据本发明一实施方式的高压岛和高压结终端的示意俯视图；
图3A是图2A所示的集成电路芯片的高压结终端沿A-A方向的剖视图；
图3B是图2B所示的集成电路芯片的高压结终端沿B-B方向的剖视图；
图4示出根据本发明一实施方式的集成电路芯片的制作方法的示意性步骤流程图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在…上”、“与…相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在…上”、“与…直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下 面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在…下”、“在…下面”、“下面的”、“在…之下”、“在…之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在…下面”和“在…下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本发明，将在下列的描述中提出详细的结构及步骤，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
实施例一
为了克服前述问题，本实施例提出一种集成电路芯片以及使用该集成电路芯片形成的栅驱动电路，该集成电路芯片内部形成有自举器件，因此无需使用外接自举二极管，从而克服了避免使用外接自举二极管给应用***电路造成的设计复杂和调试困难，且成本高的问题。 本实施例的目的是这样实现的，通过设计一种耐高压的耗尽性NMOS器件，该器件和高压集成电路的高压岛整合在一起，可基本不增加芯片的版图面积，同时提供一种可使用该器件的电路结构。
下面结合图1B至图3B对根据本发明一实施方式的集成电路芯片以及使用该集成电路芯片形成的自举电路进行说明。
首先，如图1B所示，本实施公开一种自举电路100b，其使用的集成电路芯片10b内部形成有双极晶体管Q1以及耐高压的耗尽型NMOS器件N1。
图1B所示的栅驱动电路的连接关系为：所述双极晶体管Q1的集电极和基极短接并与所述集成电路芯片10b的低侧电源端VCC连接，所述双极晶体管Q1的发射极与所述耗尽型MOS器件N1的栅极连接，所述耗尽型MOS器件N1的栅极和漏极短接，所述耗尽型MOS器件的源极与所述集成电路芯片10b的高侧电源端VB连接。所述集成电路芯片10b的低侧电源端VCC通过电阻R1与工作电源(例如600V电压的外部工作电源)连接，所述集成电路芯片10b的高侧电源端VB与自举电容C1的第一端连接，所述集成电路芯片10b的浮动电源端VS与所述自举电容C1的第二端连接，所述集成电路芯片10b的高端输出HO与第一功率管P1的栅极连接，所述第一功率管P1的源极与所述工作电源连接，所述第一功率管P的漏极与所述集成电路芯片10b的所述浮动电源端VS以及第二功率管P2的漏极连接，所述集成电路芯片10b的低端输出LO与第二功率管P2的栅极与连接，所述第二功率管P2的源极与所述集成电路芯片10b的接地端COM连接。
图1B所示栅驱动电路100b实现自举的原理为：工作时集成电路芯片10b的VS端电平周期性地在低电平和高压之间浮动，当VS端为低电平时，双极晶体管Q1处于正向导通状态，耗尽型高压NMOS 器件N1处于开启状态，从而工作电源对VB和VS两端之间所连接的自举电容C1进行充电。当VS端向高压浮动时，VB端在自举电容C1作用下电压同步提高，当VS端电位超过VCC端时，双极晶体管Q1进入反偏截止，VS端电压进一步上升后，耗尽型高压NMOS器件N1因为衬偏作用变为截止状态，这样用本发明所提供的器件(即集成电路芯片10b)就可组成图1B的栅驱动电路，从而取消了外置的分立的自举二极管。
应当理解的是，集成电路芯片10b通常包括控制电路、低侧驱动电路、高侧驱动电路以及将控制电路的低侧控制信号传递至高侧驱动电路的电平移位电路。高侧驱动电路形成在芯片或半导体衬底的高压岛中，且电位为浮动电位，通常用高压结终端包围以耐高压，并且起隔离高侧驱动电路与低侧驱动电路的作用。本实施例中高压集成电路芯片10b的双极晶体管Q1制作在集成电路芯片的低压区域，耐高压的耗尽型NMOS器件N1同时用作集成电路芯片的高压岛的高压结终端，从而基本不增加版图面积。
双极晶体管Q1可用BCD工艺平台的标准双极晶体管实现，在此不做赘述。下面结合图2A至图3B对本实施例的集成电路芯片10b的高压岛以及高压结终端进行描述，并结合目前的高压集成电路芯片10a的高压岛以及高压结终端的结构说明二者的区别。
首先参考图2A和图2B，其中图2A为一种常规的高压岛和高压结终端的示意性俯视图，图2B为本实施例提出的一种高压岛和高压结终端的示意性俯视图。传统的图2A所示高压岛(示例性地为四边形)101a被高压结终端(示例性地为四边形)102a包围，通常在高压结终端102a的一边，例如图2A中103a部分集成了2个电平移位器件，例如LDMOS器件，而在高压结终端102a的另外三边，例如图2A中104a，为常规的耐压结终端，确保高压岛的耐压。图2B示 出了本实施例提出的高压岛101b，其在高压结终端102b的三边104b集成了耗尽型高压NMOS器件，且在高压结终端的另外一边同样集成了2个高压电平移位器件103b，从图2B中可见，本实施例对常规高压岛的没有器件的3边高压结终端进行利用，在这3边高压结终端上设置耐高压的耗尽型NMOS器件，不需要额外的面积。
接着，如图3A和图3B所示，其中图3A为常规的高压结终端结构示意图，对应于图2A的剖面位置A-A，其基本结构包括，p型衬底103，位于P型衬底103中的P型埋层104和深N埋层105，以及位于P型埋层104和深N埋层105之上的外延后制作的P阱106和高压N阱107。高压N阱107用做漂移区，且其中形成有低压N阱108，在P阱106中形成有P+有源区110a，用于引出P阱并连接到P衬底，在低压N阱108中形成N+有源区110b，用于引出N阱，也就是高压岛电位VB端，P+有源区11a和N+有源区110b之间以及与其他相邻区域(未示出)之间形成有诸如场氧化层的隔离结构109，在P+有源区110a和N+有源区110b之间的隔离结构109上形成有多晶硅场板111。112a为引出P+有源区端同时引出多晶硅场板111的金属引出，112b为连接N+有源区引出高压岛电位(即高侧电源端VB)的金属引出。在金属引出和衬底之间形成有介质层以及填充有导电材料的通孔，以连接金属引出和对应的区域。
图3B为本实施例公开的高压耗尽NMOS器件的结构，其对应于图2B的剖面位置B-B，其基本结构包括：p型衬底103，在P型衬底103中形成有P型埋层104和深N埋层105。在P型埋层104和深N埋层105之上形成有P阱106和高压N阱107，高压N阱107用做漂移区，且其中形成有低压N阱108。在P阱106中形成有P+有源区110a，用于引出P阱并连接到P衬底。在低压N阱108中形成N+源区110b，用于引出N阱。在高压N阱还形成有N+漏极110c，用 于引出高压N阱即形成耗尽型NMOS器件的漏极。P+有源区110a、N+源区110b和N+漏极110c之间以及与其他相邻区域(未示出)之间形成有诸如场氧化层的隔离结构109。在N+漏极110c和N+源区110b之间的隔离结构109上形成有多晶硅场板111。金属引出112a通过通孔与P+有源区电连接，金属引出112b与N+源区110b电连接，用于与高侧电源端VB电连接。金属引出112c为高压耗尽NMOS器件的漏极和栅极的金属引出，漏极和栅极短接的方式可提高充电电流。
从图3A和图3B的对比中可以看出，本实施例的耐高压的耗尽型NMOS器件N1仅增加漏极的注入，并改变部分金属引出的连接方式，其完全可以采用标准工艺平台的现有层次制作，不需要增加额外的成本。
需要说明的是，对于图2B中高压结终端104b其剖面均为图3B所示的结构，也即对于一个高压岛，在高压结终端上形成有一个耗尽型MOS器件，该耗尽型MOS器件的宽度为高压结终端的三个边104b的长度和。
根据本实施例的集成电路芯片以及自举电路，由于在芯片内部的高压结终端形成耗尽型MOS器件，其可以承受高压，因此可以用作自举器件。这样使得形成自举电路时无需使用外接自举二极管，提高了芯片的集成度，简化了***电路，从而降低了成本，提高了可靠性。并且所集成的自举器件不需要额外的工艺，与标准工艺兼容。
实施例二
本实施例提出一种集成电路芯片的制作方法，如图4所示，包括：
步骤401，提供半导体衬底，在所述半导体衬底中形成用于制作高压栅驱动电路的高压岛。
其中，半导体衬底可以是以下所提到的材料中的至少一种：Si、 Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。半导体衬底上可以形成有器件，例如NMOS和/或PMOS等。同样，半导体衬底中还可以形成有导电构件，导电构件可以是晶体管的栅极、源极或漏极，也可以是与晶体管电连接的金属互连结构等。
所述高压岛以及高压栅驱动电路可以通过本领域常用的诸如光刻、注入、刻蚀等方法根据具体的电路布图和设计进行制作，在此不做赘述。
步骤402，在所述半导体衬底中形成围绕所述高压岛的耗尽型MOS器件，所述耗尽型MOS器件用作所述高压岛的高压结终端，并且所述耗尽型MOS器件的栅极和漏极短接，所述耗尽型MOS器件的源极与所述集成电路芯片的高侧电源端连接。
在一个实施例中，所述高压结终端/耗尽型MOS器件和高压岛的布图如图2B所示，高压岛和高压结终端呈四边形，在所述高压岛的其中三个连续边上形成所述耗尽型MOS器件。示例性地，在所述高压岛的剩余一边形成高压电平移位器件，例如LDMOS器件。
在一个实施例中，所述耗尽型MOS器件可以通过下述步骤完成：
首先，在所述半导体衬底上形成相邻的具有第一导电类型的第一阱区和具有第二导电类型的第二阱区，所述第一导电类型例如P型，所述第二导电类型例如N型；
接着，在所述半导体衬底上形成具有第一导电类型的第一埋层和具有第二导电类型的第二埋层；
接着，在所述半导体衬底上形成外延层，并在所述外延层中制作具有第一导电类型的第一阱区和具有第二导电类型的第二高压阱区， 以及在所述第二高压阱区中制作具有第二导电类型的第三低压阱区；
接着，所述外延层中形成诸如场氧的隔离结构，以定义有源区；
接着，在所述第一阱区中形成具有第一导电类型的有源区，在所述第二阱区中形成有具有第二导电类型的漏极，在所述第三阱区中形成有具有第二导电类型的源区；
接着，在所述具有第二导电类型的漏极和所述具有第二导电类型的源区之间的隔离结构上形成有多晶硅场板；
接着，形成覆盖所述第一导电类型的有源区、所述具有第二导电类型的漏极、所述具有第二导电类型源区和所述多晶硅场板的第一介质层；
接着，在所述第一介质层中形成填充有导电材料的接触孔(contact)；
接着，形成通过所述接触孔与所述第一导电类型的有源区、所述具有第二导电类型的漏极、所述具有第二导电类型的源区和所述多晶硅场板的金属引出，其中所述具有第二导电类型的漏极和所述多晶硅场板连接至同一金属引出。
步骤403，在所述半导体衬底中形成双极晶体管，所述双极晶体管的集电极和基极短接并与所述集成电路芯片的低侧电源端连接，所述双极晶体管的发射极与所述耗尽型NMOS器件的栅极连接。
应当理解的是，所述双极晶体管形成在所述半导体衬底中位于所述高压结终端之外的区域中。
至此，完成了根据本发明实施例的集成电路芯片的制作方法的工艺步骤，可以理解的是，本实施例集成电路芯片的制作方法不仅包括上述步骤，在上述步骤之前、之中或之后还可包括其他需要的步骤，比如制作双极晶体管以及低压驱动电路、控制电路的步骤。
应当理解的是，上述各步骤仅说明根据本发明实施例的集成电路 芯片的制作方所述包含的步骤，而不代表步骤的顺序，其中所提到的各步骤可能先后进行或者同时进行。
根据本实施例的集成电路芯片的制作方法，由于在芯片内部的高压结终端形成耗尽型MOS器件，其可以承受高压，因此可以用作自举器件，这样使得形成自举电路时无需使用外接自举二极管，提高了芯片的集成度，简化了***电路，从而降低了成本，提高了可靠性，并且所集成的自举器件不需要额外的工艺，与标准工艺兼容。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (15)

  1. 一种集成电路芯片，包括：
    半导体衬底，在所述半导体衬底中形成有用于制作高压栅驱动电路的高压岛；
    高压结终端，所述高压结终端包围所述高压岛，所述高压结终端包括形成在所述高压岛周围的耗尽型MOS器件，所述耗尽型MOS器件的栅极和漏极短接，所述耗尽型MOS器件的源极与高侧电源端连接；及
    双极晶体管，所述双极晶体管的集电极和基极短接，所述双极晶体管的集电极与低侧电源端连接，所述双极晶体管的发射极与所述耗尽型MOS器件的栅极连接。
  2. 根据权利要求1所述的集成电路芯片，其特征在于，所述高压岛呈四边形，所述耗尽型MOS器件形成在所述高压岛的相邻的三个边上。
  3. 根据权利要求2所述的集成电路芯片，其特征在于，在所述高压岛除所述三个边之外的第四边上形成有高压电平移位器件。
  4. 根据权利要求1所述的集成电路芯片，其特征在于，所述耗尽型MOS器件包括：
    形成在所述半导体衬底上相邻的具有第一导电类型的第一阱区和具有第二导电类型的第二阱区；
    形成在所述第一阱区中的、具有第一导电类型的有源区；
    形成在所述第二阱区中的、具有第二导电类型的漏极和第三阱区；
    形成在所述第三阱区中的、具有第二导电类型的源极；
    形成在所述半导体衬底中，且位于所述具有第一导电类型的有源区、所述具有第二导电类型的漏极和所述具有第二导电类型的源极之间的隔离结构；及
    形成在所述具有第二导电类型的漏极和所述具有第二导电类型的源极之间的隔离结构上的多晶硅场板。
  5. 根据权利要求4所述的集成电路芯片，其特征在于，所述耗尽型MOS器件还包括：
    形成在所述第一阱区和所述半导体衬底之间的具有第一导电类型的第一埋层；及
    形成在所述第三阱区和所述半导体衬底之间的具有第二导电类型的第二埋层。
  6. 根据权利要求4所述的集成电路芯片，其特征在于，所述耗尽型MOS器件还包括：
    覆盖所述第一导电类型的有源区、所述具有第二导电类型的漏极、所述具有第二导电类型源极和所述多晶硅场板的第一介质层；
    形成在所述第一介质层中的、填充有导电材料的接触孔；及
    通过所述接触孔与所述具有第一导电类型的有源区、所述具有第二导电类型的漏极、所述具有第二导电类型的源区和所述多晶硅场板连接的金属引出；
    其中，所述具有第二导电类型的漏极和所述多晶硅场板连接至同一金属引出。
  7. 根据权利要求1所述的集成电路芯片，其特征在于，所述双极晶体管形成在所述半导体衬底中位于所述高压结终端之外的区域中。
  8. 一种集成电路芯片的制作方法，包括：
    提供半导体衬底，在所述半导体衬底中形成用于制作高压栅驱动电路的高压岛；
    在所述半导体衬底中形成高压结终端，所述高压结终端包围所述高压岛，所述高压结终端包括形成在所述高压岛周围的耗尽型MOS器件，所述耗尽型MOS器件的栅极和漏极短接，所述耗尽型MOS器件的源极与所述集成电路芯片的高侧电源端连接；及
    在所述半导体衬底中形成双极晶体管，所述双极晶体管的集电极和基极短接，所述双极晶体管的集电极并与所述集成电路芯片的低侧电源端连接， 所述双极晶体管的发射极与所述耗尽型NMOS器件的栅极连接。
  9. 根据权利要求8所述的方法，其特征在于，所述高压岛呈四边形，所述耗尽型MOS器件形成在所述高压岛的相邻的三个边上。
  10. 根据权利要求9所述的方法，其特征在于，还包括：
    在所述高压岛除所述三个边之外的第四边上形成高压电平移位器件。
  11. 根据权利要求8所述的方法，其特征在于，形成所述耗尽型MOS器件的步骤，包括：
    在所述半导体衬底上形成相邻的具有第一导电类型的第一阱区和具有第二导电类型的第二阱区；
    在所述第一阱区中形成有具有第一导电类型的有源区；
    在所述第二阱区中形成具有第二导电类型的漏极和第三阱区；
    在所述第三阱区中形成有具有第二导电类型的源区；
    在所述具有第一导电类型的有源区、所述具有第二导电类型的漏极和所述具有第二导电类型的源区之间形成有隔离结构；及
    在所述具有第二导电类型的漏极和所述具有第二导电类型的源区之间的隔离结构上形成有多晶硅场板。
  12. 根据权利要求11所述的方法，其特征在于，所述在所述高压结终端中形成耗尽型MOS器件的步骤，还包括：
    在所述第一阱区和所述半导体衬底之间形成具有第一导电类型的第一埋层；及
    在所述第三阱区和所述半导体衬底之间形成具有第二导电类型的第二埋层。
  13. 根据权利要求11所述的方法，其特征在于，形成所述耗尽型MOS器件的步骤，还包括：
    形成覆盖所述第一导电类型的有源区、所述具有第二导电类型的漏极、所述具有第二导电类型的源区和所述多晶硅场板的第一介质层；
    在所述第一介质层中形成填充有导电材料的接触孔；及
    形成通过所述接触孔与所述具有第一导电类型的有源区、所述具有第二导电类型的漏极、所述具有第二导电类型的源区和所述多晶硅场板连接的金属引出，
    其中，所述具有第二导电类型的漏极和所述多晶硅场板连接至同一金属引出。
  14. 根据权利要求8所述的方法，其特征在于，所述双极晶体管形成在所述半导体衬底中位于所述高压结终端之外的区域中。
  15. 一种栅驱动电路，包括如权利要求1所述的集成电路芯片，以及电阻、自举电容、第一功率管和第二功率管，所述集成电路芯片的低侧电源端通过所述电阻与工作电源连接，所述自举电容的第一端与所述集成电路芯片的高侧电源端连接，所述自举电容的第二端与所述集成电路芯片的浮动电源端连接，所述第一功率管的栅极与所述集成电路芯片的高端输出连接，所述第一功率管的源极与所述工作电源连接，所述第一功率管的漏极与所述集成电路芯片的所述浮动电源端以及所述第二功率管的漏极连接，所述第二功率管的栅极与所述集成电路芯片的低端输出连接，所述第二功率管的源极与所述集成电路芯片的接地端连接。
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