WO2019021095A1 - System for controlling charging of secondary cell and method for detecting abnormality in secondary cell - Google Patents

System for controlling charging of secondary cell and method for detecting abnormality in secondary cell Download PDF

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Publication number
WO2019021095A1
WO2019021095A1 PCT/IB2018/055129 IB2018055129W WO2019021095A1 WO 2019021095 A1 WO2019021095 A1 WO 2019021095A1 IB 2018055129 W IB2018055129 W IB 2018055129W WO 2019021095 A1 WO2019021095 A1 WO 2019021095A1
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Prior art keywords
secondary battery
data
transistor
image data
memory cell
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PCT/IB2018/055129
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French (fr)
Japanese (ja)
Inventor
智 大下
耕平 豊高
真里奈 檜山
敏行 伊佐
亮太 田島
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株式会社半導体エネルギー研究所
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Publication of WO2019021095A1 publication Critical patent/WO2019021095A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/48—Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

Definitions

  • One aspect of the present invention relates to an object, a method, or a method of manufacturing.
  • the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • One embodiment of the present invention relates to a method for manufacturing a semiconductor device, a display device, a light-emitting device, a power storage device, a lighting device, or an electronic device.
  • the present invention relates to a charge control system, a charge control method, and an electronic device having a secondary battery.
  • One embodiment of the present invention relates to a vehicle or a vehicle electronic device provided in the vehicle.
  • a power storage device refers to all elements and devices having a power storage function.
  • a storage battery also referred to as a secondary battery
  • a lithium ion secondary battery such as a lithium ion secondary battery, a lithium ion capacitor, an all solid battery, an electric double layer capacitor, and the like are included.
  • one aspect of the present invention relates to a neural network and a charge control system using the same. Further, one aspect of the present invention relates to a vehicle using a neural network. Further, one embodiment of the present invention is not limited to a vehicle, and can also be applied to a power storage device for storing power obtained from a power generation facility such as a solar power generation panel installed in a structure or the like. Further, one embodiment of the present invention relates to an electronic device using a neural network. Further, one aspect of the present invention relates to an abnormality detection system using a neural network.
  • lithium ion secondary batteries having high output and high energy density can be used in portable information terminals such as mobile phones, smartphones, tablets, or notebook computers, portable music players, digital cameras, medical devices, or hybrid vehicles (HEVs).
  • portable information terminals such as mobile phones, smartphones, tablets, or notebook computers, portable music players, digital cameras, medical devices, or hybrid vehicles (HEVs).
  • HEVs hybrid vehicles
  • demand is rapidly expanding with the development of the semiconductor industry, such as next-generation clean energy vehicles such as electric vehicles (EVs) and plug-in hybrid vehicles (PHEVs), and modern information as a source of rechargeable energy Has become an integral part of the
  • a plurality of secondary batteries are connected in series or in parallel to form a protective circuit, which is used as a battery pack (also referred to as a battery pack).
  • the battery pack refers to a battery pack in which a plurality of secondary batteries are accommodated together with a predetermined circuit in a container (metal can, film outer package) in order to facilitate handling of the secondary battery.
  • the battery pack is provided with an ECU (Electronic Control Unit) to manage the operation state.
  • ECU Electronic Control Unit
  • neural networks In recent years, machine learning techniques such as artificial neural networks (hereinafter referred to as neural networks) have been actively developed.
  • Patent Document 1 shows an example of using a neural network to calculate the remaining capacity of a secondary battery.
  • Safety of the secondary battery is secured by detecting the abnormality of the secondary battery and changing the operating conditions of the secondary battery, for example, when a phenomenon that reduces the safety of the secondary battery is detected or foreseen. Do.
  • Another problem is to install a system for detecting an abnormality in a secondary battery by using artificial intelligence (AI) such as a neural network in a portable information terminal or an electric vehicle.
  • AI artificial intelligence
  • a secondary battery abnormality detection system for detecting an abnormality of a secondary battery with a low cost IC chip in a portable information terminal or an electric vehicle.
  • the actual and accurate remaining amount of the secondary battery can be obtained by discharging and detecting the secondary battery, but it is possible to actually discharge it to make the remaining amount zero and use the device Since it can not be done, the remaining amount is estimated from the parameter (battery voltage or integrated current) having a correlation with the remaining amount. Further, since the secondary battery uses a chemical reaction, it may be erroneous to estimate the remaining amount instantaneously based on a small amount of data.
  • An object of one embodiment of the present invention is to provide a novel battery management circuit, a power storage device, an electronic device, and the like.
  • the charge characteristics of the secondary battery are converted into image data, and a normal characteristic and an abnormal characteristic of the secondary battery are determined based on the learning data using a convolutional neural network (CNN) model. After determining that the state of the secondary battery is abnormal, a warning for the secondary battery exhibiting abnormal characteristics, or a stop of use, or a proposal for replacement of the secondary battery, or a charge control system for the secondary battery that changes the charging condition I assume.
  • CNN convolutional neural network
  • the graph with the charge voltage value on the vertical axis and the time on the horizontal axis is converted to 8-bit gray gradation image data, and then normal Turn
  • the image data is array data as shown in FIG. 2 (B) and FIG. 2 (D).
  • it is 8-bit gray tone, one pixel is represented by 8 bits, it indicates data including only brightness without color information, and gray scale is represented by 256 tones.
  • normalization is transforming data etc. based on a fixed rule, organizing in order to handle it efficiently, and making it easy to use.
  • the data is labeled as normal or abnormal.
  • the features of the image are extracted by CNN processing and pooling processing.
  • the filter parameters of the CNN for extracting features are "weights”.
  • it is determined whether the secondary battery is normal or abnormal by using a fully coupled neural network.
  • the image data is used for calculation, and the image data is not displayed. Since image data is used, determination can be made using CNN.
  • the detection accuracy can be improved, and it can be determined whether the secondary battery is a normal secondary battery or an abnormal secondary battery.
  • the charge operation may be performed on a load such as a circuit under certain conditions to acquire data. It is preferable that the power used for acquisition be supplied not from the secondary battery to be monitored, but from another secondary battery or an external power source. In addition, it is preferable that the arithmetic processing and the like be performed by supplying power from an external power supply.
  • the external power source refers to a power source such as an AC power source or a DC power source, such as a battery mounted on an electric vehicle or a stationary battery installed in a house.
  • the charge control system for a secondary battery disclosed herein comprises: a secondary battery; measurement means for measuring the voltage value of the secondary battery; and means for converting the measured voltage value of the secondary battery into image data And determination means for classifying the image data.
  • the determination means is a product-sum operation, and the determination means includes a transistor using an oxide semiconductor material as the semiconductor layer.
  • a transistor including an oxide semiconductor material typically, an oxide semiconductor containing In, Ga, and Zn in a channel for the memory can store data with relatively little power, power can be saved.
  • operating systems for software various operating systems such as Windows (registered trademark), UNIX (registered trademark), and macOS (registered trademark) can be used.
  • Software programs include Python, Go, Perl, Ruby, Prelog, Visual Basic, C, C ++, Swift, Java (registered trademark),. It can be written in various programming languages such as NET.
  • Applications may also be created using frameworks such as Chainer (available in Python), Caffe (available in Python and C ++), TensorFlow (available in C, C ++, and Python).
  • the CNN model requires a large amount of convolution processing. Since convolution processing uses product-sum operation, an LSI chip capable of forming a power-saving product-sum operation circuit, in particular, an IC chip using a transistor using an oxide semiconductor material can be used. Alternatively, an IC (also referred to as an inference chip) incorporating an artificial intelligence (AI) system may be used. An IC incorporating an AI system may be called a circuit (microcomputer) that performs neural network operations.
  • a circuit microcomputer
  • creation of an algorithm is not limited to CNN, You may use SVR, RVM (Relevance Vector Machine), a random forest etc. Although the circuit configuration is increased, CNN and Long Short-Term Memory (LSTM) may be combined as appropriate.
  • RVM Relevance Vector Machine
  • LSTM Long Short-Term Memory
  • a method of detecting an abnormality of the secondary battery is also disclosed herein.
  • the voltage value of the secondary battery is measured in a first period, and the measured voltage value of the secondary battery is converted into first image data, The first image data is classified, the voltage value of the secondary battery is measured in a second period after the first period, and the measured voltage value of the secondary battery is converted into second image data. Then, the second image data is classified, and from the classification results of the first and second image data, determination of normality or abnormality is performed.
  • the length of the second period is equal to or less than the first period. Since a certain amount of information for feature extraction is required during the first period from the start of charging, it is preferable to make the first period longer.
  • the length of the first period is preferably determined based on the abnormal data among the learning data of the secondary battery. By setting the length of the second period to be equal to or less than the first period, it is possible to give real time characteristics.
  • the determination processing period may be extended in the vicinity of the middle of the charging period where the change is small in constant current charging, in order to reduce the power consumption.
  • the measurement of the voltage value of the secondary battery may be performed at regular intervals, and the number of measurements of the abnormality detection test by the AI system may be smaller than the number of measurements of the voltage value of the secondary battery.
  • one charging period of the secondary battery is characterized by switching to constant voltage charging after performing constant current charging, and including a first period and a second period. Both the first period and the second period may be set in the constant current charging period.
  • the charge voltage value in the first period is the vertical axis
  • the time is the horizontal axis
  • the converted graph is converted into 8-bit gradation image data and then normalized. It is determined whether the secondary battery is normal or abnormal by classifying the image data.
  • data from the charging start to the second period are used as image data Convert, normalize, perform CNN processing, and pooling processing, and determine whether the secondary battery is normal or abnormal by the fully coupled neural network.
  • the image data which is array data
  • the image data is used for calculation, and the image data is not displayed. Since image data that is array data is used, determination can be made using CNN. Further, the detection accuracy can be improved by learning fine tuning or subdivision of an abnormality, and it can be determined whether it is a normal secondary battery or an abnormal secondary battery.
  • the present invention can also be applied to a solid battery using a solid electrolyte and a fuel cell, and abnormality detection can be performed.
  • the solid electrolyte is not particularly limited as long as it can conduct lithium ions and contains a solid component.
  • ceramics, polymer electrolytes and the like can be mentioned.
  • the polymer electrolyte can be roughly divided into a polymer gel electrolyte containing an electrolyte solution and a polymer solid electrolyte not containing an electrolyte solution.
  • the change of the secondary battery can be accurately grasped, and can be reflected in the management of the degree of deterioration of the secondary battery.
  • the size and cost of the entire system can be reduced without degrading the accuracy of detecting an abnormality of the secondary battery.
  • the present invention it is possible to detect a micro short circuit of a secondary battery which has conventionally been difficult to detect accurately.
  • by accurately grasping the change of the secondary battery during charging and increasing the number of times of abnormality detection it is possible to immediately execute the charging stop, and it is possible to provide a safe charging method of the secondary battery. .
  • FIG. 7 is an example of a flowchart illustrating an embodiment of the present invention. They are an example of the charge characteristic which shows one mode of the present invention, and an example of image data. It is a flowchart at the time of learning. The figure which shows the structure of a neural network. 7 is an example of a flowchart illustrating an embodiment of the present invention. 7 is an example of a flowchart illustrating an embodiment of the present invention.
  • FIG. 18 is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of
  • FIG. 18 is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • 7A and 7B are a block diagram and a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • BRIEF DESCRIPTION OF THE DRAWINGS The block diagram which shows the structural example of AI system which concerns on 1 aspect of this invention.
  • 7 is an example of a flowchart illustrating an embodiment of the present invention.
  • FIG. 7 is a diagram showing, in chronological order, image data showing one embodiment of the present invention.
  • 5 is image data representing one embodiment of the present invention.
  • It is a figure which shows the neural network of a present Example.
  • FIG. 6 illustrates an example of an electronic device.
  • FIG. 6 illustrates an example of an electronic device.
  • FIG. 6 illustrates an example
  • Embodiment 1 In this embodiment, an example will be described in which a neural network is used to detect the occurrence of an abnormality (specifically, the occurrence of a microshort) of a secondary battery.
  • an abnormality specifically, the occurrence of a microshort
  • micro short refers to a minute short inside the secondary battery, not to the extent that the positive electrode and the negative pole of the secondary battery are shorted to cause a state in which charging and discharging are not possible. This refers to a phenomenon in which a short circuit current flows for a period of 10 nanoseconds or more and less than 1 microsecond.
  • the cause of the micro short is that the charge and discharge are performed multiple times, and the uneven distribution of the positive electrode active material causes local concentration of current at a part of the positive electrode and a part of the negative electrode, and a part of the separator The occurrence of a nonfunctional part or the generation of a side reaction product.
  • the neural network is first used to form the secondary battery. Try to detect an abnormality occurrence.
  • the state of the secondary battery to be judged is analyzed to create data.
  • the capacity of the secondary battery can be determined, for example, by the product of the current and time of the secondary battery.
  • the coulomb counter CC may be used to determine the capacity of the secondary battery.
  • the SOC (state of charge) of the secondary battery may be used.
  • the SOC of the secondary battery may be determined by estimation from the voltage of the secondary battery.
  • the fully charged state can also be said to be SOC 100%.
  • the fully charged state means a state in which the battery is charged to the range of the charge termination voltage.
  • the state of charge is indicated by an SOC that represents the amount of charge being charged relative to the capacity of the secondary battery.
  • the SOC is defined as the ratio of the remaining capacity to the maximum capacity of the secondary battery.
  • step S2 If the SOC is less than 50%, the process proceeds to the next step, charging start (step S2). If the SOC is 50% or more, the secondary battery is discharged by the discharge circuit to make the SOC less than 50%, preferably 20% or less.
  • step S3 Data on charge characteristics of the secondary battery is measured until charging is started to detect an abnormality and the battery is fully charged, and the measured data is stored in the memory unit (step S3).
  • the charge curve is obtained by imaging a graph obtained by accumulating the charge data, and an example of the charge curve is FIG. 2 (A) or FIG. 2 (C).
  • FIG. 2A and FIG. 2C show charge curves with the horizontal axis representing time and the vertical axis representing voltage. Also, by taking log data, it is possible to leave a record or history even if charging is interrupted between charging start and full charging, so that data on charging characteristics can be measured even if charging is started again. .
  • the obtained charge curve is converted into image data to obtain a plurality of input data (step S4).
  • a normal charge curve is obtained, the charge curve shown in FIG. 2A is obtained, which is converted into image data and visualized as shown in FIG. 2B.
  • a charge curve in which a micro short occurs is obtained in the second half of the charge, for example, the charge curve shown in FIG. 2C is obtained, and is converted into image data and visualized in FIG.
  • the charge curve is converted into image data of 8-bit gradation from 0 to 255.
  • the discharged state (low voltage) is black and the fully charged state is white.
  • the left of FIG. 2 (B) and FIG. 2 (D) has shown charge start, and the right has shown charge completion.
  • the input data is determined (step 5).
  • this determination or classification
  • processing of a neural network is performed and product-sum operation is used.
  • the features of the input data are classified as normal or abnormal using the weight parameters created at the time of training.
  • weight parameters also referred to as filters
  • feature data are extracted in advance using data for images with correct labels as input data
  • weight parameters for feature extraction are stored in an array, and weights are set for each minibatch size.
  • Update to learn The mini-batch size is the number of data samples of the mini-batch.
  • the learning sequence that is, the flow at the time of learning is illustrated in FIG. Error back propagation is used to update learning.
  • the feature of the image is extracted, it is judged whether it is normal or abnormal, the judgment result is compared with the correct answer label, and the rate of error is calculated. Update the weight values to reduce the error. The error is gradually reduced by repetitive learning, and the weight at the minimum is used for inference.
  • FIG. 2C and FIG. 2D are examples of data corresponding to data that can be regarded as an abnormality, which is classified as an abnormality of the secondary battery due to the occurrence of a microshort.
  • FIGS. 2C and 2D it is preferable to discontinue or replace the secondary battery.
  • start timing of the series of procedures may be determined by the user or may be automatically performed periodically.
  • FIG. 2 (B) and FIG. 2 (D) image data is visualized (image display when displayed on a display device).
  • the system configuration Can be simplified. If the system is simplified, the power used for computation can be reduced, and power saving can be achieved for the entire system.
  • Second Embodiment an example of the configuration of the neural network NN used in the neural network processing at step S5 shown in FIG. 1 in Embodiment 1, that is, when classifying the state of the secondary battery is shown.
  • FIG. 4 shows an example of a neural network of one embodiment of the present invention.
  • the neural network shown in FIG. 4 has an input layer IL, an output layer OL, and a hidden layer (intermediate layer) HL.
  • the neural network can be configured by a neural network having a plurality of hidden layers HL, that is, a deep neural network. Learning in a deep neural network may be called deep learning.
  • the output layer OL, the input layer IL, and the hidden layer HL each have a plurality of neuron circuits, and neuron circuits provided in different layers are connected via a synapse circuit.
  • the function to analyze the state of the secondary battery at a certain point is added to the neural network by learning. Then, when the measured secondary battery parameters are input to the neural network, calculation processing is performed in each layer. Arithmetic processing in each layer is performed by a product-sum operation of the output of the neuron circuit of the front layer and the weighting factor.
  • the layer-to-layer connection may be a full connection in which all neuron circuits are connected to each other, or a partial connection in which some neuron circuits are connected to each other.
  • a convolutional neural network may be used, in which only certain units are coupled between adjacent layers and have convolutional and pooling layers.
  • the CNN is used, for example, for classification of image data converted from data of charging characteristics.
  • an operation using image data and weight parameters is performed.
  • the pooling layer is preferably placed immediately after the convolutional layer.
  • the convolution layer has a function of performing convolution on image data.
  • the convolution is performed by repeating an operation using a part of the image data and the filter value of the weight parameter.
  • By convolution in the convolution layer features of the image data are extracted.
  • a weight parameter (also called a weight filter) can be used for the convolution.
  • the image data input to the convolutional layer is subjected to filter processing using weight parameters.
  • the data subjected to convolution is converted by the activation function and then output to the pooling layer.
  • the activation function ReLU (Rectified Linear Unit) or the like can be used.
  • ReLU is a normalized linear function that outputs "0" when the input value is negative and outputs the input value as it is when the input value is "0" or more.
  • a sigmoid function, a tanh function or the like can be used as the activation function.
  • the pooling layer has a function of performing pooling on image data input from the convolution layer. Pooling is a process of dividing image data into a plurality of regions, extracting predetermined data for each of the regions, and arranging the data in a matrix. Pooling reduces the image data while leaving the features extracted by the convolutional layer. As pooling, maximum pooling, average pooling, Lp pooling and the like can be used.
  • CNN convolutional neural network
  • the entire bonding layer be arranged.
  • the entire bonding layer may be arranged in multiple layers.
  • the entire combined layer has a function of determining whether the secondary battery is normal or abnormal using image data subjected to convolution and pooling.
  • this embodiment mode can be freely combined with Embodiment Mode 1.
  • FIG. 1 An example which is partially different from the first embodiment is shown in FIG. This is the same as FIG. 1 except that a plurality of abnormality determination outputs are prepared, so the detailed description will be omitted.
  • the first embodiment shows an example of classifying two types, normal and abnormal.
  • the accuracy of abnormality detection can be raised by finely classifying.
  • data of the occurrence of three types of micro shorts are stored at the time of learning, and using these data, it is classified as normal or abnormal.
  • this embodiment mode can be freely combined with Embodiment Mode 1.
  • Embodiment 4 In the present embodiment, an example which is partially different from the first embodiment is shown in FIG. The process is the same as that of FIG. 1 except that the value of the measured charge data and the like are stored in the memory unit in step S3, and thus the detailed description will be omitted.
  • Power saving can be achieved by using a transistor including an oxide semiconductor for the memory portion.
  • the configuration is useful because many arithmetic processes are performed with data held in the memory unit.
  • NOSRAM nonvolatile oxide semiconductor RAM
  • 2T type, 3T type a memory device using an OS transistor
  • OS memory a memory device using an OS transistor such as a NOSRAM
  • the OS memory is a memory that has at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with extremely small off current, the OS memory has excellent retention characteristics and can function as a non-volatile memory.
  • FIG. 7 shows an example of the configuration of the NOSRAM.
  • the NOSRAM 1600 shown in FIG. 7 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670.
  • the NOSRAM 1600 is a multivalued NOSRAM that stores multivalued data in one memory cell.
  • the memory cell array 1610 has a plurality of memory cells 1611, a plurality of word lines WWL and RWL, a bit line BL, and a source line SL.
  • the word line WWL is a write word line
  • the word line RWL is a read word line.
  • 3-bit (eight-valued) data is stored in one memory cell 1611.
  • the controller 1640 controls the entire NOSRAM 1600 in a centralized manner, writes the data WDA [31: 0], and reads the data RDA [31: 0].
  • the controller 1640 processes external command signals (for example, a chip enable signal, a write enable signal, etc.) to generate control signals for the row driver 1650, the column driver 1660 and the output driver 1670.
  • the row driver 1650 has a function of selecting a row to access.
  • the row driver 1650 includes a row decoder 1651 and a word line driver 1652.
  • Column driver 1660 drives source line SL and bit line BL.
  • the column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-to-analog conversion circuit) 1663.
  • the DAC 1663 converts 3-bit digital data into an analog voltage.
  • the DAC 1663 converts 32-bit data WDA [31: 0] into analog voltages every three bits.
  • the write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and an input of the write voltage generated by the DAC 1663 to the selected source line SL.
  • the output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673.
  • the selector 1671 selects the source line SL to be accessed, and transmits the voltage of the selected source line SL to the ADC 1672.
  • the ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds the data output from the ADC 1672.
  • the configurations of the row driver 1650, the column driver 1660, and the output driver 1670 described in this embodiment are not limited to the above. Arrangements of these drivers and wirings connected to the drivers may be changed according to the configuration or driving method of the memory cell array 1610 or the like, or functions of the drivers and wirings connected to the drivers are changed Or you may add. For example, part of the functions of the source line SL may be provided to the bit line BL.
  • each memory cell 1611 is 3 bits in the above description, the configuration of the storage device described in this embodiment is not limited to this.
  • the amount of information held by each memory cell 1611 may be 2 bits or less, or 4 bits or more.
  • the DAC 1663 and the ADC 1672 may not be provided.
  • FIG. 8A is a circuit diagram showing a configuration example of the memory cell 1611.
  • the memory cell 1611 is a 2T-type gain cell, and the memory cell 1611 is electrically connected to the word lines WWL and RWL, the bit line BL, the source line SL, and the wiring BGL.
  • the memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitive element C61.
  • the OS transistor MO61 is a write transistor.
  • the transistor MP61 is a read transistor, and is formed of, for example, a p-channel Si transistor.
  • the capacitive element C61 is a holding capacitance for holding the voltage of the node SN.
  • the node SN is a data holding node and corresponds to the gate of the transistor MP61 here.
  • the NOSRAM 1600 can hold data for a long time.
  • bit line is a common bit line for writing and reading, but as shown in FIG. 8B, the bit line WBL functioning as a writing bit line and the reading bit line And the bit line RBL may be provided.
  • FIGS. 8C to 8E show other configuration examples of the memory cell.
  • FIGS. 8C to 8E show an example in which the write bit line WBL and the read bit line RBL are provided, but as shown in FIG. 8A, they are shared by writing and reading. Bit lines may be provided.
  • a memory cell 1612 shown in FIG. 8C is a modified example of the memory cell 1611, in which the read transistor is changed to an n-channel transistor (MN 61).
  • the transistor MN61 may be an OS transistor or a Si transistor.
  • the OS transistor MO61 may be an OS transistor without a back gate.
  • the memory cell 1613 illustrated in FIG. 8D is a 3T-type gain cell, and is electrically connected to the word lines WWL and RWL, the bit lines WBL and RBL, the source line SL, and the wirings BGL and PCL.
  • the memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62.
  • the OS transistor MO62 is a write transistor.
  • the transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.
  • a memory cell 1614 shown in FIG. 8E is a modification of the memory cell 1613, in which the read transistor and the select transistor are changed to n-channel transistors (MN62 and MN63).
  • the transistors MN62 and MN63 may be OS transistors or Si transistors.
  • the OS transistors provided in the memory cells 1611-1614 may be transistors without back gates or may be transistors with back gates.
  • FIG. 9 is a circuit diagram showing a configuration example of a NAND type memory cell array 1610.
  • the memory cell array 1610 illustrated in FIG. 9 includes a source line SL, a bit line RBL, a bit line WBL, a word line WWL, a word line RWL, a wiring BGL, and a memory cell 1615.
  • the memory cell 1615 includes a node SN, an OS transistor MO63, a transistor MN64, and a capacitive element C63.
  • the transistor MN64 is formed of, for example, an n-channel Si transistor.
  • the transistor MN 64 may be a p-channel Si transistor or an OS transistor.
  • the memory cell 1615 a and the memory cell 1615 b illustrated in FIG. 9 will be described as an example.
  • reference numerals of a wiring or a circuit element connected to either the memory cell 1615 a or the memory cell 1615 b are denoted by a or b.
  • the gate of the transistor MN64a, one of the source and the drain of the OS transistor MO63a, and one of the electrodes of the capacitive element C63a are electrically connected. Further, the bit line WBL and the other of the source and the drain of the OS transistor MO63a are electrically connected. In addition, the word line WWLa and the gate of the OS transistor MO63a are electrically connected. Further, the wiring BGLa and the back gate of the OS transistor MO63a are electrically connected. The word line RWLa and the other of the electrodes of the capacitive element C 63 a are electrically connected.
  • the memory cell 1615 b can be provided symmetrically with the memory cell 1615 a with the contact portion with the bit line WBL as an axis of symmetry. Accordingly, the circuit element included in the memory cell 1615 b is also connected to the wiring in the same manner as the memory cell 1615 a.
  • the source of the transistor MN64a included in the memory cell 1615a is electrically connected to the drain of the transistor MN64b in the memory cell 1615b.
  • the drain of the transistor MN64a included in the memory cell 1615a is electrically connected to the bit line RBL.
  • the source of the transistor MN64b included in the memory cell 1615b is electrically connected to the source line SL through the transistor MN64 included in the plurality of memory cells 1615.
  • the plurality of transistors MN64 are connected in series between the bit line RBL and the source line SL.
  • write operation and read operation are performed for each of a plurality of memory cells (hereinafter referred to as a memory cell column) connected to the same word line WWL (or word line RWL).
  • the write operation can be performed as follows. A potential at which the OS transistor MO63 is turned on is applied to the word line WWL connected to the memory cell column to be written, and the OS transistor MO63 of the memory cell column to be written is turned on. Thereby, the potential of the bit line WBL is applied to one of the gate of the transistor MN64 of the designated memory cell column and the electrode of the capacitive element C63, and a predetermined charge is applied to the gate. Then, when the OS transistor MO63 of the memory cell column is turned off, the predetermined charge given to the gate can be held. Thus, data can be written to the memory cell 1615 of the specified memory cell column.
  • the read operation can be performed as follows. First, to a word line RWL not connected to a memory cell column to be read, a potential that turns on the transistor MN64 regardless of the charge applied to the gate of the transistor MN64 is applied to read a memory cell column The other transistors MN64 are turned on. Then, a potential (read potential) is applied to the word line RWL connected to the memory cell column to be read by the charge of the gate of the transistor MN64 so that the on state or the off state of the transistor MN64 is selected. Then, a constant potential is applied to the source line SL, and the reading circuit connected to the bit line RBL is brought into an operating state.
  • the conductance between the source line SL and the bit line RBL is for reading It is determined by the state (on state or off state) of the transistor MN64 of the memory cell column.
  • the conductance of the transistor differs depending on the charge of the gate of the transistor MN64 in the memory cell column to be read, and accordingly, the potential of the bit line RBL takes a different value.
  • Information can be read out from the memory cell 1615 of the specified memory cell column by reading out the potential of the bit line RBL by the reading circuit.
  • the number of times of rewriting is in principle not limited, and data can be written and read with low energy.
  • the refresh frequency can be reduced.
  • the OS transistors MO61, MO62, and MO63, capacitive elements C61, C62, and C63, and transistors MP61, MP62, MP63, MN61, and MN62. , MN 63 and MN 64 can be used.
  • the area occupied by the transistor and the pair of capacitor elements in top view can be reduced, so that the memory device can be further highly integrated.
  • the storage capacity per unit area of the storage device can be increased.
  • DOSRAM registered trademark
  • 1T transistor
  • 1C capacitor
  • FIG. 10 shows a configuration example of DOSRAM.
  • the DOSRAM 1400 has a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell and a sense amplifier array 1420 (hereinafter also referred to as "MC-SA array 1420").
  • the row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414.
  • the column circuit 1415 has a global sense amplifier array 1416 and an input / output circuit 1417.
  • the global sense amplifier array 1416 has a plurality of global sense amplifiers 1447.
  • the MC-SA array 1420 has a memory cell array 1422, a sense amplifier array 1423, and global bit lines GBLL and GBLR.
  • the MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423.
  • Global bit lines GBLL and GBLR are stacked on memory cell array 1422.
  • a hierarchical bit line structure hierarchized by local bit lines and global bit lines is adopted as the structure of bit lines.
  • Memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 ⁇ 0> to 1425 ⁇ N-1>.
  • N is an integer of 2 or more
  • the local memory cell array 1425 has a plurality of memory cells 1445, a plurality of word lines WL, and a plurality of bit lines BLL and BLR.
  • the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.
  • FIG. 11B shows a circuit configuration example of a pair of memory cells 1445a and 1445b connected in pair to the common bit line BLL (BLR).
  • the memory cell 1445a includes a transistor MW1a, a capacitive element CS1a, and terminals B1a and B2a, and is connected to the word line WLa and the bit line BLL (BLR).
  • the memory cell 1445 b has a transistor MW 1 b, a capacitive element CS 1 b, terminals B 1 b and B 2 b, and is connected to the word line WLb and the bit line BLL (BLR). Note that, in the following, when one of the memory cell 1445a and the memory cell 1445b is not particularly limited, the memory cell 1445 and the configuration attached to the memory cell 1445 may not be denoted by the symbol a or b.
  • the transistor MW1a has a function of controlling charging and discharging of the capacitive element CS1a
  • the transistor MW1b has a function of controlling charging and discharging of the capacitive element CS1b.
  • the gate of transistor MW1a is electrically connected to word line WLa, the first terminal is electrically connected to bit line BLL (BLR), and the second terminal is electrically connected to the first terminal of capacitive element CS1a.
  • the gate of transistor MW1b is electrically connected to word line WLb, the first terminal is electrically connected to bit line BLL (BLR), and the second terminal is electrically connected to the first terminal of capacitive element CS1b. It is done.
  • the bit line BLL (BLR) is commonly used for the first terminal of the transistor MW1a and the first terminal of the transistor MW1b.
  • the transistor MW1 has a function of controlling charging and discharging of the capacitive element CS1.
  • the second terminal of the capacitive element CS1 is electrically connected to the terminal B2.
  • a constant voltage (for example, low power supply voltage) is input to the terminal B2.
  • the transistor MW1a, the transistor MW1b, the capacitor CS1a, and the capacitor CS1b can be used.
  • the area occupied by the transistor and the pair of capacitor elements in top view can be reduced, so that the memory device can be highly integrated.
  • the storage capacity per unit area of the storage device can be increased.
  • the transistor MW1 has a back gate, and the back gate is electrically connected to the terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed by the voltage of the terminal B1.
  • the voltage of the terminal B1 may be a fixed voltage (for example, a negative constant voltage), or the voltage of the terminal B1 may be changed according to the operation of the DOS RAM 1400.
  • the back gate of the transistor MW1 may be electrically connected to the gate, the source, or the drain of the transistor MW1. Alternatively, the transistor MW1 may not be provided with a back gate.
  • Sense amplifier array 1423 includes N local sense amplifier arrays 1426 ⁇ 0> to 1426 ⁇ N-1>.
  • the local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446.
  • a bit line pair is electrically connected to sense amplifier 1446.
  • the sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying a voltage difference between the bit line pair, and a function of holding the voltage difference.
  • the switch array 1444 has a function of selecting a bit line pair and conducting between the selected bit line pair and the global bit line pair.
  • bit line pair means two bit lines which are simultaneously compared by the sense amplifier.
  • the global bit line pair refers to two global bit lines which are simultaneously compared by the global sense amplifier.
  • a bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines.
  • bit line BLL and the bit line BLR form a pair of bit lines.
  • Global bit line GBLL and global bit line GBLR form a pair of global bit lines.
  • bit line pair (BLL, BLR) and the global bit line pair (GBLL, GBLR) are also referred to.
  • the controller 1405 has a function of controlling the overall operation of the DOS RAM 1400.
  • the controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and generates a control signal for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. And a function of holding an address signal input from the outside, and a function of generating an internal address signal.
  • the row circuit 1410 has a function of driving the MC-SA array 1420.
  • the decoder 1411 has a function of decoding an address signal.
  • the word line driver circuit 1412 generates a selection signal for selecting the word line WL in the access target row.
  • the column selector 1413 and the sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423.
  • the column selector 1413 has a function of generating a selection signal for selecting a bit line of the access target column.
  • the selection signal of column selector 1413 controls switch array 1444 of each local sense amplifier array 1426.
  • the control signals of the sense amplifier driver circuit 1414 drive the plurality of local sense amplifier arrays 1426 independently.
  • Column circuit 1415 has a function of controlling an input of data signal WDA [31: 0] and a function of controlling an output of data signal RDA [31: 0].
  • the data signal WDA [31: 0] is a write data signal
  • the data signal RDA [31: 0] is a read data signal.
  • Global sense amplifier 1447 is electrically connected to global bit line pair (GBLL, GBLR).
  • the global sense amplifier 1447 has a function of amplifying a voltage difference between the global bit line pair (GBLL, GBLR) and a function of holding this voltage difference. Writing and reading of data to the global bit line pair (GBLL, GBLR) are performed by the input / output circuit 1417.
  • Data is written to the global bit line pair by input / output circuit 1417.
  • Data of the global bit line pair is held by the global sense amplifier array 1416.
  • the data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 designated by the address.
  • the local sense amplifier array 1426 amplifies and holds the written data.
  • the row circuit 1410 selects the word line WL of the target row, and the data held by the local sense amplifier array 1426 is written to the memory cell 1445 of the selected row.
  • One row of the local memory cell array 1425 is designated by the address signal.
  • the word line WL in the target row is selected, and the data of the memory cell 1445 is written to the bit line.
  • the local sense amplifier array 1426 detects and holds the voltage difference of the bit line pair of each column as data.
  • data in the column designated by the address signal is written to the global bit line pair by switch array 1444.
  • the global sense amplifier array 1416 detects and holds data of the global bit line pair.
  • the held data of the global sense amplifier array 1416 is output to the input / output circuit 1417. Thus, the read operation is completed.
  • the number of times of rewriting is not limited in principle in the DOSRAM 1400, and data can be written and read with low energy.
  • the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.
  • the transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, charge leakage from the capacitive element CS1 can be suppressed. Therefore, the retention time of the DOS RAM 1400 is very long compared to the DRAM. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites a large amount of data with high frequency, for example, a frame memory used for image processing.
  • bit lines can be shortened to a length approximately equal to the length of local sense amplifier array 1426.
  • the bit line capacitance can be reduced and the storage capacitance of the memory cell 1445 can be reduced.
  • the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. From the above reasons, the load driven at the time of access to the DOS RAM 1400 is reduced, and power consumption can be reduced. Therefore, memory power consumption can be reduced also in neural network processing.
  • this embodiment mode can be freely combined with Embodiment Mode 1.
  • FIG. 13 shows an example of an IC in which an AI system is incorporated.
  • FIG. 12 is a block diagram showing a configuration example of the AI system 4041.
  • the AI system 4041 includes an operation unit 4010, a control unit 4020, and an input / output unit 4030.
  • the operation unit 4010 includes an analog operation circuit 4011, a DOSRAM 4012, a NOSRAM 4013, and an FPGA 4014.
  • the DOSRAM 1400 and the NOSRAM 1600 described in Embodiment 4 can be used as the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014.
  • the control unit 4020 includes a central processing unit (CPU) 4021, a graphics processing unit (GPU) 4022, a phase locked loop (PLL) 4023, a static random access memory (SRAM) 4024, and a programmable read only memory (PROM) 4025. , A memory controller 4026, a power supply circuit 4027, and a PMU (Power Management Unit) 4028.
  • CPU central processing unit
  • GPU graphics processing unit
  • PLL phase locked loop
  • SRAM static random access memory
  • PROM programmable read only memory
  • the input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general purpose input / output module 4034, and a communication module 4035.
  • the operation unit 4010 can execute learning or inference by a neural network.
  • the analog operation circuit 4011 includes an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a product-sum operation circuit.
  • the analog arithmetic circuit 4011 is preferably formed using an OS transistor.
  • the analog operation circuit 4011 using the OS transistor has an analog memory, and can perform the product-sum operation necessary for learning or inference with low power consumption.
  • the DOSRAM 4012 is a DRAM formed using an OS transistor, and the DOSRAM 4012 is a memory for temporarily storing digital data sent from the CPU 4021.
  • the DOSRAM 4012 has a memory cell including an OS transistor and a read out circuit unit including an Si transistor. Since the memory cell and the read out circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the entire circuit area.
  • Calculations using neural networks may have more than 1000 input data.
  • the SRAM has a limited circuit area and a small storage capacity, so the input data can not but be divided and stored.
  • the DOSRAM 4012 can arrange memory cells in a highly integrated manner even with a limited circuit area, and has a larger storage capacity than an SRAM. Therefore, the DOS RAM 4012 can store the input data efficiently.
  • the NOSRAM 4013 is a non-volatile memory using an OS transistor.
  • the NOSRAM 4013 consumes less power when writing data as compared to other non-volatile memories such as flash memory, ReRAM (Resistive Random Access Memory) and MRAM (Magnetoresistive Random Access Memory).
  • flash memory ReRAM (Resistive Random Access Memory)
  • MRAM Magneticoresistive Random Access Memory
  • the NOSRAM 4013 can store multi-value data of 2 bits or more in addition to 1-bit binary data.
  • the NOSRAM 4013 can reduce the memory cell area per bit by storing multi-value data.
  • the NOSRAM 4013 can store analog data. Therefore, the analog operation circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, no D / A conversion circuit or A / D conversion circuit is required. Therefore, the NOSRAM 4013 can reduce the area of peripheral circuits.
  • analog data refers to data having a resolution of 3 bits (eight values) or more. The above-mentioned multi-value data may be included in the analog data.
  • Data and parameters used for neural network calculations can be temporarily stored in the NOSRAM 4013.
  • the above data and parameters may be stored in a memory provided outside the AI system 4041 via the CPU 4021.
  • the NOSRAM 4013 provided inside has higher speed and lower power consumption than the data and parameters. Can be stored. Further, since the NOSRAM 4013 can make the bit line longer than the DOS RAM 4012, the storage capacity can be increased.
  • the FPGA 4014 is an FPGA using an OS transistor.
  • the AI system 4041 uses the FPGA 4014 to perform deep neural networks (DNN), convolutional neural networks (CNN), recursive neural networks (RNN), self-coder, deep Boltzmann machine (DBM), which will be described later in hardware. It is possible to configure connections of neural networks, such as Deep Belief Networks (DBNs).
  • DNNs Deep Belief Networks
  • the FPGA 4014 is an FPGA having an OS transistor.
  • the OS-FPGA can have a smaller memory area than an FPGA configured with SRAM. Therefore, even if the context switching function is added, the area increase is small.
  • the OS-FPGA can also transmit data and parameters at high speed by boosting.
  • the AI system 4041 can provide the analog operation circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 on one die (chip). Therefore, the AI system 4041 can perform neural network calculations at high speed and low power consumption. Further, the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be manufactured by the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.
  • the arithmetic unit 4010 need not have all the DOS RAM 4012, the NOSRAM 4013, and the FPGA 4014.
  • One or more of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 may be selected and provided in accordance with the problem that the AI system 4041 wants to solve.
  • the AI system 4041 can perform deep neural network (DNN), convolutional neural network (CNN), recursive neural network (RNN), self-coder, deep Boltzmann machine (DBM), deep belief network ( Methods such as DBN) can be implemented.
  • the PROM 4025 can store programs for performing at least one of these techniques. In addition, part or all of the program may be stored in the NOSRAM 4013.
  • the AI system 4041 preferably includes a GPU 4022.
  • the AI system 4041 can execute the product-sum operation that is rate-limiting in the operation unit 4010 and can execute the other product-sum operations in the GPU 4022. By doing so, learning and inference can be performed at high speed.
  • the power supply circuit 4027 not only generates a low power supply potential for a logic circuit, but also performs potential generation for analog operation.
  • the power supply circuit 4027 may use an OS memory.
  • the power supply circuit 4027 can reduce power consumption by storing the reference potential in the OS memory.
  • the PMU 4028 has a function of temporarily stopping the power supply of the AI system 4041.
  • the CPU 4021 and the GPU 4022 preferably have OS memory as a register.
  • OS memory By having the OS memory, the CPU 4021 and the GPU 4022 can keep data (logical value) in the OS memory even when the power supply is stopped. As a result, the AI system 4041 can save power.
  • the PLL 4023 has a function of generating a clock.
  • the AI system 4041 operates based on the clock generated by the PLL 4023.
  • the PLL 4023 preferably has an OS memory.
  • the PLL 4023 having an OS memory can hold an analog potential for controlling the oscillation cycle of the clock.
  • the AI system 4041 may store data in an external memory such as DRAM. Therefore, the AI system 4041 preferably has a memory controller 4026 that functions as an interface with an external DRAM. In addition, the memory controller 4026 is preferably disposed near the CPU 4021 or the GPU 4022. By doing so, it is possible to exchange data at high speed.
  • Part or all of the circuits illustrated in the control unit 4020 can be formed over the same die as the computing unit 4010. By doing so, the AI system 4041 can perform neural network calculations at high speed and low power consumption.
  • the AI system 4041 preferably includes an external storage control circuit 4031 that functions as an interface with an external storage device.
  • the AI system 4041 includes a voice codec 4032 and a video codec 4033.
  • the audio codec 4032 encodes (decodes) and decodes (decodes) audio data
  • the video codec 4033 encodes and decodes video data.
  • the AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general purpose input / output module 4034.
  • the general-purpose input / output module 4034 includes, for example, Universal Serial Bus (USB), Inter-Integrated Circuit (I2C), and the like.
  • the AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 preferably has a communication module 4035.
  • the analog operation circuit 4011 may use a multi-level flash memory as an analog memory.
  • the flash memory is limited in the number of rewrites.
  • the analog arithmetic circuit 4011 may use ReRAM as an analog memory.
  • ReRAM is limited in the number of times of rewriting, and there is a problem in storage accuracy.
  • the element since the element has two terminals, the circuit design that separates writing and reading of data becomes complicated.
  • the analog operation circuit 4011 may use an MRAM as an analog memory.
  • the MRAM has a low rate of change in resistance, and has problems in storage accuracy.
  • the analog arithmetic circuit 4011 use the OS memory as an analog memory.
  • the AI system can integrate a digital processing circuit made of a Si transistor such as a CPU, an analog operation circuit using an OS transistor, and an OS memory such as an OS-FPGA and DOSRAM or NOSRAM in one die.
  • a digital processing circuit made of a Si transistor such as a CPU, an analog operation circuit using an OS transistor, and an OS memory such as an OS-FPGA and DOSRAM or NOSRAM in one die.
  • FIG. 13 shows an example of an IC incorporating an AI system.
  • An AI system IC 7000 shown in FIG. 13 has a lead 7001 and a circuit portion 7003.
  • AI system IC 7000 is mounted on, for example, printed circuit board 7002.
  • a plurality of such IC chips are combined and electrically connected on the printed circuit board 7002 to complete a board (mounting board 7004) on which electronic components are mounted.
  • the various circuits described in the above embodiment are provided in one die.
  • the circuit portion 7003 has a stacked structure and is roughly classified into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked on the Si transistor layer 7031, the AI system IC 7000 can be easily miniaturized.
  • QFP Quad Flat Package
  • a digital processing circuit such as a CPU, an analog operation circuit using an OS transistor, an OS-FPGA and an OS memory such as DOSRAM or NOSRAM may be formed in the Si transistor layer 7031, the wiring layer 7032 and the OS transistor layer 7033 it can. That is, the elements constituting the above AI system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment does not need to increase the manufacturing process even if the number of elements is increased, and the above-mentioned AI system can be incorporated at low cost.
  • the state of the secondary battery to be judged is analyzed to create data. Specifically, the remaining amount information of the secondary battery is acquired (step S1).
  • the capacity of the secondary battery can be determined, for example, by the product of the current and time of the secondary battery.
  • the coulomb counter CC may be used to determine the capacity of the secondary battery.
  • the SOC (state of charge) of the secondary battery may be used.
  • the SOC of the secondary battery may be estimated from the voltage of the secondary battery.
  • step S2 If the SOC is less than 50%, the process proceeds to the next step, charging start (step S2). If the SOC is 50% or more, the secondary battery is discharged by the discharge circuit to make the SOC less than 50%, preferably 20% or less.
  • Step S3 Data on the charge characteristics of the secondary battery is measured from the start of charging for detection of abnormality to time t, and the measured data is stored in the memory unit (step S3).
  • the charging curve is an image obtained by imaging a graph obtained by accumulating the charging data.
  • the obtained charge curve is converted into image data to obtain a plurality of input data (step S4).
  • the charge curve is converted into image data (210 ⁇ 210) of 8-bit gray gradation from 0 to 255.
  • the discharged state (low voltage) is black and the fully charged state is white.
  • the left of FIG. 15 (A) has shown the charge start position.
  • the input data is determined (step 5).
  • this determination or classification
  • processing of a neural network is performed and product-sum operation is used.
  • the features of the input data are classified as normal or abnormal using the weight parameters created at the time of training.
  • the mode is divided into two types: a mode in which the voltage sharply drops as a tendency of the occurrence of a micro short and a mode in which the voltage falls slowly.
  • FIG. 16A is an example of image data when fully charged, and the right shows completion of charging.
  • the detection timing is set every 2100 seconds, but after the first detection timing is set to 2100 seconds, it may be set every 60 seconds, or it may be set closer to real time to make an abnormality. It is preferable to set it as the abnormality detection system which can respond promptly, when it detects.
  • the reason for setting the first detection timing to 2100 seconds was found from the data of the secondary battery for learning, and was obtained by trial and error. Therefore, if the type of secondary battery to be targeted changes, It may change depending on the data of the next battery. However, it can be said empirically that it is preferable to maintain the principle of lengthening the interval from the charge start to the first detection timing and making the subsequent detection intervals the same or shorter.
  • FIG. 16B shows an example of image data at the time of full charge of data in which a micro short has occurred for comparison.
  • FIG. 16 (B) although the occurrence of the micro short circuit is observed near the middle of the charge, the occurrence of the micro short is observed near the middle of the charge, so when the abnormality detection method of this embodiment is used, the abnormality is detected during the charge. It is possible to stop charging or warn immediately.
  • image data is visualized (image display when displayed on a display device).
  • a television set also referred to as a television or a television receiver
  • a monitor for a computer a digital camera, a digital video camera, a digital photo frame
  • a mobile phone A large-sized game machine such as a telephone, a mobile phone device), a portable game machine, a portable information terminal, a sound reproduction device, a pachinko machine and the like can be mentioned.
  • FIGS. 18A and 18B illustrate an example of a foldable tablet terminal.
  • the tablet terminal 9600 illustrated in FIGS. 18A and 18B includes a housing 9630a, a housing 9630b, a movable portion 9640 connecting the housing 9630a and the housing 9630b, a display portion 9631, a display mode switching switch 9626 , A power switch 9627, a power saving mode switching switch 9625, a fastener 9629, and an operation switch 9628.
  • FIG. 18A shows a state in which the tablet terminal 9600 is opened
  • FIG. 18B shows a state in which the tablet terminal 9600 is closed.
  • the tablet terminal 9600 includes a power storage body 9635 inside the housings 9630 a and 9630 b.
  • the power storage unit 9635 is provided over the housing 9630 a and the housing 9630 b through the movable portion 9640.
  • a portion of the display portion 9631 can be a touch panel region, and data can be input by touching a displayed operation key.
  • the keyboard button can be displayed on the display portion 9631 by touching the position where the keyboard display switching button of the touch panel is displayed with a finger, a stylus, or the like.
  • the display mode switching switch 9626 can switch the display orientation such as vertical display or horizontal display, and can select switching between black and white display and color display.
  • the power saving mode switching switch 9625 can optimize display luminance in accordance with the amount of outside light at the time of use detected by the light sensor incorporated in the tablet terminal 9600.
  • the tablet type terminal may incorporate not only an optical sensor but also other detection devices such as a sensor for detecting inclination of a gyro, an acceleration sensor or the like.
  • FIG. 18B shows a state where the tablet terminal 9600 is closed, and the tablet terminal includes a charge and discharge control circuit 9634 including a housing 9630, a solar cell 9633, and a DCDC converter 9636.
  • the secondary battery abnormality detection system according to one embodiment of the present invention is used with the storage battery 9635 as a monitoring target.
  • the tablet terminal can perform neural network processing for detecting an abnormality of the secondary battery by electrically connecting an IC incorporating the AI system to the storage battery 9635.
  • the tablet terminal 9600 can be folded in two, the housing 9630a and the housing 9630b can be folded so as to overlap when not in use. Since the display portion 9631 can be protected by folding, durability of the tablet terminal 9600 can be improved.
  • the power storage unit 9635 including the abnormality detection system of one embodiment of the present invention can provide a tablet terminal 9600 that can be used for a long time.
  • the tablet type terminal shown in FIGS. 18A and 18B has a function of displaying various information (still image, moving image, text image, etc.), a calendar, a date or time, etc.
  • a function of displaying on the display portion, a touch input function of performing touch input operation or editing of information displayed on the display portion, a function of controlling processing by various software (programs), and the like can be provided.
  • Electric power can be supplied to the touch panel, the display portion, the video signal processing portion, or the like by the solar battery 9633 mounted on the surface of the tablet terminal.
  • the solar battery 9633 can be provided on one side or both sides of the housing 9630, and can be efficiently charged with the power storage unit 9635.
  • FIG. 18C illustrates a solar cell 9633, a storage battery 9635, a DCDC converter 9636, a converter 9637, switches SW1 to SW3, and a display portion 9631.
  • the storage battery 9635, the DCDC converter 9636, the converter 9637, the switch SW1 to The portion SW3 corresponds to the charge / discharge control circuit 9634 shown in FIG.
  • the electric power generated by the solar cell is stepped up or down by the DCDC converter 9636 so as to be a voltage for charging the power storage unit 9635. Then, when the power from the solar cell 9633 is used for the operation of the display portion 9631, the switch SW1 is turned on, and the converter 9637 boosts or steps down the voltage necessary for the display portion 9631. In addition, when display on the display portion 9631 is not performed, the switch SW1 may be turned off and the switch SW2 may be turned on to charge the power storage unit 9635.
  • the solar cell 9633 is illustrated as an example of the power generation means, it is not particularly limited, and a configuration in which the power storage body 9635 is charged by another power generation means such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element) It may be For example, a non-contact power transmission module that transmits and receives power wirelessly (without contact) to charge the battery, or another charging unit may be combined.
  • FIG. 19 shows an example of another electronic device.
  • a display device 8000 is an example of an electronic device on which the abnormality detection system for the secondary battery 8004 is mounted.
  • the display device 8000 corresponds to a display device for receiving a TV broadcast, and includes a housing 8001, a display portion 8002, a speaker portion 8003, a secondary battery 8004, and the like.
  • the abnormality detection system according to one embodiment of the present invention is provided inside the housing 8001.
  • the display device 8000 can receive power supply from a commercial power supply, or can use power stored in the secondary battery 8004.
  • the display device 8000 can perform neural network processing for detecting an abnormality of a secondary battery by electrically connecting an IC in which an AI system is incorporated to the secondary battery 8004.
  • the display portion 8002 includes a liquid crystal display device, a light emitting device including a light emitting element such as an organic EL element in each pixel, an electrophoretic display device, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), and an FED (Field Emission Display). Etc.) can be used.
  • a light emitting device including a light emitting element such as an organic EL element in each pixel
  • an electrophoretic display device a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), and an FED (Field Emission Display). Etc.) can be used.
  • the voice input device 8005 also uses a secondary battery.
  • the voice input device 8005 can perform neural network processing for detecting an abnormality of the secondary battery by electrically connecting an IC incorporating the AI system to the secondary battery.
  • the voice input device 8005 includes a microphone and a plurality of sensors (optical sensor, temperature sensor, humidity sensor, barometric pressure sensor, illuminance sensor, motion sensor, etc.) in addition to a wireless communication element, and the user's instructional words Power supply operation of a device such as the display device 8000, light amount adjustment of the lighting device 8100, and the like can be performed.
  • the voice input device 8005 can operate peripheral devices by voice and can replace the manual remote control.
  • the voice input device 8005 has wheels and mechanical moving means, moves in the direction in which the user can hear the voice, hears the command accurately with the built-in microphone, and displays the contents on the display portion 8008. Or a touch input operation of the display portion 8008 can be performed.
  • the voice input device 8005 can also function as a charging dock of a portable information terminal 8009 such as a smartphone.
  • the portable information terminal 8009 and the voice input device 8005 can transmit and receive power by wire or wirelessly. There is no need to carry the portable information terminal indoors, and it is necessary to maintain and maintain the necessary capacity, and to avoid load and deterioration of the secondary battery, so the voice input device 8005 manages and maintains the secondary battery. It is desirable to be able to In addition, since the speaker 8007 and the microphone are included, hands-free conversation can be performed even during charging.
  • the capacity of the secondary battery of the voice input device 8005 is lowered, it moves in the direction of the arrow, and charging may be performed by wireless charging from the charging module 8010 connected to the external power supply. If an IC incorporating an AI system is mounted on the charging module 8010, it is possible to perform neural network processing indirectly for detecting an abnormality in the secondary battery of the portable information terminal 8009.
  • the voice input device 8005 is installed on the floor is shown in FIG. 19, it is not particularly limited, and wheels or mechanical moving means may be provided to move to a desired position. You may fix without providing.
  • the display device includes all display devices for displaying information, such as for personal computers, for displaying advertisements, as well as for receiving TV broadcasts.
  • a stationary lighting device 8100 is an example of an electronic device using a secondary battery 8103 controlled by a microprocessor (including APS) which controls charging.
  • the lighting device 8100 includes a housing 8101, a light source 8102, a secondary battery 8103, and the like.
  • FIG. 19 illustrates the case where the secondary battery 8103 is provided inside the ceiling 8104 on which the housing 8101 and the light source 8102 are installed, the secondary battery 8103 is provided inside the housing 8101. It may be done.
  • the lighting device 8100 can receive power from a commercial power supply. Alternatively, the lighting device 8100 can use power stored in the secondary battery 8103.
  • the secondary battery is a stationary type provided on, for example, the side wall 8105, the floor 8106, the window 8107, and the like other than the ceiling 8104. It can also be used for a lighting device, and can also be used for a desk-type lighting device or the like.
  • an artificial light source which artificially obtains light using electric power can be used.
  • a discharge lamp such as an incandescent lamp and a fluorescent lamp
  • a light emitting element such as an LED or an organic EL element are mentioned as an example of the artificial light source.
  • an air conditioner having an indoor unit 8200 and an outdoor unit 8204 is an example of an electronic device using a secondary battery 8203.
  • the indoor unit 8200 includes a housing 8201, an air outlet 8202, a secondary battery 8203, and the like.
  • FIG. 19 illustrates the case where the secondary battery 8203 is provided in the indoor unit 8200, the secondary battery 8203 may be provided in the outdoor unit 8204. Alternatively, the secondary battery 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204.
  • the air conditioner can receive power from a commercial power supply, or can use power stored in the secondary battery 8203.
  • an electric refrigerator-freezer 8300 is an example of an electronic device using a secondary battery 8304.
  • the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, a secondary battery 8304, and the like.
  • the secondary battery 8304 is provided inside the housing 8301.
  • the electric refrigerator-freezer 8300 can receive power supply from a commercial power supply, or can use power stored in the secondary battery 8304.
  • the power usage rate when the electronic equipment is not used, especially in a time zone where the ratio of the amount of power actually used (referred to as the power usage rate) to the total amount of power that can be supplied by the commercial power supply source is low.
  • the power usage rate By storing power in the secondary battery, it is possible to suppress an increase in the power usage rate outside the above time zone.
  • the electric refrigerator-freezer 8300 electric power is stored in the secondary battery 8304 at night when the cold room door 8302 and the freezer room door 8303 are not opened / closed because the air temperature is low. Then, in the daytime when the temperature of the room rises and the refrigerator door 8302 and the freezer door 8303 are opened and closed, by using the secondary battery 8304 as an auxiliary power source, it is possible to suppress the daytime power usage rate low.
  • the secondary battery can be mounted on any electronic device other than the above-described electronic device. According to one aspect of the present invention, the cycle characteristics of the secondary battery are improved. Therefore, by mounting a microprocessor (including an APS) which controls charging, which is one embodiment of the present invention, in the electronic device described in this embodiment, the electronic device can have a longer lifetime. This embodiment can be implemented in appropriate combination with the other embodiments.
  • FIG. 20A an example of a cylindrical secondary battery 600 is illustrated in FIG. 20A as an example of a secondary battery mounted in an electric device.
  • the cylindrical secondary battery 600 has a positive electrode cap (battery lid) 601 on the top and a battery can (outer can) 602 on the side and bottom.
  • the positive electrode cap 601 and the battery can (outer can) 602 are insulated by a gasket (insulation packing) 610.
  • FIG. 20 (B) is a view schematically showing a cross section of a cylindrical secondary battery.
  • a battery element in which a strip-shaped positive electrode 604 and a negative electrode 606 are wound with a separator 605 interposed therebetween.
  • the battery element is wound around the center pin.
  • One end of the battery can 602 is closed and the other end is open.
  • a metal such as nickel, aluminum, titanium or the like having corrosion resistance to an electrolytic solution, or an alloy of these or an alloy of these with another metal (for example, stainless steel or the like) can be used. .
  • the battery element in which the positive electrode, the negative electrode, and the separator are wound is sandwiched between a pair of opposing insulating plates 608 and 609.
  • a non-aqueous electrolyte (not shown) is injected into the inside of the battery can 602 provided with the battery element.
  • the secondary battery includes a positive electrode containing an active material such as lithium cobaltate (LiCoO 2 ) and lithium iron phosphate (LiFePO 4 ), a negative electrode made of a carbon material such as graphite capable of absorbing and releasing lithium ions, and ethylene It comprises a non-aqueous electrolytic solution in which an electrolyte composed of a lithium salt such as LiBF 4 or LiPF 6 is dissolved in an organic solvent such as carbonate or diethyl carbonate.
  • an active material such as lithium cobaltate (LiCoO 2 ) and lithium iron phosphate (LiFePO 4 )
  • a negative electrode made of a carbon material such as graphite capable of absorbing and releasing lithium ions
  • ethylene ethylene
  • It comprises a non-aqueous electrolytic solution in which an electrolyte composed of a lithium salt such as LiBF 4 or LiPF 6 is dissolved in an organic solvent such as carbonate or diethyl carbonate.
  • a positive electrode terminal (positive electrode current collection lead) 603 is connected to the positive electrode 604, and a negative electrode terminal (negative electrode current collection lead) 607 is connected to the negative electrode 606. Both the positive electrode terminal 603 and the negative electrode terminal 607 can be made of a metal material such as aluminum.
  • the positive electrode terminal 603 is resistance welded to the safety valve mechanism 612, and the negative electrode terminal 607 is resistance welded to the bottom of the battery can 602.
  • the safety valve mechanism 612 is electrically connected to the positive electrode cap 601 via a PTC element (Positive Temperature Coefficient) 611.
  • the safety valve mechanism 612 disconnects the electrical connection between the positive electrode cap 601 and the positive electrode 604 when the increase in internal pressure of the battery exceeds a predetermined threshold.
  • the PTC element 611 is a heat sensitive resistance element whose resistance increases when the temperature rises, and the amount of current is limited by the increase of the resistance to prevent abnormal heat generation.
  • a barium titanate (BaTiO 3 ) -based semiconductor ceramic or the like can be used for the PTC element.
  • a plurality of secondary batteries 600 may be interposed between the conductive plate 613 and the conductive plate 614 to form a module 615.
  • the plurality of secondary batteries 600 may be connected in parallel, may be connected in series, or may be connected in series and then connected in series. By configuring the module 615 including the plurality of secondary batteries 600, large power can be extracted.
  • FIG. 20D is a top view of the module 615.
  • the conductive plate 613 is shown by a dotted line to clarify the figure.
  • the module 615 may have a conductor 616 electrically connecting the plurality of secondary batteries 600.
  • the conductive plate 613 can be provided over the conductive wire 616 in an overlapping manner.
  • the temperature control device 617 may be provided between the plurality of secondary batteries 600. When the secondary battery 600 is overheated, it can be cooled by the temperature control device 617, and when the secondary battery 600 is too cold, it can be heated by the temperature control device 617. Therefore, the performance of the module 615 is less susceptible to the outside air temperature.
  • an IC incorporating an AI system is mounted as a protection circuit for the plurality of secondary batteries 600, neural network processing for detecting an abnormality in the plurality of secondary batteries 600 can be performed.
  • a next-generation clean energy vehicle such as a hybrid vehicle (HEV), an electric vehicle (EV), or a plug-in hybrid vehicle (PHEV).
  • HEV hybrid vehicle
  • EV electric vehicle
  • PHEV plug-in hybrid vehicle
  • FIG. 21 illustrates a vehicle using a secondary battery abnormality detection system according to an aspect of the present invention.
  • An automobile 8400 shown in FIG. 21A is an electric automobile using an electric motor as a motive power source for traveling.
  • it is a hybrid car that can be used by appropriately selecting and using an electric motor and an engine as a power source for traveling.
  • the automobile 8400 has a battery module 8402 having a plurality of secondary batteries. If an IC incorporating an AI system is mounted as a protection circuit for a secondary battery, neural network processing for detecting an abnormality in the secondary battery can be performed. Even in an automobile 8400 using 1000 or more secondary batteries, neural network processing for detecting an abnormality of the secondary battery can be efficiently performed.
  • the secondary battery many small cylindrical secondary batteries shown in FIG. 20C may be used side by side with respect to the floor portion in the car. Further, as shown in FIG. 21 (A), the secondary battery shown in FIG. 20 (C) may be provided with a plurality of combined battery packs with respect to the floor portion in the vehicle.
  • the secondary battery can not only drive the electric motor 8406 but can also supply power to light emitting devices such as the headlight 8401 and the room light (not shown).
  • the secondary battery can supply power to a display device such as a speedometer or a tachometer which the automobile 8400 has.
  • the secondary battery can supply power to a semiconductor device such as a navigation system of the automobile 8400.
  • a solar cell 8405 is provided on the exterior of the vehicle.
  • An automobile 8400 shown in FIG. 21A includes an electric motor 8406 in a wheel, and a camera 8403 instead of a side mirror.
  • Reference numeral 8404 in FIG. 21A denotes a windshield.
  • FIG. 21B An automobile 8500 illustrated in FIG. 21B can be charged by receiving power supply from an external charging facility to a secondary battery included in the automobile 8500 by a plug-in system, a non-contact power feeding system, or the like.
  • FIG. 21B shows a state in which the secondary battery 8024 mounted on the vehicle 8500 from the ground-mounted charging device 8021 is charged through the cable 8022.
  • the charging method, the standard of the connector, etc. may be appropriately performed by a predetermined method such as CHAdeMO (registered trademark) or combo.
  • the charging device 8021 may be a charging station provided in a commercial facility, or may be a home power source.
  • the plug-in technology can charge the secondary battery 8024 mounted on the automobile 8500 by external power supply.
  • Charging can be performed by converting AC power into DC power through a converter such as an ACDC converter included in the charging device 8021.
  • a converter such as an ACDC converter included in the charging device 8021.
  • charging can be performed even if AC power is connected.
  • an IC incorporating an AI system is mounted on the charging device 8021, neural network processing for detecting an abnormality in a secondary battery of the automobile 8500 can be performed.
  • the power receiving device may be mounted on a vehicle, and power may be supplied contactlessly from a ground power transmitting device for charging.
  • charging can be performed not only while the vehicle is stopped but also while it is traveling by incorporating the power transmission device on the road or the outer wall.
  • power may be transmitted and received between vehicles using this method of non-contact power feeding.
  • a solar cell may be provided on the exterior of the vehicle to charge the secondary battery when the vehicle is stopped or traveling.
  • an electromagnetic induction method or a magnetic resonance method can be used for such non-contact power supply.
  • FIG. 21 (C) is an example of a two-wheeled vehicle mounted with an IC incorporating an AI system.
  • a scooter 8600 shown in FIG. 21C includes a secondary battery 8602, a side mirror 8601, and a direction indicator light 8603.
  • the secondary battery 8602 can supply electricity to the direction indicator 8603.
  • An IC incorporating an AI system can detect an abnormality in the secondary battery 8602.
  • a scooter 8600 shown in FIG. 21C can store the secondary battery 8602 in the under-seat storage 8604.
  • the secondary battery 8602 can be stored in the under-seat storage 8604 even if the under-seat storage 8604 is small.
  • the secondary battery 8602 can be removed, and at the time of charging, the secondary battery 8602 may be carried indoors, carried, charged, and stored before traveling.
  • the secondary battery mounted in the vehicle can also be used as an electric power supply source other than a vehicle.
  • a commercial power supply for example, at the peak of the power demand. If it is possible to avoid using a commercial power source at the peak of power demand, it can contribute to energy saving and reduction of carbon dioxide emissions.
  • image data are used, 70% of the whole are allocated for learning and 30% for testing, and the abnormality detection accuracy is confirmed.
  • the algorithm for inference was created in Python (Chainer).
  • the image data is converted into two-dimensional data representing the charging characteristics of the secondary battery measured in advance in gray tones, that is, array data of n rows ⁇ n (n> 2) columns.
  • array data represented in gray tones an algorithm used in pattern recognition for categorizing image data can be used. Since a program or IC used in image pattern recognition can be used, the cost for development can be reduced.
  • weight parameters also referred to as filters
  • features are extracted beforehand using normal data as correct labels and image data with correct labels as input data, and weighting parameters for feature extraction are stored in an array. Update and learn weights for each mini-batch size.
  • the mini-batch size is the number of data samples of the mini-batch.
  • the learning data if it is detected as abnormal at a certain time during charging, it is determined that a micro short has occurred in the secondary battery even if there is no abnormality in data after a certain time, and labeled as abnormal data and learned.
  • the mini-batch 40 is used, and the size of the array data is set to 210 ⁇ 210 so as to form a square matrix, and the gray scale is 8 bits.
  • the neural network processing in the neural network processing, three sets of convolution processing, max pooling processing, and dropout processing are performed to be inferred.
  • the normal characteristics and the abnormal characteristics of the secondary battery are determined based on the learning data.
  • the process is performed in the order of convolution (convolution and integration, product-sum) processing, max pooling processing, and dropout processing.
  • the extracted feature quantities are pooled, and the feature quantities are used as the output of the intermediate layer.
  • the dropout process is a process of removing certain data. After three sets of the above convolution processing, max pooling processing, and dropout processing, all combination processing is performed and then output.
  • the number of samples tested was 2500, and the number of incorrect answers was 2.
  • the correct answer rate was 99.92%. From these results, it can be said that abnormality (micro short) of the secondary battery could be detected with high probability using CNN.
  • the present invention was not limited to 8 bits, and similar results could be obtained even if the image data is 6 bits.

Abstract

According to the present invention, when an abnormality is detected in a secondary cell, e.g., when a phenomenon that reduces the safety of the secondary cell is sensed or foreseen, the operating conditions of the secondary cell are changed, thereby maintaining the safety of the secondary cell. The charging characteristics of a secondary cell are converted to data for an image, and a convolutional neural network (CNN) model is used to distinguish between normal characteristics and abnormal characteristics of the secondary cell on the basis of learning data. There is achieved a system for controlling charging of the secondary cell such that, after the state of the secondary cell is assessed to be abnormal, the system issues an alarm to the secondary cell indicating abnormal characteristics, or stops use of the secondary cell, or proposes replacement of the secondary cell, or changes charging conditions.

Description

二次電池の充電制御システム及び二次電池の異常検出方法Charge control system for secondary battery and abnormality detection method for secondary battery
本発明の一様態は、物、方法、又は、製造方法に関する。または、本発明は、プロセス、マシン、マニュファクチャ、又は、組成物（コンポジション・オブ・マター）に関する。本発明の一態様は、半導体装置、表示装置、発光装置、蓄電装置、照明装置または電子機器の製造方法に関する。特に、充電制御システム、充電制御方法、及び二次電池を有する電子機器に関する。本発明の一態様は、車両、または車両に設けられる車両用電子機器に関する。 One aspect of the present invention relates to an object, a method, or a method of manufacturing. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). One embodiment of the present invention relates to a method for manufacturing a semiconductor device, a display device, a light-emitting device, a power storage device, a lighting device, or an electronic device. In particular, the present invention relates to a charge control system, a charge control method, and an electronic device having a secondary battery. One embodiment of the present invention relates to a vehicle or a vehicle electronic device provided in the vehicle.
なお、本明細書中において、蓄電装置とは、蓄電機能を有する素子及び装置全般を指すものである。例えば、リチウムイオン二次電池などの蓄電池（二次電池ともいう）、リチウムイオンキャパシタ、全固体電池、及び電気二重層キャパシタなどを含む。 Note that in the present specification, a power storage device refers to all elements and devices having a power storage function. For example, a storage battery (also referred to as a secondary battery) such as a lithium ion secondary battery, a lithium ion capacitor, an all solid battery, an electric double layer capacitor, and the like are included.
　また、本発明の一態様は、ニューラルネットワーク、及びそれを用いた充電制御システムに関する。また、本発明の一態様は、ニューラルネットワークを用いた車両に関する。また、本発明の一態様は、車両に限定されず、構造体などに設置された太陽光発電パネルなどの発電設備から得られた電力を貯蔵するための蓄電装置にも適用できる。また、本発明の一態様は、ニューラルネットワークを用いた電子機器に関する。また、本発明の一態様は、ニューラルネットワークを用いた異常検出システムに関する。 Further, one aspect of the present invention relates to a neural network and a charge control system using the same. Further, one aspect of the present invention relates to a vehicle using a neural network. Further, one embodiment of the present invention is not limited to a vehicle, and can also be applied to a power storage device for storing power obtained from a power generation facility such as a solar power generation panel installed in a structure or the like. Further, one embodiment of the present invention relates to an electronic device using a neural network. Further, one aspect of the present invention relates to an abnormality detection system using a neural network.
近年、リチウムイオン二次電池、リチウムイオンキャパシタ、空気電池等、種々の蓄電装置の開発が盛んに行われている。特に高出力、高エネルギー密度であるリチウムイオン二次電池は、携帯電話、スマートフォン、タブレット、もしくはノート型コンピュータ等の携帯情報端末、携帯音楽プレーヤ、デジタルカメラ、医療機器、又は、ハイブリッド車（ＨＥＶ）、電気自動車（ＥＶ）、もしくはプラグインハイブリッド車（ＰＨＥＶ）等の次世代クリーンエネルギー自動車など、半導体産業の発展と併せて急速にその需要が拡大し、充電可能なエネルギーの供給源として現代の情報化社会に不可欠なものとなっている。 In recent years, various storage devices such as lithium ion secondary batteries, lithium ion capacitors, air batteries, and the like have been actively developed. In particular, lithium ion secondary batteries having high output and high energy density can be used in portable information terminals such as mobile phones, smartphones, tablets, or notebook computers, portable music players, digital cameras, medical devices, or hybrid vehicles (HEVs). Demand is rapidly expanding with the development of the semiconductor industry, such as next-generation clean energy vehicles such as electric vehicles (EVs) and plug-in hybrid vehicles (PHEVs), and modern information as a source of rechargeable energy Has become an integral part of the
携帯情報端末や電気自動車などにおいては、複数の二次電池を直列接続または並列接続して保護回路を設け、電池パック（組電池ともよぶ）として使用される。電池パックとは、二次電池の取り扱いを容易にするため、複数個の二次電池を、所定の回路と共に容器（金属缶、フィルム外装体）内部に収納したものを指す。電池パックは、動作状態を管理するために、ＥＣＵ（Ｅｌｅｃｔｒｏｎｉｃ　Ｃｏｎｔｒｏｌ　Ｕｎｉｔ）が設けられる。 In portable information terminals, electric vehicles and the like, a plurality of secondary batteries are connected in series or in parallel to form a protective circuit, which is used as a battery pack (also referred to as a battery pack). The battery pack refers to a battery pack in which a plurality of secondary batteries are accommodated together with a predetermined circuit in a container (metal can, film outer package) in order to facilitate handling of the secondary battery. The battery pack is provided with an ECU (Electronic Control Unit) to manage the operation state.
　近年、人工ニューラルネットワーク（以下、ニューラルネットワークと呼ぶ）などの機械学習技術の開発が盛んに行われている。 In recent years, machine learning techniques such as artificial neural networks (hereinafter referred to as neural networks) have been actively developed.
　特許文献１には、二次電池の残存容量の演算に、ニューラルネットワークを用いる一例が示されている。 Patent Document 1 shows an example of using a neural network to calculate the remaining capacity of a secondary battery.
米国特許公開第２００６／０１８１２４５号公報U.S. Patent Publication No. 2006/0181245
二次電池の異常を検知し、例えば二次電池の安全性を低下させる現象が検知、あるいは予見される場合に、二次電池の動作条件を変更することにより、二次電池の安全性を確保する。 Safety of the secondary battery is secured by detecting the abnormality of the secondary battery and changing the operating conditions of the secondary battery, for example, when a phenomenon that reduces the safety of the secondary battery is detected or foreseen. Do.
また、ニューラルネットワークなどの人工知能（ＡＩ：Ａｒｔｉｆｉｃｉａｌ　Ｉｎｔｅｌｌｉｇｅｎｃｅ）を用いることによって二次電池の異常を検知するシステムを携帯情報端末や電気自動車に搭載することも課題の一とする。携帯情報端末や電気自動車などに人工知能を搭載させるためにはシステム全体の小型化、または省電力化させることが好ましい。低コストのＩＣチップで二次電池の異常を検知する二次電池の異常検知システムを携帯情報端末や電気自動車に搭載することも課題の一とする。 Another problem is to install a system for detecting an abnormality in a secondary battery by using artificial intelligence (AI) such as a neural network in a portable information terminal or an electric vehicle. In order to mount artificial intelligence in a portable information terminal, an electric car, etc., it is preferable to miniaturize the entire system or save power. It is also an issue to install a secondary battery abnormality detection system for detecting an abnormality of a secondary battery with a low cost IC chip in a portable information terminal or an electric vehicle.
二次電池の実際の正確な残量は、その二次電池を放電させて検出することで得ることができるが、実際に放電させて残量をゼロにしてしまってはデバイスを使用することができないため、残量と相関をもつパラメータ（電池電圧や積算電流）から残量を推定している。また、二次電池は化学反応を利用しているため、少ないデータに基づいて残量を瞬時に推定すると誤りとなる場合もある。 The actual and accurate remaining amount of the secondary battery can be obtained by discharging and detecting the secondary battery, but it is possible to actually discharge it to make the remaining amount zero and use the device Since it can not be done, the remaining amount is estimated from the parameter (battery voltage or integrated current) having a correlation with the remaining amount. Further, since the secondary battery uses a chemical reaction, it may be erroneous to estimate the remaining amount instantaneously based on a small amount of data.
本発明の一態様は、新規な電池管理回路、蓄電装置、及び電子機器等を提供することを課題の一とする。 An object of one embodiment of the present invention is to provide a novel battery management circuit, a power storage device, an electronic device, and the like.
なお、本発明の一態様の課題は、上記列挙した課題に限定されない。上記列挙した課題は、他の課題の存在を妨げるものではない。なお他の課題は、以下の記載で述べる、本項目で言及していない課題である。本項目で言及していない課題は、当業者であれば明細書又は図面等の記載から導き出せるものであり、これらの記載から適宜抽出することができる。なお、本発明の一態様は、上記列挙した記載、及び／又は他の課題のうち、少なくとも一つの課題を解決するものである。 Note that the problem of one embodiment of the present invention is not limited to the problems listed above. The issues listed above do not disturb the existence of other issues. Still other problems are problems which are not mentioned in this item described in the following description. The problems not mentioned in this item can be derived by the person skilled in the art from the description such as the specification or the drawings, and can be appropriately extracted from these descriptions. Note that one aspect of the present invention is to solve at least one of the above-described descriptions and / or other problems.
二次電池の充電特性を画像用データに変換し、畳み込みニューラルネットワーク（ＣＮＮ：Ｃｏｎｖｏｌｕｔｉｏｎａｌ　Ｎｅｕｒａｌ　Ｎｅｔｗｏｒｋ）モデルを用いて、学習データに基づいて二次電池の正常特性と異常特性を判別する。二次電池の状態を異常と判定した後は、異常特性を示す二次電池に対する警告、または使用停止、または二次電池の交換の提案、または充電条件の変更を行う二次電池の充電制御システムとする。 The charge characteristics of the secondary battery are converted into image data, and a normal characteristic and an abnormal characteristic of the secondary battery are determined based on the learning data using a convolutional neural network (CNN) model. After determining that the state of the secondary battery is abnormal, a warning for the secondary battery exhibiting abnormal characteristics, or a stop of use, or a proposal for replacement of the secondary battery, or a charge control system for the secondary battery that changes the charging condition I assume.
具体的には、まず、ある二次電池の充電特性を取得した後、充電電圧値を縦軸、時間を横軸としたグラフを８ビットのグレー階調の画像用データに変換した後、正規化する。画像用データとは、図２（Ｂ）や図２（Ｄ）に示すような配列データのことである。具体的には、８ビットのグレー階調であり、１画素を８ビットで表し、色情報を含まず明るさのみを含んだデータを指し、濃淡を２５６階調で表す。この画像用データを分類することで二次電池が正常か、異常かを判定する。なお、正規化とは、データなどを一定のルールに基づいて変形し、効率よく扱うために整理し、利用しやすくすることである。 Specifically, first, after obtaining the charge characteristics of a certain secondary battery, the graph with the charge voltage value on the vertical axis and the time on the horizontal axis is converted to 8-bit gray gradation image data, and then normal Turn The image data is array data as shown in FIG. 2 (B) and FIG. 2 (D). Specifically, it is 8-bit gray tone, one pixel is represented by 8 bits, it indicates data including only brightness without color information, and gray scale is represented by 256 tones. It is determined whether the secondary battery is normal or abnormal by classifying the image data. In addition, normalization is transforming data etc. based on a fixed rule, organizing in order to handle it efficiently, and making it easy to use.
そして、正規化後にデータを正常、或いは異常にラベル分けを行う。その後、ＣＮＮ処理、及びプーリング処理により画像の特徴を抽出する。特徴を抽出するためのＣＮＮのフィルタパラメータが「重み」となる。そして全結合ニューラルネットワークを用いることにより、二次電池が正常か、異常かを判定する。このように、画像用データは演算のために用いており、画像用データは表示されない。画像用データを用いるため、ＣＮＮを用いて判定することができる。また、学習させることで検出精度を上げることができ、正常な二次電池か、異常な二次電池かを判定することができる。 Then, after normalization, the data is labeled as normal or abnormal. Thereafter, the features of the image are extracted by CNN processing and pooling processing. The filter parameters of the CNN for extracting features are "weights". Then, it is determined whether the secondary battery is normal or abnormal by using a fully coupled neural network. Thus, the image data is used for calculation, and the image data is not displayed. Since image data is used, determination can be made using CNN. In addition, by making the learning possible, the detection accuracy can be improved, and it can be determined whether the secondary battery is a normal secondary battery or an abnormal secondary battery.
充電特性を取得するためには、回路などの負荷に対してある条件で充電動作を行い、データを取得すればよい。取得する際に用いる電力は、監視対象の二次電池からではなく、他の二次電池、或いは、外部電源から供給することが好ましい。また、演算処理なども外部電源から電力を供給して行うことが好ましい。 In order to acquire the charge characteristic, the charge operation may be performed on a load such as a circuit under certain conditions to acquire data. It is preferable that the power used for acquisition be supplied not from the secondary battery to be monitored, but from another secondary battery or an external power source. In addition, it is preferable that the arithmetic processing and the like be performed by supplying power from an external power supply.
なお、外部電源とは、交流電源や、直流電源であり、電気自動車に搭載されるバッテリー、または住宅に設置される定置型バッテリーといった電源を指している。 The external power source refers to a power source such as an AC power source or a DC power source, such as a battery mounted on an electric vehicle or a stationary battery installed in a house.
本明細書で開示する二次電池の充電制御システムは、二次電池と、二次電池の電圧値を測定する測定手段と、測定された二次電池の電圧値を画像用データに変換する手段と、画像用データを分類する判定手段と、を有する。 The charge control system for a secondary battery disclosed herein comprises: a secondary battery; measurement means for measuring the voltage value of the secondary battery; and means for converting the measured voltage value of the secondary battery into image data And determination means for classifying the image data.
上記構成において、判定手段は、積和演算であり、判定手段は、半導体層として酸化物半導体材料を用いるトランジスタを含む。メモリに酸化物半導体材料、代表的にはＩｎ、Ｇａ、Ｚｎを含む酸化物半導体をチャネルに有するトランジスタを用いる場合には、比較的少ない電力でデータを記憶できるため、省電力とすることができる。ソフトウェアのオペレーティングシステムには、Ｗｉｎｄｏｗｓ（登録商標）、ＵＮＩＸ（登録商標）、ｍａｃＯＳ（登録商標）等の各種オペレーティングシステムを用いることができる。ソフトウェアのプログラムは、Ｐｙｔｈｏｎ、Ｇｏ、Ｐｅｒｌ、Ｒｕｂｙ、Ｐｒｅｌｏｇ、Ｖｉｓｕａｌ　Ｂａｓｉｃ、Ｃ、Ｃ＋＋、Ｓｗｉｆｔ、Ｊａｖａ（登録商標）、．ＮＥＴなどの各種プログラミング言語で記述できる。また、アプリケーションをＣｈａｉｎｅｒ（Ｐｙｔｈｏｎで利用できる）、Ｃａｆｆｅ（ＰｙｔｈｏｎおよびＣ＋＋で利用できる）、ＴｅｎｓｏｒＦｌｏｗ（Ｃ、Ｃ＋＋、およびＰｙｔｈｏｎで利用できる）等のフレームワークを使用して作成してもよい。ＣＮＮモデルでは大量の畳み込み（Ｃｏｎｖｏｌｕｔｉｏｎ）処理が必要になる。畳み込み処理は積和演算を使用するため、省電力な積和演算回路を構成できるＬＳＩチップ、特に酸化物半導体材料を用いるトランジスタを用いたＩＣチップを用いることができる。また、ＡＩ（Ａｒｔｉｆｉｃｉａｌ　Ｉｎｔｅｌｌｉｇｅｎｃｅ）システムを組み込んだＩＣ（推論チップとも呼ぶ）を用いてもよい。ＡＩシステムを組み込んだＩＣは、ニューラルネット演算を行う回路（マイクロコンピュータ）と呼ぶ場合もある。 In the above configuration, the determination means is a product-sum operation, and the determination means includes a transistor using an oxide semiconductor material as the semiconductor layer. In the case where a transistor including an oxide semiconductor material, typically, an oxide semiconductor containing In, Ga, and Zn in a channel for the memory can store data with relatively little power, power can be saved. . As operating systems for software, various operating systems such as Windows (registered trademark), UNIX (registered trademark), and macOS (registered trademark) can be used. Software programs include Python, Go, Perl, Ruby, Prelog, Visual Basic, C, C ++, Swift, Java (registered trademark),. It can be written in various programming languages such as NET. Applications may also be created using frameworks such as Chainer (available in Python), Caffe (available in Python and C ++), TensorFlow (available in C, C ++, and Python). The CNN model requires a large amount of convolution processing. Since convolution processing uses product-sum operation, an LSI chip capable of forming a power-saving product-sum operation circuit, in particular, an IC chip using a transistor using an oxide semiconductor material can be used. Alternatively, an IC (also referred to as an inference chip) incorporating an artificial intelligence (AI) system may be used. An IC incorporating an AI system may be called a circuit (microcomputer) that performs neural network operations.
また、アルゴリズムの作成は、ＣＮＮに限定されず、ＳＶＲ、ＲＶＭ（Ｒｅｌｅｖａｎｃｅ　Ｖｅｃｔｏｒ　Ｍａｃｈｉｎｅ）、ランダムフォレストなどを用いてもよい。また、回路構成が大きくなるが、ＣＮＮとＬＳＴＭ（Ｌｏｎｇ　Ｓｈｏｒｔ‐Ｔｅｒｍ　Ｍｅｍｏｒｙ）とを適宜組み合わせて構成してもよい。 Moreover, creation of an algorithm is not limited to CNN, You may use SVR, RVM (Relevance Vector Machine), a random forest etc. Although the circuit configuration is increased, CNN and Long Short-Term Memory (LSTM) may be combined as appropriate.
また、二次電池の異常検出方法も本明細書で開示する。本明細書で開示する二次電池の異常検出方法では、二次電池の電圧値を第１の期間において測定し、測定された二次電池の電圧値を第１の画像用データに変換し、第１の画像用データを分類し、第１の期間の後の第２の期間において二次電池の電圧値を測定し、測定された二次電池の電圧値を第２の画像用データに変換し、第２の画像用データを分類し、第１及び第２の画像用データの分類の結果から正常、或いは異常の判定を行う。 Further, a method of detecting an abnormality of the secondary battery is also disclosed herein. In the abnormality detection method for a secondary battery disclosed herein, the voltage value of the secondary battery is measured in a first period, and the measured voltage value of the secondary battery is converted into first image data, The first image data is classified, the voltage value of the secondary battery is measured in a second period after the first period, and the measured voltage value of the secondary battery is converted into second image data. Then, the second image data is classified, and from the classification results of the first and second image data, determination of normality or abnormality is performed.
上記構成において、第２の期間の長さは、第１の期間以下であることを特徴としている。充電開始から第１の期間の間は特徴抽出するための情報量がある程度必要であるため、第１の期間を長くとることが好ましい。第１の期間の長さに関しては、二次電池の学習データのうち、異常データを基に決定することが好ましい。第２の期間の長さは、第１の期間以下とすることでリアルタイム性を持たせることができる。 In the above configuration, the length of the second period is equal to or less than the first period. Since a certain amount of information for feature extraction is required during the first period from the start of charging, it is preferable to make the first period longer. The length of the first period is preferably determined based on the abnormal data among the learning data of the secondary battery. By setting the length of the second period to be equal to or less than the first period, it is possible to give real time characteristics.
また、定電流充電において変化の少ない充電期間の中間付近は、消費電力の削減のため、判定処理期間を長くしてもよい。二次電池の電圧値の測定は等間隔で行い、ＡＩシステムによる異常検出検査の測定回数は、二次電池の電圧値の測定回数よりも少なくしてもよい。 Further, the determination processing period may be extended in the vicinity of the middle of the charging period where the change is small in constant current charging, in order to reduce the power consumption. The measurement of the voltage value of the secondary battery may be performed at regular intervals, and the number of measurements of the abnormality detection test by the AI system may be smaller than the number of measurements of the voltage value of the secondary battery.
上記構成において、二次電池の１回の充電期間は、定電流充電を行った後、定電圧充電に切り替え、第１の期間と、第２の期間とを含むことを特徴としている。定電流充電の区間に第１の期間と第２の期間を両方設定してもよい。１回の充電中に異常検出の回数を増やし、ＡＩシステムによる異常検出検査の間隔を細分化することで、異常を検出すれば、即座に充電停止や警告を行うことができ、安全な二次電池の充電制御システムを提供することができる。 In the above configuration, one charging period of the secondary battery is characterized by switching to constant voltage charging after performing constant current charging, and including a first period and a second period. Both the first period and the second period may be set in the constant current charging period. By increasing the number of anomaly detections during one charge and subdividing the intervals of anomaly detection inspections by the AI system, if an anomaly is detected, charging can be stopped or warned immediately, and a safe secondary A battery charge control system can be provided.
従来では充電中に正常、或いは異常の判定を行う二次電池の異常検出が困難であったが、本明細書で開示する二次電池の異常検出方法により、充電中であっても正確に判定することができる。 Conventionally, it has been difficult to detect abnormalities in secondary batteries that perform normal or abnormal determination during charging, but it is accurately determined even during charging according to the secondary battery abnormality detection method disclosed herein. can do.
具体的には、まず、対象としている二次電池の充電特性の一部、即ち充電開始してから第１期間まで取得した後、第１期間における充電電圧値を縦軸、時間を横軸としたグラフを８ビット階調の画像用データに変換した後、正規化する。この画像用データを分類することで二次電池が正常か、異常かを判定する。次に、充電の進行中において、同様に、第１期間から第２期間まで二次電池の充電特性の一部を取得した後、充電開始してから第２期間までのデータを画像用データに変換し、正規化し、ＣＮＮ処理、及びプーリング処理を行い、全結合ニューラルネットワークにより、二次電池が正常か、異常かを判定する。 Specifically, first, a part of the charge characteristics of the secondary battery in question, ie, after acquiring from the charge start until the first period, the charge voltage value in the first period is the vertical axis, and the time is the horizontal axis The converted graph is converted into 8-bit gradation image data and then normalized. It is determined whether the secondary battery is normal or abnormal by classifying the image data. Next, while charging is in progress, similarly, after acquiring part of the charging characteristics of the secondary battery from the first period to the second period, data from the charging start to the second period are used as image data Convert, normalize, perform CNN processing, and pooling processing, and determine whether the secondary battery is normal or abnormal by the fully coupled neural network.
このように、配列データである画像用データは演算のために用いており、画像用データは表示されない。配列データである画像用データを用いるため、ＣＮＮを用いて判定することができる。また、ファインチューニングや、異常の細分化を学習させることで検出精度を上げることができ、正常な二次電池か、異常な二次電池かを判定することができる。 As described above, the image data, which is array data, is used for calculation, and the image data is not displayed. Since image data that is array data is used, determination can be made using CNN. Further, the detection accuracy can be improved by learning fine tuning or subdivision of an abnormality, and it can be determined whether it is a normal secondary battery or an abnormal secondary battery.
また、有機溶媒などの液体を用いるリチウムイオン二次電池に限定されず、正常な二次電池のデータと、異常な二次電池のデータを複数用意できるのであれば、液体を用いない二次電池、例えば、固体電解質を用いる固体電池や、燃料電池にも適用することができ、異常検出を行うことができる。固体電解質としては、リチウムイオンを伝導でき、固体成分を含む電解質であればよく、特に限定されない。例えば、セラミックス、高分子電解質などが挙げられる。高分子電解質は、電解液を含む高分子ゲル電解質と、電解液を含まない高分子固体電解質に大きく分けることができる。 Moreover, if it is not limited to the lithium ion secondary battery using liquids, such as an organic solvent, but the data of a normal secondary battery and the data of an abnormal secondary battery can be prepared two or more, the secondary battery which does not use a liquid For example, the present invention can also be applied to a solid battery using a solid electrolyte and a fuel cell, and abnormality detection can be performed. The solid electrolyte is not particularly limited as long as it can conduct lithium ions and contains a solid component. For example, ceramics, polymer electrolytes and the like can be mentioned. The polymer electrolyte can be roughly divided into a polymer gel electrolyte containing an electrolyte solution and a polymer solid electrolyte not containing an electrolyte solution.
二次電池の変化を正確に把握することができ、二次電池の劣化度の管理に反映させることができる。 The change of the secondary battery can be accurately grasped, and can be reflected in the management of the degree of deterioration of the secondary battery.
また、ＡＩシステムを組み込んだＩＣ（推論チップ）を用いることで、二次電池の異常検出精度を落とすことなく、システム全体の小型化と低コスト化を図ることができる。 In addition, by using an IC (inference chip) incorporating the AI system, the size and cost of the entire system can be reduced without degrading the accuracy of detecting an abnormality of the secondary battery.
本発明により、従来では正確に検出することが困難であった二次電池のマイクロショートを検出することができる。また、充電中に二次電池の変化を正確に把握し、異常検出の回数を増やすことで、即座に充電停止を実行することができ、安全な二次電池の充電方法を提供することができる。 According to the present invention, it is possible to detect a micro short circuit of a secondary battery which has conventionally been difficult to detect accurately. In addition, by accurately grasping the change of the secondary battery during charging and increasing the number of times of abnormality detection, it is possible to immediately execute the charging stop, and it is possible to provide a safe charging method of the secondary battery. .
本発明の一態様を示すフローチャートの一例である。7 is an example of a flowchart illustrating an embodiment of the present invention. 本発明の一態様を示す充電特性の例と画像データの例である。They are an example of the charge characteristic which shows one mode of the present invention, and an example of image data. 学習時のフローチャートである。It is a flowchart at the time of learning. ニューラルネットワークの構成を示す図。The figure which shows the structure of a neural network. 本発明の一態様を示すフローチャートの一例である。7 is an example of a flowchart illustrating an embodiment of the present invention. 本発明の一態様を示すフローチャートの一例である。7 is an example of a flowchart illustrating an embodiment of the present invention. 本発明の一態様に係る記憶装置の構成例を示すブロック図。FIG. 18 is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. 本発明の一態様に係る記憶装置の構成例を示す回路図。FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. 本発明の一態様に係る記憶装置の構成例を示す回路図。FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. 本発明の一態様に係る記憶装置の構成例を示すブロック図。FIG. 18 is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. 本発明の一態様に係る記憶装置の構成例を示すブロック図、および回路図。7A and 7B are a block diagram and a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. 本発明の一態様に係るＡＩシステムの構成例を示すブロック図。BRIEF DESCRIPTION OF THE DRAWINGS The block diagram which shows the structural example of AI system which concerns on 1 aspect of this invention. 本発明の一態様に係るＡＩシステムを組み込んだＩＣの構成例を示す斜視模式図。The perspective view showing the example of composition of IC which incorporated the AI system concerning one mode of the present invention. 本発明の一態様を示すフローチャートの一例である。7 is an example of a flowchart illustrating an embodiment of the present invention. 本発明の一態様を示す画像用データを時系列で示した図である。FIG. 7 is a diagram showing, in chronological order, image data showing one embodiment of the present invention. 本発明の一態様を示す画像用データである。5 is image data representing one embodiment of the present invention. 本実施例のニューラルネットワークを示す図である。It is a figure which shows the neural network of a present Example. 電子機器の例を説明する図。FIG. 6 illustrates an example of an electronic device. 電子機器の例を説明する図。FIG. 6 illustrates an example of an electronic device. 円筒型二次電池を説明する図。The figure explaining a cylindrical type rechargeable battery. 電子機器の例を説明する図。FIG. 6 illustrates an example of an electronic device.
以下では、本発明の実施の形態について図面を用いて詳細に説明する。ただし、本発明は以下の説明に限定されず、その形態および詳細を様々に変更し得ることは、当業者であれば容易に理解される。また、本発明は以下に示す実施の形態の記載内容に限定して解釈されるものではない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, it is easily understood by those skilled in the art that the present invention is not limited to the following description, and various changes in the form and details thereof can be made. Further, the present invention should not be construed as being limited to the description of the embodiments below.
（実施の形態１）
本実施の形態では、ニューラルネットワークを二次電池の異常発生（具体的にはマイクロショート発生）の検出に用いる例について説明する。 Embodiment 1
In this embodiment, an example will be described in which a neural network is used to detect the occurrence of an abnormality (specifically, the occurrence of a microshort) of a secondary battery.
マイクロショートとは、二次電池の内部の微小な短絡のことを指しており、二次電池の正極と負極が短絡して充放電不可能の状態になるというほどではなく、微小な短絡部でわずかに短絡電流が１０ナノ秒以上１マイクロ秒未満の期間流れてしまう現象を指している。マイクロショートの原因は、充放電が複数回行われることによって、正極活物質の不均一な分布により、正極の一部と負極の一部で局所的な電流の集中が生じ、セパレータの一部が機能しなくなる箇所が発生すること、または副反応物が発生することにある。 The term "micro short" refers to a minute short inside the secondary battery, not to the extent that the positive electrode and the negative pole of the secondary battery are shorted to cause a state in which charging and discharging are not possible. This refers to a phenomenon in which a short circuit current flows for a period of 10 nanoseconds or more and less than 1 microsecond. The cause of the micro short is that the charge and discharge are performed multiple times, and the uneven distribution of the positive electrode active material causes local concentration of current at a part of the positive electrode and a part of the negative electrode, and a part of the separator The occurrence of a nonfunctional part or the generation of a side reaction product.
二次電池の小型化のため、セパレータの薄化が望まれており、さらに、高い電圧での急速給電による充電が望まれており、どちらも二次電池にマイクロショートが生じやすい構成となっている。また、マイクロショートが繰り返し発生することで二次電池の異常発熱、及び発火などの重大事故に繋がる可能性がある。 In order to miniaturize the secondary battery, thinning of the separator is desired, and further, charging by rapid power feeding at a high voltage is desired, and both are configured to easily cause micro short circuit in the secondary battery. There is. In addition, repeated occurrence of micro shorts may lead to abnormal heat generation of the secondary battery and serious accidents such as ignition.
従って、マイクロショートが発生した場合に早期に検出し、未然に重大事故を防ぐための充電制御システム、または二次電池の制御システムを構成する上で、まず、ニューラルネットワークを用いて二次電池の異常発生の検出を試みる。 Therefore, when configuring a charge control system or a secondary battery control system to detect a microshort at an early stage and prevent a serious accident, the neural network is first used to form the secondary battery. Try to detect an abnormality occurrence.
二次電池が正常か、異常かの判定を行う手順の一例を図１のフロー図を用いて説明する。 An example of the procedure for determining whether the secondary battery is normal or abnormal will be described using the flow chart of FIG.
まず、判定を行おうとしている二次電池の状態を解析し、データを作成する。具体的には二次電池の残量情報を取得する（ステップＳ１）。二次電池の容量は例えば、二次電池の電流と時間の積で求められる。クーロンカウンタＣＣを用いて二次電池の容量を求めてもよい。パラメータとして、二次電池のＳＯＣ（ｓｔａｔｅ　ｏｆ　ｃｈａｒｇｅ、残存容量率）を用いてもよい。あるいは二次電池のＳＯＣを、二次電池の電圧から推測して求めてもよい。満充電状態は、ＳＯＣ１００％であるともいうことができる。満充電状態とは、充電終止電圧の範囲となるまで充電した状態を意味する。充電状態は、二次電池の容量に対して充電している充電量を比率で表したＳＯＣによって示される。なお、ＳＯＣは二次電池の最大容量に対する残存容量の割合で定義する。 First, the state of the secondary battery to be judged is analyzed to create data. Specifically, the remaining amount information of the secondary battery is acquired (step S1). The capacity of the secondary battery can be determined, for example, by the product of the current and time of the secondary battery. The coulomb counter CC may be used to determine the capacity of the secondary battery. As a parameter, the SOC (state of charge) of the secondary battery may be used. Alternatively, the SOC of the secondary battery may be determined by estimation from the voltage of the secondary battery. The fully charged state can also be said to be SOC 100%. The fully charged state means a state in which the battery is charged to the range of the charge termination voltage. The state of charge is indicated by an SOC that represents the amount of charge being charged relative to the capacity of the secondary battery. The SOC is defined as the ratio of the remaining capacity to the maximum capacity of the secondary battery.
ＳＯＣが５０％未満であれば、次のステップである充電開始（ステップＳ２）に進む。ＳＯＣが５０％以上であれば、放電回路により二次電池を放電させて、ＳＯＣを５０％未満、好ましくはＳＯＣを２０％以下とする。 If the SOC is less than 50%, the process proceeds to the next step, charging start (step S2). If the SOC is 50% or more, the secondary battery is discharged by the discharge circuit to make the SOC less than 50%, preferably 20% or less.
異常検出のために充電を開始しはじめ、満充電となるまで、二次電池の充電特性に関するデータを測定し、測定データのメモリ部への蓄積を行う（ステップＳ３）。ここでは、二次電池の電圧が２．５Ｖから充電開始し、約４Ｖとなった段階で満充電とみなしている。なお、充電データの蓄積によって得られるグラフを画像化したものが充電カーブであり、その充電カーブの一例が、図２（Ａ）或いは図２（Ｃ）である。図２（Ａ）及び図２（Ｃ）は、横軸を時間（Ｔｉｍｅ）、縦軸を電圧（Ｖｏｌｔａｇｅ）として、充電カーブを示している。また、ログデータを取ることで、充電開始から満充電の間に充電を中断しても記録または履歴を残すことができるため、再度充電を開始しても充電特性に関するデータを測定することができる。 Data on charge characteristics of the secondary battery is measured until charging is started to detect an abnormality and the battery is fully charged, and the measured data is stored in the memory unit (step S3). Here, when the voltage of the secondary battery starts charging from 2.5 V and reaches about 4 V, it is considered to be fully charged. Note that the charge curve is obtained by imaging a graph obtained by accumulating the charge data, and an example of the charge curve is FIG. 2 (A) or FIG. 2 (C). FIG. 2A and FIG. 2C show charge curves with the horizontal axis representing time and the vertical axis representing voltage. Also, by taking log data, it is possible to leave a record or history even if charging is interrupted between charging start and full charging, so that data on charging characteristics can be measured even if charging is started again. .
次いで、得られた充電カーブを画像用データに変換し、複数の入力データとする（ステップＳ４）。正常な充電カーブが得られた場合、図２（Ａ）に示す充電カーブとなり、それを画像用データに変換し、可視化したものが図２（Ｂ）である。また、充電後半でマイクロショートが発生した充電カーブが得られた場合、例えば、図２（Ｃ）に示す充電カーブとなり、画像用データに変換し、可視化したのが図２（Ｄ）である。図２（Ｂ）及び図２（Ｄ）は、充電カーブを、０から２５５までの８ビット階調の画像用データに変換している。具体的には、放電状態（低電圧）を黒とし、満充電状態を白としている。また、図２（Ｂ）及び図２（Ｄ）の左が充電開始を示し、右が充電完了を示している。 Next, the obtained charge curve is converted into image data to obtain a plurality of input data (step S4). When a normal charge curve is obtained, the charge curve shown in FIG. 2A is obtained, which is converted into image data and visualized as shown in FIG. 2B. Further, when a charge curve in which a micro short occurs is obtained in the second half of the charge, for example, the charge curve shown in FIG. 2C is obtained, and is converted into image data and visualized in FIG. In FIG. 2B and FIG. 2D, the charge curve is converted into image data of 8-bit gradation from 0 to 255. Specifically, the discharged state (low voltage) is black and the fully charged state is white. Moreover, the left of FIG. 2 (B) and FIG. 2 (D) has shown charge start, and the right has shown charge completion.
次いで、入力データを判定する（ステップ５）。この判定（または分類）において、ニューラルネットワークの処理を行い、積和演算を用いる。入力データの特徴を学習時に作成した重みパラメータを使って正常か、異常か、に分類する。 Next, the input data is determined (step 5). In this determination (or classification), processing of a neural network is performed and product-sum operation is used. The features of the input data are classified as normal or abnormal using the weight parameters created at the time of training.
重みパラメータ（フィルタとも呼べる）に関しては、予め正解ラベル付きの画像用データを入力データに用いて特徴を抽出し、特徴を抽出するための重みパラメータを配列に保存し、ミニバッチサイズごとに重みを更新して学習させる。ミニバッチサイズとは、ミニバッチのデータサンプル数である。学習シーケンス、即ち学習時の流れに関しては図３に図示している。学習の更新には誤差逆伝搬を用いる。具体的には、画像の特徴を抽出し、正常か、異常かを判断し、判断した結果と正解ラベルを比較し、間違いの割合を計算する。誤差が小さくなるように重みの値を更新する。なお、誤差は繰り返し学習することで少しずつ小さくなり、最小だった時の重みを推論に利用している。 With regard to weight parameters (also referred to as filters), feature data are extracted in advance using data for images with correct labels as input data, weight parameters for feature extraction are stored in an array, and weights are set for each minibatch size. Update to learn. The mini-batch size is the number of data samples of the mini-batch. The learning sequence, that is, the flow at the time of learning is illustrated in FIG. Error back propagation is used to update learning. Specifically, the feature of the image is extracted, it is judged whether it is normal or abnormal, the judgment result is compared with the correct answer label, and the rate of error is calculated. Update the weight values to reduce the error. The error is gradually reduced by repetitive learning, and the weight at the minimum is used for inference.
また、図２（Ｃ）及び図２（Ｄ）は、マイクロショートが発生し、二次電池の異常と分類され、異常とみなすことができるデータに相当する一例である。図２（Ｃ）及び図２（Ｄ）に示す結果が得られた場合には、その二次電池は使用停止または交換することが好ましい。 Further, FIG. 2C and FIG. 2D are examples of data corresponding to data that can be regarded as an abnormality, which is classified as an abnormality of the secondary battery due to the occurrence of a microshort. When the results shown in FIGS. 2C and 2D are obtained, it is preferable to discontinue or replace the secondary battery.
また、これら一連の手順の開始タイミングは使用者が決定してもよいし、自動で定期的に行ってもよい。 In addition, the start timing of the series of procedures may be determined by the user or may be automatically performed periodically.
また、本実施の形態では、データを画像用データに変換、値を正規化してＣＮＮに入力させる例を示したが、特に限定されず、プログラムによってデータ変換すればよい。本実施の形態では、わかりやすくするために図２（Ｂ）や図２（Ｄ）に示したように画像用データを可視化（表示装置に表示した場合の映像表示）させている。 Further, in the present embodiment, an example is shown in which data is converted into image data, and the value is normalized to be input to the CNN. However, the present invention is not particularly limited, and data conversion may be performed by a program. In the present embodiment, in order to make it easy to understand, as shown in FIG. 2 (B) and FIG. 2 (D), image data is visualized (image display when displayed on a display device).
また、システムを簡素化する場合には、得られた二次電池の充電特性データの特徴を抽出し、その特徴に基づき分類できる処理が行えればよく、推論チップを用いる場合には、システム構成を簡素化できる。システムを簡素化すると、演算に用いる電力を削減でき、システム全体として省電力化が図れる。 In addition, in order to simplify the system, it is sufficient to extract features of the obtained charging characteristic data of the secondary battery and perform processing that can be classified based on the features. In the case of using an inference chip, the system configuration Can be simplified. If the system is simplified, the power used for computation can be reduced, and power saving can be achieved for the entire system.
（実施の形態２）
　本実施の形態では、実施の形態１において図１に示したステップＳ５、即ち二次電池の状態を分類する時のニューラルネットワーク処理に用いるニューラルネットワークＮＮの構成の一例を示す。 Second Embodiment
In the present embodiment, an example of the configuration of the neural network NN used in the neural network processing at step S5 shown in FIG. 1 in Embodiment 1, that is, when classifying the state of the secondary battery is shown.
　図４には、本発明の一態様のニューラルネットワークの一例を示す。図４に示すニューラルネットワークは、入力層ＩＬ、出力層ＯＬ、及び隠れ層（中間層）ＨＬを有する。ニューラルネットワークは、隠れ層ＨＬを複数有するニューラルネットワーク、すなわち、ディープニューラルネットワークによって構成することができる。なお、ディープニューラルネットワークにおける学習を、ディープラーニングと呼ぶことがある。出力層ＯＬ、入力層ＩＬ、隠れ層ＨＬはそれぞれ複数のニューロン回路を有し、異なる層に設けられたニューロン回路同士は、シナプス回路を介して接続されている。 FIG. 4 shows an example of a neural network of one embodiment of the present invention. The neural network shown in FIG. 4 has an input layer IL, an output layer OL, and a hidden layer (intermediate layer) HL. The neural network can be configured by a neural network having a plurality of hidden layers HL, that is, a deep neural network. Learning in a deep neural network may be called deep learning. The output layer OL, the input layer IL, and the hidden layer HL each have a plurality of neuron circuits, and neuron circuits provided in different layers are connected via a synapse circuit.
　ニューラルネットワークには、ある時点での二次電池の状態を解析する機能が、学習によって付加されている。そして、測定された二次電池のパラメータがニューラルネットワークに入力されると、各層において演算処理が行われる。各層における演算処理は、前層が有するニューロン回路の出力と重み係数との積和演算などにより実行される。なお、層と層との結合は、全てのニューロン回路同士が結合する全結合としてもよいし、一部のニューロン回路同士が結合する部分結合としてもよい。 The function to analyze the state of the secondary battery at a certain point is added to the neural network by learning. Then, when the measured secondary battery parameters are input to the neural network, calculation processing is performed in each layer. Arithmetic processing in each layer is performed by a product-sum operation of the output of the neuron circuit of the front layer and the weighting factor. The layer-to-layer connection may be a full connection in which all neuron circuits are connected to each other, or a partial connection in which some neuron circuits are connected to each other.
　例えば、隣接層間において、特定のユニットのみが結合を持ち、畳み込み層とプーリング層を有する、畳み込みニューラルネットワーク（ＣＮＮ）を用いてもよい。ＣＮＮは例えば、充電特性のデータから変換された画像用データの分類に用いられる。畳み込み層では、例えば、画像用データと重みパラメータとを用いた演算が行われる。プーリング層は畳み込み層の直後に配置することが好ましい。 For example, a convolutional neural network (CNN) may be used, in which only certain units are coupled between adjacent layers and have convolutional and pooling layers. The CNN is used, for example, for classification of image data converted from data of charging characteristics. In the convolutional layer, for example, an operation using image data and weight parameters is performed. The pooling layer is preferably placed immediately after the convolutional layer.
　畳み込み層は、画像用データに対して畳み込みを行う機能を有する。畳み込みは、画像用データの一部と重みパラメータのフィルタ値とを用いた演算を繰り返すことにより行われる。畳み込み層における畳み込みにより、画像用データの特徴が抽出される。 The convolution layer has a function of performing convolution on image data. The convolution is performed by repeating an operation using a part of the image data and the filter value of the weight parameter. By convolution in the convolution layer, features of the image data are extracted.
　畳み込みには、重みパラメータ（重みフィルタとも呼ぶ）を用いることができる。畳み込み層に入力された画像用データには、重みパラメータを用いたフィルタ処理が施される。 A weight parameter (also called a weight filter) can be used for the convolution. The image data input to the convolutional layer is subjected to filter processing using weight parameters.
　畳み込みが施されたデータは、活性化関数によって変換された後、プーリング層に出力される。活性化関数としては、ＲｅＬＵ（Ｒｅｃｔｉｆｉｅｄ　Ｌｉｎｅａｒ　Ｕｎｉｔ）等を用いることができる。ＲｅＬＵは、入力値が負である場合は“０”を出力し、入力値が“０”以上である場合は入力値をそのまま出力する正規化線形関数である。また、活性化関数として、シグモイド関数、ｔａｎｈ関数等を用いることもできる。 The data subjected to convolution is converted by the activation function and then output to the pooling layer. As the activation function, ReLU (Rectified Linear Unit) or the like can be used. ReLU is a normalized linear function that outputs "0" when the input value is negative and outputs the input value as it is when the input value is "0" or more. Also, a sigmoid function, a tanh function or the like can be used as the activation function.
　プーリング層は、畳み込み層から入力された画像用データに対してプーリングを行う機能を有する。プーリングは、画像用データを複数の領域に分割し、当該領域ごとに所定のデータを抽出してマトリクス状に配置する処理である。プーリングにより、畳み込み層によって抽出された特徴を残しつつ、画像用データが縮小される。なお、プーリングとしては、最大プーリング、平均プーリング、Ｌｐプーリング等を用いることができる。 The pooling layer has a function of performing pooling on image data input from the convolution layer. Pooling is a process of dividing image data into a plurality of regions, extracting predetermined data for each of the regions, and arranging the data in a matrix. Pooling reduces the image data while leaving the features extracted by the convolutional layer. As pooling, maximum pooling, average pooling, Lp pooling and the like can be used.
　畳み込みニューラルネットワーク（ＣＮＮ）は、上記の畳み込み処理およびプーリング処理により特徴を抽出する。なお、ＣＮＮは、複数の畳み込み層およびプーリング層によって構成することができる。 A convolutional neural network (CNN) extracts features by the above convolution and pooling processes. Note that CNN can be configured by multiple convolutional layers and pooling layers.
　畳み込み層とプーリング層を例えば交互に数層ずつ配置された後には、全結合層が配置されることが好ましい。全結合層は複数層、配置されてもよい。全結合層は、畳み込みおよびプーリングが行われた画像用データを用いて、二次電池が正常か異常かの判定を行う機能を有することが好ましい。 After several layers of convolutional layers and pooling layers, for example, are alternately arranged, it is preferable that the entire bonding layer be arranged. The entire bonding layer may be arranged in multiple layers. Preferably, the entire combined layer has a function of determining whether the secondary battery is normal or abnormal using image data subjected to convolution and pooling.
また、本実施の形態は、実施の形態１と自由に組み合わせることができる。 In addition, this embodiment mode can be freely combined with Embodiment Mode 1.
（実施の形態３）
本実施の形態では、実施の形態１とは一部異なる例を図５に示す。異常判定出力が複数用意されている点以外は、図１と同一であるため、詳細な説明は省略する。 Third Embodiment
In the present embodiment, an example which is partially different from the first embodiment is shown in FIG. This is the same as FIG. 1 except that a plurality of abnormality determination outputs are prepared, so the detailed description will be omitted.
実施の形態１では、正常か、異常かの２種類を分類する例を示している。一方、本実施の形態では、マイクロショートの発生の傾向が複数ある場合に、細かく分類することで、異常検出の精度を上げることができる。図５では３種類のマイクロショート発生のデータを学習時に記憶させ、それらのデータを用い、正常か、異常かが分類される。 The first embodiment shows an example of classifying two types, normal and abnormal. On the other hand, in the present embodiment, when there is a plurality of tendency of occurrence of micro short circuit, the accuracy of abnormality detection can be raised by finely classifying. In FIG. 5, data of the occurrence of three types of micro shorts are stored at the time of learning, and using these data, it is classified as normal or abnormal.
また、本実施の形態は、実施の形態１と自由に組み合わせることができる。 In addition, this embodiment mode can be freely combined with Embodiment Mode 1.
（実施の形態４）
本実施の形態では、実施の形態１とは一部異なる例を図６に示す。ステップＳ３において、測定した充電データの数値などをメモリ部に記憶させる点以外は、図１と同一であるため、詳細な説明は省略する。 Embodiment 4
In the present embodiment, an example which is partially different from the first embodiment is shown in FIG. The process is the same as that of FIG. 1 except that the value of the measured charge data and the like are stored in the memory unit in step S3, and thus the detailed description will be omitted.
メモリ部に酸化物半導体を用いたトランジスタを用いることで省電力化を図ることができる。ニューラルネットワークにおける積和演算などを行う場合、メモリ部にデータを保持した状態で多くの演算処理がおこなわれるため、当該構成は有用である。 Power saving can be achieved by using a transistor including an oxide semiconductor for the memory portion. When performing a product-sum operation or the like in a neural network, the configuration is useful because many arithmetic processes are performed with data held in the memory unit.
酸化物半導体を用いたトランジスタ（以下、ＯＳトランジスタと呼ぶ。）を用いた記憶装置の一例を図７乃至図９を用いて説明する。記憶装置の一例として、ＮＯＳＲＡＭについて説明する。ＮＯＳＲＡＭ（登録商標）とは「Ｎｏｎｖｏｌａｔｉｌｅ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　ＲＡＭ」の略称であり、ゲインセル型（２Ｔ型、３Ｔ型）のメモリセルを有するＲＡＭを指す。なお、以下において、ＮＯＳＲＡＭのようにＯＳトランジスタを用いたメモリ装置を、ＯＳメモリと呼ぶ場合がある。 An example of a memory device using a transistor including an oxide semiconductor (hereinafter referred to as an OS transistor) is described with reference to FIGS. A NOSRAM will be described as an example of a storage device. NOSRAM (registered trademark) is an abbreviation of "nonvolatile oxide semiconductor RAM" and refers to a RAM having memory cells of gain cell type (2T type, 3T type). In the following, a memory device using an OS transistor such as a NOSRAM may be referred to as an OS memory.
　ＮＯＳＲＡＭでは、メモリセルにＯＳトランジスタが用いられるメモリ装置が適用されている。ＯＳメモリは、少なくとも容量素子と、容量素子の充放電を制御するＯＳトランジスタを有するメモリである。ＯＳトランジスタが極小オフ電流のトランジスタであるので、ＯＳメモリは優れた保持特性をもち、不揮発性メモリとして機能させることができる。 In the NOSRAM, a memory device in which an OS transistor is used for a memory cell is applied. The OS memory is a memory that has at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with extremely small off current, the OS memory has excellent retention characteristics and can function as a non-volatile memory.
＜＜ＮＯＳＲＡＭ＞＞
　図７にＮＯＳＲＡＭの構成例を示す。図７に示すＮＯＳＲＡＭ１６００は、メモリセルアレイ１６１０、コントローラ１６４０、行ドライバ１６５０、列ドライバ１６６０、出力ドライバ１６７０を有する。なお、ＮＯＳＲＡＭ１６００は、１のメモリセルで多値データを記憶する多値ＮＯＳＲＡＭである。 << NOSRAM >>
FIG. 7 shows an example of the configuration of the NOSRAM. The NOSRAM 1600 shown in FIG. 7 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670. The NOSRAM 1600 is a multivalued NOSRAM that stores multivalued data in one memory cell.
　メモリセルアレイ１６１０は複数のメモリセル１６１１、複数のワード線ＷＷＬ、ＲＷＬ、ビット線ＢＬ、ソース線ＳＬを有する。ワード線ＷＷＬは書き込みワード線であり、ワード線ＲＷＬは読み出しワード線である。ＮＯＳＲＡＭ１６００では、１のメモリセル１６１１で３ビット（８値）のデータを記憶する。 The memory cell array 1610 has a plurality of memory cells 1611, a plurality of word lines WWL and RWL, a bit line BL, and a source line SL. The word line WWL is a write word line, and the word line RWL is a read word line. In the NOSRAM 1600, 3-bit (eight-valued) data is stored in one memory cell 1611.
　コントローラ１６４０は、ＮＯＳＲＡＭ１６００全体を統括的に制御し、データＷＤＡ［３１：０］の書き込み、データＲＤＡ［３１：０］の読み出しを行う。コントローラ１６４０は、外部からのコマンド信号（例えば、チップイネーブル信号、書き込みイネーブル信号など）を処理して、行ドライバ１６５０、列ドライバ１６６０および出力ドライバ１６７０の制御信号を生成する。 The controller 1640 controls the entire NOSRAM 1600 in a centralized manner, writes the data WDA [31: 0], and reads the data RDA [31: 0]. The controller 1640 processes external command signals (for example, a chip enable signal, a write enable signal, etc.) to generate control signals for the row driver 1650, the column driver 1660 and the output driver 1670.
　行ドライバ１６５０は、アクセスする行を選択する機能を有する。行ドライバ１６５０は、行デコーダ１６５１、およびワード線ドライバ１６５２を有する。 The row driver 1650 has a function of selecting a row to access. The row driver 1650 includes a row decoder 1651 and a word line driver 1652.
　列ドライバ１６６０は、ソース線ＳＬおよびビット線ＢＬを駆動する。列ドライバ１６６０は、列デコーダ１６６１、書き込みドライバ１６６２、ＤＡＣ（デジタル‐アナログ変換回路）１６６３を有する。 Column driver 1660 drives source line SL and bit line BL. The column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-to-analog conversion circuit) 1663.
　ＤＡＣ１６６３は３ビットのデジタルデータをアナログ電圧に変換する。ＤＡＣ１６６３は３２ビットのデータＷＤＡ［３１：０］を３ビットごとに、アナログ電圧に変換する。 The DAC 1663 converts 3-bit digital data into an analog voltage. The DAC 1663 converts 32-bit data WDA [31: 0] into analog voltages every three bits.
　書き込みドライバ１６６２は、ソース線ＳＬをプリチャージする機能、ソース線ＳＬを電気的に浮遊状態にする機能、ソース線ＳＬを選択する機能、選択されたソース線ＳＬにＤＡＣ１６６３で生成した書き込み電圧を入力する機能、ビット線ＢＬをプリチャージする機能、ビット線ＢＬを電気的に浮遊状態にする機能等を有する。 The write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and an input of the write voltage generated by the DAC 1663 to the selected source line SL. Have a function of precharging the bit line BL, a function of electrically floating the bit line BL, and the like.
　出力ドライバ１６７０は、セレクタ１６７１、ＡＤＣ（アナログ‐デジタル変換回路）１６７２、出力バッファ１６７３を有する。セレクタ１６７１は、アクセスするソース線ＳＬを選択し、選択されたソース線ＳＬの電圧をＡＤＣ１６７２に送信する。ＡＤＣ１６７２は、アナログ電圧を３ビットのデジタルデータに変換する機能を持つ。ソース線ＳＬの電圧はＡＤＣ１６７２において、３ビットのデータに変換され、出力バッファ１６７３はＡＤＣ１６７２から出力されるデータを保持する。 The output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673. The selector 1671 selects the source line SL to be accessed, and transmits the voltage of the selected source line SL to the ADC 1672. The ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds the data output from the ADC 1672.
　なお、本実施の形態に示す、行ドライバ１６５０、列ドライバ１６６０、および出力ドライバ１６７０の構成は、上記に限定されるものではない。メモリセルアレイ１６１０の構成または駆動方法などに応じて、これらのドライバおよび当該ドライバに接続される配線の配置を変更してもよいし、これらのドライバおよび当該ドライバに接続される配線の有する機能を変更または追加してもよい。例えば、上記のソース線ＳＬが有する機能の一部を、ビット線ＢＬに有せしめる構成にしてもよい。 The configurations of the row driver 1650, the column driver 1660, and the output driver 1670 described in this embodiment are not limited to the above. Arrangements of these drivers and wirings connected to the drivers may be changed according to the configuration or driving method of the memory cell array 1610 or the like, or functions of the drivers and wirings connected to the drivers are changed Or you may add. For example, part of the functions of the source line SL may be provided to the bit line BL.
　なお、上記においては、各メモリセル１６１１に保持させる情報量を３ビットとしたが、本実施の形態に示す記憶装置の構成はこれに限られない。各メモリセル１６１１に保持させる情報量を２ビット以下にしてもよいし、４ビット以上にしてもよい。例えば、各メモリセル１６１１に保持させる情報量を１ビットにする場合、ＤＡＣ１６６３およびＡＤＣ１６７２を設けない構成にしてもよい。 Although the amount of information held in each memory cell 1611 is 3 bits in the above description, the configuration of the storage device described in this embodiment is not limited to this. The amount of information held by each memory cell 1611 may be 2 bits or less, or 4 bits or more. For example, when the amount of information held in each memory cell 1611 is 1 bit, the DAC 1663 and the ADC 1672 may not be provided.
＜メモリセル＞
　図８（Ａ）はメモリセル１６１１の構成例を示す回路図である。メモリセル１６１１は２Ｔ型のゲインセルであり、メモリセル１６１１はワード線ＷＷＬ、ＲＷＬ、ビット線ＢＬ、ソース線ＳＬ、配線ＢＧＬに電気的に接続されている。メモリセル１６１１は、ノードＳＮ、ＯＳトランジスタＭＯ６１、トランジスタＭＰ６１、容量素子Ｃ６１を有する。ＯＳトランジスタＭＯ６１は書き込みトランジスタである。トランジスタＭＰ６１は読み出しトランジスタであり、例えばｐチャネル型Ｓｉトランジスタで構成される。容量素子Ｃ６１はノードＳＮの電圧を保持するための保持容量である。ノードＳＮはデータの保持ノードであり、ここではトランジスタＭＰ６１のゲートに相当する。 <Memory cell>
FIG. 8A is a circuit diagram showing a configuration example of the memory cell 1611. The memory cell 1611 is a 2T-type gain cell, and the memory cell 1611 is electrically connected to the word lines WWL and RWL, the bit line BL, the source line SL, and the wiring BGL. The memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitive element C61. The OS transistor MO61 is a write transistor. The transistor MP61 is a read transistor, and is formed of, for example, a p-channel Si transistor. The capacitive element C61 is a holding capacitance for holding the voltage of the node SN. The node SN is a data holding node and corresponds to the gate of the transistor MP61 here.
　メモリセル１６１１の書き込みトランジスタがＯＳトランジスタＭＯ６１で構成されているため、ＮＯＳＲＡＭ１６００は長時間データを保持することが可能である。 Since the write transistor of the memory cell 1611 is configured by the OS transistor MO61, the NOSRAM 1600 can hold data for a long time.
　図８（Ａ）の例では、ビット線は、書き込みと読み出しで共通のビット線であるが、図８（Ｂ）に示すように、書き込みビット線として機能する、ビット線ＷＢＬと、読み出しビット線として機能する、ビット線ＲＢＬとを設けてもよい。 In the example of FIG. 8A, the bit line is a common bit line for writing and reading, but as shown in FIG. 8B, the bit line WBL functioning as a writing bit line and the reading bit line And the bit line RBL may be provided.
　図８（Ｃ）−図８（Ｅ）にメモリセルの他の構成例を示す。図８（Ｃ）−図８（Ｅ）には、書き込み用のビット線ＷＢＬと読み出し用のビット線ＲＢＬを設けた例を示しているが、図８（Ａ）のように書き込みと読み出しで共有されるビット線を設けてもよい。 FIGS. 8C to 8E show other configuration examples of the memory cell. FIGS. 8C to 8E show an example in which the write bit line WBL and the read bit line RBL are provided, but as shown in FIG. 8A, they are shared by writing and reading. Bit lines may be provided.
　図８（Ｃ）に示すメモリセル１６１２は、メモリセル１６１１の変形例であり、読み出しトランジスタをｎチャネル型トランジスタ（ＭＮ６１）に変更したものである。トランジスタＭＮ６１はＯＳトランジスタであってもよいし、Ｓｉトランジスタであってもよい。 A memory cell 1612 shown in FIG. 8C is a modified example of the memory cell 1611, in which the read transistor is changed to an n-channel transistor (MN 61). The transistor MN61 may be an OS transistor or a Si transistor.
　メモリセル１６１１、１６１２において、ＯＳトランジスタＭＯ６１はバックゲートの無いＯＳトランジスタであってもよい。 In the memory cells 1611 and 1612, the OS transistor MO61 may be an OS transistor without a back gate.
　図８（Ｄ）に示すメモリセル１６１３は、３Ｔ型ゲインセルであり、ワード線ＷＷＬ、ＲＷＬ、ビット線ＷＢＬ、ＲＢＬ、ソース線ＳＬ、配線ＢＧＬ、ＰＣＬに電気的に接続されている。メモリセル１６１３は、ノードＳＮ、ＯＳトランジスタＭＯ６２、トランジスタＭＰ６２、トランジスタＭＰ６３、容量素子Ｃ６２を有する。ＯＳトランジスタＭＯ６２は書き込みトランジスタである。トランジスタＭＰ６２は読み出しトランジスタであり、トランジスタＭＰ６３は選択トランジスタである。 The memory cell 1613 illustrated in FIG. 8D is a 3T-type gain cell, and is electrically connected to the word lines WWL and RWL, the bit lines WBL and RBL, the source line SL, and the wirings BGL and PCL. The memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62. The OS transistor MO62 is a write transistor. The transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.
　図８（Ｅ）に示すメモリセル１６１４は、メモリセル１６１３の変形例であり、読み出しトランジスタおよび選択トランジスタをｎチャネル型トランジスタ（ＭＮ６２、ＭＮ６３）に変更したものである。トランジスタＭＮ６２、ＭＮ６３はＯＳトランジスタであってもよいし、Ｓｉトランジスタであってもよい。 A memory cell 1614 shown in FIG. 8E is a modification of the memory cell 1613, in which the read transistor and the select transistor are changed to n-channel transistors (MN62 and MN63). The transistors MN62 and MN63 may be OS transistors or Si transistors.
　メモリセル１６１１−１６１４に設けられるＯＳトランジスタは、バックゲートの無いトランジスタでもよいし、バックゲートが有るトランジスタであってもよい。 The OS transistors provided in the memory cells 1611-1614 may be transistors without back gates or may be transistors with back gates.
　上記においては、メモリセル１６１１などが並列に接続された、いわゆるＮＯＲ型の記憶装置について説明したが、以下に示すようなメモリセル１６１５が直列に接続された、いわゆるＮＡＮＤ型の記憶装置にしてもよい。 In the above, the so-called NOR type memory device in which the memory cells 1611 and the like are connected in parallel has been described, but a so-called NAND type memory device in which memory cells 1615 as shown below are connected in series Good.
　図９はＮＡＮＤ型のメモリセルアレイ１６１０の構成例を示す回路図である。図９に示すメモリセルアレイ１６１０は、ソース線ＳＬ、ビット線ＲＢＬ、ビット線ＷＢＬ、ワード線ＷＷＬ、ワード線ＲＷＬ、配線ＢＧＬ、およびメモリセル１６１５を有する。メモリセル１６１５は、ノードＳＮ、ＯＳトランジスタＭＯ６３、トランジスタＭＮ６４、容量素子Ｃ６３を有する。ここで、トランジスタＭＮ６４は、例えばｎチャネル型Ｓｉトランジスタで構成される。これに限られず、トランジスタＭＮ６４は、ｐチャネル型Ｓｉトランジスタ、であってもよいし、ＯＳトランジスタであってもよい。 FIG. 9 is a circuit diagram showing a configuration example of a NAND type memory cell array 1610. As shown in FIG. The memory cell array 1610 illustrated in FIG. 9 includes a source line SL, a bit line RBL, a bit line WBL, a word line WWL, a word line RWL, a wiring BGL, and a memory cell 1615. The memory cell 1615 includes a node SN, an OS transistor MO63, a transistor MN64, and a capacitive element C63. Here, the transistor MN64 is formed of, for example, an n-channel Si transistor. The transistor MN 64 may be a p-channel Si transistor or an OS transistor.
　以下では、図９に示すメモリセル１６１５ａおよびメモリセル１６１５ｂを例として説明する。ここで、メモリセル１６１５ａまたはメモリセル１６１５ｂのいずれかに接続する配線、または回路素子の符号については、ａまたはｂの符号を付して表す。 Hereinafter, the memory cell 1615 a and the memory cell 1615 b illustrated in FIG. 9 will be described as an example. Here, reference numerals of a wiring or a circuit element connected to either the memory cell 1615 a or the memory cell 1615 b are denoted by a or b.
　メモリセル１６１５ａにおいて、トランジスタＭＮ６４ａのゲートと、ＯＳトランジスタＭＯ６３ａのソースおよびドレインの一方と、容量素子Ｃ６３ａの電極の一方とは、電気的に接続されている。また、ビット線ＷＢＬとＯＳトランジスタＭＯ６３ａのソースおよびドレインの他方とは、電気的に接続されている。また、ワード線ＷＷＬａと、ＯＳトランジスタＭＯ６３ａのゲートとは、電気的に接続されている。また、配線ＢＧＬａと、ＯＳトランジスタＭＯ６３ａのバックゲートとは、電気的に接続されている。そして、ワード線ＲＷＬａと、容量素子Ｃ６３ａの電極の他方は電気的に接続されている。 In the memory cell 1615a, the gate of the transistor MN64a, one of the source and the drain of the OS transistor MO63a, and one of the electrodes of the capacitive element C63a are electrically connected. Further, the bit line WBL and the other of the source and the drain of the OS transistor MO63a are electrically connected. In addition, the word line WWLa and the gate of the OS transistor MO63a are electrically connected. Further, the wiring BGLa and the back gate of the OS transistor MO63a are electrically connected. The word line RWLa and the other of the electrodes of the capacitive element C 63 a are electrically connected.
　メモリセル１６１５ｂは、ビット線ＷＢＬとのコンタクト部を対称の軸として、メモリセル１６１５ａと対称的に設けることができる。よって、メモリセル１６１５ｂに含まれる回路素子も、上記メモリセル１６１５ａと同じように配線と接続される。 The memory cell 1615 b can be provided symmetrically with the memory cell 1615 a with the contact portion with the bit line WBL as an axis of symmetry. Accordingly, the circuit element included in the memory cell 1615 b is also connected to the wiring in the same manner as the memory cell 1615 a.
　さらに、メモリセル１６１５ａが有するトランジスタＭＮ６４ａのソースは、メモリセル１６１５ｂのトランジスタＭＮ６４ｂのドレインと電気的に接続される。メモリセル１６１５ａが有するトランジスタＭＮ６４ａのドレインは、ビット線ＲＢＬと電気的に接続される。メモリセル１６１５ｂが有するトランジスタＭＮ６４ｂのソースは、複数のメモリセル１６１５が有するトランジスタＭＮ６４を介してソース線ＳＬと電気的に接続される。このように、ＮＡＮＤ型のメモリセルアレイ１６１０では、ビット線ＲＢＬとソース線ＳＬの間に、複数のトランジスタＭＮ６４が直列に接続される。 Further, the source of the transistor MN64a included in the memory cell 1615a is electrically connected to the drain of the transistor MN64b in the memory cell 1615b. The drain of the transistor MN64a included in the memory cell 1615a is electrically connected to the bit line RBL. The source of the transistor MN64b included in the memory cell 1615b is electrically connected to the source line SL through the transistor MN64 included in the plurality of memory cells 1615. As described above, in the NAND-type memory cell array 1610, the plurality of transistors MN64 are connected in series between the bit line RBL and the source line SL.
　図９に示すメモリセルアレイ１６１０を有する記憶装置では、同じワード線ＷＷＬ（またはワード線ＲＷＬ）に接続された複数のメモリセル（以下、メモリセル列と呼ぶ。）ごとに、書き込み動作および読み出し動作を行う。例えば、書き込み動作は次のように行うことができる。書き込みを行うメモリセル列に接続されたワード線ＷＷＬにＯＳトランジスタＭＯ６３がオン状態となる電位を与え、書き込みを行うメモリセル列のＯＳトランジスタＭＯ６３をオン状態にする。これにより、指定したメモリセル列のトランジスタＭＮ６４のゲートおよび容量素子Ｃ６３の電極の一方にビット線ＷＢＬの電位が与えられ、該ゲートに所定の電荷が与えられる。それから当該メモリセル列のＯＳトランジスタＭＯ６３をオフ状態にすると、該ゲートに与えられた所定の電荷を保持することができる。このようにして、指定したメモリセル列のメモリセル１６１５にデータを書き込むことができる。 In the memory device having the memory cell array 1610 shown in FIG. 9, write operation and read operation are performed for each of a plurality of memory cells (hereinafter referred to as a memory cell column) connected to the same word line WWL (or word line RWL). Do. For example, the write operation can be performed as follows. A potential at which the OS transistor MO63 is turned on is applied to the word line WWL connected to the memory cell column to be written, and the OS transistor MO63 of the memory cell column to be written is turned on. Thereby, the potential of the bit line WBL is applied to one of the gate of the transistor MN64 of the designated memory cell column and the electrode of the capacitive element C63, and a predetermined charge is applied to the gate. Then, when the OS transistor MO63 of the memory cell column is turned off, the predetermined charge given to the gate can be held. Thus, data can be written to the memory cell 1615 of the specified memory cell column.
　また、例えば、読み出し動作は次のように行うことができる。まず、読み出しを行うメモリセル列に接続されていないワード線ＲＷＬに、トランジスタＭＮ６４のゲートに与えられた電荷によらず、トランジスタＭＮ６４がオン状態となるような電位を与え、読み出しを行うメモリセル列以外のトランジスタＭＮ６４をオン状態とする。それから、読み出しを行うメモリセル列に接続されたワード線ＲＷＬに、トランジスタＭＮ６４のゲートが有する電荷によって、トランジスタＭＮ６４のオン状態またはオフ状態が選択されるような電位（読み出し電位）を与える。そして、ソース線ＳＬに定電位を与え、ビット線ＲＢＬに接続されている読み出し回路を動作状態とする。ここで、ソース線ＳＬ−ビット線ＲＢＬ間の複数のトランジスタＭＮ６４は、読み出しを行うメモリセル列を除いてオン状態となっているため、ソース線ＳＬ−ビット線ＲＢＬ間のコンダクタンスは、読み出しを行うメモリセル列のトランジスタＭＮ６４の状態（オン状態またはオフ状態）によって決定される。読み出しを行うメモリセル列のトランジスタＭＮ６４のゲートが有する電荷によって、トランジスタのコンダクタンスは異なるから、それに応じて、ビット線ＲＢＬの電位は異なる値をとることになる。ビット線ＲＢＬの電位を読み出し回路によって読み出すことで、指定したメモリセル列のメモリセル１６１５から情報を読み出すことができる。 Also, for example, the read operation can be performed as follows. First, to a word line RWL not connected to a memory cell column to be read, a potential that turns on the transistor MN64 regardless of the charge applied to the gate of the transistor MN64 is applied to read a memory cell column The other transistors MN64 are turned on. Then, a potential (read potential) is applied to the word line RWL connected to the memory cell column to be read by the charge of the gate of the transistor MN64 so that the on state or the off state of the transistor MN64 is selected. Then, a constant potential is applied to the source line SL, and the reading circuit connected to the bit line RBL is brought into an operating state. Here, since the plurality of transistors MN64 between the source line SL and the bit line RBL are in the on state except for the memory cell column to be read, the conductance between the source line SL and the bit line RBL is for reading It is determined by the state (on state or off state) of the transistor MN64 of the memory cell column. The conductance of the transistor differs depending on the charge of the gate of the transistor MN64 in the memory cell column to be read, and accordingly, the potential of the bit line RBL takes a different value. Information can be read out from the memory cell 1615 of the specified memory cell column by reading out the potential of the bit line RBL by the reading circuit.
　容量素子Ｃ６１、容量素子Ｃ６２、または容量素子Ｃ６３の充放電によってデータを書き換えるため、ＮＯＳＲＡＭ１６００は原理的には書き換え回数に制約はなく、かつ、低エネルギーで、データの書き込みおよび読み出しが可能である。また、長時間データを保持することが可能であるので、リフレッシュ頻度を低減できる。 Since data is rewritten by charging / discharging of the capacitive element C61, the capacitive element C62, or the capacitive element C63, the number of times of rewriting is in principle not limited, and data can be written and read with low energy. In addition, since it is possible to hold data for a long time, the refresh frequency can be reduced.
　上記実施の形態に示す半導体装置をメモリセル１６１１、１６１２、１６１３、１６１４、１６１５に用いる場合、ＯＳトランジスタＭＯ６１、ＭＯ６２、ＭＯ６３、容量素子Ｃ６１、Ｃ６２、Ｃ６３、トランジスタＭＰ６１、ＭＰ６２、ＭＰ６３、ＭＮ６１、ＭＮ６２、ＭＮ６３、ＭＮ６４を用いることができる。これにより、トランジスタと容量素子一組当たりの上面視における占有面積を低減することができるので、記憶装置をさらに高集積化させることができる。よって、記憶装置の単位面積当たりの記憶容量を増加させることができる。 When the semiconductor device described in the above embodiment is used for the memory cells 1611, 1612, 1613, 1614, and 1615, the OS transistors MO61, MO62, and MO63, capacitive elements C61, C62, and C63, and transistors MP61, MP62, MP63, MN61, and MN62. , MN 63 and MN 64 can be used. Thus, the area occupied by the transistor and the pair of capacitor elements in top view can be reduced, so that the memory device can be further highly integrated. Thus, the storage capacity per unit area of the storage device can be increased.
また、ＯＳトランジスタを用いた記憶装置の一例を図１０および図１１を用いて説明する。記憶装置の一例として、ＤＯＳＲＡＭについて説明する。ＤＯＳＲＡＭ（登録商標）とは、「Ｄｙｎａｍｉｃ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　ＲＡＭ」の略称であり、１Ｔ（トランジスタ）１Ｃ（容量）型のメモリセルを有するＲＡＭを指す。 In addition, an example of a memory device using an OS transistor is described with reference to FIGS. 10 and 11. FIG. A DOS RAM will be described as an example of the storage device. DOSRAM (registered trademark) is an abbreviation of "Dynamic Oxide Semiconductor RAM", and refers to a RAM having memory cells of 1T (transistor) 1C (capacitance) type.
＜＜ＤＯＳＲＡＭ１４００＞＞
　図１０にＤＯＳＲＡＭの構成例を示す。図１０に示すように、ＤＯＳＲＡＭ１４００は、コントローラ１４０５、行回路１４１０、列回路１４１５、メモリセルおよびセンスアンプアレイ１４２０（以下、「ＭＣ−ＳＡアレイ１４２０」とも呼ぶ。）を有する。 << DOSRAM1400 >>
FIG. 10 shows a configuration example of DOSRAM. As shown in FIG. 10, the DOSRAM 1400 has a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell and a sense amplifier array 1420 (hereinafter also referred to as "MC-SA array 1420").
　行回路１４１０はデコーダ１４１１、ワード線ドライバ回路１４１２、列セレクタ１４１３、センスアンプドライバ回路１４１４を有する。列回路１４１５はグローバルセンスアンプアレイ１４１６、入出力回路１４１７を有する。グローバルセンスアンプアレイ１４１６は複数のグローバルセンスアンプ１４４７を有する。ＭＣ−ＳＡアレイ１４２０はメモリセルアレイ１４２２、センスアンプアレイ１４２３、グローバルビット線ＧＢＬＬ、ＧＢＬＲを有する。 The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414. The column circuit 1415 has a global sense amplifier array 1416 and an input / output circuit 1417. The global sense amplifier array 1416 has a plurality of global sense amplifiers 1447. The MC-SA array 1420 has a memory cell array 1422, a sense amplifier array 1423, and global bit lines GBLL and GBLR.
（ＭＣ−ＳＡアレイ１４２０）
　ＭＣ−ＳＡアレイ１４２０は、メモリセルアレイ１４２２をセンスアンプアレイ１４２３上に積層した積層構造をもつ。グローバルビット線ＧＢＬＬ、ＧＢＬＲはメモリセルアレイ１４２２上に積層されている。ＤＯＳＲＡＭ１４００では、ビット線の構造に、ローカルビット線とグローバルビット線とで階層化された階層ビット線構造が採用されている。 (MC-SA array 1420)
The MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423. Global bit lines GBLL and GBLR are stacked on memory cell array 1422. In the DOSRAM 1400, a hierarchical bit line structure hierarchized by local bit lines and global bit lines is adopted as the structure of bit lines.
　メモリセルアレイ１４２２は、Ｎ個（Ｎは２以上の整数）のローカルメモリセルアレイ１４２５＜０＞—１４２５＜Ｎ−１＞を有する。図１１（Ａ）にローカルメモリセルアレイ１４２５の構成例を示す。ローカルメモリセルアレイ１４２５は、複数のメモリセル１４４５、複数のワード線ＷＬ、複数のビット線ＢＬＬ、ＢＬＲを有する。図１１（Ａ）の例では、ローカルメモリセルアレイ１４２５の構造はオープンビット線型であるが、フォールデッドビット線型であってもよい。 Memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 <0> to 1425 <N-1>. A configuration example of the local memory cell array 1425 is shown in FIG. The local memory cell array 1425 has a plurality of memory cells 1445, a plurality of word lines WL, and a plurality of bit lines BLL and BLR. In the example of FIG. 11A, the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.
　図１１（Ｂ）に共通のビット線ＢＬＬ（ＢＬＲ）に接続される、ペア状の一組のメモリセル１４４５ａおよびメモリセル１４４５ｂの回路構成例を示す。メモリセル１４４５ａはトランジスタＭＷ１ａ、容量素子ＣＳ１ａ、端子Ｂ１ａ、Ｂ２ａを有し、ワード線ＷＬａ、ビット線ＢＬＬ（ＢＬＲ）に接続される。また、メモリセル１４４５ｂはトランジスタＭＷ１ｂ、容量素子ＣＳ１ｂ、端子Ｂ１ｂ、Ｂ２ｂを有し、ワード線ＷＬｂ、ビット線ＢＬＬ（ＢＬＲ）に接続される。なお、以下において、メモリセル１４４５ａおよびメモリセル１４４５ｂのいずれかを特に限定しない場合は、メモリセル１４４５およびそれに付属する構成にａまたはｂの符号を付さない場合がある。 FIG. 11B shows a circuit configuration example of a pair of memory cells 1445a and 1445b connected in pair to the common bit line BLL (BLR). The memory cell 1445a includes a transistor MW1a, a capacitive element CS1a, and terminals B1a and B2a, and is connected to the word line WLa and the bit line BLL (BLR). The memory cell 1445 b has a transistor MW 1 b, a capacitive element CS 1 b, terminals B 1 b and B 2 b, and is connected to the word line WLb and the bit line BLL (BLR). Note that, in the following, when one of the memory cell 1445a and the memory cell 1445b is not particularly limited, the memory cell 1445 and the configuration attached to the memory cell 1445 may not be denoted by the symbol a or b.
　トランジスタＭＷ１ａは容量素子ＣＳ１ａの充放電を制御する機能をもち、トランジスタＭＷ１ｂは容量素子ＣＳ１ｂの充放電を制御する機能をもつ。トランジスタＭＷ１ａのゲートはワード線ＷＬａに電気的に接続され、第１端子はビット線ＢＬＬ（ＢＬＲ）に電気的に接続され、第２端子は容量素子ＣＳ１ａの第１端子に電気的に接続されている。また、トランジスタＭＷ１ｂのゲートはワード線ＷＬｂに電気的に接続され、第１端子はビット線ＢＬＬ（ＢＬＲ）に電気的に接続され、第２端子は容量素子ＣＳ１ｂの第１端子に電気的に接続されている。このように、ビット線ＢＬＬ（ＢＬＲ）がトランジスタＭＷ１ａの第１端子とトランジスタＭＷ１ｂの第１端子に共通で用いられる。 The transistor MW1a has a function of controlling charging and discharging of the capacitive element CS1a, and the transistor MW1b has a function of controlling charging and discharging of the capacitive element CS1b. The gate of transistor MW1a is electrically connected to word line WLa, the first terminal is electrically connected to bit line BLL (BLR), and the second terminal is electrically connected to the first terminal of capacitive element CS1a. There is. The gate of transistor MW1b is electrically connected to word line WLb, the first terminal is electrically connected to bit line BLL (BLR), and the second terminal is electrically connected to the first terminal of capacitive element CS1b. It is done. Thus, the bit line BLL (BLR) is commonly used for the first terminal of the transistor MW1a and the first terminal of the transistor MW1b.
　トランジスタＭＷ１は容量素子ＣＳ１の充放電を制御する機能をもつ。容量素子ＣＳ１の第２端子は端子Ｂ２に電気的に接続されている。端子Ｂ２には、定電圧（例えば、低電源電圧）が入力される。 The transistor MW1 has a function of controlling charging and discharging of the capacitive element CS1. The second terminal of the capacitive element CS1 is electrically connected to the terminal B2. A constant voltage (for example, low power supply voltage) is input to the terminal B2.
　上記実施の形態に示す半導体装置をメモリセル１４４５ａ、１４４５ｂに用いる場合、トランジスタＭＷ１ａ、トランジスタＭＷ１ｂ、容量素子ＣＳ１ａ、容量素子ＣＳ１ｂを用いることができる。これにより、トランジスタと容量素子一組当たりの上面視における占有面積を低減することができるので、記憶装置を高集積化させることができる。よって、記憶装置の単位面積当たりの記憶容量を増加させることができる。 In the case where the semiconductor device described in the above embodiment is used for the memory cells 1445a and 1445b, the transistor MW1a, the transistor MW1b, the capacitor CS1a, and the capacitor CS1b can be used. Thus, the area occupied by the transistor and the pair of capacitor elements in top view can be reduced, so that the memory device can be highly integrated. Thus, the storage capacity per unit area of the storage device can be increased.
　トランジスタＭＷ１はバックゲートを備えており、バックゲートは端子Ｂ１に電気的に接続されている。そのため、端子Ｂ１の電圧によって、トランジスタＭＷ１の閾値電圧を変更することができる。例えば、端子Ｂ１の電圧は固定電圧（例えば、負の定電圧）であってもよいし、ＤＯＳＲＡＭ１４００の動作に応じて、端子Ｂ１の電圧を変化させてもよい。 The transistor MW1 has a back gate, and the back gate is electrically connected to the terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed by the voltage of the terminal B1. For example, the voltage of the terminal B1 may be a fixed voltage (for example, a negative constant voltage), or the voltage of the terminal B1 may be changed according to the operation of the DOS RAM 1400.
　トランジスタＭＷ１のバックゲートをトランジスタＭＷ１のゲート、ソース、またはドレインに電気的に接続してもよい。あるいは、トランジスタＭＷ１にバックゲートを設けなくてもよい。 The back gate of the transistor MW1 may be electrically connected to the gate, the source, or the drain of the transistor MW1. Alternatively, the transistor MW1 may not be provided with a back gate.
　センスアンプアレイ１４２３は、Ｎ個のローカルセンスアンプアレイ１４２６＜０＞—１４２６＜Ｎ−１＞を有する。ローカルセンスアンプアレイ１４２６は、１のスイッチアレイ１４４４、複数のセンスアンプ１４４６を有する。センスアンプ１４４６には、ビット線対が電気的に接続されている。センスアンプ１４４６は、ビット線対をプリチャージする機能、ビット線対の電圧差を増幅する機能、この電圧差を保持する機能を有する。スイッチアレイ１４４４は、ビット線対を選択し、選択したビット線対とグローバルビット線対との間を導通状態にする機能を有する。 Sense amplifier array 1423 includes N local sense amplifier arrays 1426 <0> to 1426 <N-1>. The local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446. A bit line pair is electrically connected to sense amplifier 1446. The sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying a voltage difference between the bit line pair, and a function of holding the voltage difference. The switch array 1444 has a function of selecting a bit line pair and conducting between the selected bit line pair and the global bit line pair.
　ここで、ビット線対とは、センスアンプによって、同時に比較される２本のビット線のことをいう。グローバルビット線対とは、グローバルセンスアンプによって、同時に比較される２本のグローバルビット線のことをいう。ビット線対を一対のビット線と呼ぶことができ、グローバルビット線対を一対のグローバルビット線と呼ぶことができる。ここでは、ビット線ＢＬＬとビット線ＢＬＲが１組のビット線対を成す。グローバルビット線ＧＢＬＬとグローバルビット線ＧＢＬＲとが１組のクローバルビット線対をなす。以下、ビット線対（ＢＬＬ，ＢＬＲ）、グローバルビット線対（ＧＢＬＬ，ＧＢＬＲ）とも表す。 Here, the bit line pair means two bit lines which are simultaneously compared by the sense amplifier. The global bit line pair refers to two global bit lines which are simultaneously compared by the global sense amplifier. A bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines. Here, the bit line BLL and the bit line BLR form a pair of bit lines. Global bit line GBLL and global bit line GBLR form a pair of global bit lines. Hereinafter, the bit line pair (BLL, BLR) and the global bit line pair (GBLL, GBLR) are also referred to.
（コントローラ１４０５）
　コントローラ１４０５は、ＤＯＳＲＡＭ１４００の動作全般を制御する機能を有する。コントローラ１４０５は、外部からの入力されるコマンド信号を論理演算して、動作モードを決定する機能、決定した動作モードが実行されるように、行回路１４１０、列回路１４１５の制御信号を生成する機能、外部から入力されるアドレス信号を保持する機能、内部アドレス信号を生成する機能を有する。 (Controller 1405)
The controller 1405 has a function of controlling the overall operation of the DOS RAM 1400. The controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and generates a control signal for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. And a function of holding an address signal input from the outside, and a function of generating an internal address signal.
（行回路１４１０）
　行回路１４１０は、ＭＣ−ＳＡアレイ１４２０を駆動する機能を有する。デコーダ１４１１はアドレス信号をデコードする機能を有する。ワード線ドライバ回路１４１２は、アクセス対象行のワード線ＷＬを選択する選択信号を生成する。 (Row circuit 1410)
The row circuit 1410 has a function of driving the MC-SA array 1420. The decoder 1411 has a function of decoding an address signal. The word line driver circuit 1412 generates a selection signal for selecting the word line WL in the access target row.
　列セレクタ１４１３、センスアンプドライバ回路１４１４はセンスアンプアレイ１４２３を駆動するための回路である。列セレクタ１４１３は、アクセス対象列のビット線を選択するための選択信号を生成する機能をもつ。列セレクタ１４１３の選択信号によって、各ローカルセンスアンプアレイ１４２６のスイッチアレイ１４４４が制御される。センスアンプドライバ回路１４１４の制御信号によって、複数のローカルセンスアンプアレイ１４２６は独立して駆動される。 The column selector 1413 and the sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423. The column selector 1413 has a function of generating a selection signal for selecting a bit line of the access target column. The selection signal of column selector 1413 controls switch array 1444 of each local sense amplifier array 1426. The control signals of the sense amplifier driver circuit 1414 drive the plurality of local sense amplifier arrays 1426 independently.
（列回路１４１５）
　列回路１４１５は、データ信号ＷＤＡ［３１：０］の入力を制御する機能、データ信号ＲＤＡ［３１：０］の出力を制御する機能を有する。データ信号ＷＤＡ［３１：０］は書き込みデータ信号であり、データ信号ＲＤＡ［３１：０］は読み出しデータ信号である。 (Column circuit 1415)
Column circuit 1415 has a function of controlling an input of data signal WDA [31: 0] and a function of controlling an output of data signal RDA [31: 0]. The data signal WDA [31: 0] is a write data signal, and the data signal RDA [31: 0] is a read data signal.
　グローバルセンスアンプ１４４７はグローバルビット線対（ＧＢＬＬ，ＧＢＬＲ）に電気的に接続されている。グローバルセンスアンプ１４４７はグローバルビット線対（ＧＢＬＬ，ＧＢＬＲ）間の電圧差を増幅する機能、この電圧差を保持する機能を有する。グローバルビット線対（ＧＢＬＬ，ＧＢＬＲ）へのデータの書き込み、および読み出しは、入出力回路１４１７によって行われる。 Global sense amplifier 1447 is electrically connected to global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying a voltage difference between the global bit line pair (GBLL, GBLR) and a function of holding this voltage difference. Writing and reading of data to the global bit line pair (GBLL, GBLR) are performed by the input / output circuit 1417.
　ＤＯＳＲＡＭ１４００の書き込み動作の概要を説明する。入出力回路１４１７によって、データがグローバルビット線対に書き込まれる。グローバルビット線対のデータは、グローバルセンスアンプアレイ１４１６によって保持される。アドレスが指定するローカルセンスアンプアレイ１４２６のスイッチアレイ１４４４によって、グローバルビット線対のデータが、対象列のビット線対に書き込まれる。ローカルセンスアンプアレイ１４２６は、書き込まれたデータを増幅し、保持する。指定されたローカルメモリセルアレイ１４２５において、行回路１４１０によって、対象行のワード線ＷＬが選択され、選択行のメモリセル１４４５にローカルセンスアンプアレイ１４２６の保持データが書き込まれる。 An outline of the write operation of the DOSRAM 1400 will be described. Data is written to the global bit line pair by input / output circuit 1417. Data of the global bit line pair is held by the global sense amplifier array 1416. The data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 designated by the address. The local sense amplifier array 1426 amplifies and holds the written data. In the designated local memory cell array 1425, the row circuit 1410 selects the word line WL of the target row, and the data held by the local sense amplifier array 1426 is written to the memory cell 1445 of the selected row.
　ＤＯＳＲＡＭ１４００の読み出し動作の概要を説明する。アドレス信号によって、ローカルメモリセルアレイ１４２５の１行が指定される。指定されたローカルメモリセルアレイ１４２５において、対象行のワード線ＷＬが選択状態となり、メモリセル１４４５のデータがビット線に書き込まれる。ローカルセンスアンプアレイ１４２６によって、各列のビット線対の電圧差がデータとして検出され、かつ保持される。スイッチアレイ１４４４によって、ローカルセンスアンプアレイ１４２６の保持データの内、アドレス信号が指定する列のデータが、グローバルビット線対に書き込まれる。クローバルセンスアンプアレイ１４１６は、グローバルビット線対のデータを検出し、保持する。グローバルセンスアンプアレイ１４１６の保持データは入出力回路１４１７に出力される。以上で、読み出し動作が完了する。 An outline of the read operation of the DOSRAM 1400 will be described. One row of the local memory cell array 1425 is designated by the address signal. In the designated local memory cell array 1425, the word line WL in the target row is selected, and the data of the memory cell 1445 is written to the bit line. The local sense amplifier array 1426 detects and holds the voltage difference of the bit line pair of each column as data. Of the data held by local sense amplifier array 1426, data in the column designated by the address signal is written to the global bit line pair by switch array 1444. The global sense amplifier array 1416 detects and holds data of the global bit line pair. The held data of the global sense amplifier array 1416 is output to the input / output circuit 1417. Thus, the read operation is completed.
　容量素子ＣＳ１の充放電によってデータを書き換えるため、ＤＯＳＲＡＭ１４００には原理的には書き換え回数に制約はなく、かつ、低エネルギーで、データの書き込みおよび読み出しが可能である。また、メモリセル１４４５の回路構成が単純であるため、大容量化が容易である。 Since the data is rewritten by the charge and discharge of the capacitive element CS1, the number of times of rewriting is not limited in principle in the DOSRAM 1400, and data can be written and read with low energy. In addition, since the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.
　トランジスタＭＷ１はＯＳトランジスタである。ＯＳトランジスタはオフ電流が極めて小さいため、容量素子ＣＳ１から電荷がリークすることを抑えることができる。したがって、ＤＯＳＲＡＭ１４００の保持時間はＤＲＡＭに比べて非常に長い。したがってリフレッシュの頻度を低減できるため、リフレッシュ動作に要する電力を削減できる。よって、ＤＯＳＲＡＭ１４００は大容量のデータを高頻度で書き換えるメモリ装置、例えば、画像処理に利用されるフレームメモリに好適である。 The transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, charge leakage from the capacitive element CS1 can be suppressed. Therefore, the retention time of the DOS RAM 1400 is very long compared to the DRAM. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites a large amount of data with high frequency, for example, a frame memory used for image processing.
　ＭＣ−ＳＡアレイ１４２０が積層構造であることよって、ローカルセンスアンプアレイ１４２６の長さと同程度の長さにビット線を短くすることができる。ビット線を短くすることで、ビット線容量が小さくなり、メモリセル１４４５の保持容量を低減することができる。また、ローカルセンスアンプアレイ１４２６にスイッチアレイ１４４４を設けることで、長いビット線の本数を減らすことができる。以上の理由から、ＤＯＳＲＡＭ１４００のアクセス時に駆動する負荷が低減され、消費電力を低減することができる。従って、ニューラルネットワーク処理においてもメモリの消費電力を低減できる。 Since MC-SA array 1420 has a stacked structure, bit lines can be shortened to a length approximately equal to the length of local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced and the storage capacitance of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. From the above reasons, the load driven at the time of access to the DOS RAM 1400 is reduced, and power consumption can be reduced. Therefore, memory power consumption can be reduced also in neural network processing.
また、本実施の形態は、実施の形態１と自由に組み合わせることができる。 In addition, this embodiment mode can be freely combined with Embodiment Mode 1.
（実施の形態５）
　本実施の形態では、図１２を用いて、上記実施の形態４に示す半導体装置を適用した、ＡＩシステムについて説明を行う。また、図１３を用いてＡＩシステムが組み込まれたＩＣの一例を示す。 Fifth Embodiment
In this embodiment, an AI system to which the semiconductor device described in the fourth embodiment is applied will be described with reference to FIG. Also, FIG. 13 shows an example of an IC in which an AI system is incorporated.
　図１２はＡＩシステム４０４１の構成例を示すブロック図である。ＡＩシステム４０４１は、演算部４０１０と、制御部４０２０と、入出力部４０３０を有する。 FIG. 12 is a block diagram showing a configuration example of the AI system 4041. As shown in FIG. The AI system 4041 includes an operation unit 4010, a control unit 4020, and an input / output unit 4030.
　演算部４０１０は、アナログ演算回路４０１１と、ＤＯＳＲＡＭ４０１２と、ＮＯＳＲＡＭ４０１３と、ＦＰＧＡ４０１４と、を有する。ＤＯＳＲＡＭ４０１２、ＮＯＳＲＡＭ４０１３、およびＦＰＧＡ４０１４として、上記実施の形態４に示す、ＤＯＳＲＡＭ１４００、およびＮＯＳＲＡＭ１６００を用いることができる。 The operation unit 4010 includes an analog operation circuit 4011, a DOSRAM 4012, a NOSRAM 4013, and an FPGA 4014. The DOSRAM 1400 and the NOSRAM 1600 described in Embodiment 4 can be used as the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014.
　制御部４０２０は、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）４０２１と、ＧＰＵ（Ｇｒａｐｈｉｃｓ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）４０２２と、ＰＬＬ（Ｐｈａｓｅ　Ｌｏｃｋｅｄ　Ｌｏｏｐ）４０２３と、ＳＲＡＭ（Ｓｔａｔｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）４０２４と、ＰＲＯＭ（Ｐｒｏｇｒａｍｍａｂｌｅ　Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）４０２５と、メモリコントローラ４０２６と、電源回路４０２７と、ＰＭＵ（Ｐｏｗｅｒ　Ｍａｎａｇｅｍｅｎｔ　Ｕｎｉｔ）４０２８と、を有する。 The control unit 4020 includes a central processing unit (CPU) 4021, a graphics processing unit (GPU) 4022, a phase locked loop (PLL) 4023, a static random access memory (SRAM) 4024, and a programmable read only memory (PROM) 4025. , A memory controller 4026, a power supply circuit 4027, and a PMU (Power Management Unit) 4028.
　入出力部４０３０は、外部記憶制御回路４０３１と、音声コーデック４０３２と、映像コーデック４０３３と、汎用入出力モジュール４０３４と、通信モジュール４０３５と、を有する。 The input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general purpose input / output module 4034, and a communication module 4035.
　演算部４０１０は、ニューラルネットワークによる学習または推論を実行することができる。 The operation unit 4010 can execute learning or inference by a neural network.
　アナログ演算回路４０１１はＡ／Ｄ（アナログ／デジタル）変換回路、Ｄ／Ａ（デジタル／アナログ）変換回路、および積和演算回路を有する。 The analog operation circuit 4011 includes an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a product-sum operation circuit.
　アナログ演算回路４０１１はＯＳトランジスタを用いて形成することが好ましい。ＯＳトランジスタを用いたアナログ演算回路４０１１は、アナログメモリを有し、学習または推論に必要な積和演算を、低消費電力で実行することが可能になる。 The analog arithmetic circuit 4011 is preferably formed using an OS transistor. The analog operation circuit 4011 using the OS transistor has an analog memory, and can perform the product-sum operation necessary for learning or inference with low power consumption.
　ＤＯＳＲＡＭ４０１２は、ＯＳトランジスタを用いて形成されたＤＲＡＭであり、ＤＯＳＲＡＭ４０１２は、ＣＰＵ４０２１から送られてくるデジタルデータを一時的に格納するメモリである。ＤＯＳＲＡＭ４０１２は、ＯＳトランジスタを含むメモリセルと、Ｓｉトランジスタを含む読み出し回路部を有する。上記メモリセルと読み出し回路部は、積層された異なる層に設けることができるため、ＤＯＳＲＡＭ４０１２は、全体の回路面積を小さくすることができる。 The DOSRAM 4012 is a DRAM formed using an OS transistor, and the DOSRAM 4012 is a memory for temporarily storing digital data sent from the CPU 4021. The DOSRAM 4012 has a memory cell including an OS transistor and a read out circuit unit including an Si transistor. Since the memory cell and the read out circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the entire circuit area.
　ニューラルネットワークを用いた計算は、入力データが１０００を超えることがある。上記入力データをＳＲＡＭに格納する場合、ＳＲＡＭは回路面積に制限があり、記憶容量が小さいため、上記入力データを小分けにして格納せざるを得ない。ＤＯＳＲＡＭ４０１２は、限られた回路面積でも、メモリセルを高集積に配置することが可能であり、ＳＲＡＭに比べて記憶容量が大きい。そのため、ＤＯＳＲＡＭ４０１２は、上記入力データを効率よく格納することができる。 Calculations using neural networks may have more than 1000 input data. When the input data is stored in the SRAM, the SRAM has a limited circuit area and a small storage capacity, so the input data can not but be divided and stored. The DOSRAM 4012 can arrange memory cells in a highly integrated manner even with a limited circuit area, and has a larger storage capacity than an SRAM. Therefore, the DOS RAM 4012 can store the input data efficiently.
　ＮＯＳＲＡＭ４０１３はＯＳトランジスタを用いた不揮発性メモリである。ＮＯＳＲＡＭ４０１３は、フラッシュメモリや、ＲｅＲＡＭ（Ｒｅｓｉｓｔｉｖｅ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、ＭＲＡＭ（Ｍａｇｎｅｔｏｒｅｓｉｓｔｉｖｅ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）などの他の不揮発性メモリと比べて、データを書き込む際の消費電力が小さい。また、フラッシュメモリやＲｅＲＡＭのように、データを書き込む際に素子が劣化することもなく、データの書き込み可能回数に制限が無い。 The NOSRAM 4013 is a non-volatile memory using an OS transistor. The NOSRAM 4013 consumes less power when writing data as compared to other non-volatile memories such as flash memory, ReRAM (Resistive Random Access Memory) and MRAM (Magnetoresistive Random Access Memory). In addition, unlike the flash memory and the ReRAM, there is no deterioration of the element when writing data, and there is no limit to the number of times data can be written.
　また、ＮＯＳＲＡＭ４０１３は、１ビットの２値データの他に、２ビット以上の多値データを記憶することができる。ＮＯＳＲＡＭ４０１３は多値データを記憶することで、１ビット当たりのメモリセル面積を小さくすることができる。 Further, the NOSRAM 4013 can store multi-value data of 2 bits or more in addition to 1-bit binary data. The NOSRAM 4013 can reduce the memory cell area per bit by storing multi-value data.
　また、ＮＯＳＲＡＭ４０１３は、デジタルデータの他にアナログデータを記憶することができる。そのため、アナログ演算回路４０１１は、ＮＯＳＲＡＭ４０１３をアナログメモリとして用いることもできる。ＮＯＳＲＡＭ４０１３は、アナログデータのまま記憶することができるため、Ｄ／Ａ変換回路やＡ／Ｄ変換回路が不要である。そのため、ＮＯＳＲＡＭ４０１３は周辺回路の面積を小さくすることができる。なお、本明細書においてアナログデータとは、３ビット（８値）以上分解能を有するデータのことを指す。上述した多値データがアナログデータに含まれる場合もある。 In addition to digital data, the NOSRAM 4013 can store analog data. Therefore, the analog operation circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, no D / A conversion circuit or A / D conversion circuit is required. Therefore, the NOSRAM 4013 can reduce the area of peripheral circuits. In the present specification, analog data refers to data having a resolution of 3 bits (eight values) or more. The above-mentioned multi-value data may be included in the analog data.
　ニューラルネットワークの計算に用いられるデータやパラメータは、一旦、ＮＯＳＲＡＭ４０１３に格納することができる。上記データやパラメータは、ＣＰＵ４０２１を介して、ＡＩシステム４０４１の外部に設けられたメモリに格納してもよいが、内部に設けられたＮＯＳＲＡＭ４０１３の方が、より高速且つ低消費電力に上記データやパラメータを格納することができる。また、ＮＯＳＲＡＭ４０１３は、ＤＯＳＲＡＭ４０１２よりもビット線を長くすることができるので、記憶容量を大きくすることができる。 Data and parameters used for neural network calculations can be temporarily stored in the NOSRAM 4013. The above data and parameters may be stored in a memory provided outside the AI system 4041 via the CPU 4021. However, the NOSRAM 4013 provided inside has higher speed and lower power consumption than the data and parameters. Can be stored. Further, since the NOSRAM 4013 can make the bit line longer than the DOS RAM 4012, the storage capacity can be increased.
　ＦＰＧＡ４０１４は、ＯＳトランジスタを用いたＦＰＧＡである。ＡＩシステム４０４１は、ＦＰＧＡ４０１４を用いることによって、ハードウェアで後述する、ディープニューラルネットワーク（ＤＮＮ）、畳み込みニューラルネットワーク（ＣＮＮ）、再帰型ニューラルネットワーク（ＲＮＮ）、自己符号化器、深層ボルツマンマシン（ＤＢＭ）、深層信念ネットワーク（ＤＢＮ）などの、ニューラルネットワークの接続を構成することができる。上記のニューラルネットワークの接続をハードウェアで構成することで、より高速に実行することができる。 The FPGA 4014 is an FPGA using an OS transistor. The AI system 4041 uses the FPGA 4014 to perform deep neural networks (DNN), convolutional neural networks (CNN), recursive neural networks (RNN), self-coder, deep Boltzmann machine (DBM), which will be described later in hardware. It is possible to configure connections of neural networks, such as Deep Belief Networks (DBNs). The connection of the above neural network can be implemented at higher speed by configuring it with hardware.
　ＦＰＧＡ４０１４はＯＳトランジスタを有するＦＰＧＡである。ＯＳ‐ＦＰＧＡは、ＳＲＡＭで構成されるＦＰＧＡよりもメモリの面積を小さくすることができる。そのため、コンテキスト切り替え機能を追加しても面積増加が少ない。また、ＯＳ‐ＦＰＧＡはブースティングによりデータやパラメータを高速に伝えることができる。 The FPGA 4014 is an FPGA having an OS transistor. The OS-FPGA can have a smaller memory area than an FPGA configured with SRAM. Therefore, even if the context switching function is added, the area increase is small. The OS-FPGA can also transmit data and parameters at high speed by boosting.
　ＡＩシステム４０４１は、アナログ演算回路４０１１、ＤＯＳＲＡＭ４０１２、ＮＯＳＲＡＭ４０１３、およびＦＰＧＡ４０１４を１つのダイ（チップ）の上に設けることができる。そのため、ＡＩシステム４０４１は、高速且つ低消費電力に、ニューラルネットワークの計算を実行することができる。また、アナログ演算回路４０１１、ＤＯＳＲＡＭ４０１２、ＮＯＳＲＡＭ４０１３、およびＦＰＧＡ４０１４は、同じ製造プロセスで作製することができる。そのため、ＡＩシステム４０４１は、低コストで作製することができる。 The AI system 4041 can provide the analog operation circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 on one die (chip). Therefore, the AI system 4041 can perform neural network calculations at high speed and low power consumption. Further, the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be manufactured by the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.
　なお、演算部４０１０は、ＤＯＳＲＡＭ４０１２、ＮＯＳＲＡＭ４０１３、およびＦＰＧＡ４０１４を、全て有する必要はない。ＡＩシステム４０４１が解決したい課題に応じて、ＤＯＳＲＡＭ４０１２、ＮＯＳＲＡＭ４０１３、およびＦＰＧＡ４０１４の一または複数を、選択して設ければよい。 Note that the arithmetic unit 4010 need not have all the DOS RAM 4012, the NOSRAM 4013, and the FPGA 4014. One or more of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 may be selected and provided in accordance with the problem that the AI system 4041 wants to solve.
　ＡＩシステム４０４１は、解決したい課題に応じて、ディープニューラルネットワーク（ＤＮＮ）、畳み込みニューラルネットワーク（ＣＮＮ）、再帰型ニューラルネットワーク（ＲＮＮ）、自己符号化器、深層ボルツマンマシン（ＤＢＭ）、深層信念ネットワーク（ＤＢＮ）などの手法を実行することができる。ＰＲＯＭ４０２５は、これらの手法の少なくとも１つを実行するためのプログラムを保存することができる。また、当該プログラムの一部または全てを、ＮＯＳＲＡＭ４０１３に保存してもよい。 The AI system 4041 can perform deep neural network (DNN), convolutional neural network (CNN), recursive neural network (RNN), self-coder, deep Boltzmann machine (DBM), deep belief network ( Methods such as DBN) can be implemented. The PROM 4025 can store programs for performing at least one of these techniques. In addition, part or all of the program may be stored in the NOSRAM 4013.
　ライブラリとして存在する既存のプログラムは、ＧＰＵの処理を前提としているものが多い。そのため、ＡＩシステム４０４１はＧＰＵ４０２２を有することが好ましい。ＡＩシステム４０４１は、学習と推論で用いられる積和演算のうち、律速となる積和演算を演算部４０１０で実行し、それ以外の積和演算をＧＰＵ４０２２で実行することができる。そうすることで、学習と推論を高速に実行することができる。 Many existing programs that exist as libraries are based on GPU processing. Therefore, the AI system 4041 preferably includes a GPU 4022. Among the product-sum operations used in learning and inference, the AI system 4041 can execute the product-sum operation that is rate-limiting in the operation unit 4010 and can execute the other product-sum operations in the GPU 4022. By doing so, learning and inference can be performed at high speed.
　電源回路４０２７は、論理回路用の低電源電位を生成するだけではなく、アナログ演算のための電位生成も行う。電源回路４０２７はＯＳメモリを用いてもよい。電源回路４０２７は、基準電位をＯＳメモリに保存することで、消費電力を下げることができる。 The power supply circuit 4027 not only generates a low power supply potential for a logic circuit, but also performs potential generation for analog operation. The power supply circuit 4027 may use an OS memory. The power supply circuit 4027 can reduce power consumption by storing the reference potential in the OS memory.
　ＰＭＵ４０２８は、ＡＩシステム４０４１の電力供給を一時的に停止する機能を有する。 The PMU 4028 has a function of temporarily stopping the power supply of the AI system 4041.
　ＣＰＵ４０２１およびＧＰＵ４０２２は、レジスタとしてＯＳメモリを有することが好ましい。ＣＰＵ４０２１およびＧＰＵ４０２２はＯＳメモリを有することで、電力供給を停止しても、ＯＳメモリ中にデータ（論理値）を保持し続けることができる。その結果、ＡＩシステム４０４１は、電力を節約することができる。 The CPU 4021 and the GPU 4022 preferably have OS memory as a register. By having the OS memory, the CPU 4021 and the GPU 4022 can keep data (logical value) in the OS memory even when the power supply is stopped. As a result, the AI system 4041 can save power.
　ＰＬＬ４０２３は、クロックを生成する機能を有する。ＡＩシステム４０４１は、ＰＬＬ４０２３が生成したクロックを基準に動作を行う。ＰＬＬ４０２３はＯＳメモリを有することが好ましい。ＰＬＬ４０２３はＯＳメモリを有することで、クロックの発振周期を制御するアナログ電位を保持することができる。 The PLL 4023 has a function of generating a clock. The AI system 4041 operates based on the clock generated by the PLL 4023. The PLL 4023 preferably has an OS memory. The PLL 4023 having an OS memory can hold an analog potential for controlling the oscillation cycle of the clock.
　ＡＩシステム４０４１は、ＤＲＡＭなどの外部メモリにデータを保存してもよい。そのため、ＡＩシステム４０４１は、外部のＤＲＡＭとのインターフェースとして機能するメモリコントローラ４０２６を有することが好ましい。また、メモリコントローラ４０２６は、ＣＰＵ４０２１またはＧＰＵ４０２２の近くに配置することが好ましい。そうすることで、データのやり取りを高速に行うことができる。 The AI system 4041 may store data in an external memory such as DRAM. Therefore, the AI system 4041 preferably has a memory controller 4026 that functions as an interface with an external DRAM. In addition, the memory controller 4026 is preferably disposed near the CPU 4021 or the GPU 4022. By doing so, it is possible to exchange data at high speed.
　制御部４０２０に示す回路の一部または全ては、演算部４０１０と同じダイの上に形成することができる。そうすることで、ＡＩシステム４０４１は、高速且つ低消費電力に、ニューラルネットワークの計算を実行することができる。 Part or all of the circuits illustrated in the control unit 4020 can be formed over the same die as the computing unit 4010. By doing so, the AI system 4041 can perform neural network calculations at high speed and low power consumption.
　ニューラルネットワークの計算に用いられるデータは外部記憶装置（ＨＤＤ（Ｈａｒｄ　Ｄｉｓｋ　Ｄｒｉｖｅ）、ＳＳＤ（Ｓｏｌｉｄ　Ｓｔａｔｅ　Ｄｒｉｖｅ）など）に保存される場合が多い。そのため、ＡＩシステム４０４１は、外部記憶装置とのインターフェースとして機能する外部記憶制御回路４０３１を有することが好ましい。 Data used for neural network calculations are often stored in an external storage device (HDD (Hard Disk Drive), SSD (Solid State Drive), etc.). Therefore, the AI system 4041 preferably includes an external storage control circuit 4031 that functions as an interface with an external storage device.
　ニューラルネットワークを用いた学習と推論は、音声や映像を扱うことが多いので、ＡＩシステム４０４１は音声コーデック４０３２および映像コーデック４０３３を有する。音声コーデック４０３２は、音声データのエンコード（符号化）およびデコード（復号）を行い、映像コーデック４０３３は、映像データのエンコードおよびデコードを行う。 Since learning and inference using neural networks often deal with voice and video, the AI system 4041 includes a voice codec 4032 and a video codec 4033. The audio codec 4032 encodes (decodes) and decodes (decodes) audio data, and the video codec 4033 encodes and decodes video data.
　ＡＩシステム４０４１は、外部センサから得られたデータを用いて学習または推論を行うことができる。そのため、ＡＩシステム４０４１は汎用入出力モジュール４０３４を有する。汎用入出力モジュール４０３４は、例えば、ＵＳＢ（Ｕｎｉｖｅｒｓａｌ　Ｓｅｒｉａｌ　Ｂｕｓ）やＩ２Ｃ（Ｉｎｔｅｒ−Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）などを含む。 The AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general purpose input / output module 4034. The general-purpose input / output module 4034 includes, for example, Universal Serial Bus (USB), Inter-Integrated Circuit (I2C), and the like.
　ＡＩシステム４０４１は、インターネットを経由して得られたデータを用いて学習または推論を行うことができる。そのため、ＡＩシステム４０４１は、通信モジュール４０３５を有することが好ましい。 The AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 preferably has a communication module 4035.
　アナログ演算回路４０１１は、多値のフラッシュメモリをアナログメモリとして用いてもよい。しかし、フラッシュメモリは書き換え可能回数に制限がある。また、多値のフラッシュメモリは、エンベディッドで形成する（演算回路とメモリを同じダイの上に形成する）ことが非常に難しい。 The analog operation circuit 4011 may use a multi-level flash memory as an analog memory. However, the flash memory is limited in the number of rewrites. In addition, it is very difficult to form multilevel flash memory by embedding (forming the arithmetic circuit and the memory on the same die).
　また、アナログ演算回路４０１１は、ＲｅＲＡＭをアナログメモリとして用いてもよい。しかし、ＲｅＲＡＭは書き換え可能回数に制限があり、記憶精度の点でも問題がある。さらに、２端子でなる素子であるため、データの書き込みと読み出しを分ける回路設計が複雑になる。 In addition, the analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM is limited in the number of times of rewriting, and there is a problem in storage accuracy. Furthermore, since the element has two terminals, the circuit design that separates writing and reading of data becomes complicated.
　また、アナログ演算回路４０１１は、ＭＲＡＭをアナログメモリとして用いてもよい。しかし、ＭＲＡＭは抵抗変化率が低く、記憶精度の点で問題がある。 The analog operation circuit 4011 may use an MRAM as an analog memory. However, the MRAM has a low rate of change in resistance, and has problems in storage accuracy.
　以上を鑑み、アナログ演算回路４０１１は、ＯＳメモリをアナログメモリとして用いることが好ましい。 In view of the above, it is preferable that the analog arithmetic circuit 4011 use the OS memory as an analog memory.
　上記ＡＩシステムは、ＣＰＵ等のＳｉトランジスタでなるデジタル処理回路と、ＯＳトランジスタを用いたアナログ演算回路、ＯＳ−ＦＰＧＡおよびＤＯＳＲＡＭ、ＮＯＳＲＡＭ等のＯＳメモリを、１のダイに集積することができる。 The AI system can integrate a digital processing circuit made of a Si transistor such as a CPU, an analog operation circuit using an OS transistor, and an OS memory such as an OS-FPGA and DOSRAM or NOSRAM in one die.
　図１３に、ＡＩシステムを組み込んだＩＣの一例を示す。図１３に示すＡＩシステムＩＣ７０００は、リード７００１及び回路部７００３を有する。ＡＩシステムＩＣ７０００は、例えばプリント基板７００２に実装される。このようなＩＣチップが複数組み合わされて、それぞれがプリント基板７００２上で電気的に接続されることで電子部品が実装された基板（実装基板７００４）が完成する。回路部７００３には、上記実施の形態で示した各種の回路が１のダイに設けられている。回路部７００３は、先の実施の形態に示すように、積層構造をもち、Ｓｉトランジスタ層７０３１、配線層７０３２、ＯＳトランジスタ層７０３３に大別される。ＯＳトランジスタ層７０３３をＳｉトランジスタ層７０３１に積層して設けることができるため、ＡＩシステムＩＣ７０００の小型化が容易である。 FIG. 13 shows an example of an IC incorporating an AI system. An AI system IC 7000 shown in FIG. 13 has a lead 7001 and a circuit portion 7003. AI system IC 7000 is mounted on, for example, printed circuit board 7002. A plurality of such IC chips are combined and electrically connected on the printed circuit board 7002 to complete a board (mounting board 7004) on which electronic components are mounted. In the circuit portion 7003, the various circuits described in the above embodiment are provided in one die. As described in the above embodiment, the circuit portion 7003 has a stacked structure and is roughly classified into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked on the Si transistor layer 7031, the AI system IC 7000 can be easily miniaturized.
　図１３では、ＡＩシステムＩＣ７０００のパッケージにＱＦＰ（Ｑｕａｄ　Ｆｌａｔ　Ｐａｃｋａｇｅ）を適用しているが、パッケージの態様はこれに限定されない。 In FIG. 13, although QFP (Quad Flat Package) is applied to the package of AI system IC7000, the aspect of a package is not limited to this.
　ＣＰＵ等のデジタル処理回路と、ＯＳトランジスタを用いたアナログ演算回路、ＯＳ−ＦＰＧＡおよびＤＯＳＲＡＭ、ＮＯＳＲＡＭ等のＯＳメモリは、全て、Ｓｉトランジスタ層７０３１、配線層７０３２およびＯＳトランジスタ層７０３３に形成することができる。すなわち、上記ＡＩシステムを構成する素子は、同一の製造プロセスで形成することが可能である。そのため、本実施の形態に示すＩＣは、構成する素子が増えても製造プロセスを増やす必要がなく、上記ＡＩシステムを低コストで組み込むことができる。 A digital processing circuit such as a CPU, an analog operation circuit using an OS transistor, an OS-FPGA and an OS memory such as DOSRAM or NOSRAM may be formed in the Si transistor layer 7031, the wiring layer 7032 and the OS transistor layer 7033 it can. That is, the elements constituting the above AI system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment does not need to increase the manufacturing process even if the number of elements is increased, and the above-mentioned AI system can be incorporated at low cost.
　本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態６）
本実施の形態では、ニューラルネットワークを二次電池の異常発生（具体的にはマイクロショート発生）の検出に用いる例について説明する。本実施の形態では、デバイス使用中あるいは充電中において、リアルタイムでの異常検出を行うことができる一例を示す。 Sixth Embodiment
In this embodiment, an example will be described in which a neural network is used to detect the occurrence of an abnormality (specifically, the occurrence of a microshort) of a secondary battery. In this embodiment, an example in which abnormality detection can be performed in real time while the device is in use or charging is described.
二次電池が正常か、異常かの判定を行う手順の一例を図１４のフロー図を用いて説明する。 An example of the procedure for determining whether the secondary battery is normal or abnormal will be described using the flowchart of FIG.
まず、判定を行おうとしている二次電池の状態を解析し、データを作成する。具体的には二次電池の残量情報を取得する（ステップＳ１）。二次電池の容量は例えば、二次電池の電流と時間の積で求められる。クーロンカウンタＣＣを用いて二次電池の容量を求めてもよい。パラメータとして、二次電池のＳＯＣ（ｓｔａｔｅ　ｏｆ　ｃｈａｒｇｅ、残存容量率）を用いてもよい。二次電池のＳＯＣは二次電池の電圧から推測して求めてもよい。 First, the state of the secondary battery to be judged is analyzed to create data. Specifically, the remaining amount information of the secondary battery is acquired (step S1). The capacity of the secondary battery can be determined, for example, by the product of the current and time of the secondary battery. The coulomb counter CC may be used to determine the capacity of the secondary battery. As a parameter, the SOC (state of charge) of the secondary battery may be used. The SOC of the secondary battery may be estimated from the voltage of the secondary battery.
ＳＯＣが５０％未満であれば、次のステップである充電開始（ステップＳ２）に進む。ＳＯＣが５０％以上であれば、放電回路により二次電池を放電させて、ＳＯＣを５０％未満、好ましくはＳＯＣを２０％以下とする。 If the SOC is less than 50%, the process proceeds to the next step, charging start (step S2). If the SOC is 50% or more, the secondary battery is discharged by the discharge circuit to make the SOC less than 50%, preferably 20% or less.
ここでは、二次電池の電圧が２．５Ｖから充電開始し、約４Ｖとなった段階で満充電とみなしている。 Here, when the voltage of the secondary battery starts charging from 2.5 V and reaches about 4 V, it is considered to be fully charged.
異常検出のために充電を開始しはじめから時間ｔまで、二次電池の充電特性に関するデータを測定し、測定データのメモリ部への蓄積を行う（ステップＳ３）。なお、充電データの蓄積によって得られるグラフを画像化したものが充電カーブである。 Data on the charge characteristics of the secondary battery is measured from the start of charging for detection of abnormality to time t, and the measured data is stored in the memory unit (step S3). Note that the charging curve is an image obtained by imaging a graph obtained by accumulating the charging data.
次いで、得られた充電カーブを画像用データに変換し、複数の入力データとする（ステップＳ４）。時間ｔ＝２１００秒の場合の画像用データの一例を図１５（Ａ）に示す。図１５（Ａ）は、充電カーブを、０から２５５までの８ビットのグレー階調の画像用データ（２１０×２１０）に変換している。具体的には、放電状態（低電圧）を黒とし、満充電状態を白としている。また、図１５（Ａ）の左が充電開始位置を示している。 Next, the obtained charge curve is converted into image data to obtain a plurality of input data (step S4). An example of the image data in the case of time t = 2100 seconds is shown in FIG. In FIG. 15A, the charge curve is converted into image data (210 × 210) of 8-bit gray gradation from 0 to 255. Specifically, the discharged state (low voltage) is black and the fully charged state is white. Moreover, the left of FIG. 15 (A) has shown the charge start position.
次いで、入力データを判定する（ステップ５）。この判定（または分類）において、ニューラルネットワークの処理を行い、積和演算を用いる。入力データの特徴を学習時に作成した重みパラメータを使って正常か、異常か、に分類する。 Next, the input data is determined (step 5). In this determination (or classification), processing of a neural network is performed and product-sum operation is used. The features of the input data are classified as normal or abnormal using the weight parameters created at the time of training.
異常と判断された場合には、即座に充電を停止してもよいし、次の検出タイミングである時間ｔ＝４２００秒の結果が正常であれば、その他に原因があるとも考えられる。 If it is determined that there is an abnormality, charging may be stopped immediately, and if the result of time t = 4200 seconds which is the next detection timing is normal, it may be considered that there are other causes.
本実施の形態では、図１４に示すように異常判定出力が複数用意されている例を示しており、２種類のマイクロショート発生のデータを学習時に記憶させ、それらのデータを用い、正常か、異常かに分類する。マイクロショートの発生の傾向が複数ある場合に、細かく分類することで、精度を上げることができる。例えば、マイクロショートの発生の傾向として電圧が急激に低下するモードと、ゆっくり低下するモードの２種類に分ける。 In the present embodiment, as shown in FIG. 14, an example is shown in which a plurality of abnormality determination outputs are prepared, two types of micro short occurrence data are stored at the time of learning, and using these data, it is normal, Classified as abnormal. In the case where there is a plurality of micro shorts, the accuracy can be improved by finely classifying. For example, the mode is divided into two types: a mode in which the voltage sharply drops as a tendency of the occurrence of a micro short and a mode in which the voltage falls slowly.
また、正常と判断された場合には、次の検出タイミングである時間ｔ＝４２００秒の時に上記手順を繰り返せばよい。時間ｔ＝４２００秒の場合の画像用データの一例を図１５（Ｂ）に示す。図１５（Ｂ）は充電開始から時間ｔ＝４２００秒までのデータを示す。また、上記作業を繰り返し、時間ｔ＝６３００秒の場合の画像用データの一例を図１５（Ｃ）に示す。本実施の形態では、２１００秒毎に自動で検出を行っている。なお、図１５（Ｄ）は時間ｔ＝２３１００秒の場合の画像用データの一例であり、図１５（Ｅ）は、時間ｔ＝２９４００秒の場合の画像用データの一例であり、図１５（Ｆ）は、時間ｔ＝４４１００秒の場合の画像用データの一例である。また、図１６（Ａ）は満充電時の画像用データの一例であり、右が充電完了を示している。 Further, if it is determined that the operation is normal, the above procedure may be repeated at time t = 4200 seconds which is the next detection timing. An example of the image data in the case of time t = 4200 seconds is shown in FIG. FIG. 15B shows data from the start of charging to time t = 4200 seconds. Further, the above operation is repeated, and an example of image data in the case of time t = 6300 seconds is shown in FIG. In this embodiment, detection is automatically performed every 2100 seconds. FIG. 15D shows an example of image data at time t = 23100 seconds, and FIG. 15E shows an example of image data at time t = 29400 seconds. F) is an example of image data at time t = 44,100 seconds. Further, FIG. 16A is an example of image data when fully charged, and the right shows completion of charging.
なお、本実施の形態では、検出タイミングを２１００秒毎に設定しているが、最初の検出タイミングを２１００秒とした後は、６０秒毎に設定してもよく、リアルタイムに近づけて、異常を検出した場合に即座に対応できる異常検出システムとすることが好ましい。なお、最初の検出タイミングを２１００秒とした根拠は、学習のための二次電池のデータから見出し、試行錯誤で求めたものであるので、対象となる二次電池の種類が変われば、その二次電池のデータ次第で変わりうるものである。ただし、充電開始から最初の検出タイミングまでの間隔を長くし、その後の検出間隔を同じまたは短くする原則を維持することが好ましいことは経験上言えるものである。 In the present embodiment, the detection timing is set every 2100 seconds, but after the first detection timing is set to 2100 seconds, it may be set every 60 seconds, or it may be set closer to real time to make an abnormality. It is preferable to set it as the abnormality detection system which can respond promptly, when it detects. The reason for setting the first detection timing to 2100 seconds was found from the data of the secondary battery for learning, and was obtained by trial and error. Therefore, if the type of secondary battery to be targeted changes, It may change depending on the data of the next battery. However, it can be said empirically that it is preferable to maintain the principle of lengthening the interval from the charge start to the first detection timing and making the subsequent detection intervals the same or shorter.
また、比較のためにマイクロショートが発生したデータの満充電時の画像用データの一例を図１６（Ｂ）に示す。図１６（Ｂ）では満充電時のものであるが、マイクロショートの発生が充電の中間付近に見受けられるため、本実施の形態の異常検出方法を用いた場合、充電途中で異常検出がなされ、即座に充電停止または警告などを行うことができる。 Further, FIG. 16B shows an example of image data at the time of full charge of data in which a micro short has occurred for comparison. In FIG. 16 (B), although the occurrence of the micro short circuit is observed near the middle of the charge, the occurrence of the micro short is observed near the middle of the charge, so when the abnormality detection method of this embodiment is used, the abnormality is detected during the charge. It is possible to stop charging or warn immediately.
また、本実施の形態では、データを画像用データに変換、値を正規化してＣＮＮに入力させる例を示したが、特に限定されず、プログラムによってデータ変換すればよい。本実施の形態では、わかりやすくするために図１５および図１６に示したように画像用データを可視化（表示装置に表示した場合の映像表示）させている。 Further, in the present embodiment, an example is shown in which data is converted into image data, and the value is normalized to be input to the CNN. However, the present invention is not particularly limited, and data conversion may be performed by a program. In the present embodiment, in order to make it easy to understand, as shown in FIG. 15 and FIG. 16, image data is visualized (image display when displayed on a display device).
（実施の形態７）
本実施の形態では、電気機器に搭載されている二次電池の異常をいち早く察知する検出システムを電子機器に実装する例について説明する。 Seventh Embodiment
In this embodiment, an example will be described in which a detection system for quickly detecting an abnormality of a secondary battery mounted in an electric device is mounted on an electronic device.
まず、二次電池を適用した電子機器として、例えば、テレビジョン装置（テレビ、又はテレビジョン受信機ともいう）、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機（携帯電話、携帯電話装置ともいう）、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。 First, as an electronic device to which a secondary battery is applied, for example, a television set (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone A large-sized game machine such as a telephone, a mobile phone device), a portable game machine, a portable information terminal, a sound reproduction device, a pachinko machine and the like can be mentioned.
次に、図１８（Ａ）および図１８（Ｂ）に、２つ折り可能なタブレット型端末の一例を示す。図１８（Ａ）および図１８（Ｂ）に示すタブレット型端末９６００は、筐体９６３０ａ、筐体９６３０ｂ、筐体９６３０ａと筐体９６３０ｂを接続する可動部９６４０、表示部９６３１、表示モード切り替えスイッチ９６２６、電源スイッチ９６２７、省電力モード切り替えスイッチ９６２５、留め具９６２９、操作スイッチ９６２８、を有する。表示部９６３１には、可撓性を有するパネルを用いることで、より広い表示部を有するタブレット端末とすることができる。図１８（Ａ）は、タブレット型端末９６００を開いた状態を示し、図１８（Ｂ）は、タブレット型端末９６００を閉じた状態を示している。 Next, FIGS. 18A and 18B illustrate an example of a foldable tablet terminal. The tablet terminal 9600 illustrated in FIGS. 18A and 18B includes a housing 9630a, a housing 9630b, a movable portion 9640 connecting the housing 9630a and the housing 9630b, a display portion 9631, a display mode switching switch 9626 , A power switch 9627, a power saving mode switching switch 9625, a fastener 9629, and an operation switch 9628. By using a flexible panel for the display portion 9631, the tablet terminal can have a wider display portion. FIG. 18A shows a state in which the tablet terminal 9600 is opened, and FIG. 18B shows a state in which the tablet terminal 9600 is closed.
また、タブレット型端末９６００は、筐体９６３０ａおよび筐体９６３０ｂの内部に蓄電体９６３５を有する。蓄電体９６３５は、可動部９６４０を通り、筐体９６３０ａと筐体９６３０ｂに渡って設けられている。 In addition, the tablet terminal 9600 includes a power storage body 9635 inside the housings 9630 a and 9630 b. The power storage unit 9635 is provided over the housing 9630 a and the housing 9630 b through the movable portion 9640.
表示部９６３１は、一部をタッチパネルの領域とすることができ、表示された操作キーにふれることでデータ入力をすることができる。また、タッチパネルのキーボード表示切り替えボタンが表示されている位置に指やスタイラスなどでふれることで表示部９６３１にキーボードボタン表示することができる。 A portion of the display portion 9631 can be a touch panel region, and data can be input by touching a displayed operation key. In addition, the keyboard button can be displayed on the display portion 9631 by touching the position where the keyboard display switching button of the touch panel is displayed with a finger, a stylus, or the like.
また、表示モード切り替えスイッチ９６２６は、縦表示又は横表示などの表示の向きを切り替え、白黒表示やカラー表示の切り替えなどを選択できる。省電力モード切り替えスイッチ９６２５は、タブレット型端末９６００に内蔵している光センサで検出される使用時の外光の光量に応じて表示の輝度を最適なものとすることができる。タブレット型端末は光センサだけでなく、ジャイロ、加速度センサ等の傾きを検出するセンサなどの他の検出装置を内蔵させてもよい。 In addition, the display mode switching switch 9626 can switch the display orientation such as vertical display or horizontal display, and can select switching between black and white display and color display. The power saving mode switching switch 9625 can optimize display luminance in accordance with the amount of outside light at the time of use detected by the light sensor incorporated in the tablet terminal 9600. The tablet type terminal may incorporate not only an optical sensor but also other detection devices such as a sensor for detecting inclination of a gyro, an acceleration sensor or the like.
図１８（Ｂ）は、タブレット型端末９６００を閉じた状態であり、タブレット型端末は、筐体９６３０、太陽電池９６３３、ＤＣＤＣコンバータ９６３６を含む充放電制御回路９６３４有する。また、蓄電体９６３５を監視対象として、本発明の一態様に係る二次電池の異常検出システムを用いる。タブレット型端末は、蓄電体９６３５に対してＡＩシステムを組み込んだＩＣを電気的に接続させることで、二次電池の異常検出のためのニューラルネットワーク処理を行うことができる。 FIG. 18B shows a state where the tablet terminal 9600 is closed, and the tablet terminal includes a charge and discharge control circuit 9634 including a housing 9630, a solar cell 9633, and a DCDC converter 9636. In addition, the secondary battery abnormality detection system according to one embodiment of the present invention is used with the storage battery 9635 as a monitoring target. The tablet terminal can perform neural network processing for detecting an abnormality of the secondary battery by electrically connecting an IC incorporating the AI system to the storage battery 9635.
なお、タブレット型端末９６００は２つ折り可能なため、未使用時に筐体９６３０ａおよび筐体９６３０ｂを重ね合せるように折りたたむことができる。折りたたむことにより、表示部９６３１を保護できるため、タブレット型端末９６００の耐久性を高めることができる。また、本発明の一態様の異常検出システムを用いた蓄電体９６３５は、長期間に渡って使用できるタブレット型端末９６００を提供できる。 Note that since the tablet terminal 9600 can be folded in two, the housing 9630a and the housing 9630b can be folded so as to overlap when not in use. Since the display portion 9631 can be protected by folding, durability of the tablet terminal 9600 can be improved. In addition, the power storage unit 9635 including the abnormality detection system of one embodiment of the present invention can provide a tablet terminal 9600 that can be used for a long time.
また、この他にも図１８（Ａ）および図１８（Ｂ）に示したタブレット型端末は、様々な情報（静止画、動画、テキスト画像など）を表示する機能、カレンダー、日付又は時刻などを表示部に表示する機能、表示部に表示した情報をタッチ入力操作又は編集するタッチ入力機能、様々なソフトウェア（プログラム）によって処理を制御する機能、等を有することができる。 In addition to this, the tablet type terminal shown in FIGS. 18A and 18B has a function of displaying various information (still image, moving image, text image, etc.), a calendar, a date or time, etc. A function of displaying on the display portion, a touch input function of performing touch input operation or editing of information displayed on the display portion, a function of controlling processing by various software (programs), and the like can be provided.
タブレット型端末の表面に装着された太陽電池９６３３によって、電力をタッチパネル、表示部、又は映像信号処理部等に供給することができる。なお、太陽電池９６３３は、筐体９６３０の片面又は両面に設けることができ、蓄電体９６３５の充電を効率的に行う構成とすることができる。 Electric power can be supplied to the touch panel, the display portion, the video signal processing portion, or the like by the solar battery 9633 mounted on the surface of the tablet terminal. Note that the solar battery 9633 can be provided on one side or both sides of the housing 9630, and can be efficiently charged with the power storage unit 9635.
また、図１８（Ｂ）に示す充放電制御回路９６３４の構成、および動作について図１８（Ｃ）にブロック図を示し説明する。図１８（Ｃ）には、太陽電池９６３３、蓄電体９６３５、ＤＣＤＣコンバータ９６３６、コンバータ９６３７、スイッチＳＷ１乃至ＳＷ３、表示部９６３１について示しており、蓄電体９６３５、ＤＣＤＣコンバータ９６３６、コンバータ９６３７、スイッチＳＷ１乃至ＳＷ３が、図１８（Ｂ）に示す充放電制御回路９６３４に対応する箇所となる。 The structure and operation of the charge and discharge control circuit 9634 illustrated in FIG. 18B will be described with reference to a block diagram in FIG. FIG. 18C illustrates a solar cell 9633, a storage battery 9635, a DCDC converter 9636, a converter 9637, switches SW1 to SW3, and a display portion 9631. The storage battery 9635, the DCDC converter 9636, the converter 9637, the switch SW1 to The portion SW3 corresponds to the charge / discharge control circuit 9634 shown in FIG.
まず外光により太陽電池９６３３により発電がされる場合の動作の例について説明する。太陽電池で発電した電力は、蓄電体９６３５を充電するための電圧となるようＤＣＤＣコンバータ９６３６で昇圧又は降圧がなされる。そして、表示部９６３１の動作に太陽電池９６３３からの電力が用いられる際にはスイッチＳＷ１をオンにし、コンバータ９６３７で表示部９６３１に必要な電圧に昇圧又は降圧をすることとなる。また、表示部９６３１での表示を行わない際には、スイッチＳＷ１をオフにし、スイッチＳＷ２をオンにして蓄電体９６３５の充電を行う構成とすればよい。 First, an example of operation in the case where electric power is generated by the solar battery 9633 by external light will be described. The electric power generated by the solar cell is stepped up or down by the DCDC converter 9636 so as to be a voltage for charging the power storage unit 9635. Then, when the power from the solar cell 9633 is used for the operation of the display portion 9631, the switch SW1 is turned on, and the converter 9637 boosts or steps down the voltage necessary for the display portion 9631. In addition, when display on the display portion 9631 is not performed, the switch SW1 may be turned off and the switch SW2 may be turned on to charge the power storage unit 9635.
なお太陽電池９６３３については、発電手段の一例として示したが、特に限定されず、圧電素子（ピエゾ素子）や熱電変換素子（ペルティエ素子）などの他の発電手段による蓄電体９６３５の充電を行う構成であってもよい。例えば、無線（非接触）で電力を送受信して充電する無接点電力伝送モジュールや、また他の充電手段を組み合わせて行う構成としてもよい。 Although the solar cell 9633 is illustrated as an example of the power generation means, it is not particularly limited, and a configuration in which the power storage body 9635 is charged by another power generation means such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element) It may be For example, a non-contact power transmission module that transmits and receives power wirelessly (without contact) to charge the battery, or another charging unit may be combined.
図１９に、他の電子機器の例を示す。図１９において、表示装置８０００は、二次電池８００４の異常検出システムを実装する電子機器の一例である。具体的に、表示装置８０００は、ＴＶ放送受信用の表示装置に相当し、筐体８００１、表示部８００２、スピーカ部８００３、二次電池８００４等を有する。本発明の一態様に係る異常検出システムは、筐体８００１の内部に設けられている。表示装置８０００は、商用電源から電力の供給を受けることもできるし、二次電池８００４に蓄積された電力を用いることもできる。表示装置８０００は、二次電池８００４に対してＡＩシステムを組み込んだＩＣを電気的に接続させることで、二次電池の異常検出のためのニューラルネットワーク処理を行うことができる。 FIG. 19 shows an example of another electronic device. In FIG. 19, a display device 8000 is an example of an electronic device on which the abnormality detection system for the secondary battery 8004 is mounted. Specifically, the display device 8000 corresponds to a display device for receiving a TV broadcast, and includes a housing 8001, a display portion 8002, a speaker portion 8003, a secondary battery 8004, and the like. The abnormality detection system according to one embodiment of the present invention is provided inside the housing 8001. The display device 8000 can receive power supply from a commercial power supply, or can use power stored in the secondary battery 8004. The display device 8000 can perform neural network processing for detecting an abnormality of a secondary battery by electrically connecting an IC in which an AI system is incorporated to the secondary battery 8004.
表示部８００２には、液晶表示装置、有機ＥＬ素子などの発光素子を各画素に備えた発光装置、電気泳動表示装置、ＤＭＤ（Ｄｉｇｉｔａｌ　Ｍｉｃｒｏｍｉｒｒｏｒ　Ｄｅｖｉｃｅ）、ＰＤＰ（Ｐｌａｓｍａ　Ｄｉｓｐｌａｙ　Ｐａｎｅｌ）、ＦＥＤ（Ｆｉｅｌｄ　Ｅｍｉｓｓｉｏｎ　Ｄｉｓｐｌａｙ）などの、半導体表示装置を用いることができる。 The display portion 8002 includes a liquid crystal display device, a light emitting device including a light emitting element such as an organic EL element in each pixel, an electrophoretic display device, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), and an FED (Field Emission Display). Etc.) can be used.
また、音声入力デバイス８００５も二次電池を用いる。音声入力デバイス８００５は、二次電池に対してＡＩシステムを組み込んだＩＣを電気的に接続させることで、二次電池の異常検出のためのニューラルネットワーク処理を行うことができる。音声入力デバイス８００５は、無線通信素子の他、マイク、複数のセンサ（光学センサ、温度センサ、湿度センサ、気圧センサ、照度センサ、モーションセンサなど）を有し、使用者の命令する言葉によって他のデバイス、例えば表示装置８０００の電源操作、照明装置８１００の光量調節などを行うことができる。音声入力デバイス８００５は音声で周辺機器の操作が行え、手動リモコンの代わりとなる。 The voice input device 8005 also uses a secondary battery. The voice input device 8005 can perform neural network processing for detecting an abnormality of the secondary battery by electrically connecting an IC incorporating the AI system to the secondary battery. The voice input device 8005 includes a microphone and a plurality of sensors (optical sensor, temperature sensor, humidity sensor, barometric pressure sensor, illuminance sensor, motion sensor, etc.) in addition to a wireless communication element, and the user's instructional words Power supply operation of a device such as the display device 8000, light amount adjustment of the lighting device 8100, and the like can be performed. The voice input device 8005 can operate peripheral devices by voice and can replace the manual remote control.
また、音声入力デバイス８００５は、車輪や機械式移動手段を有しており、使用者の発声が聞こえる方向に移動し、内蔵されているマイクで正確に命令を聞き取るとともに、その内容を表示部８００８に表示する、または表示部８００８のタッチ入力操作が行える構成としている。 In addition, the voice input device 8005 has wheels and mechanical moving means, moves in the direction in which the user can hear the voice, hears the command accurately with the built-in microphone, and displays the contents on the display portion 8008. Or a touch input operation of the display portion 8008 can be performed.
また、音声入力デバイス８００５は、スマートフォンなどの携帯情報端末８００９の充電ドックとしても機能させることができる。携帯情報端末８００９と音声入力デバイス８００５は、有線または無線で電力の授受を可能としている。携帯情報端末は、室内においては、特に持ち運ぶ必要がなく、必要な容量を確保しつつ、二次電池に負荷がかかり劣化することを回避したいため、音声入力デバイス８００５によって二次電池の管理、メンテナンスなどを行えることが望ましい。また、スピーカ８００７及びマイクを有しているため、充電中であってもハンズフリーで会話することもできる。また、音声入力デバイス８００５の二次電池の容量が低下すれば、矢印の方向に移動し、外部電源と接続された充電モジュール８０１０から無線充電によって充電を行えばよい。また、充電モジュール８０１０に対してＡＩシステムを組み込んだＩＣを実装すれば、間接的に携帯情報端末８００９の二次電池の異常検出のためのニューラルネットワーク処理を行うことができる。 In addition, the voice input device 8005 can also function as a charging dock of a portable information terminal 8009 such as a smartphone. The portable information terminal 8009 and the voice input device 8005 can transmit and receive power by wire or wirelessly. There is no need to carry the portable information terminal indoors, and it is necessary to maintain and maintain the necessary capacity, and to avoid load and deterioration of the secondary battery, so the voice input device 8005 manages and maintains the secondary battery. It is desirable to be able to In addition, since the speaker 8007 and the microphone are included, hands-free conversation can be performed even during charging. In addition, if the capacity of the secondary battery of the voice input device 8005 is lowered, it moves in the direction of the arrow, and charging may be performed by wireless charging from the charging module 8010 connected to the external power supply. If an IC incorporating an AI system is mounted on the charging module 8010, it is possible to perform neural network processing indirectly for detecting an abnormality in the secondary battery of the portable information terminal 8009.
また、図１９においては音声入力デバイス８００５を床に設置する例を示したが、特に限定されず、車輪や機械式移動手段を設けて所望の位置に移動させてもよく、或いは台や車輪を設けず固定してもよい。 In addition, although an example in which the voice input device 8005 is installed on the floor is shown in FIG. 19, it is not particularly limited, and wheels or mechanical moving means may be provided to move to a desired position. You may fix without providing.
なお、表示装置には、ＴＶ放送受信用の他、パーソナルコンピュータ用、広告表示用など、全ての情報表示用表示装置が含まれる。 The display device includes all display devices for displaying information, such as for personal computers, for displaying advertisements, as well as for receiving TV broadcasts.
図１９において、据え付け型の照明装置８１００は、充電を制御するマイクロプロセッサ（ＡＰＳを含む）で制御される二次電池８１０３を用いた電子機器の一例である。具体的に、照明装置８１００は、筐体８１０１、光源８１０２、二次電池８１０３等を有する。図１９では、二次電池８１０３が、筐体８１０１及び光源８１０２が据え付けられた天井８１０４の内部に設けられている場合を例示しているが、二次電池８１０３は、筐体８１０１の内部に設けられていても良い。照明装置８１００は、商用電源から電力の供給を受けることもできるし、二次電池８１０３に蓄積された電力を用いることもできる。 In FIG. 19, a stationary lighting device 8100 is an example of an electronic device using a secondary battery 8103 controlled by a microprocessor (including APS) which controls charging. Specifically, the lighting device 8100 includes a housing 8101, a light source 8102, a secondary battery 8103, and the like. Although FIG. 19 illustrates the case where the secondary battery 8103 is provided inside the ceiling 8104 on which the housing 8101 and the light source 8102 are installed, the secondary battery 8103 is provided inside the housing 8101. It may be done. The lighting device 8100 can receive power from a commercial power supply. Alternatively, the lighting device 8100 can use power stored in the secondary battery 8103.
なお、図１９では天井８１０４に設けられた据え付け型の照明装置８１００を例示しているが、二次電池は、天井８１０４以外、例えば側壁８１０５、床８１０６、窓８１０７等に設けられた据え付け型の照明装置に用いることもできるし、卓上型の照明装置などに用いることもできる。 Although the stationary lighting device 8100 provided on the ceiling 8104 is illustrated in FIG. 19, the secondary battery is a stationary type provided on, for example, the side wall 8105, the floor 8106, the window 8107, and the like other than the ceiling 8104. It can also be used for a lighting device, and can also be used for a desk-type lighting device or the like.
また、光源８１０２には、電力を利用して人工的に光を得る人工光源を用いることができる。具体的には、白熱電球、蛍光灯などの放電ランプ、ＬＥＤや有機ＥＬ素子などの発光素子が、上記人工光源の一例として挙げられる。 Further, as the light source 8102, an artificial light source which artificially obtains light using electric power can be used. Specifically, a discharge lamp such as an incandescent lamp and a fluorescent lamp, and a light emitting element such as an LED or an organic EL element are mentioned as an example of the artificial light source.
図１９において、室内機８２００及び室外機８２０４を有するエアコンディショナーは、二次電池８２０３を用いた電子機器の一例である。具体的に、室内機８２００は、筐体８２０１、送風口８２０２、二次電池８２０３等を有する。図１９では、二次電池８２０３が、室内機８２００に設けられている場合を例示しているが、二次電池８２０３は室外機８２０４に設けられていても良い。或いは、室内機８２００と室外機８２０４の両方に、二次電池８２０３が設けられていても良い。エアコンディショナーは、商用電源から電力の供給を受けることもできるし、二次電池８２０３に蓄積された電力を用いることもできる。 In FIG. 19, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 is an example of an electronic device using a secondary battery 8203. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a secondary battery 8203, and the like. Although FIG. 19 illustrates the case where the secondary battery 8203 is provided in the indoor unit 8200, the secondary battery 8203 may be provided in the outdoor unit 8204. Alternatively, the secondary battery 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The air conditioner can receive power from a commercial power supply, or can use power stored in the secondary battery 8203.
図１９において、電気冷凍冷蔵庫８３００は、二次電池８３０４を用いた電子機器の一例である。具体的に、電気冷凍冷蔵庫８３００は、筐体８３０１、冷蔵室用扉８３０２、冷凍室用扉８３０３、二次電池８３０４等を有する。図１９では、二次電池８３０４が、筐体８３０１の内部に設けられている。電気冷凍冷蔵庫８３００は、商用電源から電力の供給を受けることもできるし、二次電池８３０４に蓄積された電力を用いることもできる。 In FIG. 19, an electric refrigerator-freezer 8300 is an example of an electronic device using a secondary battery 8304. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, a secondary battery 8304, and the like. In FIG. 19, the secondary battery 8304 is provided inside the housing 8301. The electric refrigerator-freezer 8300 can receive power supply from a commercial power supply, or can use power stored in the secondary battery 8304.
また、電子機器が使用されない時間帯、特に、商用電源の供給元が供給可能な総電力量のうち、実際に使用される電力量の割合（電力使用率と呼ぶ）が低い時間帯において、二次電池に電力を蓄えておくことで、上記時間帯以外において電力使用率が高まるのを抑えることができる。例えば、電気冷凍冷蔵庫８３００の場合、気温が低く、冷蔵室用扉８３０２、冷凍室用扉８３０３の開閉が行われない夜間において、二次電池８３０４に電力を蓄える。そして、気温が高くなり、冷蔵室用扉８３０２、冷凍室用扉８３０３の開閉が行われる昼間において、二次電池８３０４を補助電源として用いることで、昼間の電力使用率を低く抑えることができる。 Also, when the electronic equipment is not used, especially in a time zone where the ratio of the amount of power actually used (referred to as the power usage rate) to the total amount of power that can be supplied by the commercial power supply source is low. By storing power in the secondary battery, it is possible to suppress an increase in the power usage rate outside the above time zone. For example, in the case of the electric refrigerator-freezer 8300, electric power is stored in the secondary battery 8304 at night when the cold room door 8302 and the freezer room door 8303 are not opened / closed because the air temperature is low. Then, in the daytime when the temperature of the room rises and the refrigerator door 8302 and the freezer door 8303 are opened and closed, by using the secondary battery 8304 as an auxiliary power source, it is possible to suppress the daytime power usage rate low.
上述の電子機器の他、二次電池はあらゆる電子機器に搭載することができる。本発明の一態様により、二次電池のサイクル特性が良好となる。そのため本発明の一態様である充電を制御するマイクロプロセッサ（ＡＰＳを含む）を、本実施の形態で説明した電子機器に搭載することで、より長寿命の電子機器とすることができる。本実施の形態は、他の実施の形態と適宜組み合わせて実施することが可能である。 The secondary battery can be mounted on any electronic device other than the above-described electronic device. According to one aspect of the present invention, the cycle characteristics of the secondary battery are improved. Therefore, by mounting a microprocessor (including an APS) which controls charging, which is one embodiment of the present invention, in the electronic device described in this embodiment, the electronic device can have a longer lifetime. This embodiment can be implemented in appropriate combination with the other embodiments.
（実施の形態８）
本実施の形態では、電気機器に搭載している二次電池の一例として、円筒型の二次電池６００の例について図２０（Ａ）に示す。円筒型の二次電池６００は、図２０（Ｂ）に示すように、上面に正極キャップ（電池蓋）６０１を有し、側面および底面に電池缶（外装缶）６０２を有している。これら正極キャップ６０１と電池缶（外装缶）６０２とは、ガスケット（絶縁パッキン）６１０によって絶縁されている。 Eighth Embodiment
In this embodiment, an example of a cylindrical secondary battery 600 is illustrated in FIG. 20A as an example of a secondary battery mounted in an electric device. As shown in FIG. 20B, the cylindrical secondary battery 600 has a positive electrode cap (battery lid) 601 on the top and a battery can (outer can) 602 on the side and bottom. The positive electrode cap 601 and the battery can (outer can) 602 are insulated by a gasket (insulation packing) 610.
図２０（Ｂ）は、円筒型の二次電池の断面を模式的に示した図である。中空円柱状の電池缶６０２の内側には、帯状の正極６０４と負極６０６とがセパレータ６０５を間に挟んで捲回された電池素子が設けられている。図示しないが、電池素子はセンターピンを中心に捲回されている。電池缶６０２は、一端が閉じられ、他端が開いている。電池缶６０２には、電解液に対して耐腐食性のあるニッケル、アルミニウム、チタン等の金属、又はこれらの合金やこれらと他の金属との合金（例えば、ステンレス鋼等）を用いることができる。また、電解液による腐食を防ぐため、ニッケルやアルミニウム等を被覆することが好ましい。電池缶６０２の内側において、正極、負極およびセパレータが捲回された電池素子は、対向する一対の絶縁板６０８、６０９により挟まれている。また、電池素子が設けられた電池缶６０２の内部は、非水電解液（図示せず）が注入されている。二次電池は、コバルト酸リチウム（ＬｉＣｏＯ２）やリン酸鉄リチウム（ＬｉＦｅＰＯ４）などの活物質を含む正極と、リチウムイオンの吸蔵・放出が可能な黒鉛等の炭素材料からなる負極と、エチレンカーボネートやジエチルカーボネートなどの有機溶媒に、ＬｉＢＦ４やＬｉＰＦ６等のリチウム塩からなる電解質を溶解させた非水電解液などにより構成される。 FIG. 20 (B) is a view schematically showing a cross section of a cylindrical secondary battery. Inside the hollow cylindrical battery can 602 is provided a battery element in which a strip-shaped positive electrode 604 and a negative electrode 606 are wound with a separator 605 interposed therebetween. Although not shown, the battery element is wound around the center pin. One end of the battery can 602 is closed and the other end is open. For the battery can 602, a metal such as nickel, aluminum, titanium or the like having corrosion resistance to an electrolytic solution, or an alloy of these or an alloy of these with another metal (for example, stainless steel or the like) can be used. . In addition, in order to prevent corrosion by the electrolytic solution, it is preferable to coat nickel, aluminum or the like. Inside the battery can 602, the battery element in which the positive electrode, the negative electrode, and the separator are wound is sandwiched between a pair of opposing insulating plates 608 and 609. In addition, a non-aqueous electrolyte (not shown) is injected into the inside of the battery can 602 provided with the battery element. The secondary battery includes a positive electrode containing an active material such as lithium cobaltate (LiCoO 2 ) and lithium iron phosphate (LiFePO 4 ), a negative electrode made of a carbon material such as graphite capable of absorbing and releasing lithium ions, and ethylene It comprises a non-aqueous electrolytic solution in which an electrolyte composed of a lithium salt such as LiBF 4 or LiPF 6 is dissolved in an organic solvent such as carbonate or diethyl carbonate.
円筒型の二次電池に用いる正極および負極は捲回するため、集電体の両面に活物質を形成することが好ましい。正極６０４には正極端子（正極集電リード）６０３が接続され、負極６０６には負極端子（負極集電リード）６０７が接続される。正極端子６０３および負極端子６０７は、ともにアルミニウムなどの金属材料を用いることができる。正極端子６０３は安全弁機構６１２に、負極端子６０７は電池缶６０２の底にそれぞれ抵抗溶接される。安全弁機構６１２は、ＰＴＣ素子（Ｐｏｓｉｔｉｖｅ　Ｔｅｍｐｅｒａｔｕｒｅ　Ｃｏｅｆｆｉｃｉｅｎｔ）６１１を介して正極キャップ６０１と電気的に接続されている。安全弁機構６１２は電池の内圧の上昇が所定の閾値を超えた場合に、正極キャップ６０１と正極６０４との電気的な接続を切断するものである。また、ＰＴＣ素子６１１は温度が上昇した場合に抵抗が増大する熱感抵抗素子であり、抵抗の増大により電流量を制限して異常発熱を防止するものである。ＰＴＣ素子には、チタン酸バリウム（ＢａＴｉＯ３）系半導体セラミックス等を用いることができる。 In order to wind the positive electrode and the negative electrode used for the cylindrical secondary battery, it is preferable to form an active material on both sides of the current collector. A positive electrode terminal (positive electrode current collection lead) 603 is connected to the positive electrode 604, and a negative electrode terminal (negative electrode current collection lead) 607 is connected to the negative electrode 606. Both the positive electrode terminal 603 and the negative electrode terminal 607 can be made of a metal material such as aluminum. The positive electrode terminal 603 is resistance welded to the safety valve mechanism 612, and the negative electrode terminal 607 is resistance welded to the bottom of the battery can 602. The safety valve mechanism 612 is electrically connected to the positive electrode cap 601 via a PTC element (Positive Temperature Coefficient) 611. The safety valve mechanism 612 disconnects the electrical connection between the positive electrode cap 601 and the positive electrode 604 when the increase in internal pressure of the battery exceeds a predetermined threshold. The PTC element 611 is a heat sensitive resistance element whose resistance increases when the temperature rises, and the amount of current is limited by the increase of the resistance to prevent abnormal heat generation. A barium titanate (BaTiO 3 ) -based semiconductor ceramic or the like can be used for the PTC element.
また、図２０（Ｃ）のように複数の二次電池６００を、導電板６１３および導電板６１４の間に挟んでモジュール６１５を構成してもよい。複数の二次電池６００は、並列接続されていてもよいし、直列接続されていてもよいし、並列に接続された後さらに直列に接続されていてもよい。複数の二次電池６００を有するモジュール６１５を構成することで、大きな電力を取り出すことができる。 Alternatively, as illustrated in FIG. 20C, a plurality of secondary batteries 600 may be interposed between the conductive plate 613 and the conductive plate 614 to form a module 615. The plurality of secondary batteries 600 may be connected in parallel, may be connected in series, or may be connected in series and then connected in series. By configuring the module 615 including the plurality of secondary batteries 600, large power can be extracted.
図２０（Ｄ）はモジュール６１５の上面図である。図を明瞭にするために導電板６１３を点線で示した。図２０（Ｄ）に示すようにモジュール６１５は、複数の二次電池６００を電気的に接続する導線６１６を有していてもよい。導線６１６上に導電板６１３を重畳して設けることができる。また複数の二次電池６００の間に温度制御装置６１７を有していてもよい。二次電池６００が過熱されたときは、温度制御装置６１７により冷却し、二次電池６００が冷えすぎているときは温度制御装置６１７により加熱することができる。そのためモジュール６１５の性能が外気温に影響されにくくなる。 FIG. 20D is a top view of the module 615. FIG. The conductive plate 613 is shown by a dotted line to clarify the figure. As shown in FIG. 20D, the module 615 may have a conductor 616 electrically connecting the plurality of secondary batteries 600. The conductive plate 613 can be provided over the conductive wire 616 in an overlapping manner. Further, the temperature control device 617 may be provided between the plurality of secondary batteries 600. When the secondary battery 600 is overheated, it can be cooled by the temperature control device 617, and when the secondary battery 600 is too cold, it can be heated by the temperature control device 617. Therefore, the performance of the module 615 is less susceptible to the outside air temperature.
複数の二次電池６００の保護回路として、ＡＩシステムを組み込んだＩＣを実装すれば、複数の二次電池６００の異常検出のためのニューラルネットワーク処理を行うことができる。 If an IC incorporating an AI system is mounted as a protection circuit for the plurality of secondary batteries 600, neural network processing for detecting an abnormality in the plurality of secondary batteries 600 can be performed.
（実施の形態９）
本実施の形態では、車両に複数の二次電池を搭載する例を示す。 (Embodiment 9)
In the present embodiment, an example in which a plurality of secondary batteries are mounted on a vehicle is shown.
二次電池を車両に搭載すると、ハイブリッド車（ＨＥＶ）、電気自動車（ＥＶ）、又はプラグインハイブリッド車（ＰＨＥＶ）等の次世代クリーンエネルギー自動車を実現できる。 When the secondary battery is mounted on a vehicle, it is possible to realize a next-generation clean energy vehicle such as a hybrid vehicle (HEV), an electric vehicle (EV), or a plug-in hybrid vehicle (PHEV).
図２１において、本発明の一態様である二次電池の異常検出システムを用いた車両を例示する。図２１（Ａ）に示す自動車８４００は、走行のための動力源として電気モーターを用いる電気自動車である。また、走行のための動力源として電気モーターとエンジンを適宜選択して用いることが可能なハイブリッド自動車である。また、自動車８４００は複数の二次電池を有する電池モジュール８４０２を有する。二次電池の保護回路として、ＡＩシステムを組み込んだＩＣを実装すれば、二次電池の異常検出のためのニューラルネットワーク処理を行うことができる。１０００個以上の二次電池を用いる自動車８４００であっても二次電池の異常検出のためのニューラルネットワーク処理を効率よく行うことができる。二次電池は、車内の床部分に対して、図２０（Ｃ）に示した小型の円筒型の二次電池を多く並べて使用すればよい。また、図２０（Ｃ）に示す二次電池を図２１（Ａ）に示したように、複数組み合わせた電池パックを車内の床部分に対して設置してもよい。二次電池は電気モーター８４０６を駆動するだけでなく、ヘッドライト８４０１やルームライト（図示せず）などの発光装置に電力を供給することができる。 FIG. 21 illustrates a vehicle using a secondary battery abnormality detection system according to an aspect of the present invention. An automobile 8400 shown in FIG. 21A is an electric automobile using an electric motor as a motive power source for traveling. In addition, it is a hybrid car that can be used by appropriately selecting and using an electric motor and an engine as a power source for traveling. In addition, the automobile 8400 has a battery module 8402 having a plurality of secondary batteries. If an IC incorporating an AI system is mounted as a protection circuit for a secondary battery, neural network processing for detecting an abnormality in the secondary battery can be performed. Even in an automobile 8400 using 1000 or more secondary batteries, neural network processing for detecting an abnormality of the secondary battery can be efficiently performed. As the secondary battery, many small cylindrical secondary batteries shown in FIG. 20C may be used side by side with respect to the floor portion in the car. Further, as shown in FIG. 21 (A), the secondary battery shown in FIG. 20 (C) may be provided with a plurality of combined battery packs with respect to the floor portion in the vehicle. The secondary battery can not only drive the electric motor 8406 but can also supply power to light emitting devices such as the headlight 8401 and the room light (not shown).
また、二次電池は、自動車８４００が有するスピードメーター、タコメーターなどの表示装置に電力を供給することができる。また、二次電池は、自動車８４００が有するナビゲーションシステムなどの半導体装置に電力を供給することができる。また、車両の外装部に太陽電池８４０５を設けている。図２１（Ａ）に示す自動車８４００は、ホイール内に電気モーター８４０６を有し、サイドミラーの代わりにカメラ８４０３を備えている。また、図２１（Ａ）中の８４０４はフロントガラスである。 In addition, the secondary battery can supply power to a display device such as a speedometer or a tachometer which the automobile 8400 has. In addition, the secondary battery can supply power to a semiconductor device such as a navigation system of the automobile 8400. In addition, a solar cell 8405 is provided on the exterior of the vehicle. An automobile 8400 shown in FIG. 21A includes an electric motor 8406 in a wheel, and a camera 8403 instead of a side mirror. Reference numeral 8404 in FIG. 21A denotes a windshield.
図２１（Ｂ）に示す自動車８５００は、自動車８５００が有する二次電池にプラグイン方式や非接触給電方式等により外部の充電設備から電力供給を受けて、充電することができる。図２１（Ｂ）に、地上設置型の充電装置８０２１から自動車８５００に搭載された二次電池８０２４に、ケーブル８０２２を介して充電を行っている状態を示す。充電に際しては、充電方法やコネクターの規格等はＣＨＡｄｅＭＯ（登録商標）やコンボ等の所定の方式で適宜行えばよい。充電装置８０２１は、商用施設に設けられた充電ステーションでもよく、また家庭の電源であってもよい。例えば、プラグイン技術によって、外部からの電力供給により自動車８５００に搭載された二次電池８０２４を充電することができる。充電は、充電装置８０２１が有するＡＣＤＣコンバータ等の変換装置を介して、交流電力を直流電力に変換して行うことができる。また充電用ＡＣＤＣコンバータ８０２５が搭載された自動車８５００の場合は、交流電源を接続しても充電を行うことができる。充電装置８０２１に対してＡＩシステムを組み込んだＩＣを実装させれば、自動車８５００の二次電池の異常検出のためのニューラルネットワーク処理を行うことができる。 An automobile 8500 illustrated in FIG. 21B can be charged by receiving power supply from an external charging facility to a secondary battery included in the automobile 8500 by a plug-in system, a non-contact power feeding system, or the like. FIG. 21B shows a state in which the secondary battery 8024 mounted on the vehicle 8500 from the ground-mounted charging device 8021 is charged through the cable 8022. At the time of charging, the charging method, the standard of the connector, etc. may be appropriately performed by a predetermined method such as CHAdeMO (registered trademark) or combo. The charging device 8021 may be a charging station provided in a commercial facility, or may be a home power source. For example, the plug-in technology can charge the secondary battery 8024 mounted on the automobile 8500 by external power supply. Charging can be performed by converting AC power into DC power through a converter such as an ACDC converter included in the charging device 8021. In the case of a car 8500 equipped with a charging ACDC converter 8025, charging can be performed even if AC power is connected. If an IC incorporating an AI system is mounted on the charging device 8021, neural network processing for detecting an abnormality in a secondary battery of the automobile 8500 can be performed.
また、図示しないが、受電装置を車両に搭載し、地上の送電装置から電力を非接触で供給して充電することもできる。この非接触給電方式の場合には、道路や外壁に送電装置を組み込むことで、停車中に限らず走行中に充電を行うこともできる。また、この非接触給電の方式を利用して、車両どうしで電力の送受信を行ってもよい。さらに、車両の外装部に太陽電池を設け、停車時や走行時に二次電池の充電を行ってもよい。このような非接触での電力の供給には、電磁誘導方式や磁界共鳴方式を用いることができる。 Although not shown, the power receiving device may be mounted on a vehicle, and power may be supplied contactlessly from a ground power transmitting device for charging. In the case of this non-contact power feeding method, charging can be performed not only while the vehicle is stopped but also while it is traveling by incorporating the power transmission device on the road or the outer wall. In addition, power may be transmitted and received between vehicles using this method of non-contact power feeding. Furthermore, a solar cell may be provided on the exterior of the vehicle to charge the secondary battery when the vehicle is stopped or traveling. For such non-contact power supply, an electromagnetic induction method or a magnetic resonance method can be used.
また、図２１（Ｃ）は、ＡＩシステムを組み込んだＩＣを実装した二輪車の一例である。図２１（Ｃ）に示すスクータ８６００は、二次電池８６０２、サイドミラー８６０１、方向指示灯８６０３を備える。二次電池８６０２は、方向指示灯８６０３に電気を供給することができる。ＡＩシステムを組み込んだＩＣにより二次電池８６０２の異常を検知することができる。 FIG. 21 (C) is an example of a two-wheeled vehicle mounted with an IC incorporating an AI system. A scooter 8600 shown in FIG. 21C includes a secondary battery 8602, a side mirror 8601, and a direction indicator light 8603. The secondary battery 8602 can supply electricity to the direction indicator 8603. An IC incorporating an AI system can detect an abnormality in the secondary battery 8602.
また、図２１（Ｃ）に示すスクータ８６００は、座席下収納８６０４に、二次電池８６０２を収納することができる。二次電池８６０２は、座席下収納８６０４が小型であっても、座席下収納８６０４に収納することができる。二次電池８６０２は、取り外し可能となっており、充電時には二次電池８６０２を屋内に持って運び、充電し、走行する前に収納すればよい。 A scooter 8600 shown in FIG. 21C can store the secondary battery 8602 in the under-seat storage 8604. The secondary battery 8602 can be stored in the under-seat storage 8604 even if the under-seat storage 8604 is small. The secondary battery 8602 can be removed, and at the time of charging, the secondary battery 8602 may be carried indoors, carried, charged, and stored before traveling.
また、車両に搭載した二次電池を車両以外の電力供給源としても用いることもできる。この場合、例えば電力需要のピーク時に商用電源を用いることを回避することができる。電力需要のピーク時に商用電源を用いることを回避できれば、省エネルギー、および二酸化炭素の排出の削減に寄与することができる。 Moreover, the secondary battery mounted in the vehicle can also be used as an electric power supply source other than a vehicle. In this case, it is possible to avoid using a commercial power supply, for example, at the peak of the power demand. If it is possible to avoid using a commercial power source at the peak of power demand, it can contribute to energy saving and reduction of carbon dioxide emissions.
本実施の形態は、他の実施の形態と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the other embodiments.
本実施例では、画像用データを４０００個用い、全体の７割を学習用、３割をテスト用に振り分けて異常検出精度を確認する。推論を行うアルゴリズムは、Ｐｙｔｈｏｎ（Ｃｈａｉｎｅｒ）で作成した。画像用データは、予め測定した二次電池の充電特性をグレー階調で表した２次元データ、即ちｎ行×ｎ（ｎ＞２）列の配列データに変換したものである。グレー階調で表した配列データとすることで画像データをカテゴライズするパターン認識で用いられているアルゴリズムを用いることができる。画像パターン認識で用いられているプログラムやＩＣを用いることができるため、開発のためのコストを低減することができる。 In the present embodiment, 4000 image data are used, 70% of the whole are allocated for learning and 30% for testing, and the abnormality detection accuracy is confirmed. The algorithm for inference was created in Python (Chainer). The image data is converted into two-dimensional data representing the charging characteristics of the secondary battery measured in advance in gray tones, that is, array data of n rows × n (n> 2) columns. By using array data represented in gray tones, an algorithm used in pattern recognition for categorizing image data can be used. Since a program or IC used in image pattern recognition can be used, the cost for development can be reduced.
重みパラメータ（フィルタとも呼べる）に関しては、予め、正常データを正解ラベルとし、正解ラベル付きの画像用データを入力データに用いて特徴を抽出し、特徴を抽出するための重みパラメータを配列に保存し、ミニバッチサイズごとに重みを更新して学習させる。ミニバッチサイズとは、ミニバッチのデータサンプル数である。 With regard to weight parameters (also referred to as filters), features are extracted beforehand using normal data as correct labels and image data with correct labels as input data, and weighting parameters for feature extraction are stored in an array. Update and learn weights for each mini-batch size. The mini-batch size is the number of data samples of the mini-batch.
また、学習データにおいて、充電の経過途中のある時間で異常として検出した場合、ある時間以降のデータに異常がなくとも二次電池にマイクロショートは発生したこととし、異常データとしてラベルし、学習させた。 In addition, in the learning data, if it is detected as abnormal at a certain time during charging, it is determined that a micro short has occurred in the secondary battery even if there is no abnormality in data after a certain time, and labeled as abnormal data and learned The
本実施例では、ミニバッチ４０とし、正方行列となるように配列データのサイズを２１０×２１０とし、８ビットのグレー階調としている。 In this embodiment, the mini-batch 40 is used, and the size of the array data is set to 210 × 210 so as to form a square matrix, and the gray scale is 8 bits.
また、本実施例において、ニューラルネットワーク処理は、図１７に示すように、畳み込み処理、マックスプーリング処理、ドロップアウト処理を３セット行って推論させた。学習データに基づいて二次電池の正常特性と異常特性を判別させている。図１７において、畳み込み（畳み込み積分、積和）処理、マックスプーリング処理、ドロップアウト処理の順で行われる。抽出された特徴量をプーリング処理し、特徴量を中間層の出力とする。ドロップアウト処理は、ある特定のデータを除去する処理である。上記畳み込み処理、マックスプーリング処理、ドロップアウト処理を３セット行った後は、全結合処理を行い、その後、出力する。 Further, in the present embodiment, as shown in FIG. 17, in the neural network processing, three sets of convolution processing, max pooling processing, and dropout processing are performed to be inferred. The normal characteristics and the abnormal characteristics of the secondary battery are determined based on the learning data. In FIG. 17, the process is performed in the order of convolution (convolution and integration, product-sum) processing, max pooling processing, and dropout processing. The extracted feature quantities are pooled, and the feature quantities are used as the output of the intermediate layer. The dropout process is a process of removing certain data. After three sets of the above convolution processing, max pooling processing, and dropout processing, all combination processing is performed and then output.
サンプル数２５００のテストを行い、誤答は２個であり、正答率は９９．９２％であった。これらの結果からＣＮＮを用いて高い確率で二次電池の異常（マイクロショート）を検知することができたと言える。 The number of samples tested was 2500, and the number of incorrect answers was 2. The correct answer rate was 99.92%. From these results, it can be said that abnormality (micro short) of the secondary battery could be detected with high probability using CNN.
また、８ビットに限定されず、画像用データを６ビットとしても同様の結果を得ることができた。 Also, the present invention was not limited to 8 bits, and similar results could be obtained even if the image data is 6 bits.
Ｂ１：端子、Ｂ１ａ：端子、Ｂ１ｂ：端子、Ｂ２：端子、Ｃ６１：容量素子、Ｃ６２：容量素子、Ｃ６３：容量素子、Ｃ６３ａ：容量素子、ＣＳ１：容量素子、ＣＳ１ａ：容量素子、ＣＳ１ｂ：容量素子、ＭＮ６１：トランジスタ、ＭＮ６２：トランジスタ、ＭＮ６４：トランジスタ、ＭＮ６４ａ：トランジスタ、ＭＮ６４ｂ：トランジスタ、ＭＯ６１：ＯＳトランジスタ、ＭＯ６２：ＯＳトランジスタ、ＭＯ６３：ＯＳトランジスタ、ＭＯ６３ａ：ＯＳトランジスタ、ＭＰ６１：トランジスタ、ＭＰ６２：トランジスタ、ＭＰ６３：トランジスタ、ＭＷ１：トランジスタ、ＭＷ１ａ：トランジスタ、ＭＷ１ｂ：トランジスタ、ＳＷ１：スイッチ、ＳＷ３：スイッチ、６００：二次電池、６０１：正極キャップ、６０２：電池缶、６０３：正極端子、６０４：正極、６０５：セパレータ、６０６：負極、６０７：負極端子、６０８：絶縁板、６０９：絶縁板、６１１：ＰＴＣ素子、６１２：安全弁機構、６１３：導電板、６１４：導電板、６１５：モジュール、６１６：導線、６１７：温度制御装置、１４００：ＤＯＳＲＡＭ、１４０５：コントローラ、１４１０：行回路、１４１１：デコーダ、１４１２：ワード線ドライバ回路、１４１３：列セレクタ、１４１４：センスアンプドライバ回路、１４１５：列回路、１４１６：グローバルセンスアンプアレイ、１４１７：入出力回路、１４２０：メモリセルおよびセンスアンプアレイ、１４２２：メモリセルアレイ、１４２３：センスアンプアレイ、１４２５：ローカルメモリセルアレイ、１４２６：ローカルセンスアンプアレイ、１４４４：スイッチアレイ、１４４５：メモリセル、１４４５ａ：メモリセル、１４４５ｂ：メモリセル、１４４６：センスアンプ、１４４７：グローバルセンスアンプ、１６００：ＮＯＳＲＡＭ、１６１０：メモリセルアレイ、１６１１：メモリセル、１６１１−１６１４：メモリセル、１６１２：メモリセル、１６１３：メモリセル、１６１４：メモリセル、１６１５：メモリセル、１６１５ａ：メモリセル、１６１５ｂ：メモリセル、１６４０：コントローラ、１６５０：行ドライバ、１６５１：行デコーダ、１６５２：ワード線ドライバ、１６６０：列ドライバ、１６６１：列デコーダ、１６６２：ドライバ、１６６３：ＤＡＣ、１６７０：出力ドライバ、１６７１：セレクタ、１６７２：ＡＤＣ、１６７３：出力バッファ、４０１０：演算部、４０１１：アナログ演算回路、４０１２：ＤＯＳＲＡＭ、４０１３：ＮＯＳＲＡＭ、４０１４：ＦＰＧＡ、４０２０：制御部、４０２１：ＣＰＵ、４０２２：ＧＰＵ、４０２３：ＰＬＬ、４０２５：ＰＲＯＭ、４０２６：メモリコントローラ、４０２７：電源回路、４０２８：ＰＭＵ、４０３０：入出力部、４０３１：外部記憶制御回路、４０３２：音声コーデック、４０３３：映像コーデック、４０３４：汎用入出力モジュール、４０３５：通信モジュール、４０４１：ＡＩシステム、７０００：ＡＩシステムＩＣ、７００１：リード、７００２：プリント基板、７００３：回路部、７００４：実装基板、７０３１：Ｓｉトランジスタ層、７０３２：配線層、７０３３：ＯＳトランジスタ層、８０００：表示装置、８００１：筐体、８００２：表示部、８００３：スピーカ部、８００４：二次電池、８００５：音声入力デバイス、８００７：スピーカ、８００８：表示部、８００９：携帯情報端末、８０１０：充電モジュール、８０２１：充電装置、８０２２：ケーブル、８０２４：二次電池、８０２５：充電用ＡＣＤＣコンバータ、８１００：照明装置、８１０１：筐体、８１０２：光源、８１０３：二次電池、８１０４：天井、８１０５：側壁、８１０６：床、８１０７：窓、８２００：室内機、８２０１：筐体、８２０２：送風口、８２０３：二次電池、８２０４：室外機、８３００：電気冷凍冷蔵庫、８３０１：筐体、８３０２：冷蔵室用扉、８３０３：冷凍室用扉、８３０４：二次電池、８４００：自動車、８４０１：ヘッドライト、８４０２：電池モジュール、８４０３：カメラ、８４０４：フロントガラス、８４０５：太陽電池、８４０６：電気モーター、８５００：自動車、８６００：スクータ、８６０１：サイドミラー、８６０２：二次電池、８６０３：方向指示灯、８６０４：座席下収納、９６００：タブレット型端末、９６２５：スイッチ、９６２６：スイッチ、９６２７：電源スイッチ、９６２８：操作スイッチ、９６２９：留め具、９６３０：筐体、９６３０ａ：筐体、９６３０ｂ：筐体、９６３１：表示部、９６３３：太陽電池、９６３４：充放電制御回路、９６３５：蓄電体、９６３６：ＤＣＤＣコンバータ、９６３７：コンバータ、９６４０：可動部 B1: terminal, B1a: terminal, B1b: terminal, B2: terminal, C61: capacitive element, C62: capacitive element, C63: capacitive element, C63a: capacitive element, CS1: capacitive element, CS1a: capacitive element, CS1b: capacitive element , MN61: transistor, MN62: transistor, MN64: transistor, MN64a: transistor, MN64b: transistor, MO61: OS transistor, MO62: OS transistor, MO63: OS transistor, MO63a: OS transistor, MP61: transistor, MP62: transistor, MP63 A transistor, MW1: transistor, MW1a: transistor, MW1b: transistor, SW1: switch, SW3: switch, 600: secondary battery, 601: positive electrode cap, 602: battery can, 603: positive Terminals 604: positive electrode 605: separator 606: negative electrode 607: negative electrode terminal 608: insulating plate 609: insulating plate 611: PTC element 612: safety valve mechanism 613: conductive plate 614: conductive plate 615 A module 616: a conductor 617: a temperature controller, 1400: a DOSRAM, 1405: a controller, 1410: a row circuit, 1411: a decoder, 1412: a word line driver circuit, 1413: a column selector, 1414: a sense amplifier driver circuit, 1415 : Column circuit, 1416: Global sense amplifier array, 1417: Input / output circuit, 1420: Memory cell and sense amplifier array, 1422: Memory cell array, 1423: Sense amplifier array, 1425: Local memory cell array, 1426: Local sense amplifier array 1444: switch array, 1445: memory cell, 1445a: memory cell, 1445b: memory cell, 1446: sense amplifier, 1447: global sense amplifier, 1600: NOSRAM, 1610: memory cell array, 1611: memory cell, 1611-1614: memory Cell, 1612: Memory cell, 1613: Memory cell, 1614: Memory cell, 1615: Memory cell, 1615a: Memory cell, 1615b: Memory cell, 1640: Controller, 1650: Row driver, 1651: Row decoder, 1652: Word line Driver, 1660: Column driver, 1661: Column decoder, 1662: Driver, 1663: DAC, 1670: Output driver, 1671: Selector, 1672: ADC, 1673: Output buffer, 401 0: Arithmetic unit, 4011: Analog arithmetic circuit, 4012: DOSRAM, 4013: NOSRAM, 4014: FPGA, 4020: Control unit, 4021: CPU, 4022: GPU, 4023: PLL, 4025: PROM, 4026: Memory controller, 4027 Power supply circuit 4028: PMU 4030: input / output unit 4031: external storage control circuit 4032: audio codec, 4033: video codec, 4034: general purpose input / output module 4035: communication module 4041: AI system 7000: 7000 AI system IC, 7001: lead, 7002: printed circuit board, 7003: circuit portion, 7004: mounting substrate, 7031: Si transistor layer, 7032: wiring layer, 7033: OS transistor layer, 8000: display, 8001: Body 8002: display unit 8003: speaker unit 8004: secondary battery 8005: voice input device 8007: speaker 8008: display unit 8009: portable information terminal 8010: charging module 8021: charging device 8022 A: cable, 8024: secondary battery, 8025: ACDC converter for charging, 8100: lighting device, 8101: housing, 8102: light source, 8103: secondary battery, 8104: ceiling, 8105: side wall, 8106: floor, 8107: Window, 8200: indoor unit, 8201: housing, 8202: air outlet, 8203: secondary battery, 8204: outdoor unit, 8300: electric refrigerator-freezer, 8301: housing, 8302: door for refrigerator compartment, 8303: freezer compartment For door, 8304: secondary battery, 8400: car, 8401: headlight, 8402: battery module LE, 8403: Camera, 8404: Windscreen, 8405: Solar cell, 8406: Electric motor, 8500: Automobile, 8600: Scooter, 8601: Side mirror, 8602: Secondary battery, 8603: Direction indicator, 8604: Seat Bottom storage 9600: tablet type terminal 9625: switch 9626: switch 9627: power switch, 9628: operation switch, 9629: fastener, 9630: housing, 9630a: housing, 9630b: housing, 9631: display Part, 9633: solar cell, 9634: charge and discharge control circuit, 9635: storage battery, 9636: DCDC converter, 9637: converter, 9640: movable part

Claims (13)

  1. 二次電池と、
    前記二次電池の電圧値を測定する測定手段と、
    測定された二次電池の電圧値を画像用データに変換する手段と、
    学習データに基づいて画像用データを分類する判定手段と、を有する二次電池の充電制御システム。     With a secondary battery,
    Measurement means for measuring the voltage value of the secondary battery;
    A means for converting the measured voltage value of the secondary battery into image data;
    And a determination unit that classifies image data based on learning data.
  2. 請求項１において、前記判定手段は、積和演算を含み、
    前記判定手段は、半導体層として酸化物半導体材料を用いるトランジスタを用いる二次電池の充電制御システム。     The apparatus according to claim 1, wherein the determination means includes a product-sum operation.
    The determination control unit is a charge control system of a secondary battery using a transistor using an oxide semiconductor material as a semiconductor layer.
  3. 請求項１において、前記二次電池の電圧値を測定する測定手段は、外部電源から電力を供給されて測定する二次電池の充電制御システム。 2. The charge control system for a secondary battery according to claim 1, wherein the measurement means for measuring the voltage value of the secondary battery is supplied with power from an external power source and measured.
  4. 請求項１において、前記判定手段は、外部電源から電力を供給されて演算する二次電池の充電制御システム。 The charge control system for a secondary battery according to claim 1, wherein the determination unit is operated by being supplied with power from an external power supply.
  5. 請求項１において、前記画像用データは表示させない二次電池の充電制御システム。 The charge control system for a secondary battery according to claim 1, wherein the image data is not displayed.
  6. 請求項１において、さらに前記二次電池の充電特性データを記憶するメモリ部を有する二次電池の充電制御システム。 The charge control system for a secondary battery according to claim 1, further comprising a memory unit for storing charge characteristic data of the secondary battery.
  7. 請求項１乃至６のいずれか一において、前記画像用データは、８ビットのグレー階調の配列データである二次電池の充電制御システム。 The charge control system for a secondary battery according to any one of claims 1 to 6, wherein the image data is array data of 8-bit gray gradation.
  8. 二次電池の電圧値を第１の期間において測定し、
    測定された二次電池の電圧値を第１の画像用データに変換し、
    前記第１の画像用データを分類し、
    前記第１の期間の後の第２の期間において二次電池の電圧値を測定し、
    測定された二次電池の電圧値を第２の画像用データに変換し、
    学習データに基づいて前記第２の画像用データを分類し、
    前記第１及び前記第２の画像用データの分類の結果から正常、或いは異常の判定を行う二次電池の異常検出方法。     The voltage value of the secondary battery is measured in the first period,
    Converting the measured voltage value of the secondary battery into first image data;
    Classify the first image data;
    Measuring a voltage value of the secondary battery in a second period after the first period;
    Convert the measured voltage value of the secondary battery into second image data;
    Classifying the second image data based on learning data;
    The abnormality detection method of the secondary battery which determines normality or abnormality from the result of classification of said 1st and 2nd data for image.
  9. 請求項８において、前記第２の期間の長さは、前記第１の期間以下であることを特徴とする二次電池の異常検出方法。 The method according to claim 8, wherein the length of the second period is equal to or less than the first period.
  10. 請求項８において、前記二次電池の１回の充電期間は、第１の期間と、第２の期間とを含むことを特徴とする二次電池の異常検出方法。 The method according to claim 8, wherein one charging period of the secondary battery includes a first period and a second period.
  11. 請求項８乃至１０のいずれか一において、前記第１の画像用データ及び前記第２の画像用データは、８ビットのグレー階調の配列データである二次電池の充電制御システム。 The charge control system for a secondary battery according to any one of claims 8 to 10, wherein the first image data and the second image data are 8-bit gray gradation array data.
  12. 請求項８において、前記二次電池はリチウムイオン二次電池である異常検出方法。 9. The abnormality detection method according to claim 8, wherein the secondary battery is a lithium ion secondary battery.
  13. 請求項８において、前記二次電池は固体電池である異常検出方法。 The abnormality detection method according to claim 8, wherein the secondary battery is a solid battery.
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