WO2019010975A1 - 压阻检测电路、压阻检测基板、显示面板及显示装置 - Google Patents

压阻检测电路、压阻检测基板、显示面板及显示装置 Download PDF

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WO2019010975A1
WO2019010975A1 PCT/CN2018/076319 CN2018076319W WO2019010975A1 WO 2019010975 A1 WO2019010975 A1 WO 2019010975A1 CN 2018076319 W CN2018076319 W CN 2018076319W WO 2019010975 A1 WO2019010975 A1 WO 2019010975A1
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Prior art keywords
transistor
piezoresistive
gate
disposed
display panel
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PCT/CN2018/076319
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English (en)
French (fr)
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WO2019010975A8 (zh
Inventor
郑智仁
郭玉珍
王鹏鹏
丁小梁
曹学友
韩艳玲
刘伟
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京东方科技集团股份有限公司
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Priority to US16/301,523 priority Critical patent/US11301076B2/en
Priority to EP18796355.8A priority patent/EP3654152A4/en
Publication of WO2019010975A1 publication Critical patent/WO2019010975A1/zh
Publication of WO2019010975A8 publication Critical patent/WO2019010975A8/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3262—Power saving in digitizer or tablet
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0414—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using force sensing means to determine a position
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0414—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using force sensing means to determine a position
    • G06F3/04144—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using force sensing means to determine a position using an array of force sensing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens

Definitions

  • Embodiments of the present disclosure relate to a piezoresistive detection circuit, a piezoresistive detection substrate, a display panel, and a display device.
  • the piezoresistive detection circuit refers to a circuit in which a varistor in a circuit is subjected to a change in resistance and then a change in resistance is converted into a standard signal output.
  • the current piezoresistive detection circuit usually includes a piezoresistive sensor, a selection switch transistor and a resistive voltage amplifier. The change of the output voltage of the piezoresistive detection circuit is used to obtain a change in the piezoresistive force, thereby obtaining the magnitude of the pressure it receives.
  • At least one embodiment of the present disclosure provides a piezoresistive detection circuit including: a first transistor, a second transistor, a fixed resistor, and a pressure sensitive resistor; the first end of the fixed resistor is connected to the first voltage signal end, and the second end Connected to the first node; the first end of the voltage sensitive resistor is connected to the first node, and the second end is grounded; the gate of the first transistor is connected to the first node, the source and the second voltage The signal ends are connected, the drain is connected to the source of the second transistor; the gate of the second transistor is connected to the scanning signal line, and the drain is connected to the read signal line.
  • the first end and the second end of the pressure sensitive resistor are in an off state when not under pressure, and the resistance value of the pressure resistor is affected by The pressure becomes larger and decreases.
  • At least one embodiment of the present disclosure provides a piezoresistive detection substrate, including: a substrate substrate, a plurality of piezoresistive detection circuits disposed in a detection region of the substrate substrate, a plurality of read signal lines, and a plurality of scan signal lines
  • Each of the piezoresistive detection circuits includes: a first transistor, a second transistor, a fixed resistor, and a pressure sensitive resistor; a first end of the fixed resistor is connected to the first voltage signal end, and the second end is connected to the first node Connected to; the first end of the voltage sensitive resistor is connected to the first node, the second end is grounded; the gate of the first transistor is connected to the first node, and the source is connected to the second voltage signal end, A drain is connected to a source of the second transistor; a gate of the second transistor is connected to the scan signal line, and a drain is connected to the read signal line.
  • the piezoresistive detection circuits are arranged in an array; each of the piezoresistive detection circuits in each column is connected to the same read signal line, each row The piezoresistive detecting circuit is connected to the same scanning signal line; or each of the piezoresistive detecting circuits is connected to the same read signal line, and each of the piezoresistive detecting circuits and the same strip in each column The scanning signal lines are connected.
  • the piezoresistive detection substrate provided by at least one embodiment of the present disclosure further includes: a constant current source, an amplifier, and an analog-to-digital converter disposed in a non-detection region of the base substrate; wherein each of the read signals One end of the line is connected to the one-to-one corresponding constant current source, and one end of each of the read signal lines is connected to a one-to-one corresponding input end of the amplifier; an output end of the amplifier and the modulus The inputs of the converter are connected.
  • the piezoresistive detection substrate provided by at least one embodiment of the present disclosure further includes an acquisition circuit, wherein an output end of the amplifier is connected to an input end of the acquisition circuit; an output end of the acquisition circuit and the modulus The inputs of the converter are connected.
  • the acquisition circuit includes: a switching device and a capacitor; wherein one end of the switching device is connected to an output end of the amplifier, and another of the switching device One end is grounded as an output through the capacitor.
  • a plurality of the acquisition circuits are connected to one of the analog-to-digital converters, and each of the acquisition circuits connected to the same analog-to-digital converter
  • the switching device is time-divisionally turned on.
  • one of the acquisition circuits is connected to one of the analog to digital converters.
  • the first end and the second end of the pressure sensitive resistor are in an off state when not under pressure, and the resistance value of the pressure resistor is affected by The pressure becomes larger and decreases.
  • At least one embodiment of the present disclosure provides a display panel including the above-described piezoresistive detecting circuit or the piezoresistive detecting substrate, and a plurality of pixel circuits disposed in a display region of the base substrate.
  • a display area and a detection area of the base substrate are the same area;
  • the pixel circuit includes: a switching transistor, a driving transistor, and an organic light emitting diode; Provided on the switching transistor and the driving transistor; a source and a drain of the switching transistor, a source and a drain of the driving transistor, a source and a drain of the first transistor, and a source and drain of the second transistor a very similar layer is disposed on the source/drain metal layer; an active layer of the switching transistor, an active layer of the driving transistor, an active layer of the first transistor, and an active layer of the second transistor are disposed in the same layer And a source/drain metal layer disposed between the semiconductor layer and the organic light emitting diode.
  • the fixed resistor and the pressure sensitive resistor are disposed between the base substrate and the semiconductor layer; the display panel further includes: The first ends of the fixed resistors are respectively connected to the plurality of first electrodes connected to each other, and the first electrodes are used as the first voltage signal end; the ground electrodes connected to the second ends of the pressure sensitive resistors are respectively The second end of each of the fixed resistors and the first end of each of the piezoresistive resistors are connected to each other in a one-to-one correspondence, and each of the second electrodes serves as a first node.
  • the ground electrode, the pressure sensitive resistor, the second electrode, the fixed resistor, and the first electrode are sequentially stacked on the base substrate. Settings.
  • a gate of the switching transistor and a gate of the driving transistor are disposed on a gate metal layer, and the gate metal layer is disposed on the source and drain.
  • the first electrode is disposed between the semiconductor layer and the fixed resistor; each of the second electrode portions overlaps with the fixed resistor, and the portion is the first The active layer of the transistor overlaps as the gate of the first transistor.
  • each of the first transistors further includes a floating gate disposed in the gate metal layer.
  • a gate of the switching transistor, a gate of the driving transistor, a gate of the first transistor, and a gate of the second transistor are disposed on the gate in the same layer.
  • a metal layer, the gate metal layer is disposed between the semiconductor layer and the second electrode;
  • the fixed resistor is disposed between the gate metal layer and the second electrode;
  • the two electrode portions overlap the fixed resistor, partially overlap the gate of the first transistor and are connected through the via.
  • each of the first electrodes is disposed in the source/drain metal layer or in the gate metal layer.
  • At least one embodiment of the present disclosure provides a display device including the above display panel.
  • FIG. 1 is a schematic structural view of a piezoresistive array sensor
  • FIG. 2 is a schematic circuit diagram of a piezoresistive detection circuit
  • FIG. 3 is a schematic structural diagram of a piezoresistive detection circuit according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a piezoresistive detection substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a circuit structure of a piezoresistive detection substrate according to an embodiment of the present disclosure
  • FIG. 6 is a timing diagram of a piezoresistive detection substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a planar structure of a display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic circuit diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic cross-sectional view of a display panel according to another embodiment of the present disclosure.
  • FIG. 11 is a schematic cross-sectional view of a display panel according to still another embodiment of the present disclosure.
  • FIG. 1 is a schematic structural view of a piezoresistive array sensor.
  • the piezoresistive array sensor includes a gate driver circuit (Analog Circuit), an analog circuit 01 (Analog Circuit), and a plurality of piezoresistive detection circuits.
  • a plurality of piezoresistive detection circuits are disposed in the detection area and arranged in an array; the gate drive circuit is disposed in the non-detection area to perform progressive scan on the plurality of scan signal lines of the detection area; the analog circuit is disposed in the non-detection area,
  • the demultiplexer MUX performs signal conversion and reading on a plurality of read signal lines of the detection area.
  • the piezoresistive detection circuit is composed of a piezoresistive sensor P R , a selection switch TFT and a resistive voltage amplifier; the resistance of the piezoresistive sensor P R is R X , and the output of the piezoresistive detection circuit V OU The voltage is R F /R X ⁇ V B , so the change in piezoresistance can be obtained by detecting the change in the output V OU .
  • the piezoresistive sensor P R in the above-described piezoresistive detecting circuit is connected to the resistive voltage amplifier and performs the detection output, the piezoresistive detecting circuit is in a normally open state, and the current often leaks out during operation. For example, a leakage current of N ⁇ V B /R X is generated, where N is the number of columns of piezoresistive detection circuits, which causes a large leakage current during the piezoresistive detection process, which is disadvantageous to the accuracy of the final detection result.
  • the resistance of the selection switch TFT is related to the characteristics of the device itself, and the trace resistance is related to the length of the trace. Therefore, the measured output will be unstable, which may cause errors in the final test result.
  • At least one embodiment of the present disclosure provides a piezoresistive detection circuit including a first transistor, a second transistor, a fixed resistor, and a pressure sensitive resistor; a first end of the fixed resistor is connected to the first voltage signal end, and the second end is first The node is connected; the first end of the voltage sensitive resistor is connected to the first node, and the second end is grounded; the gate of the first transistor is connected to the first node, the source is connected to the second voltage signal end, and the drain is connected to the second transistor The source is connected; the gate of the second transistor is connected to the scanning signal line, and the drain is connected to the read signal line.
  • the second transistor When the piezoresistive detection circuit collects the pressure sense, the second transistor can be turned on by the scan signal line, and the potential of the first node controls the voltage of the first voltage signal end flowing through the first transistor to Controlling the magnitude of the voltage signal transmitted to the read signal line connected to the drain of the second transistor, and determining the pressure sense of the piezoresistive detection circuit by determining the magnitude of the voltage signal outputted from the read signal line, and determining the touch
  • the change of the voltage signal read by the read signal line before the control and after the touch can remove the influence of the threshold voltage of the first transistor on the read voltage signal, thereby improving the detection accuracy.
  • the second transistor is turned on only during the acquisition detection, so that the piezoresistive detection circuit is actively detected, and is less susceptible to leakage current, thereby improving the sensitivity of the pressure sensing detection.
  • the piezoresistive detection circuit 200 includes a T1, a second transistor T2, a fixed resistor R B, and a pressure sensitive resistor P R ; the first of the fixed resistor R B The terminal is connected to the first voltage signal terminal V TOP , and the second terminal is connected to the first node X; the first end of the pressure sensitive resistor P R is connected to the first node X, and the second terminal is grounded; the gate of the first transistor T1 is The first node X is connected, the source is connected to the second voltage signal terminal V DD , the drain is connected to the source of the second transistor T2 , the gate of the second transistor T2 is connected to the scanning signal line SEL , and the drain and the read signal are connected.
  • Line Readline is connected.
  • the second transistor T2 when the pressure sense received by the piezoresistive detection circuit 200 is collected, the second transistor T2 is made through the scan signal line SEL connected to the gate of the second transistor T2.
  • the potential of the first node X connected to the gate of the first transistor T1 controls the magnitude of the voltage of the first voltage signal terminal VDD flowing through the first transistor T1 to control transmission to the second transistor.
  • the pressure sensing condition of the piezoresistive detecting circuit 200 can be determined by judging the magnitude of the voltage signal output from the read signal line Readline.
  • the operation timing of the piezoresistive detection substrate provided by the embodiment of the present disclosure will be described in detail.
  • the piezoresistive detection circuit 200 is first subjected to signal acquisition.
  • the gate voltage of the first transistor T1 that is, the voltage of the first node X is the voltage value of the first voltage signal terminal V TOP , due to the threshold voltage V TH of the first transistor T1
  • the scan signal line SEL 1 is turned on, the second transistor T2 is in an on state, and the voltage signal collected by the read signal line Readline is V TOP -V TH , that is, the read signal line Readline will be the first transistor T1
  • the threshold voltage is collected.
  • the pressure sensitive resistor P R in the piezoresistive detecting circuit 200 changes to become R R through the pressing resistor, so that a partial pressure is generated for the first node X, and the first can be obtained by calculation.
  • the voltage of the node X becomes V TOP ⁇ R R /(R B +R R ). Due to the presence of the threshold voltage V TH of the first transistor T1, when the scanning signal line SEL 1 is turned on, the second transistor T2 is in an on state.
  • the voltage signal collected by the read signal line Readline is V TOP ⁇ R R /(R B +R R )-V TH .
  • the difference between the voltage signals collected by the read signal line Readline is V TOP ⁇ R B /(R B +R R ), the influence of the threshold voltage of the first transistor T1 is removed, and the difference between the obtained voltages is only subjected to pressure change.
  • the influence of the resistance value of the pressure sensitive resistor P R is brought about. Therefore, the change in the voltage difference can be induced by the change in the voltage difference, and the difference in the detected voltage discharges the influence of the threshold voltage of the first transistor T1, the detection accuracy can be improved, and the second transistor T2 is turned on only during the acquisition detection.
  • the piezoresistive detection circuit 200 is actively detected, is not susceptible to leakage current, and can improve the sensitivity of pressure sensing.
  • the pressure sensitive resistor P R may be configured such that the first end and the second end of the pressure sensitive resistor P R are in an off state when not under pressure, and the first end and the second end of the pressure resistor P R are when turned on under pressure, and, by selecting a material pressure P R of the resistor, the resistance value of the pressure P R is the resistance becomes larger as the pressure applied increases. That is, the larger the pressure, the smaller the resistance value of the pressure resistor P R , so that the larger the voltage of the first node X is, the smaller the voltage signal output from the read signal line Readline is, and thus the initial state, that is, when the pressure is not under pressure. The larger the difference between the initial voltage signals output from the read signal line Readline, the greater the perceived change in pressure sensitivity.
  • the piezoresistive detection substrate includes: a substrate substrate 100, and a plurality of piezoresistive detection circuits 200 disposed in the detection area A of the substrate substrate 100. , a plurality of read signal lines Readline and a plurality of scan signal lines SEL.
  • each piezoresistive detecting circuit 200 includes a first transistor T1, a second transistor T2, a fixed resistor R B, and a voltage sensitive resistor P R .
  • the first end of the fixed resistor R B is connected to the first voltage signal terminal V TOP , and the second end is connected to the first node X; the first end of the pressure sensitive resistor P R is connected to the first node X, and the second end is grounded.
  • the gate of the first transistor T1 is connected to the first node X, the source is connected to the second voltage signal terminal V DD , the drain is connected to the source of the second transistor T2 , and the gate of the second transistor T2 is connected to the scanning signal line
  • the SEL is connected and the drain is connected to the read signal line Readline.
  • the second scanning signal line SEL connected to the gate of the second transistor T2 is used to make the second The transistor T2 is in an on state, and the potential of the first node X connected to the gate of the first transistor T1 controls the voltage of the first voltage signal terminal VDD flowing through the first transistor T1 to control the transmission to the first The voltage signal of the read signal line Readline connected to the drain of the second transistor T2.
  • the pressure sensing condition of the piezoresistive detecting circuit 200 can be determined by judging the magnitude of the voltage signal output from the read signal line Readline.
  • a read signal line Readline can read the pressure sensitive signals of the plurality of piezoresistive detecting circuits 200 in a time division manner by the second transistor T2 provided in each piezoresistive detecting circuit 200.
  • the operation timing of the piezoresistive detection substrate provided in this embodiment will be described in detail in conjunction with the timing chart shown in FIG. 6.
  • signal acquisition is performed on each piezoresistive detecting circuit 200 in the piezoresistive detecting substrate.
  • the gate voltage of the first transistor T1 that is, the voltage of the first node X is the voltage of the first voltage signal terminal V TOP .
  • the pressure sensitive resistor P R in the piezoresistive detecting circuit 200 changes to become R R through the pressing resistor, so that a partial pressure is generated for the first node X, and the first can be obtained by calculation.
  • the voltage of the node X becomes V TOP ⁇ R R /(R B +R R ).
  • the voltage signal collected by the read signal line Readline is V TOP ⁇ R R /(R B +R R )-V TH .
  • the difference between the voltage signals collected by the read signal line Readline is V TOP ⁇ R B /(R B +R R ), the influence of the threshold voltage of the first transistor T1 is removed, and the difference between the obtained voltages is only subjected to pressure change.
  • the influence of the resistance value of the pressure sensitive resistor P R is brought about.
  • the change in the voltage difference can be induced by the change in the voltage difference, and the difference in the detected voltage discharges the influence of the threshold voltage of the first transistor T1, the detection accuracy can be improved, and the second transistor T2 is turned on only during the acquisition detection.
  • the piezoresistive detection circuit 200 is actively detected, is not susceptible to leakage current, and can improve the sensitivity of pressure sensing.
  • the first end and the second end of the pressure sensitive resistor P R are in an off state when not under pressure, and the first end and the second end of the pressure resistor P R are end when pressure is turned on, and, by selecting a material pressure P R of the resistor, the resistance value of the pressure P R is the resistance becomes larger as the pressure applied increases. That is, the larger the pressure, the smaller the resistance value of the pressure resistor P R , so that the larger the voltage of the first node X is, the smaller the voltage signal output from the read signal line Readline is, and thus the initial state, that is, when the pressure is not under pressure. The larger the difference between the initial voltage signals output from the read signal line Readline, the greater the perceived change in pressure sensitivity.
  • each piezoresistive detection circuit may be arranged in an array, for example, to improve the effective detection area of the detection area and reduce the complexity of the wiring, as shown in FIG.
  • the resistance detecting circuits 200 are arranged in an array; at this time, each of the read signal lines Readline and each of the scanning signal lines SEL may be connected to the plurality of piezoresistive detecting circuits 200.
  • each of the piezoresistive detection circuits 200 can be connected to the same read signal line Readline, and each of the piezoresistive detection circuits 200 can be connected to the same scan signal line SEL; or, each row of piezoresistive detection circuits 200 can be Connected to the same read signal line Readline, each of the piezoresistive detecting circuits 200 can be connected to the same scanning signal line SEL, which can reduce the number of wirings of the read signal line Readline and the scanning signal line SEL.
  • the voltage signal of each read signal line Readline may be collected by a progressive scan method to determine the pressure sense change of each piezoresistive detection circuit 200; or, each read may be acquired by column-by-column scanning. The voltage signal of the signal line Readline is determined to determine the pressure change of each piezoresistive detecting circuit 200.
  • the piezoresistive detection substrate provided in this embodiment may further include: a constant current source I B disposed in the non-detection region, an amplifier 300, and an analog-to-digital converter ADC.
  • the piezoresistive detection substrate can also include an acquisition circuit 400 coupled between the amplifier 300 and an analog to digital converter ADC.
  • the above circuit configuration can ensure that the voltage signals read by the respective read signal lines Readline can be effectively detected.
  • each read signal line Readline is connected to a one-to-one constant current source I B , and one end of each read signal line Readline is connected to the input end of the one-to-one corresponding amplifier 300 .
  • the amplifier 300 is responsible for A-magnifying the voltage signal V OUT output from the read signal line Readline to ensure that the voltage change caused by the pressing can be effectively recognized.
  • the output of amplifier 300 is coupled to the input of acquisition circuit 400.
  • the acquisition circuit 400 is responsible for outputting the voltage signal AV OUT amplified by A times by the amplifier 300 to the analog-to-digital converter ADC of the back end.
  • the output of acquisition circuit 400 is coupled to the input of an analog to digital converter ADC.
  • the analog-to-digital converter ADC is responsible for converting the received analog voltage signal into a digital signal D OUT for output.
  • the acquisition circuit 400 may include a switching device SH and a capacitor Cs.
  • one end of the switching device SH is connected to the output of the amplifier 300, and the other end of the switching device SH is used as an output terminal to be grounded through the capacitor C S .
  • the acquisition circuit 400 can output a voltage signal AV OUT amplified by the amplifier 300 to the analog ADC of the back end when the switching device SH is in the on state; and make the amplifier when the switching device SH is in the off state.
  • the 300 and analog to digital converter ADCs are off. For example, in combination with the timing diagram shown in FIG.
  • the analog-to-digital converter ADC outputs a corresponding value when the switching device SH is turned on, by detecting the D2 and the touch pressure sensing output when the voltage control is touched ( After the non-touch) output D1 is subtracted, the voltage change of the first node can be obtained, thereby judging whether there is voltage control.
  • a plurality of acquisition circuits 400 can be connected to an analog-to-digital converter ADC, and at this time, switches in the respective acquisition circuits 400 connected to the same analog-to-digital converter ADC can be connected.
  • the device SH is configured to be time-divisional, and an analog-to-digital converter ADC is time-divisionally outputting multiple voltage signals of the read signal line Readline, thereby reducing the number of analog-to-digital converter ADCs and saving costs.
  • an acquisition circuit 400 may be connected to an analog-to-digital converter ADC.
  • An acquisition circuit 400 is coupled to an analog to digital converter ADC.
  • the embodiment of the present disclosure further provides a display panel comprising: the above-described piezoresistive detection or piezoresistive detection substrate provided by the embodiment of the present disclosure, and a plurality of pixel circuits disposed on the display area of the base substrate.
  • the display panel provided by the embodiment of the present disclosure can simultaneously integrate the functions of piezoresistive detection and display.
  • the detection area of the piezoresistive detection can be set according to actual needs.
  • a detection area of the piezoresistive detection may be set in a partial area of a non-display area as needed to implement a function such as a pressure sensitive touch button, or a detection area may be set in the display area to realize the use of the piezoresistive while displaying.
  • the detection implements the touch function, which is not limited in this embodiment.
  • the display area B and the detection area A of the base substrate 100 can be set to the same area, that is, the touch and display functions are implemented in the same area.
  • the pixel circuit 500 for realizing display and the piezoresistive detecting circuit 200 for implementing pressure sensitive touch can be formed in the same area.
  • the piezoresistive detection circuit 200 can be disposed between the respective pixel circuits 500 such that the piezoresistive detection circuit 200 does not affect the normal display of the pixel circuit 500.
  • the number of piezoresistive detection circuits 200 is not greater than the number of pixel circuits 500.
  • the pixel circuit 500 may include a switching transistor 501, a driving transistor 502, and an organic light emitting diode 503.
  • the pixel circuit 500 may include a plurality of switching transistors 501 and driving transistors 502, and the number of the switching transistors 501 and the driving transistors 502 is not limited in this embodiment.
  • Fig. 8 shows the structure of a pixel circuit 500.
  • a plurality of switching transistors 501 and driving transistors 502 can be provided as needed to implement the function of threshold voltage compensation.
  • the organic light emitting diode 503 may be disposed over the switching transistor 501 and the driving transistor 502.
  • the organic light emitting diode 503 includes at least an anode 5031, a light emitting layer 5032, and a cathode 5033 which are disposed in a stacked manner.
  • the cathode 5033 may be provided as a whole layer.
  • the organic light emitting diode 503 can be, for example, a bottom emission type, that is, the light emitted from the organic light emitting diode 503 is emitted from the cathode 5033 and reflected by the anode 5031.
  • the switching transistor 501 and the second transistor T2 are not shown in the cross-sectional structural diagram of the display panel shown in FIGS. 9 to 11.
  • the structure of the two transistors can be referred to the driving transistor 502.
  • the source and drain of the switching transistor 501, the source and drain of the driving transistor 502, the source and drain of the first transistor T1, and the source and drain of the second transistor T2 may be disposed in the same layer.
  • the active layer of the switching transistor 501, the active layer of the driving transistor 502, the active layer of the first transistor T1, and the active layer of the second transistor T2 may be disposed in the same layer on the semiconductor layer 700. This arrangement can save production. Process steps.
  • the source and drain metal layer 600 may be disposed between the semiconductor layer 700 and the organic light emitting diode 503, that is, the switching transistor 501, the driving transistor 502, the first transistor T1, and the second transistor T2 are both disposed on the organic light emitting diode 503 and the lining. Between the base substrates 100.
  • the second end of the fixed resistor R B and the first end of the pressure sensitive resistor P R in the piezoresistive detection circuit 200 pass through the first node X and the gate of the first transistor T1.
  • the fixed resistor R B and the pressure sensitive resistor P R may be disposed between the base substrate 100 and the semiconductor layer 700, that is, the fixed resistor R B and the pressure sensitive resistor P R are disposed. Below the semiconductor layer 700.
  • the display panel provided in this embodiment may further include a plurality of first electrodes 800 connected in one-to-one correspondence with the first ends of the fixed resistors R B , for example, the first electrodes 800 . It can be used as the first voltage signal terminal V TOP to ensure that the first voltage signal is applied to the first end of the fixed resistor R B through the first voltage signal terminal V TOP .
  • the display panel in the present embodiment may further comprise providing a ground electrode 900 connected to the second end of each of the pressure-sensitive resistors P R to ensure that the second end of the pressure sensing resistor P R Ground.
  • the display panel provided in this embodiment may further include a plurality of connections corresponding to the second ends of the fixed resistors R B and the first ends of the piezoresistors P R .
  • the second electrodes 010 and the second electrodes 010 can be used as the first node X, for example.
  • the fixed resistor R B may be disposed under the pressure sensitive resistor P R , or the pressure sensitive resistor P R may be disposed under the fixed resistor R B , which is fixed in this embodiment.
  • the specific positional relationship between the resistor R B and the pressure sensitive resistor P R is not limited.
  • each of the pressure sensitive resistors P R may be provided as a whole layer of pressure sensitive material, and the corresponding ground electrode 900 may also be provided as an entire layer of electrodes, thereby functioning as a shield electrode.
  • the ground electrode 900, the piezoresistive resistor P R , the second electrode 010, and the fixed resistor R B may be sequentially stacked on the base substrate 100.
  • the first electrode 800 the ground electrode 900, the piezoresistive resistor P R , the second electrode 010, and the fixed resistor R B may be sequentially stacked on the base substrate 100.
  • the first electrode 800 the first electrode 800.
  • each of the second electrodes 010 is connected to the gate of the first transistor T1 as the first node X, and the second electrode 010 is disposed under the fixed resistor R B , and thus is also located in the semiconductor.
  • the first transistor T1 can be disposed as a bottom gate transistor, that is, the gate of the first transistor T1 is located under the semiconductor layer 700, thereby facilitating the respective second electrodes 010 and The connection of the gate of a transistor T1.
  • the types of the switching transistor 501 and the driving transistor 502 are not limited, and a top gate type transistor or a bottom gate type transistor may be used.
  • the switching transistor 501 and the driving transistor 502 are top-gate transistors, as shown in FIGS. 9 and 10, the gate of the switching transistor 501 and the gate of the driving transistor 502 are, for example,
  • the same layer may be disposed between the source and drain metal layer 600 and the semiconductor layer 700.
  • the first electrode 800 may be disposed between the semiconductor layer 700 and the fixed resistor R B . .
  • each of the second electrodes 010 may partially overlap the fixed resistor R B and partially overlap the active layer of the first transistor T1 as the gate of the first transistor T1, that is, the gate pattern of the first transistor T1 is not separately provided. Instead, the portion of the second electrode 010 is directly used as the gate of the first transistor T1.
  • each of the first transistors T1 is a top gate transistor, as shown in FIG. 10, a position corresponding to the active layer of the first transistor T1 in the gate metal layer 020
  • the floating gate 021 can also be disposed to block the influence of the light emission of the organic light emitting diode 503 on the active layer of the first transistor T1, to avoid generating a photo-leakage current in the first transistor T1, and affecting the voltage of the first switching transistor T1. Resistance detection sensitivity.
  • the switching transistor 501 and the driving transistor 502 are bottom-gate transistors, as shown in FIG. 11, the gate of the switching transistor 501, the gate of the driving transistor 502, and the first transistor.
  • the gate of T1 and the gate of the second transistor T2 may be disposed in the same layer on the gate metal layer 020, and the gate metal layer 020 may be disposed between the semiconductor layer 700 and the second electrode 010.
  • the fixed resistor R B is disposed between the gate metal layer 020 and the second electrode 010; each of the second electrodes 010 may partially overlap the fixed resistor R B and partially overlap the gate of the first transistor T1 and pass through
  • the hole connection, that is, the second electrode 010 and the gate of the first transistor T1 are two different film layers.
  • each of the first electrodes 800 may be disposed in the source/drain metal layer 600 or in the gate metal layer 020 as shown in FIG. 11 , thereby saving the manufacturing process. This example does not limit this.
  • this embodiment does not limit the type of the second transistor T2, and the second transistor T2 may be a top gate transistor or a bottom gate transistor.
  • the type of the second transistor T2 can be set to be the same as the switching transistor 501 and the driving transistor 502 to save the manufacturing process.
  • the fixed resistor R B can be made of a conductor having a large resistance, for example, indium tin oxide (ITO), etc., which is not limited in this embodiment.
  • ITO indium tin oxide
  • the embodiment of the present disclosure further provides a display device, which includes the above display panel provided by the embodiment of the present disclosure, and the display device can be any display for a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like. Functional product or part.
  • the display device reference may be made to the embodiment of the above display panel, and the repeated description is omitted.
  • Embodiments of the present disclosure provide a piezoresistive detection circuit, a piezoresistive detection substrate, a display panel, and a display device.
  • the piezoresistive detection circuit collects the pressure sense
  • the second transistor can be turned on by the scan signal line, and the potential of the first node controls the voltage of the first voltage signal end flowing through the first transistor. Controlling the magnitude of the voltage signal transmitted to the read signal line connected to the drain of the second transistor, determining the pressure sense of the piezoresistive detection circuit by determining the magnitude of the voltage signal output from the read signal line, and determining The change of the voltage signal read by the read signal line before and after the touch can remove the influence of the threshold voltage of the first transistor on the read voltage signal, thereby improving the detection accuracy.
  • the second transistor is turned on only during the acquisition detection, so that the piezoresistive detection circuit is actively detected, and is less susceptible to leakage current, thereby improving the sensitivity of the pressure sensing detection.

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Abstract

压阻检测电路、压阻检测基板、显示面板及显示装置。该压阻检测电路包括第一晶体管(T1)、第二晶体管(T2)、固定电阻(R B)和压感电阻(P R)。该压阻检测电路在进行压感检测可以去除第一晶体管(T1)的阈值电压对读取的电压信号的影响，具有较高的检测精度。

Description

压阻检测电路、压阻检测基板、显示面板及显示装置
本申请要求于2017年7月13日递交的中国专利申请第201710571545.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种压阻检测电路、压阻检测基板、显示面板及显示装置。
背景技术
压阻检测电路是指电路中的压敏电阻受压后产生电阻变化,然后将电阻的变化转换为标准信号输出的电路。目前的压阻检测电路通常包括一个压阻传感器、一个选择开关晶体管和一个电阻式电压放大器，通过检测压阻检测电路输出信号的变化来得到压阻的变化，进而得出其受到的压力大小。
发明内容
本公开至少一实施例提供一种压阻检测电路，包括：第一晶体管、第二晶体管、固定电阻和压感电阻；所述固定电阻的第一端与第一电压信号端相连，第二端与第一节点相连；所述压感电阻的第一端与所述第一节点相连，第二端接地；所述第一晶体管的栅极与所述第一节点相连，源极与第二电压信号端相连，漏极与所述第二晶体管的源极相连；所述第二晶体管的栅极与扫描信号线相连，漏极与读取信号线相连。
例如，本公开至少一实施例提供的压阻检测电路中，所述压感电阻的第一端和第二端在未受压力时为断开状态，所述压力电阻的电阻值随着所受压力的变大而减小。
本公开至少一实施例提供一种压阻检测基板，包括：衬底基板，设置于所述衬底基板的检测区的多个压阻检测电路，多条读取信号线和多条扫描信号线；其中，各所述压阻检测电路包括：第一晶体管、第二晶体管、固定电阻和压感电阻；所述固定电阻的第一端与第一电压信号端相连，第二端与第 一节点相连；所述压感电阻的第一端与所述第一节点相连，第二端接地；所述第一晶体管的栅极与所述第一节点相连，源极与第二电压信号端相连，漏极与所述第二晶体管的源极相连；所述第二晶体管的栅极与所述扫描信号线相连，漏极与所述读取信号线相连。
例如，本公开至少一实施例提供的压阻检测基板中，所述压阻检测电路呈阵列排布；每列各所述压阻检测电路与同一条所述读取信号线相连，每行各所述压阻检测电路与同一条所述扫描信号线相连；或，每行各所述压阻检测电路与同一条所述读取信号线相连，每列各所述压阻检测电路与同一条所述扫描信号线相连。
例如，本公开至少一实施例提供的压阻检测基板，还包括：设置于所述衬底基板的非检测区的恒流源、放大器和模数转换器；其中，每条所述读取信号线的一端与一一对应的所述恒流源相连，且每条所述读取信号线的一端与一一对应的所述放大器的输入端相连；所述放大器的输出端与所述模数转换器的输入端相连。
例如，本公开至少一实施例提供的压阻检测基板，还包括采集电路，其中，所述放大器的输出端与所述采集电路的输入端相连；所述采集电路的输出端与所述模数转换器的输入端相连。
例如，本公开至少一实施例提供的压阻检测基板中，所述采集电路包括：开关器件和电容；其中，所述开关器件的一端与所述放大器的输出端相连，所述开关器件的另一端作为输出端通过所述电容接地。
例如，本公开至少一实施例提供的压阻检测基板中，多个所述采集电路与一个所述模数转换器相连，与同一所述模数转换器相连的各所述采集电路中的所述开关器件分时导通。
例如，本公开至少一实施例提供的压阻检测基板中，一个所述采集电路与一个所述模数转换器相连。
例如，本公开至少一实施例提供的压阻检测基板中，所述压感电阻的第一端和第二端在未受压力时为断开状态，所述压力电阻的电阻值随着所受压力的变大而减小。
本公开至少一实施例提供一种显示面板，包括上述压阻检测电路或者上述压阻检测基板，以及设置于所述衬底基板的显示区的多个像素电路。
例如，本公开至少一实施例提供的显示面板中，所述衬底基板的显示区 和检测区为同一区域；所述像素电路包括：开关晶体管、驱动晶体管和有机发光二极管；所述有机发光二极管设置于所述开关晶体管和所述驱动晶体管之上；所述开关晶体管的源漏极、所述驱动晶体管的源漏极、所述第一晶体管的源漏极和所述第二晶体管的源漏极同层设置于源漏金属层；所述开关晶体管的有源层、所述驱动晶体管的有源层、所述第一晶体管的有源层和所述第二晶体管的有源层同层设置于半导体层；所述源漏极金属层设置于所述半导体层与所述有机发光二极管之间。
例如，本公开至少一实施例提供的显示面板中，所述固定电阻和所述压感电阻设置于所述衬底基板与所述半导体层之间；所述显示面板还包括：与各所述固定电阻的第一端一一对应连接的多个第一电极，各所述第一电极作为所述第一电压信号端；与各所述压感电阻的第二端连接的接地电极；分别与各所述固定电阻的第二端和各所述压感电阻的第一端一一对应连接的多个第二电极，各所述第二电极作为第一节点。
例如，本公开至少一实施例提供的显示面板中，所述接地电极、所述压感电阻、所述第二电极、所述固定电阻和所述第一电极在所述衬底基板上依次层叠设置。
例如，本公开至少一实施例提供的显示面板中，所述开关晶体管的栅极和所述驱动晶体管的栅极同层设置于栅极金属层，所述栅极金属层设置于所述源漏金属层和所述半导体层之间；所述第一电极设置于所述半导体层与所述固定电阻之间；各所述第二电极部分与所述固定电阻交叠，部分与所述第一晶体管的有源层交叠作为所述第一晶体管的栅极。
例如，本公开至少一实施例提供的显示面板中，各所述第一晶体管还包括设置于所述栅极金属层中的浮空栅极。
例如，本公开至少一实施例提供的显示面板中，所述开关晶体管的栅极、所述驱动晶体管的栅极、所述第一晶体管的栅极和第二晶体管的栅极同层设置于栅极金属层，所述栅极金属层设置于所述半导体层与所述第二电极之间；所述固定电阻设置于所述栅极金属层与所述第二电极之间；各所述第二电极部分与所述固定电阻交叠，部分与所述第一晶体管的栅极交叠且通过过孔连接。
例如，本公开至少一实施例提供的显示面板中，各所述第一电极设置于所述源漏金属层中，或设置于所述栅极金属层中。
本公开至少一实施例提供一种显示装置，包括上述显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种压阻阵列式传感器的结构示意图；
图2为一种压阻检测电路的电路结构示意图；
图3为本公开一实施例提供的压阻检测电路的结构示意图；
图4为本公开一实施例提供的压阻检测基板的结构示意图；
图5为本公开一实施例提供的压阻检测基板的电路结构示意图；
图6为本公开一实施例提供的压阻检测基板的时序图；
图7为本公开一实施例提供的显示面板的平面结构示意图；
图8为本公开一实施例提供的显示面板中像素电路的电路示意图；
图9为本公开一实施例提供的显示面板的截面结构示意图；
图10为本公开另一实施例提供的显示面板的截面结构示意图；
图11为本公开再一实施例提供的显示面板的截面结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、 “左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种压阻阵列式传感器的结构示意图。如图1所示，该压阻阵列式传感器包括栅极驱动电路(Gate Driver)、模拟电路01(Analog Circuit)以及多个压阻检测电路。多个压阻检测电路设置在检测区，并且呈阵列排布；栅极驱动电路设置在非检测区以对检测区的多条扫描信号线进行逐行扫描；模拟电路设置在非检测区，通过多路分配器MUX对检测区的多条读取信号线执行讯号转换及读取。
图2为一种压阻检测电路的示意图。如图2所示，该压阻检测电路由一个压阻传感器P R、一个选择开关TFT和一个电阻式电压放大器组成；压阻传感器P R的电阻为R X，压阻检测电路的输出V OU的电压为R F/R X×V B，因此，可以通过检测输出V OU的变化来得到压阻的变化。
发明人在研究中发现，由于上述压阻检测电路中的压阻传感器P R是连接到电阻式电压放大器后进行检测输出，因此压阻检测电路属于常开状态，进而电流经常漏出，在操作时例如会产生N×V B/R X的漏电流，其中N为压阻检测电路列的数目，导致压阻检测过程中漏电流较大，不利于最后的检测结果精度。并且，由于上述压阻检测电路中的选择开关TFT、走线电阻和压阻传感器P R为串联关系，而选择开关TFT的电阻与器件本身特性有关，而走线电阻和走线的长度有关，因此测到的输出就会不稳定，有可能造成最后的检测结果出现误差。
本公开至少一实施例提供一种压阻检测电路，包括第一晶体管、第二晶体管、固定电阻和压感电阻；固定电阻的第一端与第一电压信号端相连，第二端与第一节点相连；压感电阻的第一端与第一节点相连，第二端接地；第一晶体管的栅极与第一节点相连，源极与第二电压信号端相连，漏极与第二晶体管的源极相连；第二晶体管的栅极与扫描信号线相连，漏极与读取信号线相连。压阻检测电路在对压感进行采集时，可以通过扫描信号线使第二晶体管处于导通状态，这时第一节点的电位会控制第一电压信号端流经第一晶体管的电压大小，以控制传输到与第二晶体管的漏极连接的读取信号线的电压信号大小，通过判断读取信号线输出的电压信号大小可以确定出压阻检测电路的压感情况，并且，通过确定在触控之前和触控之后读取信号线读取的电压信号变化，可以去除第一晶体管阈值电压对读取出的电压信号的影响， 从而可以提高检测精度。并且，仅在采集检测时开启第二晶体管，使压阻检测电路为主动式检测，不易受到漏电流的影响，可以提高压感检测的灵敏度。
下面结合附图，对本公开实施例提供的压阻检测电路、压阻检测基板、显示面板及显示装置的具体实施方式进行详细地说明。
附图中各层薄膜厚度和区域大小形状不反映阵列基板或彩膜基板的真实比例，目的只是示意说明本公开内容。
本公开一实施例提供一种压阻检测电路，如图3所示，压阻检测电路200包括T1、第二晶体管T2、固定电阻R B和压感电阻P R；固定电阻R B的第一端与第一电压信号端V TOP相连，第二端与第一节点X相连；压感电阻P R的第一端与第一节点X相连，第二端接地；第一晶体管T1的栅极与第一节点X相连，源极与第二电压信号端V DD相连，漏极与第二晶体管T2的源极相连；第二晶体管T2的栅极与扫描信号线SEL相连，漏极与读取信号线Readline相连。
例如，在本实施例提供的压阻检测基板中，在对压阻检测电路200受到的压感进行采集时，通过与第二晶体管T2的栅极连接的扫描信号线SEL，使第二晶体管T2处于导通状态，这时与第一晶体管T1的栅极连接的第一节点X的电位会控制第一电压信号端V DD流经第一晶体管T1的电压大小，以控制传输到与第二晶体管T2的漏极连接的读取信号线Readline的电压信号大小。通过判断读取信号线Readline输出的电压信号大小可以确定出压阻检测电路200的压感情况。
例如，结合如图6所示的时序图，对本公开实施例提供的压阻检测基板的工作时序进行详细的说明。在进行触控压感检测之前(non-touch)，即在未收压力的初始状态时，先对压阻检测电路200进行信号采集。由于压感电阻P R按压前为开态，因此，第一晶体管T1的栅极电压即第一节点X的电压为第一电压信号端V TOP的电压值，由于第一晶体管T1阈值电压V TH的存在，当扫描信号线SEL 1打开时，第二晶体管T2处于导通状态，读取信号线Readline采集到的电压信号为V TOP-V TH，即读取信号线Readline会将第一晶体管T1的阈值电压采集下来。当进行压控检测(touch)时，压阻检测电路200中的压感电阻P R经过按压电阻产生了变化变为R R，因此对第一节点X产生了分压，通过计算可以得到第一节点X的电压变为V TOP×R R/(R B+R R)，由于第一晶体管T1阈值电压V TH的存在，当扫描信号线SEL 1打开时，第 二晶体管T2处于导通状态，读取信号线Readline采集到的电压信号为V TOP×R R/(R B+R R)-V TH。读取信号线Readline两次采集到的电压信号之差为V TOP×R B/(R B+R R)，去除了第一晶体管T1阈值电压的影响，得到的电压之差为仅受到压力变化带来的压感电阻P R的电阻值的影响。因此，通过电压之差的变化可以推得压感的变化，并且，检测得到电压之差排出了第一晶体管T1阈值电压的影响，可以提高检测精度，且仅在采集检测时开启第二晶体管T2，使压阻检测电路200为主动式检测，不易受到漏电流的影响，可以提高压感检测的灵敏度。
例如，本实施中，压感电阻P R可以配置为压感电阻P R的第一端和第二端在未受压力时为断开状态，而压力电阻P R的第一端和第二端在受到压力时变为导通状态，并且，可以通过选择压力电阻P R的材料，使压力电阻P R的电阻值随着所受压力的变大而减小。即压力越大，压力电阻P R的电阻值越小，这样第一节点X的电压越大，从读取信号线Readline输出的电压信号也就越小，从而与初始状态即未受压力时的读取信号线Readline输出的初始电压信号之差越大，从而感知压感变化越大。
本公开一实施例提供的一种压阻检测基板，如图4所示，该压阻检测基板包括：衬底基板100，设置于衬底基板100的检测区A的多个压阻检测电路200，多条读取信号线Readline和多条扫描信号线SEL。例如，如图5所示，各压阻检测电路200包括第一晶体管T1、第二晶体管T2、固定电阻R B和压感电阻P R。例如，固定电阻R B的第一端与第一电压信号端V TOP相连，第二端与第一节点X相连；压感电阻P R的第一端与第一节点X相连，第二端接地；第一晶体管T1的栅极与第一节点X相连，源极与第二电压信号端V DD相连，漏极与第二晶体管T2的源极相连；第二晶体管T2的栅极与扫描信号线SEL相连，漏极与读取信号线Readline相连。
例如，在本实施例提供的压阻检测基板中，在对某个压阻检测电路200处的压感进行采集时，通过与第二晶体管T2的栅极连接的扫描信号线SEL，使第二晶体管T2处于导通状态，这时与第一晶体管T1的栅极连接的第一节点X的电位会控制第一电压信号端V DD流经第一晶体管T1的电压大小，以控制传输到与第二晶体管T2的漏极连接的读取信号线Readline的电压信号大小。通过判断读取信号线Readline输出的电压信号大小可以确定出压阻检测电路200的压感情况。
例如，通过各压阻检测电路200中设置的第二晶体管T2可以使一条读取信号线Readline分时读取多个压阻检测电路200的压感信号。
例如，结合如图6所示的时序图，对本实施例提供的压阻检测基板的工作时序进行详细的说明。当进行触控压感检测之前(non-touch)，即在未收压力的初始状态时，先对压阻检测基板中的各压阻检测电路200进行信号采集。以其中一个压阻检测电路200为例，由于压感电阻P R按压前为开态，因此，第一晶体管T1的栅极电压即第一节点X的电压为第一电压信号端V TOP的电压值，由于第一晶体管T1阈值电压V TH的存在，当扫描信号线SEL1打开时，第二晶体管T2处于导通状态，读取信号线Readline采集到的电压信号为V TOP-V TH，即读取信号线Readline会将第一晶体管T1的阈值电压采集下来。当进行压控检测(touch)时，压阻检测电路200中的压感电阻P R经过按压电阻产生了变化变为R R，因此对第一节点X产生了分压，通过计算可以得到第一节点X的电压变为V TOP×R R/(R B+R R)，由于第一晶体管T1阈值电压V TH的存在，当扫描信号线SEL 1打开时，第二晶体管T2处于导通状态，读取信号线Readline采集到的电压信号为V TOP×R R/(R B+R R)-V TH。读取信号线Readline两次采集到的电压信号之差为V TOP×R B/(R B+R R)，去除了第一晶体管T1阈值电压的影响，得到的电压之差为仅受到压力变化带来的压感电阻P R的电阻值的影响。因此，通过电压之差的变化可以推得压感的变化，并且，检测得到电压之差排出了第一晶体管T1阈值电压的影响，可以提高检测精度，且仅在采集检测时开启第二晶体管T2，使压阻检测电路200为主动式检测，不易受到漏电流的影响，可以提高压感检测的灵敏度。
例如，在本实施例提供的上述压阻检测基板中，压感电阻P R的第一端和第二端在未受压力时为断开状态，而压力电阻P R的第一端和第二端在受到压力时变为导通状态，并且，可以通过选择压力电阻P R的材料，使压力电阻P R的电阻值随着所受压力的变大而减小。即压力越大，压力电阻P R的电阻值越小，这样第一节点X的电压越大，从读取信号线Readline输出的电压信号也就越小，从而与初始状态即未受压力时的读取信号线Readline输出的初始电压信号之差越大，从而感知压感变化越大。
例如，在本实施例提供的压阻检测基板中，各压阻检测电路例如可以呈阵列排布，以提高检测区的有效检测面积并且降低布线的复杂程度，如图4所示，多个压阻检测电路200呈阵列排布；此时，每条读取信号线Readline 和每条扫描信号线SEL可以连接多个压阻检测电路200。例如，每列各压阻检测电路200可以与同一条读取信号线Readline相连，每行各压阻检测电路200可以与同一条扫描信号线SEL相连；或者，每行各压阻检测电路200可以与同一条读取信号线Readline相连，每列各压阻检测电路200可以与同一条扫描信号线SEL相连，这样可以降低读取信号线Readline和扫描信号线SEL的布线数量。此时，例如可以通过逐行扫描的方式，采集各读取信号线Readline的电压信号，以确定各压阻检测电路200的压感变化；或者，可以通过逐列扫描的方式，采集各读取信号线Readline的电压信号，以确定各压阻检测电路200的压感变化。
例如，如图5所示，本实施例提供的压阻检测基板还可以包括：设置于非检测区的恒流源I B、放大器300和模数转换器ADC。例如，在一个示例中，压阻检测基板还可以包括连接在放大器300和模数转换器ADC之间的采集电路400。例如，当各压阻检测电路200输出的电压信号较小时，上述电路结构可以保证各条读取信号线Readline读取的电压信号可以被有效地检测。
例如，每条读取信号线Readline的一端与一一对应的恒流源I B相连，且每条读取信号线Readline的一端与一一对应的放大器300的输入端相连。放大器300负责将读取信号线Readline输出的电压信号V OUT进行A倍的放大，以保证在按压带来的电压变化可以被有效地识别。
例如，放大器300的输出端与采集电路400的输入端相连。采集电路400负责将经过放大器300放大A倍的电压信号AV OUT输出给后端的模数转换器ADC。
例如，采集电路400的输出端与模数转换器ADC的输入端相连。模数转换器ADC负责将接收到的模拟电压信号转换为数字信号D OUT后进行输出。
例如，在本实施例提供的压阻检测基板中，如图5所示，采集电路400可以包括开关器件SH和电容Cs。例如，开关器件SH的一端与放大器300的输出端相连，开关器件SH的另一端作为输出端通过电容C S接地。例如，采集电路400可以在开关器件SH处于导通状态时，将经过放大器300放大A倍的电压信号AV OUT输出给后端的模数转换器ADC；在开关器件SH处于断开状态时，使放大器300和模数转换器ADC处于断开状态。例如，结合 如图6所示的时序图，开关器件SH在导通时模数转换器ADC会输出相应的数值，通过将压控检测(touch)时输出的D2与触控压感检测之前(non-touch)输出的D1相减后就可得到第一节点的电压变化，从而判断出是否存在压控。
例如，在本实施例提供的压阻检测基板中，可以将多个采集电路400与一个模数转换器ADC相连，此时可以将与同一模数转换器ADC相连的各采集电路400中的开关器件SH配置为分时导通，实现一个模数转换器ADC分时输出多条读取信号线Readline的电压信号，从而减少模数转换器ADC的数量，节省成本。
例如，在本实施例提供的压阻检测基板中，也可以将一个采集电路400与一个模数转换器ADC相连，例如，当压阻检测基板中的读取信号线Readline的数量不多时，可以将一个采集电路400与一个模数转换器ADC相连。
本公开实施例还提供了一种显示面板，包括：本公开实施例提供的上述压阻检测或者压阻检测基板，以及设置于衬底基板的显示区的多个像素电路。
例如，本公开实施例提供的显示面板可以同时集成压阻检测和显示的功能。本实施例中，例如可以根据实际需要设置压阻检测的检测区。例如可以根据需要在某个非显示区的局部区域设置为压阻检测的检测区，以实现诸如压感触控按钮的功能，也可以在显示区内设置检测区，实现在显示的同时利用压阻检测实现触控功能，本实施例对此不做限定。
例如，在本实施例提供的显示面板中，如图7所示，可以将衬底基板100的显示区B和检测区A设置为同一区域，即在同一区域内实现触控和显示功能。例如，可以在同一区域内形成用于实现显示的像素电路500和用于实现压感触控的压阻检测电路200。例如，可以将压阻检测电路200设置于各像素电路500之间，从而压阻检测电路200不会影响到像素电路500的正常显示。例如，压阻检测电路200的数量不大于像素电路500的数量。
例如，在本实施例提供的显示面板中，如图8所示，像素电路500可以包括开关晶体管501、驱动晶体管502和有机发光二极管503。例如，像素电路500可以包括多个开关晶体管501和驱动晶体管502，本实施例对开关晶体管501和驱动晶体管502的数量不做限定。例如，图8示出了一种像素 电路500的结构，在实际应用时例如可以根据需要设置多个开关晶体管501和驱动晶体管502，以实现阈值电压补偿的功能。
图9至图11为本发明一些实施例提供的显示面板的截面结构示意图。例如，有机发光二极管503可以设置于开关晶体管501和驱动晶体管502之上。有机发光二极管503至少包括层叠设置的阳极5031、发光层5032和阴极5033，例如阴极5033可以设置为一整层。在一些实施例中，有机发光二极管503例如可以采用底发射型，即有机发光二极管503的发光从阴极5033出射，被阳极5031反射。
需要注意的是，为了方便示意，图9至图11示出的显示面板的截面结构示意图中并未示出开关晶体管501和第二晶体管T2，这两种晶体管的结构可以参见驱动晶体管502。
例如，如图9至图11所示，可以将开关晶体管501的源漏极、驱动晶体管502的源漏极、第一晶体管T1的源漏极和第二晶体管T2的源漏极同层设置于源漏金属层600。例如，可以将开关晶体管501的有源层、驱动晶体管502的有源层、第一晶体管T1的有源层和第二晶体管T2的有源层同层设置于半导体层700，该设置可以节省制作工艺步骤。例如，可以将源漏极金属层600设置于半导体层700与有机发光二极管503之间，即开关晶体管501、驱动晶体管502、第一晶体管T1和第二晶体管T2均设置在有机发光二极管503和衬底基板100之间。
例如，在本实施例提供的显示面板中，压阻检测电路200中的固定电阻R B的第二端和压感电阻P R的第一端通过第一节点X与第一晶体管T1的栅极连接，因此如图9至图11所示，例如可以将固定电阻R B和压感电阻P R设置于衬底基板100与半导体层700之间，即固定电阻R B和压感电阻P R设置于半导体层700之下。
例如，如图9至图11所示，在本实施例提供的显示面板还可以包括与各固定电阻R B的第一端一一对应连接的多个第一电极800，各第一电极800例如可以作为第一电压信号端V TOP，以保证通过第一电压信号端V TOP对固定电阻R B的第一端加载第一电压信号。
例如，如图9至图11所示，在本实施例提供的显示面板还可以包括与各压感电阻P R的第二端连接的接地电极900，以保证压感电阻P R的第二端接地。
例如，如图9至图11所示，在本实施例提供的显示面板还可以包括分别与各固定电阻R B的第二端和各压感电阻P R的第一端一一对应连接的多个第二电极010，各第二电极010例如可以作为第一节点X。
例如，在本实施例提供的显示面板中，可以将固定电阻R B设置于压感电阻P R的下方，也可以将压感电阻P R设置于固定电阻R B的下方，本实施例对固定电阻R B和压感电阻P R具***置关系不做限定。例如，各压感电阻P R可以设置为整层的压敏材料，相应的接地电极900也可以设置为整层的电极，从而起到屏蔽电极的作用。
例如，在本实施例提供的显示面板中，如图9至图11所示，可以在衬底基板100上依次层叠设置接地电极900、压感电阻P R、第二电极010、固定电阻R B和第一电极800。
例如，在本实施例提供的显示面板中，各第二电极010作为第一节点X并和第一晶体管T1的栅极连接，第二电极010设置于固定电阻R B之下，因此也位于半导体层700之下，例如，如图11所示，可以将第一晶体管T1设置为底栅型晶体管，即第一晶体管T1的栅极位于半导体层700之下，从而方便各第二电极010与第一晶体管T1的栅极的连接。
需要说明的是，本实施例不限定开关晶体管501和驱动晶体管502的类型，可以采用顶栅型晶体管，也可以采用底栅型晶体管。
例如，在本实施例提供的显示面板中，当开关晶体管501和驱动晶体管502为顶栅型晶体管时，如图9和图10所示，开关晶体管501的栅极和驱动晶体管502的栅极例如可以同层设置于栅极金属层020，栅极金属层020设置于源漏金属层600和半导体层700之间，此时，第一电极800可以设置于半导体层700与固定电阻R B之间。
例如，各第二电极010可以部分与固定电阻R B交叠，部分与第一晶体管T1的有源层交叠作为第一晶体管T1的栅极，即不单独设置第一晶体管T1的栅极图案，而是直接使用第二电极010的部分作为第一晶体管T1的栅极。
例如，在本实施例提供的显示面板中，当各第一晶体管T1为顶栅型晶体管时，如图10所示，在栅极金属层020中与第一晶体管T1的有源层对应的位置还可以设置浮空栅极021，以遮挡有机发光二极管503的发光对第一晶体管T1的有源层的影响，避免在第一晶体管T1中产生光生漏电流，而影 响第一开关晶体管T1的压阻检测灵敏性。
例如，在本实施例提供的显示面板中，当开关晶体管501和驱动晶体管502为底栅型晶体管时，如图11所示，开关晶体管501的栅极、驱动晶体管502的栅极、第一晶体管T1的栅极和第二晶体管T2的栅极可以同层设置于栅极金属层020，栅极金属层020设置于半导体层700与第二电极010之间。
例如，固定电阻R B设置于栅极金属层020与第二电极010之间；各第二电极010可以部分与固定电阻R B交叠，部分与第一晶体管T1的栅极交叠且通过过孔连接，即第二电极010与第一晶体管T1的栅极为两个不同的膜层。
例如，在本实施例提供的显示面板中，可以将各第一电极800设置于源漏金属层600中，或如图11所示设置于栅极金属层020中，从而节省制作工序，本实施例对此不做限定。
需要注意的是，本实施例不限定第二晶体管T2的类型，第二晶体管T2可以为顶栅型晶体管，也可以为底栅型晶体管。例如，可以将第二晶体管T2的类型设置为与开关晶体管501和驱动晶体管502相同，以节省制作工序。
例如，在本实施例提供的显示面板中，固定电阻R B可以采用电阻较大的导体制作，例如可以氧化铟锡(ITO)等制作，本实施例对此不做限定。
本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板，该显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
本公开实施例提供了压阻检测电路、压阻检测基板、显示面板及显示装置。该压阻检测电路在对压感进行采集时，可以通过扫描信号线使第二晶体管处于导通状态，这时第一节点的电位会控制第一电压信号端流经第一晶体管的电压大小，以控制传输到与第二晶体管的漏极连接的读取信号线的电压信号大小，通过判断读取信号线输出的电压信号大小可以确定出压阻检测电路的压感情况，并且，通过确定在触控之前和触控之后读取信号线读取的电压信号变化，可以去除第一晶体管阈值电压对读取出的电压信号的影响，从而可以提高检测精度。并且，仅在采集检测时开启第二晶体管，使压阻检测电路为主动式检测，不易受到漏电流的影响，可以提高压感检测的灵敏度。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种压阻检测电路，包括：第一晶体管、第二晶体管、固定电阻和压感电阻；
    所述固定电阻的第一端与第一电压信号端相连，第二端与第一节点相连；
    所述压感电阻的第一端与所述第一节点相连，第二端接地；
    所述第一晶体管的栅极与所述第一节点相连，源极与第二电压信号端相连，漏极与所述第二晶体管的源极相连；
    所述第二晶体管的栅极与扫描信号线相连，漏极与读取信号线相连。
  2. 如权利要求1所述的压阻检测电路，其中，所述压感电阻的第一端和第二端在未受压力时为断开状态，所述压力电阻的电阻值随着所受压力的变大而减小。
  3. 一种压阻检测基板，包括：衬底基板，设置于所述衬底基板的检测区的多个压阻检测电路，多条读取信号线和多条扫描信号线；其中，
    各所述压阻检测电路包括：第一晶体管、第二晶体管、固定电阻和压感电阻；
    所述固定电阻的第一端与第一电压信号端相连，第二端与第一节点相连；
    所述压感电阻的第一端与所述第一节点相连，第二端接地；
    所述第一晶体管的栅极与所述第一节点相连，源极与第二电压信号端相连，漏极与所述第二晶体管的源极相连；
    所述第二晶体管的栅极与所述扫描信号线相连，漏极与所述读取信号线相连。
  4. 如权利要求3所述的压阻检测基板，其中，所述压阻检测电路呈阵列排布；
    每列各所述压阻检测电路与同一条所述读取信号线相连，每行各所述压阻检测电路与同一条所述扫描信号线相连；或，
    每行各所述压阻检测电路与同一条所述读取信号线相连，每列各所述压阻检测电路与同一条所述扫描信号线相连。
  5. 如权利要求3或4所述的压阻检测基板，还包括：设置于所述衬底 基板的非检测区的恒流源、放大器和模数转换器；其中，
    每条所述读取信号线的一端与一一对应的所述恒流源相连，且每条所述读取信号线的一端与一一对应的所述放大器的输入端相连；
    所述放大器的输出端与所述模数转换器的输入端相连。
  6. 如权利要求5所述的压阻检测基板，还包括采集电路，其中，
    所述放大器的输出端与所述采集电路的输入端相连；
    所述采集电路的输出端与所述模数转换器的输入端相连。
  7. 如权利要求6所述的压阻检测基板，其中，所述采集电路包括：开关器件和电容；其中，所述开关器件的一端与所述放大器的输出端相连，所述开关器件的另一端作为输出端通过所述电容接地。
  8. 如权利要求6所述的压阻检测基板，其中，多个所述采集电路与一个所述模数转换器相连，与同一所述模数转换器相连的各所述采集电路中的所述开关器件分时导通。
  9. 如权利要求6所述的压阻检测基板，其中，一个所述采集电路与一个所述模数转换器相连。
  10. 如权利要求3-9任一项所述的压阻检测基板，其中，所述压感电阻的第一端和第二端在未受压力时为断开状态，所述压力电阻的电阻值随着所受压力的变大而减小。
  11. 一种显示面板，包括如权利要求3-10任一项所述的压阻检测基板，以及设置于所述衬底基板的显示区的多个像素电路。
  12. 如权利要求11所述的显示面板，其中，所述衬底基板的显示区和检测区为同一区域；
    所述像素电路包括：开关晶体管、驱动晶体管和有机发光二极管；
    所述有机发光二极管设置于所述开关晶体管和所述驱动晶体管之上；
    所述开关晶体管的源漏极、所述驱动晶体管的源漏极、所述第一晶体管的源漏极和所述第二晶体管的源漏极同层设置于源漏金属层；
    所述开关晶体管的有源层、所述驱动晶体管的有源层、所述第一晶体管的有源层和所述第二晶体管的有源层同层设置于半导体层；
    所述源漏极金属层设置于所述半导体层与所述有机发光二极管之间。
  13. 如权利要求12所述的显示面板，其中，所述固定电阻和所述压感电阻设置于所述衬底基板与所述半导体层之间；
    所述显示面板还包括：与各所述固定电阻的第一端一一对应连接的多个第一电极，各所述第一电极作为所述第一电压信号端；
    与各所述压感电阻的第二端连接的接地电极；
    分别与各所述固定电阻的第二端和各所述压感电阻的第一端一一对应连接的多个第二电极，各所述第二电极作为第一节点。
  14. 如权利要求13所述的显示面板，其中，所述接地电极、所述压感电阻、所述第二电极、所述固定电阻和所述第一电极在所述衬底基板上依次层叠设置。
  15. 如权利要求14所述的显示面板，其中，所述开关晶体管的栅极和所述驱动晶体管的栅极同层设置于栅极金属层，所述栅极金属层设置于所述源漏金属层和所述半导体层之间；
    所述第一电极设置于所述半导体层与所述固定电阻之间；
    各所述第二电极部分与所述固定电阻交叠，部分与所述第一晶体管的有源层交叠作为所述第一晶体管的栅极。
  16. 如权利要求15所述的显示面板，其中，各所述第一晶体管还包括设置于所述栅极金属层中的浮空栅极。
  17. 如权利要求14所述的显示面板，其中，所述开关晶体管的栅极、所述驱动晶体管的栅极、所述第一晶体管的栅极和第二晶体管的栅极同层设置于栅极金属层，所述栅极金属层设置于所述半导体层与所述第二电极之间；
    所述固定电阻设置于所述栅极金属层与所述第二电极之间；
    各所述第二电极部分与所述固定电阻交叠，部分与所述第一晶体管的栅极交叠且通过过孔连接。
  18. 如权利要求17所述的显示面板，其中，各所述第一电极设置于所述源漏金属层中，或设置于所述栅极金属层中。
  19. 一种显示装置，包括：如权利要求11-18任一项所述的显示面板。
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