WO2019010953A1 - 一种阵列基板、其制备方法、显示面板及显示装置 - Google Patents

一种阵列基板、其制备方法、显示面板及显示装置 Download PDF

Info

Publication number
WO2019010953A1
WO2019010953A1 PCT/CN2018/073990 CN2018073990W WO2019010953A1 WO 2019010953 A1 WO2019010953 A1 WO 2019010953A1 CN 2018073990 W CN2018073990 W CN 2018073990W WO 2019010953 A1 WO2019010953 A1 WO 2019010953A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
shielding layer
anode
layer
orthographic projection
Prior art date
Application number
PCT/CN2018/073990
Other languages
English (en)
French (fr)
Inventor
王灿
张粲
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/087,002 priority Critical patent/US11211442B2/en
Publication of WO2019010953A1 publication Critical patent/WO2019010953A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, a display panel, and a display device.
  • OLED displays have the advantages of active illumination, wide viewing angle, light weight, small thickness, fast response, high dynamic picture quality, wide temperature range and flexible display. Concerned, and has been applied in display fields such as mobile phones, tablets, and digital cameras.
  • the OLED generally comprises an anode, a light-emitting layer and a cathode which are arranged in a stack.
  • Embodiments of the present disclosure provide an array substrate, a method of fabricating the same, a display panel, and a display device.
  • an array substrate including: a substrate substrate and a plurality of pixels on a side of the substrate substrate; each of the pixels includes an anode; and the array substrate further includes: The anode is provided with a shielding layer; the shielding layer is for shielding an electric field between two adjacent pixels.
  • an orthographic projection of the shielding layer on the substrate substrate and an orthographic projection of a gap between each adjacent pixel on the substrate substrate at least partially intersect Stack.
  • the shielding layer is located on a side of each of the anodes facing the substrate.
  • the shielding layer is disposed in the same layer as each of the anodes and located at a gap between each of the pixels.
  • the shielding layer has a first portion and a second portion, the first portion is located on a side of each of the anodes facing the substrate, and the second portion and each The anode is disposed in the same layer and is located at a gap between each of the pixels.
  • the material of the shielding layer includes a conductive material, and the shielding layer is grounded.
  • an orthographic projection of a gap between the adjacent pixels on the substrate is within an orthographic projection of the shielding layer on the substrate;
  • the shielding layer has a first coupling capacitance between each of the anodes, and a second coupling capacitance between two adjacent anodes; a capacitance value of the first coupling capacitor corresponding to each of the anodes is not less than a corresponding second The capacitance value of the coupling capacitor.
  • the edge of the shielding layer and the anode is in a direction perpendicular to the substrate substrate and the anode adjacent to the anode
  • the opposing areas are equal, and the distance between the shield layer and the anode is no greater than the distance between the anode and its adjacent anode.
  • the shielding layer and the shielding layer are equal, the shielding layer and the shielding layer
  • the facing area of the edge of the anode in a direction perpendicular to the substrate substrate is not less than the facing area between the anode and its adjacent anode.
  • the array substrate further includes: a top electrode located in each of the pixels of the shielding layer facing the substrate substrate, the top electrode and the a first insulating layer between the shielding layers, and a second insulating layer between the shielding layer and each of the anodes;
  • Each of the anodes is electrically connected to a corresponding top electrode through a first via hole penetrating the first insulating layer and the second insulating layer; wherein each of the first via holes is positive on the base substrate Projecting is located in an orthographic projection of the corresponding top electrode on the substrate, and an orthographic projection of each of the first vias on the substrate and a positive of the shield on the substrate The projections have no overlap.
  • the shielding layer is disposed in the same thickness as each of the anodes.
  • the array substrate further includes: a top electrode located in each of the pixels of the shielding layer facing the substrate substrate, and the shielding layer and the a third insulating layer between the top electrodes;
  • Each of the anodes is electrically connected to a corresponding top electrode through a second via hole penetrating the third insulating layer; wherein an orthographic projection of each of the second via holes on the substrate substrate is located at a corresponding top electrode.
  • the conductive material includes a metal material.
  • a display panel comprising any of the above array substrates provided by the embodiments of the present disclosure.
  • a display device comprising the above display panel provided by an embodiment of the present disclosure.
  • a method for fabricating any of the above array substrates including:
  • a shielding layer is formed on the base substrate and an anode located in each of the pixels and insulated from the shielding layer; wherein the shielding layer is for shielding an electric field between two adjacent pixels.
  • the method before the forming a shielding layer on the substrate and the anodes in each of the pixels and insulated from the shielding layer, the method further includes:
  • the forming the shielding layer specifically includes: forming a shielding layer on the substrate substrate on which the first insulating layer is formed;
  • the forming an anode that is located in each pixel and insulated from the shielding layer comprises: forming each of the anodes in each pixel of the base substrate on which the first via is formed, and passing each of the anodes through The first via is electrically connected to the corresponding top electrode.
  • the method before the forming a shielding layer on the substrate and the anodes in each of the pixels and insulated from the shielding layer, the method further includes:
  • each of the second via holes is in the An orthographic projection on the substrate substrate is located in an orthographic projection of the corresponding top electrode on the substrate;
  • Forming a shielding layer on the substrate, and an anode located in each pixel and insulated from the shielding layer specifically includes:
  • each of the anodes passes through a corresponding second via hole and a corresponding top
  • the electrodes are electrically connected; wherein an orthographic projection of each of the second vias on the substrate substrate does not overlap with an orthographic projection of the shield layer on the substrate.
  • the material of the shielding layer formed includes a conductive material, and the shield layer formed is grounded.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 1b is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • 1c is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a top plan view of the array substrate shown in FIG. 1a;
  • FIG. 3 is a flow chart of a preparation method provided by an embodiment of the present disclosure.
  • 5a to 5c are schematic cross-sectional views, respectively, of various steps in accordance with yet another embodiment of the present disclosure.
  • an element or layer when an element or layer is referred to as being “on” another element or layer, it may be directly on the other element or layer, or an element or layer may be present; likewise, when the element or layer is When the other element or layer is "under”, it may be directly under the other element or layer, or there may be at least one intermediate element or layer; when the element or layer is referred to as being between two or two layers It may be a single element or layer between two or two layers, or more than one intermediate element or layer may be present.
  • OLEDs generally include a stacked anode, a light emitting layer, and a cathode.
  • the anodes in each pixel of the OLED display typically have a thickness such that the anodes in the adjacent two pixels have a coupling capacitance between opposing faces that are perpendicular to the direction of the OLED display.
  • the anode in the pixel will have a certain voltage. Due to the small distance between the adjacent two pixels and the coupling effect, the anode in the adjacent pixel has a coupling voltage, resulting in interference.
  • Other pixels emit light, reducing the display effect.
  • the distance between adjacent pixels is smaller, which causes the phenomenon of interference with other pixels to be more noticeable.
  • the array substrate includes: a substrate substrate 100 and a plurality of pixels 110 on a side of the substrate substrate 100; each of the pixels 110 includes an anode 111;
  • the substrate may further include: a shielding layer 120 disposed in insulation with each of the anodes 111; the shielding layer 120 is configured to shield an electric field between the adjacent two pixels 110.
  • the anode in the illuminating pixel may be adjacent to the illuminating pixel when the pixel emits light.
  • the electric field between the anodes in the pixel is shielded. Therefore, the coupling between adjacent pixels can be avoided, so that the anode of the illuminating pixel has a coupling voltage in the anode of the adjacent pixel, thereby eliminating the coupling effect between the anodes of the adjacent two pixels. Illumination interference improves the display.
  • the display panel in the prior art works normally, and one of the adjacent two pixels emits light and the other pixel does not emit light, the pixel that emits light will not be due to the coupling between adjacent pixels.
  • the illuminated pixels are disturbed by the electric field, thereby affecting the display effect.
  • the display panel formed by the array substrate provided by the embodiment of the present disclosure operates normally, the coupling effect between the anodes in the adjacent two pixels can be eliminated by the shielding layer provided, thereby improving the display effect.
  • the shielding layer 120 may be located on a side of each anode 111 facing the substrate substrate 100, and the shielding layer 120 is on the substrate substrate 100.
  • the orthographic projection of the gap S1 between the adjacent pixels 110 on the base substrate 100 at least partially overlaps. Therefore, in the process of preparing a high-resolution display panel, particularly in the process of forming a high-resolution display panel of a small size or a small size, a process for forming an array substrate is required to be small, so that the process difficulty can be reduced.
  • the orthographic projection of the gap between adjacent pixels on the substrate may be within the orthographic projection of the shield on the substrate.
  • the orthographic projection of the shielding layer on the substrate may also be located within the orthographic projection of the gap between adjacent pixels on the substrate.
  • the shielding layer 120 may also be disposed in the same layer as each anode 111 and located at the gap S1 between the pixels 110. In this way, the shielding layer 120 can directly shield the electric field generated between the anodes 111 of the adjacent two pixels 110, thereby improving the shielding effect of the shielding layer 120. It is also possible to reduce the overall thickness of the array substrate.
  • the array substrate may include a shielding layer 120 having a first portion and a second portion.
  • the first portion of the shielding layer 120 may be located on a side of each anode 111 facing the substrate substrate 100, and a gap between the orthographic projection of the shielding layer 120 on the substrate substrate 100 and each adjacent pixel 110 is on the substrate substrate 100.
  • the upper orthographic projections at least partially overlap; the second portion of the shielding layer 120 may be disposed in the same layer as each of the anodes 111 and located at a gap S1 between the respective pixels 110.
  • the array substrate further includes: a light emitting function layer 112 and a cathode stacked on the side of the anode 111 facing away from the base substrate 100. 113.
  • the light-emitting function layer may specifically include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer which are stacked on the anode.
  • the material of the light-emitting layer may be an organic light-emitting material.
  • the light-emitting layer may be a white light-emitting layer.
  • the light-emitting layer may be a monochromatic light-emitting layer, which is not limited herein.
  • the anode when the pixel emits light, generally, the anode generates holes, the cathode generates electrons, and holes and electrons perform combined light emission in the light-emitting layer.
  • the material of the anode may be a transparent single-layer conductive film, for example, may be ITO, IZO, carbon nanotube, graphene, nano gold or nano silver.
  • the material of the anode may also be a transparent composite conductive film, for example, ITO, Ag, and ITO which are laminated, ITO, Al, and ITO stacked, Al and TiN stacked, or laminated Al And MoO x and the like, which are not limited herein.
  • the substrate may be a glass substrate or a flexible substrate.
  • the base substrate may also be a silicon substrate.
  • the silicon substrate may be a polycrystalline silicon substrate, an amorphous silicon substrate, or a single crystal silicon substrate.
  • the base substrate 100 further includes a pixel driving circuit 130 located in each of the pixels 110.
  • the specific structure and the manufacturing process of the pixel driving circuit in the above-mentioned respective substrates are substantially the same as those in the prior art, and can be understood by those skilled in the art, and details are not described herein.
  • the pixel size is usually about 5 ⁇ m, and the distance between the pixels is about 1 ⁇ m or less.
  • the distance between the pixel and the pixel is small, and the solution provided by the embodiment can effectively improve the mutual interference between the pixels and improve the display effect.
  • the shielding layer 120 is located on the side of each anode 111 facing the substrate substrate 100, and the orthographic projection of the shielding layer 120 on the substrate substrate 100 and the phases
  • the orthographic projection of the gap between the adjacent pixels 110 on the base substrate 100 at least partially overlaps will be described as an example.
  • the material of the shielding layer may be a conductive material.
  • the shield is grounded so that the shield has a zero potential to form an electric field with the anode.
  • the conductive material may be a transparent conductive material, and may be, for example, an indium tin oxide (ITO) material, an indium zinc oxide (IZO) material, carbon nanotubes, graphene, nano gold or nano silver.
  • the electrically conductive material may also be a metallic material, such as one or a combination of gold, silver, aluminum, copper, and molybdenum. It should be understood that, in practical applications, the material of the shielding layer may also be other materials having the function of shielding the electric field between two adjacent pixels, which is not limited herein.
  • the array substrate may further include: a top electrode 114 located in each pixel 110 of the shielding layer 120 facing the substrate substrate 100, A first insulating layer 140 between the top electrode 114 and the shielding layer 120, and a second insulating layer 150 between the shielding layer 120 and each of the anodes 111. Further, each anode 111 is electrically connected to the corresponding top electrode 114 through the first via 115 penetrating the first insulating layer 140 and the second insulating layer 150.
  • the orthographic projection of each of the first vias 115 on the substrate 100 is located in the orthographic projection of the corresponding top electrode 114 on the substrate 100, and the orthographic projection of each of the first vias 115 on the substrate 100 There is no overlap with the orthographic projection of the shield layer 120 on the base substrate 100. Since the shield layer 120 is provided, in practical applications, the anode 111 and the top electrode 114 in each pixel 110 need to be electrically connected to transmit an electrical signal of light emission. In order to prevent the shield layer 120 from being electrically connected to the anode 111 and the top electrode 114, an insulating effect is achieved between the top electrode 114 and the shield layer 120 by providing the first insulating layer 140, and the anodes are provided by providing the second insulating layer 150.
  • the first via 115 corresponding to the top electrode 114 is provided to electrically connect the anode 111 to the corresponding top electrode 114 through the corresponding first via 115. And in order to avoid the influence of the shielding layer 120 on the electrical signal transmitted between the anode 111 and the top electrode 114, the first via 115 does not overlap the shielding layer 120 in a direction perpendicular to the substrate substrate 100.
  • the orthographic projection of the shielding layer 120 on the substrate substrate 100 covers the orthographic projection of the edge of each anode 111 on the substrate substrate 100.
  • the first coupling capacitor is disposed between the shielding layer 120 and each of the anodes 111
  • the second coupling capacitor is disposed between the two adjacent anodes 111.
  • the capacitance of the first coupling capacitor corresponding to each anode 111 is not less than the corresponding second coupling capacitor.
  • the value of the capacitor is not less than the corresponding second coupling capacitor.
  • the orthographic projection of the shielding layer 120 on the substrate substrate 100 covers the orthographic projection of the edge of each anode 111 on the substrate substrate 100 such that the edge of the shielding layer 120 and each anode 111 is perpendicular to the lining.
  • the base substrate 100 has a facing area S2 in the direction of the base substrate 100.
  • a first coupling capacitance is formed between the shield layer 120 and the anode 111 in the facing region S2, and the shielding layer 120 and the edge of each anode 111 are positive in the facing region S2 in the direction perpendicular to the substrate substrate 100.
  • the adjacent two anodes 111 also have a facing area between the cross-sectional areas in the direction perpendicular to the base substrate 100, a second coupling capacitance is formed between the two anodes in the facing area, and The adjacent two anodes 111 also have a facing area in a facing area in a direction perpendicular to the base substrate 100.
  • the capacitance value of the first coupling capacitor corresponding to each anode is greater than the capacitance value of the corresponding second coupling capacitor, since the shielding layer is directly grounded, when a certain pixel emits light and the anode has a voltage, the light is emitted.
  • the anode in the pixel preferentially generates an electric field through a coupling capacitor having a large capacitance value. That is, the anode in the illuminating pixel preferentially generates an electric field through the first coupling capacitor, so that the anode in the illuminating pixel can be prevented from generating an electric field through the second coupling capacitor. Furthermore, it is possible to prevent the anode in the luminescent pixel from interfering with the illumination of other adjacent pixels due to the coupling action, thereby improving the display effect.
  • the capacitance value of the first coupling capacitor corresponding to each anode is equal to the capacitance value of the corresponding second coupling capacitor, since the anode is generally provided with an illuminating functional layer for illuminating, the load on the anode is large, and the shielding layer Directly grounded and without additional load. Therefore, when a certain pixel emits light and the anode has a voltage, the anode in the illuminating pixel preferentially generates an electric field through the first coupling capacitor, so that the anode in the illuminating pixel can be prevented from generating an electric field through the second coupling capacitor. Furthermore, it is possible to prevent the anode in the luminescent pixel from interfering with the illumination of other adjacent pixels due to the coupling action, thereby improving the display effect.
  • the capacitance value C 0 of the capacitor satisfies the formula: Where ⁇ is the dielectric constant of the medium between the two electrodes of the capacitor, S is the facing area of the two electrodes of the capacitor, k is the electrostatic force constant, and d is the distance between the two electrodes of the capacitor.
  • capacitance value C 0 is found satisfied, by adjusting the alignment area of the capacitance between the two electrodes or adjusting the distance between the two electrodes of the capacitor to adjust the size of the capacitance value C 0 is the capacitance.
  • shielding may be performed for each anode.
  • the facing area of the edge of the layer and the anode is equal to the facing area between the anode and the anode adjacent thereto, and the distance between the shield layer and the anode is not greater than the distance between the anode and the anode adjacent thereto.
  • the distance between the shielding layer and the anode and the distance between the anode and the anode adjacent thereto may be made equal, and the facing area of the shielding layer and the edge of the anode is not less than the anode adjacent thereto.
  • the area between the anodes This allows you to first determine a variable (the area between the two electrodes of the capacitor or the distance between the two electrodes of the capacitor), and then adjust the other variable (the distance between the two electrodes of the capacitor or the two of the capacitor)
  • the facing area between the electrodes can achieve the effect that the capacitance value of the first coupling capacitor corresponding to each anode is not less than the capacitance value of the corresponding second coupling capacitor.
  • each anode by simultaneously adjusting the distance between the shield layer and the anode and the distance between the anode and the anode adjacent thereto, and adjusting the facing area of the shield layer and the edge of the anode and the anode and phase thereof
  • the size of the facing area between the adjacent anodes is such that the capacitance value of the first coupling capacitor corresponding to each anode is not less than the capacitance value of the corresponding second coupling capacitor, which is not limited herein.
  • the material of the first insulating layer and the material of the second insulating layer may be inorganic materials, for example, SiN x , SiO 2 , or the like.
  • the material of the first insulating layer and the material of the second insulating layer may be an organic material, for example, an organic resin-based material or the like, which is not limited herein.
  • the top electrode is used to electrically connect with the pixel driving circuit in the pixel, so that the pixel driving circuit inputs a current to the anode through the top electrode, thereby driving the light emitting layer.
  • the material of the top electrode may be a conductive material.
  • the shielding layer may be a grid-like integrated structure.
  • the shielding layer can be formed by one patterning process, which can simplify the preparation process and reduce the production cost.
  • the shielding layer may also be a plurality of strip structures electrically connected, which is not limited herein.
  • the array substrate may further include a second portion of the shielding layer disposed in the same layer as each anode and located at a gap between the respective pixels.
  • the shielding layer has a first portion and a second portion, as shown in FIG. 1c, wherein the first portion of the shielding layer 120 is located on a side of each anode 111 facing the substrate substrate 100, and the shielding layer 120 is positive on the substrate substrate 100.
  • the remaining film layers in the array substrate shown in FIG. 1c are all referred to the embodiment of FIG. 1a above, and are not described herein.
  • the shielding layer 120 is disposed in the same layer as each anode 111 and is located at a gap S1 between the pixels 110 as an example.
  • the material of the shielding layer may be a conductive material, and the shielding layer is grounded so that the shielding layer has a zero potential.
  • the conductive material may be a transparent conductive material, and may be, for example, an indium tin oxide (ITO) material, an indium zinc oxide (IZO) material, carbon nanotubes, graphene, nano gold or nano silver.
  • the electrically conductive material may also be a metallic material, such as one or a combination of gold, silver, aluminum, copper, and molybdenum. It should be understood that, in practical applications, the material of the shielding layer may also be other materials having the function of shielding the electric field between two adjacent pixels, which is not limited herein.
  • the shielding layer 120 and each of the anodes 111 may be disposed in the same layer and at a gap S1 between the pixels 110.
  • the electric field between the adjacent two anodes 111 can be completely shielded by the grounded shielding layer 120, so that the electric field can be completely isolated by the coupling between the two adjacent anodes, thereby avoiding the anode in the illuminating pixel.
  • the coupling effect is enhanced by the coupling effect on the illumination of other adjacent pixels.
  • the shielding layer may be a grid-like integrated structure.
  • the shielding layer can be formed by one patterning process, which can simplify the preparation process and reduce the production cost.
  • the shielding layer may also be a plurality of strip structures electrically connected, which is not limited herein.
  • the shielding layer may be made the same as each anode material.
  • the shielding layer and each anode can be formed by one patterning process. Therefore, the process of preparing the shielding layer is not added, the preparation process can be simplified, and the production cost can be saved.
  • the array substrate further includes: a top electrode 114 located in each pixel 110 of the shielding layer 120 facing the substrate substrate 100, and A third insulating layer 160 is located between the shield layer 120 and the top electrode 114.
  • Each of the anodes 111 is electrically connected to the corresponding top electrode 114 through a second via 116 penetrating through the third insulating layer 160.
  • the orthographic projection of each of the second via holes 116 on the substrate substrate 100 is located in the orthographic projection of the corresponding top electrode 114 on the substrate substrate 100, and the orthographic projection of each of the second via holes 116 on the substrate substrate 100 There is no overlap with the orthographic projection of the shield layer 120 on the base substrate 100. Since the shield layer 120 is provided, in practical applications, the anode 111 and the top electrode 114 in each pixel 110 need to be electrically connected to transmit an electrical signal of light emission.
  • an insulating effect is achieved between the top electrode 114 and the shield layer 120 by providing the third insulating layer 160.
  • a second via 116 corresponding to the top electrode 114 is provided to electrically connect the anode 111 to the corresponding top electrode 114 through the corresponding second via 116.
  • the second via 116 does not overlap the shielding layer 120 in a direction perpendicular to the substrate substrate 100.
  • the third insulating layer may be an inorganic material, for example, SiN x , SiO 2 , or the like.
  • the third insulating layer may be an organic material, for example, an organic resin-based material or the like, which is not limited herein.
  • the top electrode is used to electrically connect with the pixel driving circuit in the pixel, so that the pixel driving circuit inputs a current to the anode through the top electrode, thereby driving the light emitting layer.
  • the material of the top electrode may be a conductive material.
  • the array substrate may further include: a fourth insulating layer located on a side of the shielding layer facing away from the substrate substrate, and the fourth insulating layer is positive on the substrate substrate.
  • the projection covers the orthographic projection of the shielding layer on the base substrate, and the orthographic projection of the fourth insulating layer on the substrate substrate does not overlap with the orthographic projection of each anode on the substrate substrate.
  • the arrangement is such that the shielding layer disposed in the same layer has better insulation effect between the anodes and the fourth insulating layer is prevented from affecting the anode to input holes into the light-emitting functional layer.
  • the embodiment of the present disclosure further provides a method for preparing any one of the above array substrates provided by the embodiments of the present disclosure. As shown in FIG. 3, the steps of the preparation method may include:
  • S301 Form a shielding layer on the base substrate and an anode located in each pixel and insulated from the shielding layer; wherein the shielding layer is used to shield an electric field between adjacent two pixels.
  • the method further includes: forming the substrate on the anode A light-emitting functional layer and a cathode are sequentially formed on the substrate.
  • the shielding layer in the prepared array substrate is located on a side of each anode facing the substrate, and the orthographic projection of the shielding layer on the substrate substrate and the orthographic projection of the gap between adjacent pixels on the substrate substrate are at least
  • the method may further include:
  • Forming the shielding layer may specifically include: forming a shielding layer on the substrate formed with the first insulating layer;
  • the method further includes: forming a second insulating layer on the substrate substrate on which the shielding layer is formed, and penetrating the first insulating layer and the second layer Each of the first vias of the insulating layer; wherein an orthographic projection of each of the first vias on the substrate is located in an orthographic projection of the corresponding top electrode on the substrate, and each of the first vias is on the substrate The orthographic projection and the orthographic projection of the shielding layer on the substrate substrate do not overlap;
  • Forming an anode located in each pixel and insulated from the shielding layer may specifically include: forming each anode in each pixel of the base substrate on which the first via is formed, and passing each anode through the corresponding first via and the corresponding top The electrodes are electrically connected. And when each anode is formed in each pixel of the base substrate on which the first via hole is formed, the method further includes: forming a second layer shielding layer located at a gap between the anodes.
  • the array substrate prepared by the method refer to the embodiment of the above array substrate, and the repeated description is omitted.
  • the shielding layer in the prepared array substrate is disposed in the same layer as each anode and is located at a gap between the pixels.
  • the shielding is formed on the substrate.
  • Forming a shielding layer on the base substrate and an anode located in each pixel and insulated from the shielding layer may specifically include:
  • the method of preparing the shielding layer 120 as shown in FIG. 1a on the array substrate of each anode 111 facing the substrate substrate 100 includes: forming a top electrode 114 in each pixel 110 on the substrate substrate 100, as shown in FIG. Shown in 4a.
  • the top electrode 114 located in each of the pixels 110 is formed on the base substrate 100 by a single patterning process.
  • the base substrate 100 has been formed with the pixel driving circuit 130 located in each pixel 110 in advance, and the formed top electrode 114 is electrically connected to the corresponding pixel driving circuit 130.
  • the method according to this embodiment further includes forming a first insulating layer 140 on the base substrate 100 on which the top electrode 114 is formed, as shown in FIG. 4b.
  • the first insulating layer 140 is formed on the base substrate 100 on which the top electrode 114 is formed by one patterning process.
  • the method step according to this embodiment further includes forming a shield layer 120 on the base substrate 100 on which the first insulating layer 140 is formed, as shown in FIG. 4c.
  • the shield layer 120 is formed on the base substrate 100 on which the first insulating layer 140 is formed by one patterning process.
  • the material of the formed shielding layer 120 may be a conductive material, and the shielding layer 120 is grounded.
  • the conductive material may be a transparent conductive material, and may be, for example, an ITO material, an IZO material, carbon nanotubes, graphene, nano gold or nano silver.
  • the electrically conductive material may also be a metallic material, such as one or a combination of gold, silver, aluminum, copper, and molybdenum.
  • the film thickness of the shield layer 120 formed that is, the thickness in the direction perpendicular to the substrate 100 is about 5 to 100 nm.
  • the method step according to the embodiment further includes forming a second insulating layer 150 and first vias 115 penetrating the first insulating layer 140 and the second insulating layer 150 on the base substrate 100 on which the shielding layer 120 is formed, such as Figure 4d shows.
  • the orthographic projection of each of the first vias 115 on the substrate 100 is located in the orthographic projection of the corresponding top electrode 114 on the substrate 100, and the orthographic projection of each of the first vias 115 on the substrate 100 There is no overlap with the orthographic projection of the shield layer 120 on the base substrate 100.
  • the second insulating layer 150 and the first via holes 115 penetrating the first insulating layer 140 and the second insulating layer 150 are formed on the base substrate 100 on which the shielding layer 120 is formed by using one patterning process.
  • the method step according to this embodiment further includes forming each anode 111 in each of the pixels 110 of the base substrate 100 on which the first via 115 is formed, passing each anode 111 through the corresponding first via 115 and the corresponding top electrode 114 electrical connection, as shown in Figure 4e.
  • each anode 111 is formed in each of the pixels 110 of the base substrate 100 on which the first via 115 is formed by one patterning process.
  • the step may further include forming a second shielding layer at the gap of each anode.
  • the method steps according to this embodiment may also include forming the light-emitting functional layer 112 and the cathode 113 as shown in FIG. 1a.
  • the method of preparing the array substrate disposed in the same layer as the anode 111 as shown in FIG. 1b includes: forming a top electrode 114 in each of the pixels 110 on the base substrate 100; as shown in FIG. 5a .
  • the top electrode 114 located in each of the pixels 110 is formed on the base substrate 100 by a single patterning process.
  • the base substrate 100 has been formed with the pixel driving circuit 130 located in each pixel 110 in advance, and the formed top electrode 114 is electrically connected to the corresponding pixel driving circuit 130.
  • the method step according to the embodiment further includes: forming a third insulating layer 160 on the base substrate 100 on which the top electrode 114 is formed, and each of the second via holes 116 penetrating the third insulating layer 160 in each of the pixels 100, such as Figure 5b shows.
  • the orthographic projection of each of the second via holes 116 on the base substrate 100 is located in the orthographic projection of the corresponding top electrode 114 on the base substrate 100.
  • a third insulating layer 160 and respective second via holes 116 penetrating the third insulating layer 160 in each of the pixels 100 are formed on the base substrate 100 on which the top electrode 114 is formed by using one patterning process.
  • the method step according to the embodiment further includes: forming a shielding layer 120 on the base substrate 100 on which the third insulating layer 160 is formed, and an anode 111 located in each of the pixels 110 and insulated from the shielding layer 120, so that the anodes 111 pass correspondingly
  • the second via 116 is electrically coupled to the corresponding top electrode 114 as shown in Figure 5c.
  • the orthographic projection of each of the second via holes 116 on the substrate substrate 100 does not overlap with the orthographic projection of the shield layer 120 on the substrate substrate 100.
  • the shield layer 120 and the anode 111 located in each of the pixels 110 and insulated from the shield layer 120 are formed on the base substrate 100 on which the third insulating layer 160 is formed by one patterning process.
  • the shielding layer 120 and the anode 111 are made of the same material and have the same thickness. It should be understood that the shielding layer 120 and the anode 111 located in each of the pixels 110 and insulated from the shielding layer 120 may be formed by using two patterning processes respectively, so that the shielding layer 120 is in the same layer and the same thickness as the anode 111.
  • the material of the formed shielding layer may be a conductive material, and the shielding layer is grounded.
  • the conductive material may be a transparent conductive material, and may be, for example, an ITO material, an IZO material, carbon nanotubes, graphene, nano gold or nano silver.
  • the electrically conductive material may also be a metallic material, such as one of gold, silver, aluminum, copper, and molybdenum, or a combination thereof. It should be understood that, in practical applications, the material of the shielding layer may also be other materials having the function of shielding the electric field between two adjacent pixels, which is not limited herein.
  • the method steps according to this embodiment may also include forming the light-emitting functional layer 112 and the cathode 113 as shown in FIG. 1b.
  • the method further includes forming a fourth insulating layer on the substrate substrate on which the shielding layer and the anode are formed by using one patterning process.
  • the orthographic projection of the fourth insulating layer on the substrate substrate covers the orthographic projection of the shielding layer on the substrate, and the orthographic projection of the fourth insulating layer on the substrate and the orthographic projection of each anode on the substrate No overlap.
  • the patterning process may include a photolithography process.
  • the patterning process may include a photolithography process as well as an etching step.
  • other processes for forming various components of a predetermined shape such as printing, inkjet, and the like, may also be included.
  • the photolithography process refers to a process of forming various components by using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, development, and thermal baking.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present disclosure.
  • an embodiment of the present disclosure further provides a display panel, including any of the above array substrates provided by the embodiments of the present disclosure.
  • the principle of the display panel is similar to that of the foregoing array substrate. Therefore, the implementation of the display panel can be referred to the foregoing embodiment of the array substrate, and the repeated description is not repeated herein.
  • the above display panel may be an organic light emitting display panel (OLED display panel) of a large size, a medium size, a small size, and a minute size.
  • the display panel provided by the embodiment of the present disclosure may be a high resolution organic light emitting display panel.
  • the display panel provided by the embodiments of the present disclosure may be applied to a head-mounted video player, a head-mounted home theater, a head-mounted virtual reality simulator, a head-mounted game machine, a pilot helmet system, and a single-armed combat.
  • System infrared night vision, head-mounted medical diagnostic system and other equipment.
  • an embodiment of the present disclosure further provides a display device, including the above display panel provided by an embodiment of the present disclosure.
  • the display device can be: mobile phone, tablet computer, television, display, notebook computer, head-mounted video player, head-mounted home theater, head-mounted virtual reality simulator, head-mounted game machine, pilot helmet system, Any product or component with display function, such as individual combat system, infrared night vision device, and head-mounted medical diagnostic system.
  • Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the disclosure.
  • For the implementation of the display device refer to the embodiment of the above array substrate, and the repeated description is omitted.
  • the array substrate provided by the embodiment of the present disclosure, the preparation method thereof, the display panel, and the display device can be provided when the pixel is illuminated by providing a shielding layer insulated from each anode and capable of shielding an electric field between two adjacent pixels.
  • the electric field between the anode in the luminescent pixel and the anode in its adjacent pixel is shielded. Therefore, the coupling between adjacent pixels can be avoided, so that the anode of the illuminating pixel has a coupling voltage in the anode of the adjacent pixel, thereby eliminating the coupling effect between the anodes of the adjacent two pixels. Illumination interference improves the display.

Abstract

一种阵列基板、其制备方法、显示面板及显示装置，通过设置与各阳极(111)绝缘的并且能够屏蔽相邻两个像素(110)之间的电场的屏蔽层(120)，可以在像素发光时，将该发光像素(110)中的阳极(111)与其相邻的像素中的阳极之间的电场进行屏蔽，从而可以避免由于耦合作用，导致该发光像素(110)的阳极(111)使其相邻的像素中的阳极具有耦合电压，进而可以消除相邻两个像素(110)中的阳极(111)之间的耦合作用对像素发光的干扰，提高显示效果。

Description

一种阵列基板、其制备方法、显示面板及显示装置
本申请要求于2017年7月13日递交的中国专利申请第201710570694.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板、其制备方法、显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示器具有主动发光、宽视角、重量轻、厚度小、响应速度快、动态画面质量高、使用温度范围广及可实现柔性显示等优点，引起了广泛的关注，并在手机、平板电脑、数码相机等显示领域得到了应用。其中，OLED一般包括层叠设置的阳极、发光层以及阴极。
发明内容
本公开实施例提供一种阵列基板、其制备方法、显示面板及显示装置。
根据本公开的第一方面，提供了一种阵列基板，包括：衬底基板以及位于所述衬底基板一侧的多个像素；各所述像素包括阳极；所述阵列基板还包括：与各所述阳极绝缘设置的屏蔽层；所述屏蔽层用于屏蔽相邻两个所述像素之间的电场。
在本公开实施例提供的上述阵列基板中，所述屏蔽层在所述衬底基板上的正投影与各所述相邻像素之间的间隙在所述衬底基板上的正投影至少部分交叠。
在本公开实施例提供的上述阵列基板中，所述屏蔽层位于各所述阳极 面向所述衬底基板的一侧。
在本公开实施例提供的上述阵列基板中，所述屏蔽层与各所述阳极同层设置且位于各所述像素之间的间隙处。
在本公开实施例提供的上述阵列基板中，所述屏蔽层具有第一部分和第二部分，所述第一部分位于各所述阳极面向所述衬底基板的一侧，所述第二部分与各所述阳极同层设置且位于各所述像素之间的间隙处。
在本公开实施例提供的上述阵列基板中，所述屏蔽层的材料包括导电材料，并且所述屏蔽层接地。
在本公开实施例提供的上述阵列基板中，所述相邻像素之间的间隙在所述衬底基板上的正投影在所述屏蔽层在所述衬底基板上的正投影内；
所述屏蔽层与各所述阳极之间具有第一耦合电容，相邻两个阳极之间具有第二耦合电容；每个所述阳极对应的第一耦合电容的电容值不小于对应的第二耦合电容的电容值。
在本公开实施例提供的上述阵列基板中，针对所述阳极，所述屏蔽层与所述阳极的边缘在垂直于所述衬底基板方向上的正对面积和所述阳极与其相邻的阳极之间的正对面积相等，所述屏蔽层与所述阳极之间的距离不大于所述阳极与其相邻的阳极之间的距离。
在本公开实施例提供的上述阵列基板中，针对所述阳极，所述屏蔽层与所述阳极之间的距离和所述阳极与其相邻的阳极之间的距离相等，所述屏蔽层与所述阳极的边缘在垂直于所述衬底基板方向上的正对面积不小于所述阳极与其相邻的阳极之间的正对面积。
在本公开实施例提供的上述阵列基板中，所述阵列基板还包括：位于所述屏蔽层面向所述衬底基板一侧的各所述像素中的顶电极，位于所述顶电极与所述屏蔽层之间的第一绝缘层，以及位于所述屏蔽层与各所述阳极之间的第二绝缘层；
各所述阳极通过贯穿所述第一绝缘层与所述第二绝缘层的第一过孔与对应的顶电极电连接；其中，各所述第一过孔在所述衬底基板上的正投影 位于对应的顶电极在所述衬底基板上的正投影内，且各所述第一过孔在所述衬底基板上的正投影与所述屏蔽层在所述衬底基板上的正投影无交叠。
在本公开实施例提供的上述阵列基板中，所述屏蔽层与各所述阳极同厚度设置。
在本公开实施例提供的上述阵列基板中，所述阵列基板还包括：位于所述屏蔽层面向所述衬底基板一侧的各所述像素中的顶电极，以及位于所述屏蔽层与所述顶电极之间的第三绝缘层；
各所述阳极通过贯穿所述第三绝缘层的第二过孔与对应的顶电极电连接；其中，各所述第二过孔在所述衬底基板上的正投影位于对应的顶电极在所述衬底基板上的正投影内，且各所述第二过孔在所述衬底基板上的正投影与所述屏蔽层在所述衬底基板上的正投影无交叠。
在本公开实施例提供的上述阵列基板中，所述导电材料包括金属材料。
根据本公开的第二方面，还提供了一种显示面板，包括本公开实施例提供的上述任一种阵列基板。
根据本公开的第三方面，还提供了一种显示装置，包括本公开实施例提供的上述显示面板。
根据本公开的第四方面，还提供了一种本公开实施例提供的上述任一种阵列基板的制备方法，包括：
在衬底基板上形成屏蔽层以及位于各像素中且与所述屏蔽层绝缘的阳极；其中，所述屏蔽层用于屏蔽相邻两个所述像素之间的电场。
在本公开实施例提供的上述制备方法中，所述在衬底基板上形成屏蔽层以及位于各像素中且与所述屏蔽层绝缘的阳极之前，还包括：
在衬底基板上形成位于各所述像素中的顶电极；
在形成有所述顶电极的衬底基板上形成第一绝缘层；
所述形成屏蔽层，具体包括：在形成有所述第一绝缘层的衬底基板上形成屏蔽层；
所述在形成屏蔽层之后，且在形成位于各像素中且与所述屏蔽层绝缘 的阳极之前，还包括：在形成有所述屏蔽层的衬底基板上形成第二绝缘层以及贯穿所述第一绝缘层与所述第二绝缘层的各第一过孔；其中，各所述第一过孔在所述衬底基板上的正投影位于对应的顶电极在所述衬底基板上的正投影内，且各所述第一过孔在所述衬底基板上的正投影与所述屏蔽层在所述衬底基板上的正投影无交叠；
所述形成位于各像素中且与所述屏蔽层绝缘的阳极，具体包括：在形成有所述第一过孔的衬底基板的各像素中形成各所述阳极，使各所述阳极通过对应的第一过孔与对应的顶电极电连接。
在本公开实施例提供的上述制备方法中，所述在衬底基板上形成屏蔽层以及位于各像素中且与所述屏蔽层绝缘的阳极之前，还包括：
在衬底基板上形成位于各所述像素中的顶电极；
在形成有所述顶电极的衬底基板上形成第三绝缘层以及位于各所述像素中的贯穿所述第三绝缘层的各第二过孔；其中，各所述第二过孔在所述衬底基板上的正投影位于对应的顶电极在所述衬底基板上的正投影内；
所述在衬底基板上形成屏蔽层以及位于各像素中且与所述屏蔽层绝缘的阳极，具体包括：
在形成有所述第三绝缘层的衬底基板上形成所述屏蔽层以及位于各像素中且与所述屏蔽层绝缘的阳极，使各所述阳极通过对应的第二过孔与对应的顶电极电连接；其中，各所述第二过孔在所述衬底基板上的正投影与所述屏蔽层在所述衬底基板的上正投影无交叠。
在本公开实施例提供的上述制备方法中，形成的所述屏蔽层的材料包括导电材料，且形成的所述屏蔽层接地。
附图说明
图1a为本公开实施例提供的阵列基板的结构示意图；
图1b为本公开实施例提供的阵列基板的结构示意图；
图1c为本公开实施例提供的阵列基板的结构示意图；
图2为图1a所示的阵列基板的俯视图；
图3为本公开实施例提供的制备方法的流程图；
图4a至图4e分别为根据本公开的实施例的各步骤后的剖面结构示意图；
图5a至图5c分别为根据本公开的又一实施的各步骤后的剖面结构示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的阵列基板、其制备方法、显示面板及显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅用于说明和解释本公开，并不用于限定本公开。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本发明中描绘的流程图仅仅是一个例子。在不脱离本发明精神的情况下，可以存在该流程图或其中描述的步骤的很多变型。例如，所述步骤可以以不同的顺序进行，或者可以添加、删除或者修改步骤。这些变型都被认为是所要求保护的方面的一部分。
在本公开的描述中，术语“上”、“之上”、“下”、“之下”、“之间”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。此外，当元件或层被称为在另一元件或层“上”时，它可以直接在该另一元件或层上，或者可以存在中间的元件或层；同样，当元件或层被称为在另一元件或层“下”时，它可以直接在该另一元件或层下，或者可以存在至少一个中间的元件或层；当元件或层被称为在两元件或两层“之间”时，其可以为该两元件或两层之间的唯一的元件或层，或者可以存在一个以上的中间元件或层。
附图中各层薄膜的厚度、大小以及形状均不反映阵列基板的真实比例，目的只是示意说明本公开内容。
OLED一般包括层叠设置的阳极、发光层以及阴极。OLED显示器的各像素中的阳极一般具有一定的厚度，导致相邻的两个像素中的阳极在垂直于OLED显示器方向上的相对面之间具有耦合电容。在像素发光时，该像素中的阳极上会具有一定电压，由于相邻的两个像素之间的距离较小以及耦合的作用，会使其相邻的像素中的阳极具有耦合电压，导致干扰其他像素发光，降低显示效果。尤其是在小尺寸或微尺寸的高分辨率OLED显示器中，相邻像素之间的距离更小，导致干扰其他像素发光的现象更明显。
本公开实施例提供了一种阵列基板，如图1a至图1c所示，阵列基板包括：衬底基板100以及位于衬底基板100一侧的多个像素110；各像素110包括阳极111；阵列基板还可以包括：与各阳极111绝缘设置的屏蔽层120；该屏蔽层120用于屏蔽相邻两个像素110之间的电场。
本公开实施例提供的上述阵列基板，通过设置与各阳极绝缘的并且能够屏蔽相邻两个像素之间的电场的屏蔽层，可以在像素发光时，将该发光像素中的阳极与其相邻的像素中的阳极之间的电场进行屏蔽。从而可以避免由于相邻像素之间的耦合作用，导致该发光像素的阳极使其相邻的像素中的阳极具有耦合电压，进而可以消除相邻两个像素中的阳极之间的耦合作用对像素发光的干扰，提高显示效果。例如，在现有技术中的显示面板正常工作时，且相邻的两个像素中的一个像素发光而另一个像素不发光时，由于相邻像素之间的耦合作用，发光的像素会使不发光的像素受到电场的干扰，从而影响显示效果。而在由本公开实施例提供的阵列基板形成的显示面板正常工作时，通过设置的屏蔽层可以将相邻两个像素中的阳极之间的耦合作用消除，从而提高显示效果。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图1a所示，屏蔽层120可以位于各阳极111面向衬底基板100的一侧，并且屏蔽层120在衬底基板100上的正投影与各相邻像素110之间的间隙S1在衬底基板 100上的正投影至少部分交叠。因此，在高分辨率显示面板的制备过程中，尤其是形成小尺寸或微小尺寸的高分辨率显示面板的工艺中，对形成阵列基板的工艺要求较小，从而可以降低工艺难度。在本公开的实施例中，各相邻像素之间的间隙在衬底基板上的正投影可以在屏蔽层在衬底基板上的正投影内。在本公开的又一实施例中，屏蔽层在衬底基板上的正投影也可以位于各相邻像素之间的间隙在衬底基板上的正投影内。
在本公开实施例中，如图1b所示，屏蔽层120也可以与各阳极111同层设置且位于各像素110之间的间隙S1处。这样可以使屏蔽层120直接对相邻两个像素110中的阳极111之间产生的电场进行屏蔽，提高屏蔽层120的屏蔽效果。并且还可以降低阵列基板的整体厚度。
为了进一步提高屏蔽层屏蔽电场的效果，在具体实施时，在本公开实施例提供的上述阵列基板中，如图1c所示，阵列基板可以包括屏蔽层120，屏蔽层具有第一部分和第二部分。其中屏蔽层120的第一部分可以位于各阳极111面向衬底基板100的一侧，并且屏蔽层120在衬底基板100上的正投影与各相邻像素110之间的间隙S1在衬底基板100上的正投影至少部分交叠；屏蔽层120的第二部分可以与各阳极111同层设置且位于各像素110之间的间隙S1处。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图1a至图1c所示，阵列基板还包括：层叠设置于阳极111背离衬底基板100一侧的发光功能层112与阴极113。其中，发光功能层具体可以包括：层叠设置于阳极上的空穴注入层、空穴传输层、发光层、电子传输层以及电子注入层。并且，发光层的材料可以为有机发光材料。其中，发光层可以为白光发光层，可替换地，发光层也可以为单色光发光层，在此不作限定。并且，如图1a至图1c所示，在像素发光时，一般阳极产生空穴，阴极产生电子，空穴和电子在发光层中进行复合发光。
在具体实施时，在本公开实施例提供的上述阵列基板中，阳极的材料可以采用透明的单层导电薄膜，例如，可以为ITO、IZO、碳纳米管、石墨 烯、纳米金或纳米银等。可替换地，阳极的材料也可以采用透明的复合导电薄膜，例如，可以为层叠设置的ITO、Ag以及ITO，层叠设置的ITO、Al以及ITO，层叠设置的Al与TiN，或者层叠设置的Al与MoO x等，在此不作限定。
在具体实施时，在本公开实施例提供的上述阵列基板中，衬底基板可以为玻璃基板或者柔性基板。可替换地，衬底基板也可以为硅基板。并且，该硅基板可以为多晶硅基板、非晶硅基板或者单晶硅基板。如图1a至图1c所示，衬底基板100还包括位于各像素110中的像素驱动电路130。上述各基板中像素驱动电路的具体结构与制备工艺与现有技术中的基本相同，为本领域技术人员可以理解具有的，在此不作赘述。由于采用硅基板形成的显示面板具有体积小，分辨率高的特点，在该硅基显示面板中，像素尺寸通常在约5um左右，像素之间的距离在约1um以下。像素与像素之间距离较小，通过本实施例提供的方案可以有效改善像素之间相互干扰的问题，改善显示效果。
下面分别对本公开实施例提供的上述阵列基板的结构进行说明。
实施例一、
在图1a所示的本公开实施例提供的上述阵列基板中，以屏蔽层120位于各阳极111面向衬底基板100的一侧，并且屏蔽层120在衬底基板100上的正投影与各相邻像素110之间的间隙在衬底基板100上的正投影至少部分交叠为例进行说明。
在具体实施时，在本公开实施例提供的上述阵列基板中，屏蔽层的材料可以为导电材料。并且屏蔽层接地，以使屏蔽层具有零电势，以便与阳极形成电场。其中，该导电材料可以为透明导电材料，例如可以为氧化铟锡(ITO)材料、氧化铟锌(IZO)材料、碳纳米管、石墨烯、纳米金或纳米银等。可替换地，该导电材料也可以为金属材料，例如可以为金、银、铝、铜和钼中之一或其组合。应当理解，在实际应用中，屏蔽层的材料还可以为其他具有屏蔽相邻两个像素之间的电场的功能的材料，在此不作限 定。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图1a所示，阵列基板还可以包括：位于屏蔽层120面向衬底基板100一侧的各像素110中的顶电极114，位于顶电极114与屏蔽层120之间的第一绝缘层140，以及位于屏蔽层120与各阳极111之间的第二绝缘层150。并且，各阳极111通过贯穿第一绝缘层140与第二绝缘层150的第一过孔115与对应的顶电极114电连接。其中，各第一过孔115在衬底基板100上的正投影位于对应的顶电极114在衬底基板100上的正投影内，且各第一过孔115在衬底基板100上的正投影与屏蔽层120在衬底基板100上的正投影无交叠。由于设置有屏蔽层120，而在实际应用中，各像素110中的阳极111与顶电极114需要进行电连接以传输发光的电信号。为了避免屏蔽层120与阳极111以及顶电极114电连接，因此通过设置第一绝缘层140以使顶电极114与屏蔽层120之间实现绝缘效果，以及通过设置第二绝缘层150以使各阳极111与屏蔽层120之间实现绝缘效果。并且为了使顶电极114与阳极111电连接，通过设置与顶电极114一一对应的第一过孔115，以使阳极111通过对应的第一过孔115与对应的顶电极114实现电连接。并且为了避免屏蔽层120对阳极111与顶电极114之间传输的电信号的影响，使第一过孔115在垂直于衬底基板100的方向上与屏蔽层120无交叠。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图1a所示，屏蔽层120在衬底基板100上的正投影覆盖各阳极111的边缘在衬底基板100上的正投影。
屏蔽层120与各阳极111之间具有第一耦合电容，相邻两个阳极111之间具有第二耦合电容，每个阳极111对应的第一耦合电容的电容值不小于对应的第二耦合电容的电容值。其中，如图2所示，屏蔽层120在衬底基板100上的正投影覆盖各阳极111的边缘在衬底基板100上的正投影，使得屏蔽层120与各阳极111的边缘在垂直于衬底基板100的方向上具有正对区域S2。该正对区域S2中的屏蔽层120与阳极111之间形成了第一 耦合电容，并且使得屏蔽层120与各阳极111的边缘在垂直于衬底基板100的方向上的正对区域S2具有正对面积。另外，相邻两个阳极111在垂直于衬底基板100的方向上的横截面积之间也具有正对区域，该正对区域中的两个阳极之间形成了第二耦合电容，并且使得相邻两个阳极111在垂直于衬底基板100的方向上的正对区域也具有正对面积。
具体地，在每个阳极对应的第一耦合电容的电容值大于对应的第二耦合电容的电容值时，由于屏蔽层直接接地，在某一个像素发光而使其中的阳极具有电压时，该发光像素中的阳极会优先通过电容值大的耦合电容产生电场。即发光像素中的阳极会优先通过第一耦合电容产生电场，从而可以避免发光像素中的阳极通过第二耦合电容产生电场。进而可以避免发光像素中的阳极由于耦合作用而对相邻的其他像素发光产生干扰，提高显示效果。
在每个阳极对应的第一耦合电容的电容值等于对应的第二耦合电容的电容值时，由于阳极上一般还设置有用于发光的发光功能层，因此阳极上的负载较大，而屏蔽层直接接地且无额外负载。从而在某一个像素发光而使其中的阳极具有电压时，该发光像素中的阳极也会优先通过第一耦合电容产生电场，从而可以避免发光像素中的阳极通过第二耦合电容产生电场。进而可以避免发光像素中的阳极由于耦合作用而对相邻的其他像素发光产生干扰，提高显示效果。
电容的电容值C 0满足公式：
Figure PCTCN2018073990-appb-000001
其中ε为电容的两个电极之间的介质的介电常数，S为电容的两个电极的正对面积，k为静电力常量，d为电容的两个电极之间的距离。通过上述电容值C 0满足的公式可知，可以通过调节电容的两个电极之间的正对面积或调节电容的两个电极之间的距离，来调节电容的电容值C 0的大小。为了使每个阳极对应的第一耦合电容的电容值不小于对应的第二耦合电容的电容值，在具体实施时，在本公开 实施例提供的上述阵列基板中，针对各阳极，可以使屏蔽层与阳极的边缘的正对面积和阳极与其相邻的阳极之间的正对面积相等，并使屏蔽层与阳极之间的距离不大于阳极与其相邻的阳极之间的距离。
可替换地，针对各阳极，也可以使屏蔽层与阳极之间的距离和阳极与其相邻的阳极之间的距离相等，并使屏蔽层与阳极的边缘的正对面积不小于阳极与其相邻的阳极之间的正对面积。这样可以先确定一个变量(电容的两个电极之间的正对面积或电容的两个电极之间的距离)，再调整另一个变量(电容的两个电极之间的距离或电容的两个电极之间的正对面积)，这样可以较快的达到使每个阳极对应的第一耦合电容的电容值不小于对应的第二耦合电容的电容值的效果。
应当理解，也可以针对各阳极，通过同时调节屏蔽层与阳极之间的距离和阳极与其相邻的阳极之间的距离的大小，以及调节屏蔽层与阳极的边缘的正对面积和阳极与其相邻的阳极之间的正对面积的大小，来达到使每个阳极对应的第一耦合电容的电容值不小于对应的第二耦合电容的电容值的效果，在此不作限定。
在具体实施时，在本公开实施例提供的上述阵列基板中，第一绝缘层的材料与第二绝缘层的材料可以为无机材料，例如可以为SiN x、SiO 2等。可替换地，第一绝缘层的材料与第二绝缘层的材料也可以为有机材料，例如可以为有机树脂类材料等，在此不作限定。
在具体实施时，在本公开实施例提供的上述阵列基板中，顶电极用于与所在的像素中的像素驱动电路电连接，以使像素驱动电路通过顶电极向阳极输入电流，从而驱动发光层发光。并且，顶电极的材料可以为导电材料。
在具体实施时，在本公开实施例提供的上述阵列基板中，屏蔽层可以为网格状的一体结构。这样可以采用一次构图工艺形成屏蔽层，可以简化制备工艺，降低生产成本。应当理解，屏蔽层也可以为电连接的多个条状结构，在此不作限定。
在本公开的实施例中，为了进一步地屏蔽相邻两个像素之间的电场，阵列基板还可以包括与各阳极同层设置且位于各像素之间的间隙处的屏蔽层的第二部分。这样，屏蔽层具有第一部分和第二部分，如图1c所示，其中屏蔽层120的第一部分位于各阳极111面向衬底基板100的一侧，并且屏蔽层120在衬底基板100上的正投影与各相邻像素110之间的间隙S1在衬底基板100上的正投影至少部分交叠，屏蔽层120的第二部分与各阳极111同层设置且位于各像素110之间的间隙S1处。图1c所示的阵列基板中的其余膜层均参照上述图1a的实施例，在此不作赘述。
实施例二、
在图1b所示的本公开实施例提供的上述阵列基板中，以屏蔽层120与各阳极111同层设置且位于各像素110之间的间隙S1处为例进行说明。
在具体实施时，在本公开实施例提供的上述阵列基板中，屏蔽层的材料可以为导电材料，并且屏蔽层接地，以使屏蔽层具有零电势。其中，该导电材料可以为透明导电材料，例如可以为氧化铟锡(ITO)材料、氧化铟锌(IZO)材料、碳纳米管、石墨烯、纳米金或纳米银等。可替换地，该导电材料也可以为金属材料，例如可以为金、银、铝、铜和钼中之一或其组合。应当理解，在实际应用中，屏蔽层的材料还可以为其他具有屏蔽相邻两个像素之间的电场的功能的材料，在此不作限定。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图1b所示，屏蔽层120与各阳极111可以同层同厚度设置且位于各像素110之间的间隙S1处。这样，可以通过接地的屏蔽层120将相邻的两个阳极111之间的电场完全屏蔽，从而可以完全隔绝相邻的两个阳极之间通过耦合作用形成电场，进而可以避免发光像素中的阳极由于耦合作用对相邻的其他像素发光的干扰，从而提高显示效果。
在具体实施时，在本公开实施例提供的上述阵列基板中，屏蔽层可以为网格状的一体结构。这样可以采用一次构图工艺形成屏蔽层，可以简化制备工艺，降低生产成本。应当理解，屏蔽层也可以为电连接的多个条状 结构，在此不作限定。
进一步地，在具体实施时，在本公开实施例提供的上述阵列基板中，可以使屏蔽层与各阳极材料相同。这样在制备阵列基板时只需要在形成各阳极时改变原有的构图图形，即可通过一次构图工艺形成屏蔽层与各阳极。从而不用增加额外制备屏蔽层的工艺，可以简化制备工艺流程，节省生产成本。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图1b所示，阵列基板还包括：位于屏蔽层120面向衬底基板100一侧的各像素110中的顶电极114，以及位于屏蔽层120与顶电极114之间的第三绝缘层160。
各阳极111通过贯穿第三绝缘层160的第二过孔116与对应的顶电极114电连接。其中，各第二过孔116在衬底基板100上的正投影位于对应的顶电极114在衬底基板100上的正投影内，且各第二过孔116在衬底基板100上的正投影与屏蔽层120在衬底基板100上的正投影无交叠。由于设置有屏蔽层120，而在实际应用中，各像素110中的阳极111与顶电极114需要进行电连接以传输发光的电信号。为了避免屏蔽层120与阳极111以及顶电极114电连接，因此通过设置第三绝缘层160以使顶电极114与屏蔽层120之间实现绝缘效果。并且为了使顶电极114与阳极111电连接，通过设置与顶电极114一一对应的第二过孔116，以使阳极111通过对应的第二过孔116与对应的顶电极114实现电连接。并且为了避免屏蔽层120对阳极111与顶电极114之间传输的电信号的影响，使第二过孔116在垂直于衬底基板100的方向上与屏蔽层120无交叠。
在具体实施时，在本公开实施例提供的上述阵列基板中，第三绝缘层可以为无机材料，例如可以为SiN x、SiO 2等。可替换地，第三绝缘层也可以为有机材料，例如可以为有机树脂类材料等，在此不作限定。
在具体实施时，在本公开实施例提供的上述阵列基板中，顶电极用于与所在的像素中的像素驱动电路电连接，以使像素驱动电路通过顶电极向阳极输入电流，从而驱动发光层发光。并且，顶电极的材料可以为导电材 料。
在具体实施时，在本公开实施例提供的上述阵列基板中，阵列基板还可以包括：位于屏蔽层背离衬底基板一侧的第四绝缘层，并且第四绝缘层在衬底基板上的正投影覆盖屏蔽层在衬底基板上的正投影，且第四绝缘层在衬底基板上的正投影与各阳极在衬底基板上的正投影无交叠。这样设置以使同层设置的屏蔽层与各阳极之间具有较好的绝缘效果，以及避免第四绝缘层影响阳极向发光功能层输入空穴。
基于同一公开构思，本公开实施例还提供了一种本公开实施例提供的上述任一种阵列基板的制备方法，如图3所示，制备方法的步骤可以包括：
S301、在衬底基板上形成屏蔽层以及位于各像素中且与屏蔽层绝缘的阳极；其中，屏蔽层用于屏蔽相邻两个像素之间的电场。
在具体实施时，在本公开实施例提供的上述制备方法中，在衬底基板上形成屏蔽层以及位于各像素中且与屏蔽层绝缘的阳极之后，还可以包括：在形成有阳极的衬底基板上依次形成发光功能层与阴极。
在制备完成的阵列基板中的屏蔽层位于各阳极面向衬底基板的一侧，并且屏蔽层在衬底基板上的正投影与各相邻像素之间的间隙在衬底基板上的正投影至少部分交叠，在具体实施时，在本公开实施例提供的上述制备方法中，在衬底基板上形成屏蔽层以及位于各像素中且与屏蔽层绝缘的阳极之前，还可以包括：
在衬底基板上形成位于各像素中的顶电极；
在形成有顶电极的衬底基板上形成第一绝缘层；
形成屏蔽层，具体可以包括：在形成有第一绝缘层的衬底基板上形成屏蔽层；
在形成屏蔽层之后，且在形成位于各像素中且与屏蔽层绝缘的阳极之前，还可以包括：在形成有屏蔽层的衬底基板上形成第二绝缘层以及贯穿第一绝缘层与第二绝缘层的各第一过孔；其中，各第一过孔在衬底基板上的正投影位于对应的顶电极在衬底基板上的正投影内，且各第一过孔在衬 底基板上的正投影与屏蔽层在衬底基板上的正投影无交叠；
形成位于各像素中且与屏蔽层绝缘的阳极，具体可以包括：在形成有第一过孔的衬底基板的各像素中形成各阳极，使各阳极通过对应的第一过孔与对应的顶电极电连接。并且在形成有第一过孔的衬底基板的各像素中形成各阳极时，还包括：形成位于各所述阳极之间的间隙处的第二层屏蔽层。通过本方法制备完成的阵列基板可以参见上述阵列基板的实施例，重复之处不再赘述。
在制备完成的阵列基板中的屏蔽层与各阳极同层设置且位于各像素之间的间隙处，在具体实施时，在本公开实施例提供的上述制备方法中，在衬底基板上形成屏蔽层以及位于各像素中且与屏蔽层绝缘的阳极之前，还可以包括：
在衬底基板上形成位于各像素中的顶电极；
在形成有顶电极的衬底基板上形成第三绝缘层以及位于各像素中的贯穿第三绝缘层的各第二过孔；其中，各第二过孔在衬底基板上的正投影位于对应的顶电极在衬底基板上的正投影内；
在衬底基板上形成屏蔽层以及位于各像素中且与屏蔽层绝缘的阳极，具体可以包括：
在形成有第三绝缘层的衬底基板上形成屏蔽层以及位于各像素中且与屏蔽层绝缘的阳极，使各阳极通过对应的第二过孔与对应的顶电极电连接；其中，各第二过孔在衬底基板上的正投影与屏蔽层在衬底基板上的正投影无交叠。通过本方法制备完成的阵列基板可以参见上述阵列基板的实施例，重复之处不再赘述。
实施例三、
具体地，制备如图1a所示的屏蔽层120位于各阳极111面向衬底基板100一侧的阵列基板的方法步骤包括：衬底基板100上形成位于各像素110中的顶电极114，如图4a所示。具体地，采用一次构图工艺在衬底基板100上形成位于各像素110中的顶电极114。并且在实际制备时，该衬底基板 100已经提前形成有位于各像素110中的像素驱动电路130，且形成的顶电极114与对应的像素驱动电路130电连接。
根据该实施例的方法还包括：在形成有顶电极114的衬底基板100上形成第一绝缘层140，如图4b所示。具体地，采用一次构图工艺在形成有顶电极114的衬底基板100上形成第一绝缘层140。
根据该实施例的方法步骤还包括：在形成有第一绝缘层140的衬底基板100上形成屏蔽层120，如图4c所示。具体地，采用一次构图工艺在形成有第一绝缘层140的衬底基板100上形成屏蔽层120。其中，形成的屏蔽层120的材料可以为导电材料，并且屏蔽层120接地。其中，该导电材料可以为透明导电材料，例如可以为ITO材料、IZO材料、碳纳米管、石墨烯、纳米金或纳米银等。可替换地，该导电材料也可以为金属材料，例如可以为金、银、铝、铜和钼中之一或其组合。并且形成的屏蔽层120的膜厚，即垂直于衬底基板100方向上的厚度为约5～100nm。
根据该实施例的方法步骤还包括：在形成有屏蔽层120的衬底基板100上形成第二绝缘层150以及贯穿第一绝缘层140与第二绝缘层150的各第一过孔115，如图4d所示。其中，各第一过孔115在衬底基板100上的正投影位于对应的顶电极114在衬底基板100上的正投影内，且各第一过孔115在衬底基板100上的正投影与屏蔽层120在衬底基板100上的正投影无交叠。具体地，采用一次构图工艺在形成有屏蔽层120的衬底基板100上形成第二绝缘层150以及贯穿第一绝缘层140与第二绝缘层150的各第一过孔115。
根据该实施例的方法步骤还包括：在形成有第一过孔115的衬底基板100的各像素110中形成各阳极111，使各阳极111通过对应的第一过孔115与对应的顶电极114电连接，如图4e所示。具体地，采用一次构图工艺在形成有第一过孔115的衬底基板100的各像素110中形成各阳极111。该步骤还可包括：在各阳极的间隙处形成第二层屏蔽层。
根据该实施例的方法步骤还可以包括形成发光功能层112与阴极113， 如图1a所示。
实施例四、
具体地，制备如图1b所示的屏蔽层120与各阳极111同层设置的阵列基板的方法步骤包括：在衬底基板100上形成位于各像素110中的顶电极114；如图5a所示。具体地，采用一次构图工艺在衬底基板100上形成位于各像素110中的顶电极114。并且在实际制备时，该衬底基板100已经提前形成有位于各像素110中的像素驱动电路130，且形成的顶电极114与对应的像素驱动电路130电连接。
根据该实施例的方法步骤还包括：在形成有顶电极114的衬底基板100上形成第三绝缘层160以及位于各像素100中的贯穿第三绝缘层160的各第二过孔116，如图5b所示。其中，各第二过孔116在衬底基板100上的正投影位于对应的顶电极114在衬底基板100上的正投影内。具体地，采用一次构图工艺在形成有顶电极114的衬底基板100上形成第三绝缘层160以及位于各像素100中的贯穿第三绝缘层160的各第二过孔116。
根据该实施例的方法步骤还包括：在形成有第三绝缘层160的衬底基板100上形成屏蔽层120以及位于各像素110中且与屏蔽层120绝缘的阳极111，使各阳极111通过对应的第二过孔116与对应的顶电极114电连接，如图5c所示。其中，各第二过孔116在衬底基板100上的正投影与屏蔽层120在衬底基板100上的正投影无交叠。具体地，采用一次构图工艺在形成有第三绝缘层160的衬底基板100上形成屏蔽层120以及位于各像素110中且与屏蔽层120绝缘的阳极111。这样使屏蔽层120与阳极111同层同材料，且厚度相同。应当理解，也可以分别采用两次构图工艺形成屏蔽层120以及位于各像素110中且与屏蔽层120绝缘的阳极111，以使屏蔽层120与阳极111同层且厚度相同。其中，形成的屏蔽层的材料可以为导电材料，并且屏蔽层接地。其中，该导电材料可以为透明导电材料，例如可以为ITO材料、IZO材料、碳纳米管、石墨烯、纳米金或纳米银等。可替换地，该导电材料也可以为金属材料，例如可以为金、银、铝、铜和钼中之一或其 组合。应当理解，在实际应用中，屏蔽层的材料还可以为其他具有屏蔽相邻两个像素之间的电场的功能的材料，在此不作限定。
根据该实施例的方法步骤还可以包括形成发光功能层112与阴极113，如图1b所示。在实际制备过程中，在该步骤之后，且在形成发光功能层与阴极之前，还可以包括，采用一次构图工艺在形成有屏蔽层与阳极的衬底基板上形成第四绝缘层。其中，第四绝缘层在衬底基板上的正投影覆盖屏蔽层在衬底基板上的正投影，并且第四绝缘层在衬底基板上的正投影与各阳极在衬底基板上的正投影无交叠。
需要说明的是，在本公开实施例提供的上述制备方法中，构图工艺可包括光刻工艺。可替换地，构图工艺可以包括光刻工艺以及刻蚀步骤。附加地，还可以包括打印、喷墨等其他用于形成预定形状的各部件的工艺。光刻工艺是指包括成膜、曝光、显影、热烘等工艺过程的利用光刻胶、掩模板、曝光机等形成各部件的工艺。在具体实施时，可根据本公开中所形成的结构选择相应的构图工艺。
基于同一公开构思，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述任一种阵列基板。该显示面板解决问题的原理与前述阵列基板相似，因此该显示面板的实施可以参见前述阵列基板的实施例，重复之处在此不再赘述。并且上述显示面板可以为大尺寸、中尺寸、小尺寸以及微小尺寸的有机发光显示面板(OLED显示面板)。
在具体实施时，本公开实施例提供的显示面板可以为高分辨率的有机发光显示面板。
在具体实施时，本公开实施例提供的显示面板可以应用于头戴式视频播放器、头戴式家庭影院、头戴式虚拟现实模拟器、头戴式游戏机、飞行员头盔***、单兵作战***、红外夜视仪、头戴医用诊断***等设备中。
基于同一公开构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、头戴式视频播放器、头戴式家庭影院、头戴 式虚拟现实模拟器、头戴式游戏机、飞行员头盔***、单兵作战***、红外夜视仪、头戴医用诊断***等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述阵列基板的实施例，重复之处不再赘述。
本公开实施例提供的阵列基板、其制备方法、显示面板及显示装置，通过设置与各阳极绝缘的并且能够屏蔽相邻两个像素之间的电场的屏蔽层，可以在像素发光时，将该发光像素中的阳极与其相邻的像素中的阳极之间的电场进行屏蔽。从而可以避免由于相邻像素之间的耦合作用，导致该发光像素的阳极使其相邻的像素中的阳极具有耦合电压，进而可以消除相邻两个像素中的阳极之间的耦合作用对像素发光的干扰，提高显示效果。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (19)

  1. 一种阵列基板，包括：衬底基板以及位于所述衬底基板一侧的多个像素；各所述像素包括阳极；其中，所述阵列基板还包括：与各所述阳极绝缘设置的屏蔽层；所述屏蔽层用于屏蔽相邻两个所述像素之间的电场。
  2. 如权利要求1所述的阵列基板，其中，所述屏蔽层在所述衬底基板上的正投影与各所述相邻像素之间的间隙在所述衬底基板上的正投影至少部分交叠。
  3. 如权利要求2所述的阵列基板，其中，所述屏蔽层位于各所述阳极面向所述衬底基板的一侧。
  4. 如权利要求2所述的阵列基板，其中，所述屏蔽层与各所述阳极同层设置且位于各所述像素之间的间隙处。
  5. 如权利要求2所述的阵列基板，其中，所述屏蔽层具有第一部分和第二部分，所述第一部分位于各所述阳极面向所述衬底基板的一侧，所述第二部分与各所述阳极同层设置且位于各所述像素之间的间隙处。
  6. 如权利要求1-5中任一项所述的阵列基板，其中，所述屏蔽层的材料包括导电材料，并且所述屏蔽层接地。
  7. 如权利要求3所述的阵列基板，其中，所述相邻像素之间的间隙在所述衬底基板上的正投影在所述屏蔽层在所述衬底基板上的正投影内；
    所述屏蔽层与各所述阳极之间具有第一耦合电容，相邻两个阳极之间具有第二耦合电容；每个所述阳极对应的第一耦合电容的电容值不小于对应的第二耦合电容的电容值。
  8. 如权利要求7所述的阵列基板，其中，针对所述阳极，所述屏蔽层与所述阳极的边缘在垂直于所述衬底基板方向上的正对面积和所述阳极与其相邻的阳极之间的正对面积相等，所述屏蔽层与所述阳极之间的距离不大于所述阳极与其相邻的阳极之间的距离。
  9. 如权利要求7所述的阵列基板，其中，针对所述阳极，所述屏蔽层与所述阳极之间的距离和所述阳极与其相邻的阳极之间的距离相等，所述 屏蔽层与所述阳极的边缘在垂直于所述衬底基板方向上的正对面积不小于所述阳极与其相邻的阳极之间的正对面积。
  10. 如权利要求3所述的阵列基板，所述阵列基板还包括：位于所述屏蔽层面向所述衬底基板一侧的各所述像素中的顶电极，位于所述顶电极与所述屏蔽层之间的第一绝缘层，以及位于所述屏蔽层与各所述阳极之间的第二绝缘层；
    各所述阳极通过贯穿所述第一绝缘层与所述第二绝缘层的第一过孔与对应的顶电极电连接；其中，各所述第一过孔在所述衬底基板上的正投影位于对应的顶电极在所述衬底基板上的正投影内，且各所述第一过孔在所述衬底基板上的正投影与所述屏蔽层在所述衬底基板上的正投影无交叠。
  11. 如权利要求4所述的阵列基板，其中，所述屏蔽层与各所述阳极同厚度设置。
  12. 如权利要求4所述的阵列基板，其中，所述阵列基板还包括：位于所述屏蔽层面向所述衬底基板一侧的各所述像素中的顶电极，以及位于所述屏蔽层与所述顶电极之间的第三绝缘层；
    各所述阳极通过贯穿所述第三绝缘层的第二过孔与对应的顶电极电连接；其中，各所述第二过孔在所述衬底基板上的正投影位于对应的顶电极在所述衬底基板上的正投影内，且各所述第二过孔在所述衬底基板上的正投影与所述屏蔽层在所述衬底基板上的正投影无交叠。
  13. 如权利要求6所述的阵列基板，其中，所述导电材料包括金属材料。
  14. 一种显示面板，其中，包括如权利要求1-13任一项所述的阵列基板。
  15. 一种显示装置，其中，包括如权利要求14所述的显示面板。
  16. 一种如权利要求1-13任一项所述的阵列基板的制备方法，其中，包括：
    在衬底基板上形成屏蔽层以及位于各像素中且与所述屏蔽层绝缘的阳 极；其中，所述屏蔽层用于屏蔽相邻两个所述像素之间的电场。
  17. 如权利要求16所述的制备方法，其中，所述在衬底基板上形成屏蔽层以及位于各像素中且与所述屏蔽层绝缘的阳极之前，还包括：
    在衬底基板上形成位于各所述像素中的顶电极；
    在形成有所述顶电极的衬底基板上形成第一绝缘层；
    其中，所述形成屏蔽层，具体包括：在形成有所述第一绝缘层的衬底基板上形成屏蔽层；
    所述在形成屏蔽层之后，且在形成位于各像素中且与所述屏蔽层绝缘的阳极之前，还包括：在形成有所述屏蔽层的衬底基板上形成第二绝缘层以及贯穿所述第一绝缘层与所述第二绝缘层的各第一过孔；其中，各所述第一过孔在所述衬底基板上的正投影位于对应的顶电极在所述衬底基板上的正投影内，且各所述第一过孔在所述衬底基板上的正投影与所述屏蔽层在所述衬底基板上的正投影无交叠；
    所述形成位于各像素中且与所述屏蔽层绝缘的阳极，具体包括：在形成有所述第一过孔的衬底基板的各像素中形成各所述阳极，使各所述阳极通过对应的第一过孔与对应的顶电极电连接。
  18. 如权利要求16所述的制备方法，其中，所述在衬底基板上形成屏蔽层以及位于各像素中且与所述屏蔽层绝缘的阳极之前，还包括：
    在衬底基板上形成位于各所述像素中的顶电极；
    在形成有所述顶电极的衬底基板上形成第三绝缘层以及位于各所述像素中的贯穿所述第三绝缘层的各第二过孔；其中，各所述第二过孔在所述衬底基板上的正投影位于对应的顶电极在所述衬底基板上的正投影内；
    所述在衬底基板上形成屏蔽层以及位于各像素中且与所述屏蔽层绝缘的阳极，具体包括：
    在形成有所述第三绝缘层的衬底基板上形成所述屏蔽层以及位于各像素中且与所述屏蔽层绝缘的阳极，使各所述阳极通过对应的第二过孔与对应的顶电极电连接；其中，各所述第二过孔在所述衬底基板上的正投影与 所述屏蔽层在所述衬底基板上的正投影无交叠。
  19. 如权利要求16-18任一项所述的制备方法，其中，形成的所述屏蔽层的材料包括导电材料，且形成的所述屏蔽层接地。
PCT/CN2018/073990 2017-07-13 2018-01-24 一种阵列基板、其制备方法、显示面板及显示装置 WO2019010953A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/087,002 US11211442B2 (en) 2017-07-13 2018-01-24 Array substrate, with shielding layer, method for fabricating array substrate with shielding layer, display panel, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710570694.6A CN107369700B (zh) 2017-07-13 2017-07-13 一种阵列基板、其制备方法、显示面板及显示装置
CN201710570694.6 2017-07-13

Publications (1)

Publication Number Publication Date
WO2019010953A1 true WO2019010953A1 (zh) 2019-01-17

Family

ID=60306749

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/073990 WO2019010953A1 (zh) 2017-07-13 2018-01-24 一种阵列基板、其制备方法、显示面板及显示装置

Country Status (3)

Country Link
US (1) US11211442B2 (zh)
CN (1) CN107369700B (zh)
WO (1) WO2019010953A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107369700B (zh) * 2017-07-13 2020-01-07 京东方科技集团股份有限公司 一种阵列基板、其制备方法、显示面板及显示装置
CN107634087A (zh) * 2017-10-27 2018-01-26 京东方科技集团股份有限公司 一种显示面板及显示装置
CN109216585B (zh) 2018-09-17 2020-03-31 京东方科技集团股份有限公司 显示基板和显示装置
CN109887985B (zh) 2019-04-10 2022-08-16 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置
CN110137236B (zh) * 2019-06-03 2022-01-28 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置
CN112242405A (zh) * 2019-07-18 2021-01-19 群创光电股份有限公司 显示装置
CN111162095B (zh) * 2020-01-02 2022-11-11 京东方科技集团股份有限公司 驱动背板及其制备方法、显示面板、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101266996A (zh) * 1999-09-17 2008-09-17 株式会社半导体能源研究所 El显示装置和用于制造所述显示装置的方法
CN103676375A (zh) * 2013-12-09 2014-03-26 京东方科技集团股份有限公司 阵列基板及其制作方法
CN104597670A (zh) * 2014-12-29 2015-05-06 上海天马微电子有限公司 一种阵列基板及其制作方法及显示装置
CN106773394A (zh) * 2016-10-14 2017-05-31 合肥京东方光电科技有限公司 一种阵列基板、显示面板及显示装置
CN107369700A (zh) * 2017-07-13 2017-11-21 京东方科技集团股份有限公司 一种阵列基板、其制备方法、显示面板及显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0622998D0 (en) 2006-11-17 2006-12-27 Microemissive Displays Ltd Colour optoelectronic device
US9791733B2 (en) * 2014-12-29 2017-10-17 Shanghai Tianma Micro-electronics Co., Ltd. Array substrate, manufacture method thereof, and display device
CN104659063A (zh) * 2014-12-30 2015-05-27 京东方科技集团股份有限公司 显示基板及其制造方法、显示面板和掩膜板
US9935165B2 (en) * 2015-08-31 2018-04-03 Joled, Inc. Semiconductor device, display unit, method of manufacturing display unit, and electronic apparatus
CN106960913A (zh) * 2017-03-31 2017-07-18 武汉华星光电技术有限公司 量子点发光二极管显示面板及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101266996A (zh) * 1999-09-17 2008-09-17 株式会社半导体能源研究所 El显示装置和用于制造所述显示装置的方法
CN103676375A (zh) * 2013-12-09 2014-03-26 京东方科技集团股份有限公司 阵列基板及其制作方法
CN104597670A (zh) * 2014-12-29 2015-05-06 上海天马微电子有限公司 一种阵列基板及其制作方法及显示装置
CN106773394A (zh) * 2016-10-14 2017-05-31 合肥京东方光电科技有限公司 一种阵列基板、显示面板及显示装置
CN107369700A (zh) * 2017-07-13 2017-11-21 京东方科技集团股份有限公司 一种阵列基板、其制备方法、显示面板及显示装置

Also Published As

Publication number Publication date
US20210202644A1 (en) 2021-07-01
US11211442B2 (en) 2021-12-28
CN107369700B (zh) 2020-01-07
CN107369700A (zh) 2017-11-21

Similar Documents

Publication Publication Date Title
WO2019010953A1 (zh) 一种阵列基板、其制备方法、显示面板及显示装置
WO2020038200A1 (zh) 显示面板及制备方法以及电子设备
WO2018205651A1 (zh) Oled触控显示面板及其制作方法、触控显示装置
KR101574390B1 (ko) 유기 발광 다이오드, 터치 디스플레이 장치 및 그의 제조 방법
WO2020200168A1 (zh) Amoled显示屏、显示设备及移动终端
CN108010945B (zh) 显示面板和显示装置
WO2019233391A1 (zh) Oled基板及显示面板、显示装置
WO2021093687A1 (zh) 显示基板及其制备方法、显示装置
TWI606283B (zh) 顯示裝置
WO2018149106A1 (zh) 复合透明电极、oled及其制备方法、阵列基板和显示装置
WO2020154875A1 (zh) 像素单元及其制造方法和双面oled显示装置
JP6837410B2 (ja) 発光領域を含むディスプレイ装置
CN111796718A (zh) 触控显示面板及其制备方法、显示装置
TWI785080B (zh) 顯示面板、顯示裝置、顯示模組以及電子裝置
CN109119451A (zh) 显示基板及其制造方法、显示装置
WO2018219025A1 (zh) 阵列基板、电致发光显示面板及显示装置
WO2016090747A1 (zh) Oled显示装置及其制造方法
JP7267744B2 (ja) タッチパネル、その製造方法及び表示装置
WO2021238755A1 (zh) 触控面板及其制备方法、显示装置
US8963145B2 (en) OLED touch display panel structure
WO2020233485A1 (zh) 发光器件及其制造方法、掩膜板、显示装置
CN109755281B (zh) Oled显示面板及其制作方法
KR20150075016A (ko) 표시 장치
TW200906209A (en) System for displaying image and fabrication method thereof
WO2021203320A1 (zh) 阵列基板及其制备方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18832919

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 120A DATED 20/05/2020)

122 Ep: pct application non-entry in european phase

Ref document number: 18832919

Country of ref document: EP

Kind code of ref document: A1