WO2019005174A1

WO2019005174A1 - Apparatus for generating rf second and higher harmonics

Info

Publication number: WO2019005174A1
Application number: PCT/US2017/040524
Authority: WO
Inventors: Sasikanth Manipatruni; Dmitri E. Nikonov; Ian A. Young
Original assignee: Intel Corporation
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03

Abstract

An apparatus is provided which comprises: a source to provide a sinusoidal signal; a capacitor comprising ferroelectric material, the capacitor coupled to the source; and a device coupled in series with the capacitor. An apparatus is also provided which comprises: a first layer comprising metal; a second layer comprising metal; a third layer comprising metal, wherein the third layer is disposed between the first and second metal layers; a first capacitor comprising ferroelectric material, the first capacitor adjacent to the third metal layer; a second capacitor comprising ferroelectric material, the second capacitor adjacent to the third metal layer; a first dielectric between the first capacitor and the first layer; and a second dielectric between the second capacitor and the second layer.

Description

APPARATUS FOR GENERATING RF SECOND AND HIGHER HARMONICS

BACKGROUND

[0001] Passive circuit elements such as diode based RF (radio frequency) converters suffer from dead band. Existing on-chip RF converters are limited by efficiency of signal insertion into active silicon layer and also limited by signal swing which is limited to the voltages of the diodes. For high harmonic conversion (e.g., converting an input into higher harmonics) may require several steps of RF conversion, and each step adds to insertion loss.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Fig. 1 illustrates a cross-section of a non-linear ferroelectric capacitor, according to some embodiments of the disclosure.

[0004] Fig. 2 illustrates a cross-section of a non-linear ferroelectric capacitor, according to some embodiments of the disclosure.

[0005] Fig. 3A illustrates an apparatus for generating second and higher harmonics using voltage driven non-linear ferroelectric capacitors of Fig. 1 or Fig. 2, according to some embodiments of the disclosure.

[0006] Fig. 3B illustrates a plot showing a transfer function of the non-linear ferroelectric capacitors of Fig. 1 or Fig. 2.

[0007] Fig. 4 illustrates a plot showing generation of an ultra-wide band (UWB) signal using the apparatus of Fig. 3Α, in accordance with some embodiments.

[0008] Fig. 5Α illustrates a three dimensional (3D) view and a corresponding cross- section of a travelling wave phase matched second harmonic generator using lumped integrated non-linear ferroelectric capacitors of Fig. 1 or Fig. 2, according to some embodiments of the disclosure.

[0009] Fig. 5B illustrates a 3D view and a corresponding cross-section of a travelling wave phase matched second harmonic generator using distributed integrated non-linear ferroelectric capacitors of Fig. 1 or Fig. 2, according to some embodiments of the disclosure. [0010] Fig. 6 illustrates propagation and generation of second harmonics as properties of the travelling wave phase matched second harmonic generators of Fig. 5A or Fig. 5B are adjusted, according to some embodiments.

[0011] Fig. 7 illustrates a plot showing generation of second harmonic using travelling wave phase matched second harmonic generators of Fig. 5A or Fig. 5B, according to some embodiments.

[0012] Fig. 8 illustrates a plot showing generation of higher harmonics using travelling wave phase matched second harmonic generators of Fig. 5A or Fig. 5B, according to some embodiments.

[0013] Fig. 9 illustrates an apparatus for generating harmonics using current driven non-linear ferroelectric capacitors of Fig. 1 or Fig. 2 with capacitive loading, according to some embodiments of the disclosure.

[0014] Fig. 10 illustrates an apparatus for generating harmonics using current driven non-linear ferroelectric capacitors of Fig. 1 or Fig. 2 with resistive loading, according to some embodiments of the disclosure.

[0015] Fig. 11 illustrates a smart device or a computer system or a SoC (System-on-

Chip) using the apparatus for generating second and/or higher harmonics, according to some embodiments.

DETAILED DESCRIPTION

[0016] Some embodiments disclose a non-linear ferroelectric capacitor that can be used for generating second and/or higher harmonics. In some embodiments, non-linear ferroelectric capacitor comprises high dielectric constant materials (e.g., perovskites and their super lattices with relative permittivity 'K' greater than 100). Some embodiments describe the interface materials to enable such non-linear ferroelectric capacitors. Some embodiments describe circuit elements or apparatus to enable frequency conversion (e.g., to convert an input signal with a frequency into an output signal with second and/or higher harmonics).

[0017] There are many technical effects of various embodiments. For example, the apparatus of various embodiments allow for second harmonic generation in the backend of an integrated chip. The apparatus of various embodiments can be configured to generate higher harmonics (e.g., second, third, fourth, and fifth harmonics) according to the response time of the ferroelectric material. Some embodiments can generate phase coherent high harmonics. Some embodiments can generate ultra-wide band (UWB) according to the response time of the ferroelectric material. Other technical effects will be evident from the various embodiments and figures.

[0018] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0019] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0020] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0021] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified).

Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. [0022] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0023] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term "MN" indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term "MP" indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0024] Here, the term "backend" generally refers to a section of a die which is opposite of a "frontend" and where package couples to the die bumps. For example, high level metal layers (e.g., metal layer 6 and above in a ten metal stack die) and corresponding vias that are closer to a die package are considered part of the backend of the die.

Conversely, the term "frontend" generally refers to a section of the die that includes the active region (e.g., where transistors are fabricated) and low level metal layers and corresponding vias that are closer to the active region (e.g., metal layer 5 and below in the ten metal stack die example).

[0025] Fig. 1 illustrates a cross-section of a non-linear ferroelectric capacitor 100, according to some embodiments of the disclosure. In some embodiments, ferroelectric capacitor 100 comprises two or more layers between metal plates or interconnect. Here, metal plates or interconnect 101 and 103 are shown with ferroelectric capacitor material of two or more layers 102 between them. In some embodiments, metal plates 101 and 103 include one or more of: Cu, Ag, Au, Al, or W.

[0026] In some embodiments, ferroelectric capacitor material 102 comprises a first conductive layer 101a, a layer 101b comprising perovskite, a second conductive layer 101c, and a conductive seed layer lOld. In some embodiments, first and second conductive layers lOla/c are conductive oxides that include one of the following elements: Sr, Ru, and O. In some embodiments, first and second conductive layers lOla/c are conductive oxides which comprise: SrRuCb, (La,Sr)Co03 [LSCO], Lao.sSro.sMni-xNkO, Cu-doped SrFeo.9Nbo.1O3, (La,Sr)Cr0₃.

[0027] In some embodiments, layer 102b comprising perovskite is sandwiched between first and second conductive layers lOla/c such that layer 102b is adjacent to first and second conductive layers lOla/c. In some embodiments, layer 102b comprises a low leakage perovskite. A perovskite has a cubic structure with general formula of ABO3. In this cubic structure, 'A' represents A-site ion (e.g., alkaline earth or rare earth element) which is positioned on the corners of the lattice, 'B' represents B-site ion (e.g., 3d, 4d, and 5d transition metal elements) on the center of the lattice, and oxide Ό' within the lattice forming an angled cube. For example, ABO3 where the valance of 'B' is larger than the valance of Ά'.

[0028] In some embodiments, material A includes one of: Na, K, Rb, Cs, Ca, Sr, Ba,

Lu, Ag, Cd, In, Ti, Pb, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Pu, or Am. In some embodiments, material B includes one of: Lu, Mg, Ca, Sr, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Al, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Cd, In, Sn, Sb, I, Lu, Hf, Ta, W, Ir, Hg, Pb, Ce, Pr, Hi, Er, Tm, Yb, Th, Pa, U, Np, Pu, or Am. In some embodiments, layer 102b includes one of SrTiC , BiFeC , BiTiC , or BaTiCb. In some embodiments, layer 102b includes lanthanum strontium manganite (LSMO), Nb doped Strontium titanate (STO), La doped STO, and similar class of oxides and perovskites.

[0029] In some embodiments, a seed layer (or starting layer) 1 Old is deposited first and then layers 101c, 101b, and 101a are deposited. In some embodiments, seed layer lOld is used to template the conductive layer 101c. In some embodiments, seed layer lOle is deposited in addition to or instead of layer lOld. In some embodiments, seed layer lOld/e includes one of: Ti, Al, Nb, La, or STO (SrTi03). In some embodiments, seed layer lOld/e includes one of: TiAl, Nb doped STO, or La doped STO.

[0030] Fig. 2 illustrates a cross-section of a non-linear ferroelectric capacitor 200, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 2 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. The ferroelectric capacitor of Fig. 2 is similar to the ferroelectric capacitor of Fig. 1 except that perovskite layer 101b is replaced by super lattice 201b. In some embodiments, super lattice 201b includes alternating layers of materials. For example, layer 202 comprises PbTi03, layer 203 comprises SrTi03, layer 204 comprises PbTi03, and layer 206 comprises SrTi03, and so on. One layer can be a non-polar oxide of the type (A⁺²B⁺⁴03) such as SrZrC , and another layer can be a polar oxide of the type (A⁺¹B⁺⁵Cb or A⁺ B⁺ Cb) such as LaAlCb and LaGaC , where 'A' can comprise La, Sr, Pb, Pr, Nd, Sm, Gd, Y, Tb, Dy, Ho, Er, Tm, Lu, Ce, Li, Na, K, Rb, and Ag, and 'B' can comprise Ga, Al, Sc, In, Ta, Ti, and Zr. As more alternating layers of PbTiC and SrTiC are added, ferroelectric capacitor can store more charge. In some embodiments, the two or more layers of super lattice 201b has a thickness that extends from the first metal layer 101a to the second metal layer 101c. In some embodiments the thickness is in a range of 1 nm to 100 nm. In some embodiments, the two or more layers of super lattice 201b have a width which is perpendicular to the thickness, and wherein the width is in a range of 1 nm to 100 nm.

[0031] Fig. 3A illustrates apparatus 300 for generating second and higher harmonics using voltage driven non-linear ferroelectric capacitors of Fig. 1 or Fig. 2, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 3A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0032] Apparatus 300 comprises a voltage source 301 providing sinusoidal input, non-linear ferroelectric capacitor 302 (e.g., 102 or 200), and resistive device 303 having resistance Rext, in accordance with some embodiments. The output node 304 provides an output which is also sinusoidal. The non-linear ferroelectric capacitor 302 can be modeled as a non-linear capacitor CFE coupled in series with an internal resistor Rint. In various embodiments, the output Vout has second and higher harmonics depending on the configuration of ferroelectric capacitor 302 (e.g., types and thickness of ferroelectric material) and/or ratios of internal to the external resistances (Rim: Rext).

[0033] Fig. 3B illustrates plot 320 showing transfer function of the non-linear ferroelectric capacitors of Fig. 1 or Fig. 2. Conventional capacitors have a linear relationship between charge and voltage (e.g., Q=CV). In various embodiments, ferroelectric capacitor 302 has a non-linear relationship between charge and voltage. Plot 320 illustrates such nonlinear behavior. Here, the x-axis is charge accumulation (in nano Coulombs nC) in the nonlinear ferroelectric capacitor 302 while the y-axis is voltage across the non-linear ferroelectric capacitor 302. The transfer function of plot 320 illustrates three regions.

[0034] First, the linear dielectric regions are regions significantly away from the origin and exhibit classic dielectric response of the material. Here, voltage across ferroelectric capacitor 302 has a linear relationship with charge. [0035] Second, the linear ferro/para electric region is near the origin of the transfer curve and exhibits classic ferroelectric response near zero-charge (with negative capacitance).

[0036] Third, the non-linear ferro/para electric regions are on either sides of the linear ferro/para electric region. These regions span the hysteretic turn around points and the origin are the non-linear ferroelectric/di electric response. Since the charge increases and decreases between the two non-linear ferro/para electric regions, frequency doubles. For example, modulation of the input voltage, charge, and/or current spanning these non-linear regions produces harmonics. As such, the non-linear ferroelectric capacitors of Fig. 1 or Fig. 2 can be used as strong second harmonic (and high harmonic) generators.

[0037] The free energy F of a crystal with ferroelectric polarization can be expressed in simplified formed as:

F = U - EP = F₀ + -P² + ^ P + -P⁶ - EP

2 4 6

where U is the internal energy of the ferroelectric, E is electric field, P is polarization, and a, β, and γ are material dependent constants associated with the Landau-Khalatnikov equation.

[0038] The intrinsic switching of a ferroelectric (according to the Landau-

Khalatnikov equation) can be expressed as:

1 E \ /ⁱ

τ = - — ¹

where U is the internal energy of the ferroelectric, Q_F = AP is the charge stored in the ferroelectric, A is the electrode area, E_cin Is the critical switching field, τ is the time response of the material.

[0039] According to the Landau-Khalatnikov model:

^VF = ^τΊίΓ ⁺ (^2a& ^{+ 4}^ ^{+ 6}^f )

where V_Fis the voltage across the ferroelectric material. The equivalent non-linear capacitance of the ferroelectric can be expressed as:

C_F(Q_F) = (2a + 4/?ρ + 6γρ⁴)-ι

[0040] In various embodiments, the choice of ferroelectric material is used to set the non-linearity.

[0041] Fig. 4 illustrates plot 400 showing generation of a UWB signal using the apparatus of Fig. 3A, in accordance with some embodiments. Here, the x-axis is frequency in log scale, the y-axis to the left is the input (e.g., input on node 301 in V/sqrt(Hz)), and the y-axis to the right is output (e.g., output on node 304 in V/sqrt(Hz)). Plot 400 shows the generation of second and high harmonics using the non-linearity of the ferroelectric capacitor 302. The presence of high harmonics (e.g., third, fourth, fifth harmonics) results in an ultra- wide band (UWB) signal. This UWB signal comprises of several phase coherent harmonics.

[0042] Fig. 5A illustrates a 3D view and a corresponding cross-section of a travelling wave phase matched second harmonic generator 500 using lumped integrated non-linear ferroelectric capacitors of Fig. 1 or Fig. 2, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 5A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0043] In some embodiments, harmonic generator 500 comprises a wave-guide like structure such that input RF signal is provided to one end of the wave-guide and an output RF with harmonic(s) is received at another end of the waveguide. Here, the terms harmonic generator 500 and waveguide 500 are interchangeably used. In some embodiments, harmonic generator 500 comprises first metal layer 501a, second metal layer 501b, first ferroelectric capacitor 502a, second ferroelectric capacitor 502b, and third layer 503 (also referred to as signal plane).

[0044] In some embodiments, third layer 503 comprises metal, wherein third layer

503 is disposed between the first and second metal layers. In some embodiments, third layer 503 includes one or more of: Cu, Al, Au, or Ag. In some embodiments, first ferroelectric capacitor 502a is adjacent to third metal layer 503. In some embodiments, second ferroelectric capacitor 502b is adjacent to third metal layer 503, such that first ferroelectric capacitor 502a and second ferroelectric capacitor 502b are on opposite sides of third layer 503. In some embodiments, harmonic generator 500 comprises a first dielectric between first ferroelectric capacitor 502a and the first metal layer 501a. The thickness of the first dielectric is represented by hi. In some embodiments, harmonic generator 500 comprises a second dielectric between second ferroelectric capacitor 502b and the second metal layer 501b. The thickness of the second dielectric is represented by h2. In some embodiments, hi is equal to h2. In some embodiments, hi is un-equal to h2. For example, hi is greater than h2. Some examples of first and second dielectrics include SiC , HfC and doped versions, and

AA'BB'Cb (e.g., perovskites) in non-ferroelectric phase or range of operation or above Tc (ferroelectric critical temperature).

[0045] In some embodiments, first and second layers 501a/b are ground layers (e.g., coupled to ground supply Vss). In some embodiments, first and second layers 501 a/b include one or more of: Cu, Ag, Au, or Al. In some embodiments, an RF signal generator (not shown) is provided which is coupled to one end of third layer 503, wherein the RF signal generator is to provide an RF signal as input to third layer 503. Any suitable RF generator may be used to generate an RF signal. In some embodiments, an RF receiver (not shown) is provided and is coupled to another end of third layer 503, wherein the RF receiver is to receive harmonics of the RF signal. Any suitable RF receiver may be used which can receive and process one or more harmonics.

[0046] In some embodiments, the composition of first and second ferroelectric capacitors 502a/b is according to ferroelectric capacitors 102 and/or 200. Here, width 'W is the width or thickness of first and second ferroelectric capacitors 502a/b. While ' W illustrates as the total width of first and second ferroelectric capacitors 502a/b, the width of ferroelectric material 101b or 201b may have a stronger impact to the behavior of first and second ferroelectric capacitors 502a/b than changing the widths (or thicknesses) of seed layer l Ol d, or layers l Ole/c. Here, the term "behavior" generally refers to changing harmonic properties. For example, a change in behavior of first and second ferroelectric capacitors 502a/b may cause harmonic generator 500 to produce first and second harmonics. In another example, a change in behavior of first and second ferroelectric capacitors 502a/b may cause harmonic generator 500 to produce higher harmonics (e.g., forming an UWB signal).

[0047] In some embodiments, the width of layers l Ol a/b/c/d/e may be modified to change the behavior of first and second ferroelectric capacitors 502a/b without changing the total width 'W of the first and second ferroelectric capacitors 502a/b. For example, the width of ferroelectric material 101b or 201b may be increased while the width or thickness of layers lOla/c/d/e may be reduced so that that the overall width is the same while changing the overall behavior of the first and second ferroelectric capacitors 502a/b. In some

embodiments, by varying hi and h2, and the width ' W of first and second ferroelectric capacitors 502a/b (or the width of any of layers l Ol a/b/c/d/e), output behavior can be changed.

[0048] Cross-section AA illustrates that the first and second ferroelectric capacitors

502a/b are lumped capacitors. Here, the term "lumped capacitors" generally refers to ferroelectric capacitors that extend without spacing throughout the waveguide along the signal plane or third layer 503. In some embodiments, harmonic generator 500 is fabricated in the backend of an integrated circuit (IC) die. In some embodiments, harmonic generator 500 is fabricated in the frontend of an IC die. In some embodiments, phase matching techniques may be used to generate second harmonics. [0049] In some embodiments, a lumped resistor (not shown) is coupled to the output of the waveguide 500. In one such example, the lumped resistor is akin to resistor 303 while the waveguide 500 is akin to ferroelectric capacitor 302. In some embodiments, the lumped resistor is fabricated in the frontend of the IC (integrated circuit) die. In some embodiments, the lumped resistor is fabricated in the backend of the IC die. In some embodiments, the lumped resistor is fabricated on the same side of the IC die as waveguide 500. In some embodiments, the lumped resistor is fabricated on the different sides of the IC die than waveguide 500. In some embodiments, the input is coupled to a voltage source (e.g., voltage source 301). In some embodiments, the input is coupled to a current source. In some embodiments, the output forms a voltage divider (e.g., like node 304) and this output provides the harmonics.

[0050] Fig. 5B illustrates a 3D view and a corresponding cross-section of a travelling wave phase matched second harmonic generator 520 using distributed integrated non-linear ferroelectric capacitors of Fig. 1 or Fig. 2, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 5B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0051] Harmonic generator 520 is similar to harmonic generator 500 but for using distributed ferroelectric capacitors instead of lumped ferroelectric capacitors. Here, the term "distributed capacitors" generally refers to ferroelectric capacitors that are divided into smaller capacitors in more numbers, and that are positioned throughout the waveguide with spacing along the signal plane or third layer 503. The gaps between the distributed capacitors is filed with dielectric (e.g., first and/or second dielectric), in accordance with some embodiments.

[0052] Here, a total of four distributed capacitors are shown 502al, 502a2, 502bl, and 502b2. Any number of distributed capacitors may be used along signal plane 503.

Composition wise, the distributed capacitors shown as 502al, 502a2, 502bl, and 502b2 are according to capacitors 102b or 200. In some embodiments, changing the number of distributed capacitors may change the behavior of the output. In some embodiments, harmonic generator 520 is fabricated in the backend of an IC die. In some embodiments, harmonic generator 500 is fabricated in the frontend of an IC die. In some embodiments, phase matching techniques may be used to generate second harmonics. In some

embodiments, distributed resistors (not shown) are coupled to the output of the waveguide 520. In some embodiments, the resistance is from the line resistance of the waveguide. [0053] In some embodiments, the input is coupled to a voltage source (e.g., voltage source 301). In some embodiments, the input is coupled to a current source. In some embodiments, the output forms a voltage divider (e.g., like node 304) and this output provides the harmonics.

[0054] Fig. 6 illustrates propagation and generation of second harmonics as properties of the travelling wave phase matched second harmonic generators of Fig. 5A or Fig. 5B are adjusted, according to some embodiments. Apparatus 600 shows propagation of waves through signal plane 503 where strong second harmonic is not generated because the refractive indexes associated with first and second harmonics are not the same (e.g., η2ω≠ η_ω). Here, η_ω is the refractive index associated with the first harmonic 601, while η2ω is the refractive index associated with the second harmonic 602, which in this example is out of phase relative to the first harmonic 601, k_w is the momentum vector, and S_w is the Poynting vector (e.g., flow of energy).

[0055] Apparatus 620 shows propagation of waves through signal plane 503 where strong second harmonic is generated because the refractive indexes associated with the first and second harmonics are the same (e.g., η2ω= η_ω). Here, the first harmonic 601is in phase (e.g., phase matched) with the second harmonic 602, which results in a strong second harmonic 602 are the output of the waveguide.

[0056] Fig. 7 illustrates plot 700 showing the generation of second harmonic using travelling wave phase matched second harmonic generators of Fig. 5A or Fig. 5B, according to some embodiments. In some embodiments, the ratio of the internal to the external resistances (RintRext) sets the amount of non-linearity. The ratio allows the impedance matching and optimization of the harmonic to be generated.

[0057] Fig. 8 illustrates plot 270 showing the generation of higher harmonics using travelling wave phase matched second harmonic generators of Fig. 5A or Fig. 5B, according to some embodiments. Here, UWB signal is generated with strength (e.g., amplitude) of each harmonic being substantially similar. In some embodiments, the UWB signal is generated by tuning the ratio of the internal to the external resistances (RintRext).

[0058] Fig. 9 illustrates apparatus 900 for generating harmonics using current driven non-linear ferroelectric capacitors of Fig. 1 or Fig. 2 with capacitive loading, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 9 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. [0059] Apparatus 900 comprises a current source 901 providing sinusoidal input, non-linear ferroelectric capacitor 902 (e.g., 102 or 200), and capacitive device 903 having capacitance Cext, in accordance with some embodiments. The output node 904 provides an output which is also sinusoidal. The non-linear ferroelectric capacitor 902 can be modeled as a non-linear capacitor CFE coupled in series with an internal resistor Rint. In various embodiments, the output Vout has second and higher harmonics depending on the configuration of ferroelectric capacitor 902 (e.g., types and thickness of ferroelectric material), and/or ratios of internal to the external resistances (RintRext).

[0060] Fig. 10 illustrates apparatus 1000 for generating harmonics using current driven non-linear ferroelectric capacitors of Fig. 1 or Fig. 2 with resistive loading, according to some embodiments of the disclosure. Apparatus 1000 comprises a current source 901 providing sinusoidal input, non-linear ferroelectric capacitor 1002 (e.g., 102 or 200), and resistive device 1003 having resistance Eext, in accordance with some embodiments. The output node 1004 provides an output which is also sinusoidal. The non-linear ferroelectric capacitor 1002 can be modeled as a non-linear capacitor CFE coupled in series with an internal resistor Rint. In various embodiments, the output Vout has second and higher harmonics depending on the configuration of ferroelectric capacitor 1002 (e.g., types and thickness of ferroelectric material), and/or ratios of internal to the external resistances

(Rin Rext).

[0061] Fig. 11 illustrates a smart device or a computer system or a SoC (System-on-

Chip) using the apparatus for generating second and/or higher harmonics, according to some embodiments. It is pointed out that those elements of Fig. 11 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0062] Fig. 11 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0063] In some embodiments, computing device 1600 includes first processor 1610 with the apparatus for generating second and/or higher harmonics, according to some embodiments discussed. Other blocks of the computing device 1600 may also include or use the apparatus for generating second and/or higher harmonics, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant. In some embodiments, apparatus for generating second and/or higher harmonics is part of Connectivity block 1670, and is used to provide second and higher RF harmonics.

[0064] In some embodiments, processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0065] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0066] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0067] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0068] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0069] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0070] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0071] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0072] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0073] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0074] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[0075] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0076] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0077] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0078] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0079] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0080] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0081] Example 1 is an apparatus which comprises: a source to provide a sinusoidal signal; a capacitor comprising ferroelectric material, the capacitor coupled to the source; and a device coupled in series with the capacitor.

[0082] Example 2 includes all features of example 1, wherein the source is one of a current source or a voltage source.

[0083] Example 3 is to any one of examples 1 or 2, wherein the capacitor includes: two or more layers coupled between first and second metal layers, wherein the two or more layers include: a first layer comprising a conductive oxide; a second layer comprising a conductive oxide; and a third layer comprising a perovskite, wherein the third layer is adjacent to the first and second layers.

[0084] Example 4 includes all features of example 3, wherein the two or more layers comprises a fourth layer adjacent to one of the first or second layers, wherein the fourth layer comprises a conductive seed layer.

[0085] Example 5 includes all features of example 4, wherein the fourth layer includes one of: Ti, Al, Nb, La, or STO.

[0086] Example 6 includes all features of example 4, wherein the fourth layer includes one of: TiAl, Nb doped STO, or La doped STO.

[0087] Example 7 is according to any one of examples 3 or 4, wherein the first and second layers include one of: Sr, Ru, or O.

[0088] Example 8 is according to any one of examples 3 or 4, wherein the third layer includes one of: SrTi03, BiFe03, BiTe03, or BaTi03.

[0089] Example 9 is according to any one of examples 3 or 4, wherein the third layer includes a super lattice of PbTi03 and SrTi03.

[0090] Example 10 is according to any one of the preceding examples, wherein the two or more layers has a thickness that extends from the first metal layer to the second metal layer, and wherein the thickness is in a range of 2 nm to 100 nm, and wherein the two or more layers have a width which is perpendicular to the thickness, and wherein the width is in a range of 5 nm to 10 nm. [0091] Example 11 is according to any one of the preceding examples, wherein the two or more layers has a thickness that extends from the first metal layer to the second metal layer, and wherein the thickness is in a range of 1 nm to 50 nm, and wherein the two or more layers have a width which is perpendicular to the thickness, and wherein the width is in a range of 1 nm to 50 nm.

[0092] Example 12 is according to any one of the preceding examples, wherein the device is one of a resistive device or a capacitive device.

[0093] Example 13 is an apparatus which comprises: a first layer comprising metal; a second layer comprising metal; a third layer comprising metal, wherein the third layer is disposed between the first and second metal layers; a first capacitor comprising ferroelectric material, wherein the first capacitor is adjacent to the third metal layer; a second capacitor comprising ferroelectric material, wherein the second capacitor is adj acent to the third metal layer; a first dielectric between the first capacitor and the first layer; and a second dielectric between the second capacitor and the second layer.

[0094] Example 14 includes all features of example 13, wherein the first and second layers are ground layers.

[0095] Example 15 is according to any one of examples 13 to 14 comprises an RF signal generator coupled to one end of the third layer, wherein the RF signal generator is to provide an RF signal.

[0096] Example 16 includes all features of example 15, and comprises an RF receiver coupled to another end of the third layer, wherein the RF receiver is to receive harmonics of the RF signal.

[0097] Example 17 is according to any one of examples 13 to 16, wherein each of the first and second capacitors include: two or more layers coupled between the first and second metal layers, wherein the two or more layers include: a first layer comprising a conductive oxide; a second layer comprising a conductive oxide; and a third layer comprising a perovskite, wherein the third layer is adjacent to the first and second layers.

[0098] Example 18 includes all features of example 17, wherein the two or more layers comprises a fourth layer adjacent to one of the first or second layers, and wherein the fourth layer comprises a conductive seed layer.

[0099] Example 19 includes all features of example 18, wherein the fourth layer includes one of: Ti, Al, Nb, La, or STO.

[00100] Example 20 includes all features of example 18, wherein the fourth layer includes one of: TiAl, Nb doped STO, or La doped STO. [00101] Example 21 is according to any one of examples 17 or 18, wherein the first and second layers include one of: Sr, Ru, or O.

[00102] Example 22 is according to any one of examples 17 or 18, wherein the third layer includes one of: SrTiC , BiFeCb, BiTeC , or BaTiC .

[00103] Example 23 is according to any one of examples 17 or 18, wherein the third layer includes a super lattice of PbTiC and SrTiC .

[00104] Example 24 is according to any of the preceding examples 13 to 23, wherein the first and second capacitors are lumped capacitors.

[00105] Example 25 is according to any of the preceding examples 13 to 23, wherein the first and second capacitors are distributed capacitors.

[00106] Example 26 is a system comprising: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus examples 1 to 12; and a wireless interface to allow the processor to communicate with another device.

[00107] Example 27 is a method which comprises: forming a first layer comprising metal; forming a second layer comprising metal; forming a third layer comprising metal, wherein the third layer is disposed between the first and second metal layers; forming a first capacitor comprising ferroelectric material, wherein the first capacitor is adjacent to the third metal layer; forming a second capacitor comprising ferroelectric material, wherein the second capacitor is adjacent to the third metal layer; forming a first dielectric between the first capacitor and the first layer; and forming a second dielectric between the second capacitor and the second layer.

[00108] Example 28 includes all features of example 27, wherein the first and second layers are ground layers.

[00109] Example 29 is according to any one of examples 27 to 28 comprises: coupling an RF signal generator to one end of the third layer; and providing an RF signal.

[00110] Example 30 includes all features of example 29, and comprises coupling an

RF receiver coupled to another end of the third layer, wherein the RF receiver is to receive harmonics of the RF signal.

[00111] Example 31 is according to any one of examples 27 to 31, wherein forming each of the first and second capacitors include: forming two or more layers coupled between the first and second metal layers, wherein the forming two or more layers include: forming a first layer comprising a conductive oxide; forming a second layer comprising a conductive oxide; and forming a third layer comprising a perovskite, wherein the third layer is adjacent to the first and second layers. [00112] Example 32 includes all features of example 31, wherein forming the two or more layers comprises forming a fourth layer adjacent to one of the first or second layers, and wherein forming the fourth layer comprises forming a conductive seed layer.

[00113] Example 33 includes all features of example 32, wherein the fourth layer includes one of: Ti, Al, Nb, La, or STO.

[00114] Example 34 includes all features of example 32, wherein the fourth layer includes one of: TiAl, Nb doped STO, or La doped STO.

[00115] Example 35 is according to any one of examples 27 or 28, wherein the first and second layers include one of: Sr, Ru, or O.

[00116] Example 36 is according to any one of examples 27 or 28, wherein the third layer includes one of: SrTi03, BiFe03, BiTe03, or BaTi03.

[00117] Example 37 is according to any one of examples 27 or 28, wherein the third layer includes a super lattice of PbTi03 and SrTi03.

[00118] Example 38 is according to any of the preceding examples 27 to 37, wherein the first and second capacitors are lumped capacitors.

[00119] Example 39 is according to any of the preceding examples 27 to 37, wherein the first and second capacitors are distributed capacitors.

[00120] Example 40 is a method which comprises: providing a sinusoidal signal via a source; forming a capacitor comprising ferroelectric material, the capacitor coupled to the source; and forming a device coupled in series with the capacitor.

[00121] Example 41 includes all features of example 40, wherein the source is one of a current source or a voltage source.

[00122] Example 42 is according to any one of examples 40 or 41 , wherein forming the capacitor includes: forming two or more layers and coupling the two or more layers between first and second metal layers, wherein forming the two or more layers include: forming a first layer comprising a conductive oxide; forming a second layer comprising a conductive oxide; and forming a third layer comprising a perovskite, wherein the third layer is adjacent to the first and second layers.

[00123] Example 43 includes all features of example 42, wherein forming the two or more layers comprises forming a fourth layer adjacent to one of the first or second layers, wherein forming the fourth layer comprises forming a conductive seed layer.

[00124] Example 44 includes all features of example 43, wherein the fourth layer includes one of: Ti, Al, Nb, La, or STO. [00125] Example 45 includes all features of example 44, wherein the fourth layer includes one of: TiAl, Nb doped STO, or La doped STO.

[00126] Example 46 is according to any one of examples 43 or 44, wherein the first and second layers include one of: Sr, Ru, or O.

[00127] Example 47 is according to any one of examples 43 or 44, wherein the third layer includes one of: SrTiC , BiFeCb, BiTeC , or BaTiC .

[00128] Example 48 is according to any one of examples 43 or 44, wherein the third layer includes a super lattice of PbTiC and SrTiC .

[00129] Example 49 is according to any one examples 40 to 48, wherein the two or more layers has a thickness that extends from the first metal layer to the second metal layer, and wherein the thickness is in a range of 2 nm to 100 nm, and wherein the two or more layers have a width which is perpendicular to the thickness, and wherein the width is in a range of 5 nm to 10 nm.

[00130] Example 50 is according to any one examples 40 to 48, wherein the two or more layers has a thickness that extends from the first metal layer to the second metal layer, and wherein the thickness is in a range of 1 nm to 50 nm, and wherein the two or more layers have a width which is perpendicular to the thickness, and wherein the width is in a range of 1 nm to 50 nm.

[00131] Example 51 is according to any one examples 40 to 48, wherein the device is one of a resistive device or a capacitive device.

[00132] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An apparatus comprising:

a source to provide a sinusoidal signal;

a capacitor comprising ferroelectric material, the capacitor coupled to the source; and a device coupled in series with the capacitor.

2. The apparatus of claim 1, wherein the source is one of a current source or a voltage

source.

3. The apparatus according to any one of claims 1 or 2, wherein the capacitor includes: two or more layers coupled between first and second metal layers, wherein the two or more layers include:

a first layer comprising a conductive oxide;

a second layer comprising a conductive oxide; and

a third layer comprising a perovskite, wherein the third layer is adjacent to the first and second layers.

4. The apparatus of claim 3, wherein the two or more layers comprises a fourth layer

adjacent to one of the first or second layers, wherein the fourth layer comprises a conductive seed layer.

5. The apparatus of claim 4, wherein the fourth layer includes one of: Ti, Al, Nb, La, or STO.

6. The apparatus of claim 4, wherein the fourth layer includes one of: TiAl, Nb doped STO, or La doped STO.

7. The apparatus according to any one of claims 3 or 4, wherein the first and second layers include one of: Sr, Ru, or O.

8. The apparatus according to any one of claims 3 or 4, wherein the third layer includes one of: SrTi0₃, BiFe0₃, BiTe0₃, or BaTiOs.

9. The apparatus according to any one of claims 3 or 4, wherein the third layer includes a super lattice of PbTiCb and SrTiCb.

10. The apparatus according to any one of the preceding claims, wherein the two or more layers has a thickness that extends from the first metal layer to the second metal layer, and wherein the thickness is in a range of 2 nm to 100 nm, and wherein the two or more layers have a width which is perpendicular to the thickness, and wherein the width is in a range of 5 nm to 10 nm.

11. The apparatus according to any one of the preceding claims, wherein the two or more layers has a thickness that extends from the first metal layer to the second metal layer, and wherein the thickness is in a range of 1 nm to 50 nm, and wherein the two or more layers have a width which is perpendicular to the thickness, and wherein the width is in a range of 1 nm to 50 nm.

12. The apparatus according to any one of the preceding claims, wherein the device is one of a resistive device or a capacitive device.

13. An apparatus comprising:

a first layer comprising metal;

a second layer comprising metal;

a third layer comprising metal, wherein the third layer is disposed between the first and second metal layers;

a first capacitor comprising ferroelectric material, wherein the first capacitor is adjacent to the third metal layer;

a second capacitor comprising ferroelectric material, wherein the second capacitor is adjacent to the third metal layer;

a first dielectric between the first capacitor and the first layer; and

a second dielectric between the second capacitor and the second layer.

14. The apparatus of claim 13, wherein the first and second layers are ground layers.

15. The apparatus according to any one of claims 13 to 14 comprises an RF signal generator coupled to one end of the third layer, wherein the RF signal generator is to provide an RF signal.

16. The apparatus of claim 15 comprises an RF receiver coupled to another end of the third layer, wherein the RF receiver is to receive harmonics of the RF signal.

17. The apparatus according to any one of claims 13 to 16, wherein each of the first and second capacitors include: two or more layers coupled between the first and second metal layers, wherein the two or more layers include:

a first layer comprising a conductive oxide;

a second layer comprising a conductive oxide; and

18. The apparatus of claim 17, wherein the two or more layers comprises a fourth layer adjacent to one of the first or second layers, and wherein the fourth layer comprises a conductive seed layer.

19. The apparatus of claim 18, wherein the fourth layer includes one of: Ti, Al, Nb, La, or STO.

20. The apparatus of claim 18, wherein the fourth layer includes one of: TiAl, Nb doped STO, or La doped STO.

21. The apparatus according to any one of claims 17 or 18, wherein the first and second layers include one of: Sr, Ru, or O.

22. The apparatus according to any one of claims 17 or 18, wherein the third layer includes one of: SrTi0₃, BiFeOs, BiTeOs, or BaTiOs.

23. The apparatus according to any one of claims 17 or 18, wherein the third layer includes a super lattice of PbTi03 and SrTi03.

24. The apparatus according to any of the preceding claims 13 to 23, wherein the first and second capacitors are lumped capacitors, or wherein the first and second capacitors are distributed capacitors.

25. A system comprising: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus claims 1 to 12 or claims 13 to 24; and a wireless interface to allow the processor to communicate with another device.