WO2019005163A1

WO2019005163A1 - Top hat electrode for memory applications and methods of fabrication

Info

Publication number: WO2019005163A1
Application number: PCT/US2017/040504
Authority: WO
Inventors: Ravi Pillarisetty; Abhishek A. Sharma; Gilbert Dewey; Van H. Le; Jack T. Kavalieros
Original assignee: Intel Corporation
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03

Abstract

A memory structure includes a conductive interconnect disposed above a substrate, a memory device disposed above the conductive interconnect and coupled with the conductive interconnect. The memory device has sidewalls and an uppermost surface. For memory device and fabrication enablement, a top hat electrode is disposed on the memory device. The top hat electrode has sidewalls, a lowermost surface and an uppermost surface. The sidewalls of the top hat electrode extend beyond the sidewalls of the memory device. The top hat electrode has a lowermost surface area that is larger than an area of the uppermost surface of the memory device. A second conductive interconnect is disposed on the top hat electrode. The second conductive interconnect includes a via having sidewalls and a lowermost surface that is in contact with the uppermost surface of the top hat electrode.

Description

TOP HAT ELECTRODE FOR MEMORY APPLICATIONS AND METHODS OF FABRICATION

TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit fabrication and, in particular, a top hat electrode for memory applications and methods of fabrication.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Non-volatile embedded resistive memory integrated with transistors (1T-1R), for example, on-chip embedded memory with non-volatility can enable energy and computational efficiency. Typically, a 1T-1R cell includes a transistor whose drain terminal is connected in series with a memory device. With scaling in transistor cell and memory device size, the interconnects connecting the memory devices need to be precisely aligned. An interconnecting via misaligned with respect to a memory device can render the memory device functionless.

Such imprecisions can present formidable roadblocks to commercialization of this technology as devices continue to scale in size. Thus, furthering development in the areas of integrating novel structures that overcome limitations imposed by scaling memory and interconnects is an integral part of the non-volatile memory roadmap.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 A illustrates a cross-sectional view of a memory device having a top hat electrode, in accordance with an embodiment of the present disclosure.

Figure IB illustrates a plan view representing alignment between a top hat electrode and a memory device, in accordance with embodiments of the present disclosure.

Figure 1C illustrates a plan view representing alignment between a top hat electrode and a via, in accordance with embodiments of the present disclosure.

Figure ID illustrates a plan view of the top hat electrode above a circular memory device, in accordance with embodiments of the present disclosure.

Figure IE illustrates a plan view of a circular via above a top hat electrode, in accordance with embodiments of the present disclosure. Figure IE illustrates a cross-sectional representing potential mis-alignment between the top hat electrode, the memory device and the via, in accordance with embodiments of the present disclosure.

Figure IF illustrates a cross-sectional view representing mis-alignment between a top hat electrode and a memory device, in accordance with embodiments of the present disclosure.

Figure 1G illustrates a cross-sectional view representing mis-alignment between a via and a top hat electrode, in accordance with embodiments of the present disclosure.

Figure 2A illustrates a cross-sectional view of a top hat electrode formed on a resistive random access memory (RRAM) device formed above a conductive interconnect.

Figure 2B illustrates a cross-sectional view of a top hat electrode formed on a magnetic tunnel junction (MTJ) memory device formed above a conductive interconnect.

Figure 3 A illustrates a cross-sectional view of a memory device having a top hat electrode, where a dielectric spacer is disposed on sidewalls of the memory device and under the top hat electrode, in accordance with an embodiment of the present disclosure.

Figure 3B illustrates a cross-sectional view of a pair of memory devices each having a respective top hat electrode, and where a dielectric spacer extends continuously between the pair of memory devices, in accordance with an embodiment of the present disclosure.

Figures 4A-4K illustrate cross sectional views of a sequence of operations to co-fabricate an array of memory devices alongside interconnects for logic transistors.

Figure 4A illustrates a cross-sectional view of a dielectric layer formed above conductive interconnects formed above a substrate.

Figure 4B illustrates the structure of Figure 4 A following the removal of a portion of the dielectric layer and an underlying etch stop layer to expose conductive interconnects to fabricate memory devices in a portion of the substrate.

Figure 4C illustrates the structure of Figure 4B following the formation of a material layer stack in the memory region and in the logic region of the substrate to form memory devices in the memory region of the substrate.

Figure 4D illustrates the structure of Figure 4C following the formation of memory devices.

Figure 4E illustrates the structure of Figure 4D following a blanket deposition of a dielectric spacer layer in the memory and in the logic region of the substrate.

Figure 4F illustrates the structure of Figure 4E following the deposition of a second dielectric layer over the entire substrate and a planarization process to expose uppermost portions of the memory devices.

Figure 4G illustrates the structure of Figure 4F following the deposition of a top hat electrode layer over the entire substrate.

Figure 4H illustrates the structure of Figure 4G following the formation of a top hat electrode above each memory device.

Figure 41 illustrates the structure of Figure 4H following a blanket deposition of a third dielectric layer and a planarization process to expose uppermost surfaces of the top hat electrode.

Figure 4 J illustrates the structure of Figure 41 following the formation of a vias and metal interconnects in the logic region.

Figure 4K illustrates the structure of Figure 4 J following the formation of metal interconnects and vias above previously formed metal interconnects in the logic region and the formation of a via above each top hat electrode and a metal interconnect connecting each of the vias above the top hat electrode.

Figure 5 illustrates a cross-sectional view of a memory device including a top hat electrode, where the memory device is formed on a conductive interconnect coupled to an access transistor, in accordance with an embodiment of the present disclosure.

Figure 6 illustrates a computing device in accordance with embodiments of the present disclosure.

Figure 7 illustrates an integrated circuit (IC) structure that includes one or more embodiments of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

A top hat electrode for memory applications and methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as transistor operations and switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Integrating a non-volatile memory device such as a spin transfer torque memory (STTM) device or a resistive random access memory device onto an access transistor enables the formation of embedded memory for system on chip. However, approaches to integrate memory devices onto an access transistor presents challenges that have become far more formidable with scaling. One example of this challenge is the difficulty in connecting smaller devices to smaller vias and trenches without rendering the devices functionless. Vias and trenches are components of metal interconnects and together form an important component of a memory cell that connect the embedded memory to other functionally integrated circuit components. In an embodiment, a metal interconnect structure includes a trench disposed on a via. The via is disposed on the memory device. In an embodiment, the via has a width that is larger than a maximum width of the memory device. In one such embodiment, a small amount of mis-alignment can expose the sidewalls of the memory device during the process of forming an opening to fabricate the via. When the opening is filled with a conductive metal, shorting between the conductive metal and the metallic layers of the memory device can render the device functionless. In an embodiment, the shorting between the conductive metal and the metallic layers of the memory device can be partially mitigated by making the width of the via smaller than the device. However, misalignment between a smaller via and a device remains a problem. In an embodiment, the minimum dimensions of the vias are also regulated by upper limits on electrical resistance of interconnects.

A solution to overcome shorting and mis-alignment problems while remaining independent of the size of the device or the via includes fabricating an intermediate electrode, between the memory device and the via. In an embodiment, the intermediate electrode has a lowermost surface having an area that is larger than an area of the uppermost surface of the memory device. In an embodiment, the lowermost surface area of the intermediate electrode is between 5-10 times larger than the area of the uppermost surface of the memory device and covers the memory device. In an event where a mis-alignment occurs between the intermediate electrode and the memory device, the uppermost surface of the memory device remains covered. In an embodiment, the intermediate electrode has an uppermost surface having an area that is larger than an area of a lowermost surface of the via. The uppermost surface of the intermediate electrode may be between 5-10 times larger than the area of the lowermost surface of the via. In an event where a mis-alignment occurs between the via and the intermediate electrode, the via does not contact the memory device. In an embodiment, an intermediate electrode of a memory device is isolated from intermediate electrodes formed over adjacent memory devices. An intermediate electrode that covers each memory device is referred to herein as a top hat electrode.

The fabrication of embedded memory hinges on fabrication of memory devices above transistors which are fabricated at the same time, and located at a same level as transistors dedicated for logic functions. The process of fabricating memory devices above access transistors that lie on the same plane as logic transistors involves replacing one or more levels of interconnects above the access transistors with memory devices. Fabrication of memory devices with top hat electrodes over access transistors at the same time as fabricating interconnects over logic transistors at the same level is highly advantageous from a process standpoint.

In an embodiment of the present disclosure, a memory structure includes a conductive interconnect disposed above a substrate. The memory structure includes a memory device disposed above the conductive interconnect and coupled with the conductive interconnect. The memory device has sidewalls and an uppermost surface. For memory device and fabrication enablement, a top hat electrode is disposed on the memory device. The top hat electrode has sidewalls, a lowermost surface and an uppermost surface. The sidewalls of the top hat electrode extend beyond the sidewalls of the memory device. The top hat electrode has a lowermost surface area that is larger than an area of the uppermost surface of the memory device. A second conductive interconnect is disposed on the top hat electrode. The second conductive

interconnect includes a via having sidewalls and a lowermost surface that is in contact with the uppermost surface of the top hat electrode. In an embodiment, the memory device and the top hat electrode have a combined thickness that is approximately equivalent to a thickness of a single layer of metal interconnect disposed at a same level in a logic region of the substrate facilitating embedded memory fabrication.

Figure 1 A illustrates a cross-sectional view of a memory structure 100. In an

embodiment, a memory structure 100 includes a conductive interconnect 102 disposed in a first dielectric layer 104 above a substrate 150. A memory device 106 is disposed above the conductive interconnect 102 and coupled with the conductive interconnect 102. The memory device 106 has sidewalls and an uppermost surface. A second dielectric layer 108 is disposed on the conductive interconnect 102, on the first dielectric layer 104 and laterally adjacent to the memory device 106. A top hat electrode 110 is disposed on the memory device 106 and on the first dielectric layer 104. The top hat electrode 110 is surrounded by a third dielectric layer 112 having an uppermost surface that is substantially coplanar with the uppermost surface of the top hat electrode 110. A via 114 is disposed on the top hat electrode 110. The via 114 is surrounded by a fourth dielectric layer 116 having an uppermost surface that is substantially coplanar with the uppermost surface of the via 114. The fourth dielectric layer 116 is disposed on a portion of the top hat electrode 110 and on the third dielectric layer 112.

The top hat electrode 110 has sidewalls, a lowermost surface 118 and an uppermost surface 120. The lowermost surface 118 of the top hat electrode 110 has a planar cross-sectional area that is larger than a planar cross-sectional area of the uppermost surface 122 of the memory device 106. In an embodiment, the lowermost surface 118 and the uppermost surface 120 of the top hat electrode 110 each have a planar cross-sectional area that is larger than the planar cross- sectional area of the uppermost surface 122 of the memory device 106. In an embodiment, the uppermost surface 122 of the memory device 106 has a planar cross-sectional area that is between 2% and 35% of a planar cross-sectional area of the lowermost surface 118 of the top hat electrode 110. The uppermost surface 120 of the top hat electrode 110 has a planar cross- sectional area sufficiently large enough to prevent a via 114 from shorting to the memory device 106. In an embodiment, the top hat electrode 110 has a center, CT, in an X direction, and the memory device has a center, CM, also in an X direction as is depicted in the cross-sectional illustration of Figure 1 A. In an embodiment, the center, CT, of the top hat electrode 110 is aligned with the center, CM, of the memory device 106 as illustrated in Figure 1 A.

Referring again to Figure 1 A, in an embodiment, the top hat electrode 110 has a thickness between 30nm-70nm. The thickness of the top hat electrode 110 is designed to be substantially similar to a thickness of a portion of an interconnect structure that is located in a logic region of the substrate. The interconnect structure has an uppermost surface (not shown) that is coplanar with the uppermost surface of the top hat electrode 110.

In an embodiment, the top hat electrode 110 includes a conductive metal selected from the group consisting of tantalum, titanium, tungsten or a metal alloy selected from the group consisting of, tantalum nitride, titanium nitride and tungsten nitride.

Referring again to Figure 1 A, the conductive interconnect 102 is disposed in a first dielectric layer 104 formed above a substrate 150. In an embodiment, the conductive

interconnect 102 includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the first dielectric layer 104 includes an electrically insulating material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the second dielectric layer 108 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the third dielectric layer 112 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the fourth dielectric layer 116 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the first dielectric layer 104, the second dielectric layer 108, the third dielectric layer 112 and the fourth dielectric layer 116 include a silicon oxide.

In an embodiment, the substrate 150 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate 150 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound. Logic devices such as MOSFET transistors and access transistors and may be formed on the substrate 150. Logic devices such as access transistors may be electrically coupled with memory devices such as memory device 106 to form embedded memory through the conductive interconnect 102. Embedded memory including memory devices and logic MOSFET transistors may be combined to form functional integrated circuit such as a system on chip.

Figure IB illustrates a plan view along the A-A' direction of Figure 1 A and depicts the shape and size of the top hat electrode 110 and the memory device 106 in accordance with embodiments of the present disclosure. The top hat electrode 110 and the memory device 106 are illustrated in Figure IB to highlight the relative size and alignment between each element. In an embodiment, the lowermost surface 118 of the top hat electrode 110 has a rectangular profile as illustrated in the plan view illustration of Figure IB and extends over a single memory device 106. In an embodiment, the lowermost surface 118 of the top hat electrode 110 has a width WT, and a length LT. In an embodiment, the width WT, ranges from 50nm-150nm. In an

embodiment, the length LT ranges from 50nm-150nm. In an embodiment, the memory device 106 has a width WD, along the X direction and a length LD along the Y direction. In an embodiment, the memory device 106 has a width WD, between 10nm-50nm and a length LD, between 10nm-50nm.

In an embodiment, the sidewall 124 of the top hat electrode 110 extends beyond the sidewall 126 of the memory device 106 by an amount, Wi in the X direction. In an

embodiment, the sidewall 128 of the top hat electrode 110 extends beyond the sidewall 130 of the memory device 106 by an amount W2 in the Y direction as is depicted in the plan view illustration of Figure IB. In one embodiment, Wi is between 10nm-20nm. In another embodiment, Wi is between 20nm-60nm. In one embodiment, W2 is between 10nm-20nm. In another embodiment, W2 is between 20nm-60nm. In an embodiment, Wi and W2 are both approximately lOnm. In one embodiment, when Wi and W2 are both approximately lOnm, then a maximum allowable mis-alignment between the memory device 106 and the top hat electrode 110 is lOnm in either X or Y direction.

Referring again to Figure 1 A, in an embodiment, the via 114 has a center, C in an X direction as depicted in the cross-sectional illustration of Figure 1 A. In an embodiment, the center, CT, of the top hat electrode 110 is aligned with the center, Cv, of the via 114 along an X direction, as illustrated in Figure 1 A. The lowermost surface 132 of the via 114 has a planar cross-sectional area that is smaller than the planar cross-sectional area of the uppermost surface 120 of the top hat electrode 110. In an embodiment, the lowermost surface 132 of the via 114 has a planar cross-sectional area that is between 5% and 35% of the planar cross-sectional area of the uppermost surface 120 of the top hat electrode 110.

Figure 1C illustrates a plan view along the A-A' direction of Figure 1 A and depicts the shape, size and location of the via 114 in relation to the top hat electrode 110 in accordance with embodiments of the present disclosure. In an embodiment, the via 114 has a width Wv, along the X direction and a length Lv along the Y direction. In an embodiment, the memory device 106 has a width Wv, between 10nm-50nm and a length Lv, between 10nm-50nm.

In an embodiment, the sidewall 124 of the top hat electrode 110 extends beyond the sidewall 134 of the via 114 by an amount, W₃, in the X direction. In one embodiment, W₃ is between 10nm-20nm. In another embodiment, W₃ is between 20nm-60nm. In an embodiment, the sidewall 136 of the top hat electrode 110 extends beyond the sidewall 138 of the via 114 by an amount, W₄, in the Y direction as is depicted in the plan view illustration of Figure 1C. In an embodiment, W₄ is between 10nm-20nm. In another embodiment, W₄ is between 20nm-60nm. Unlike a relatively narrow tolerance for mis-alignment between the top hat electrode 110 and the memory device 106, mis-alignment between the via 114 and the top hat electrode 106 is more relaxed. As will be discussed further below the via 114 can be mis-aligned from the top hat electrode 110 by 10nm-60nm without adversely impacting device functionality.

Referring again to the Figure 1 A, in an embodiment, the via 114 has a thickness between 30nm-70nm. The thickness of the via 114 is designed to be substantially similar to a thickness of a via that is located in a logic region of the substrate. The via located in the logic region has an uppermost surface that is coplanar with the uppermost surface of the via 114 above the top hat electrode 110. In an embodiment, the via 114 includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium.

In one embodiment the uppermost surface 122 of the memory device 106 has a planar cross-sectional profile that is rectangular as is depicted in Figure IB. In another embodiment, the memory device 106 can have an uppermost surface 122 with a planar cross-sectional profile that is circular as is depicted in Figure ID. In one embodiment the lowermost surface 132 of the via 114 has a planar cross-sectional profile that is rectangular as is depicted in Figure 1C. In another embodiment, the via 114 can have a lowermost surface 132 with a planar cross-sectional profile that is circular as is depicted in Figure IE.

Figure IF illustrates a cross-sectional view representing mis-alignment between the top hat electrode 110 and the memory device 106 along an x direction, in accordance with embodiments of the present disclosure. In an embodiment, the center, CT, of the top hat electrode 110 is mis-aligned from the center, CM, of the memory device 106. In an embodiment, the center, CT, of the top hat electrode 110 is mis-aligned from the center, CM, of the memory device (in an X direction) by an amount between 3nm-10nm. In an embodiment, the sidewall 124 of the top hat electrode 110 extends beyond the sidewall 126 of the memory device by a minimum lateral distance, WMIN, as is depicted in the cross-sectional illustration of Figure IF. In an embodiment, the minimum lateral distance, WMIN, between the sidewall of the memory device 106 and the sidewall 124 of the top hat electrode 110 is at least lOnm. In an embodiment, the via 114 is aligned with the top hat electrode 110 as illustrated in Figure IF.

Figure 1G illustrates a cross-sectional view representing mis-alignment between the via 114 and the top hat electrode 110 along an x direction, in accordance with embodiments of the present disclosure. In an embodiment, the center of the top hat electrode 110, CT, is mis-aligned from the center, Cv, of the via 114. In an embodiment, the center, CT, of the top hat electrode 110 is mis-aligned from the center, Cv, of the via 114 by an amount between 3nm-10nm. In an embodiment, the center, CT, of the top hat electrode 110 is mis-aligned from the center, Cv, of the via 114 of the top hat electrode 110 by an amount between 3nm-10nm. In an embodiment, a portion of the via 114 is adjacent to the sidewall 124 of the top hat electrode 110 as depicted in the cross-sectional illustration of Figure IF. In an embodiment, a portion of the via 114 is adjacent to one or more sidewalls (not shown) of the top hat electrode 110. In an embodiment, the via 114 has a lowermost surface 132 that is below the uppermost surface 120 of the top hat electrode 110 as is depicted in the cross-sectional illustration of Figure IF. When a center, CT, of the top hat electrode 110 is mis-aligned from a center, Cv, of the via 114 of the top hat electrode 110, an amount between 4%-20% of the planar cross-sectional surface of the lowermost surface 132 of the via 114 is disposed outside of the uppermost surface 120 of the top hat electrode 110.

In an embodiment, the memory device 106 includes a resistive random access memory (RRAM) device. Figure 2 A illustrates a cross-sectional view of a top hat electrode 110 formed on a memory device such as a resistive random access memory (RRAM) device 200 formed above a conductive interconnect 102. In an embodiment, the RRAM device 200 includes a bottom electrode 202, a switching layer 204 including a metal oxide disposed on the bottom electrode 202, an oxygen exchange layer 206 disposed on the switching layer 204, and a top electrode 208 disposed on the oxygen exchange layer 206. In an embodiment, the RRAM device 200 has a height, HRM, between 60nm-100nm and width between lOnm and 50nm. In an embodiment, the via 114 has a lowermost surface that is entirely disposed on an uppermost surface of the top hat electrode 110 as is depicted in the cross-sectional illustration of Figure 2A.

In an embodiment, the memory device includes a magnetic tunnel junction (MTJ) device. Figure 2B illustrates a cross-sectional view of a top hat electrode 110 formed on a memory device such as a magnetic tunnel junction (MTJ) memory device 250 formed above a conductive interconnect. In an embodiment, the MTJ memory device 250 includes a bottom electrode 252 disposed above the conductive interconnect 102, a fixed magnet 254 disposed above the bottom electrode 252, a tunnel barrier 256 including an MgO disposed on the fixed magnet 254, a free magnet 258 disposed on the tunnel barrier 256 and a top electrode 260 disposed on the free magnet 258. In an embodiment, the MTJ memory device 250 has a height, HMTJ, between 60nm- lOOnm and a width between lOnm and 50nm. In an embodiment, the via 114 has a lowermost surface that is entirely disposed on an uppermost surface of the top hat electrode 110 as is depicted in the cross-sectional illustration of Figure 2 A.

In an embodiment, a memory device has a dielectric spacer disposed laterally on sidewalls. Figure 3A illustrates a memory device 300 where a dielectric spacer 302 is disposed on the sidewalls of the memory device 300 and on a portion of the conductive interconnect 102. In an embodiment, the dielectric spacer 302 extends from a lowermost portion of the memory device 300 and extends to a lowermost surface of a top hat electrode 308. In an embodiment, the dielectric spacer 302 includes an insulating material such as but not limited to silicon nitride, silicon oxynitride or carbon doped silicon nitride. In an embodiment, the dielectric spacer 302 has a thickness between 10nm-30nm.

A top hat electrode 308 is disposed on the memory device 300, on the uppermost surface of the dielectric spacer 302 and on a portion of the second dielectric layer 304. The top hat electrode 308 has sidewalls 310 that extend beyond sidewalls 312 of the dielectric spacer 302 adjacent to the second dielectric layer 304 by a minimum amount, DMIN as depicted in the cross- sectional illustration of Figure 3A. The top hat electrode 308 includes a material that is similar or substantially similar to the material of the top hat electrode 110 described in association with Figure 1A.

In an embodiment, a second dielectric layer 304 is adjacent to dielectric spacer 302 on the sidewall of the memory device. In an embodiment, the second dielectric layer 304 has an uppermost surface that is coplanar with the uppermost surface of the dielectric spacer 302, coplanar with an uppermost surface of the memory device 300. In an embodiment, the second dielectric layer 304 is similar or substantially similar to the second dielectric layer 108 described in association with Figure 1 A.

In an embodiment, the center, CT, of the top hat electrode 308 is aligned with the center,

CM, of the memory device 300 as illustrated in Figure 3A. In other embodiments, the center of the top hat electrode 308 is mis-aligned from the center of the memory device by an amount between 3nm-10nm. In an embodiment, a lateral distance, DMIN, between a sidewall 310 of the top hat electrode 308 and a sidewall 312 of the dielectric spacer 302 is between 0nm-60nm. In an embodiment, the uppermost surface of the memory device has a planar cross-sectional area that is between 2% and 35% of a planar cross-sectional area of the lowermost surface of the top hat electrode 308.

A third dielectric layer 314 is disposed on the second dielectric layer 304, adjacent to the top hat electrode. The third dielectric layer 314 has an uppermost surface that is coplanar or substantially coplanar with an uppermost surface of the top hat electrode 308. The third dielectric layer 314 is similar or substantially similar to the third dielectric layer 112 described in association with Figure 1 A.

A via 318 is disposed on the top hat electrode 308. The via 318 has sidewalls and a lowermost surface in contact with the uppermost surface of the top hat electrode 308. The via 318 includes a material that is similar or substantially similar to the material of the via 114 described in association with Figure 1 A.

In an embodiment, the center, CT, of the top hat electrode 308 is aligned with the center, Cv, of the via 318 as illustrated in Figure 3 A. In other embodiments, the center, CT, of the top hat electrode 308 is mis-aligned from the center, Cv, of the via 318 by an amount between 3nm- lOnm. In an embodiment, the lateral distance, VMIN, between the sidewall 320 of the via 318 and sidewall 310 of the top hat electrode 308 is between 10nm-60nm. In an embodiment, the lowermost surface of the via 318 has a planar cross-sectional area that is between 5% and 35% of a planar cross-sectional area of the lowermost surface of the top hat electrode 308.

Figure 3B illustrates a cross-sectional view of a pair of memory devices 300 A and 300B, depicting the continuity of a dielectric spacer layer 330 across adjacent memory devices, in accordance with an embodiment of the present disclosure.

In an embodiment, a dielectric spacer layer 330 is disposed on the sidewalls of the first memory device 300 A, on a conductive interconnect 102 A, extends on to the first dielectric layer 104 separating the first memory device 300A and the second memory device 300B. The dielectric spacer layer 330 is further disposed on a conductive interconnect 102B and on sidewalls of the second memory device 300B. In an embodiment, a second dielectric layer 340 is disposed on and adjacent to dielectric spacer layer 330. In an embodiment, the dielectric spacer layer 330 includes an insulating material such as but not limited to silicon nitride, silicon oxynitride or carbon doped silicon nitride. In an embodiment, the dielectric spacer layer 330 has a thickness between 5nm-30nm.

In an embodiment, the second dielectric layer 340 includes an insulating material that is substantially the same as the material of the second dielectric layer 304. In an embodiment, the conductive interconnects 102A and 102B each include a material that is substantially the same as the material of the conductive interconnect 102.

In an embodiment, the memory device 300 A and 300B are RRAM devices or MTJ memory devices. In an embodiment, the top hat electrodes 308A and 308B each include a material that is substantially the same as the material of the top hat electrode 110. In an embodiment, the top hat electrodes 308A and 308B are isolated from each other along a first dimension as depicted in the cross-sectional illustration of Figure 3B. In an embodiment, the top hat electrodes 308A and 308B are isolated from each other along a first dimension and along a second dimension, where the second dimension is orthogonal to the first dimension (not shown).

Figures 4A-4K illustrate cross-sectional views of a sequence of operations to co-fabricate an array of memory devices alongside interconnects for logic transistors.

Figure 4A illustrates conductive interconnects formed in a memory region 400 such as conductive interconnects 402A and 402B and conductive interconnects formed in a logic region 450, such as conductive interconnect 452A and 452B. In an embodiment, the conductive interconnects 402A, 402B, 452A and 452B are surrounded by a dielectric layer 401 formed above a substrate 404. In an embodiment, the conductive interconnects 402A, 402B, 452A and 452B are formed in a dielectric layer 401 by a damascene or a dual damascene process that is well known in the art. In an embodiment, the conductive interconnects 402A, 402B, 452A and 452B includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the conductive interconnects 402A, 402B, 452A and 452B are fabricated using a subtractive etch process when materials other than copper are utilized. In an embodiment, the dielectric layer 401 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the dielectric layer 401 has an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnects 402 A, 402B, 452 A and 452B. In an embodiment, the dielectric layer 401 has a total thickness between 90nm -300nm. In an embodiment, conductive interconnects 402A, 402B, 452A and 452B are each electrically connected to a circuit element such as a transistor (not shown). In an embodiment, conductive interconnects 402A and 402B each include one or more vias. In an embodiment, conductive interconnect 402A includes a via 403 A and conductive interconnect 402B includes a via 403B as depicted in the cross-sectional illustration of Figure 4 A. In an embodiment, conductive interconnects 452 A and 452B each include one or more vias. In an embodiment, conductive interconnect 452A includes a pair of vias 453 A, and conductive interconnect 452B includes a pair of vias 453B as depicted in the cross-sectional illustration of Figure 4 A.

Figure 4B illustrates the structure of Figure 4 A following the formation of an etch stop layer 406 on the conductive interconnects 402A, 402B, 452A and 452B and on the first dielectric layer 401, formation of a second dielectric layer 408 on the etch stop layer 406 followed by removal of a portion of the second dielectric layer 408 and a portion of the underlying etch stop layer 406 in the memory region 400, to expose conductive interconnect 402A and conductive interconnect 402B.

In an embodiment, the etch stop layer 406 is blanket deposited using a physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment, the etch stop layer 406 may be any suitable dielectric material such as but not limited to carbon doped silicon nitride or silicon nitride. An etch stop layer 406 including a nitride of silicon acts as an etch stop while etching the second dielectric layer 408 above. In an embodiment, the etch stop layer 406 has a thickness that ranges from 10nm-50nm. In an embodiment, the second dielectric layer 408 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the second dielectric layer 408 is blanket deposited using a physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment, the second dielectric layer 408 is deposited to a total thickness between 80nm- 150nm. In an embodiment, the second dielectric layer 408 has an uppermost surface that is approximately coplanar with uppermost surfaces of memory devices that will be subsequently formed in the memory region 400.

In an embodiment, a photoresist mask with an opening in the memory region 400 is formed on the second dielectric layer 408. The photoresist mask covers the logic region 450. In an embodiment, a plasma etch process is utilized to etch the second dielectric layer 408 and stop on the etch stop layer 406. In an embodiment, a second subsequent plasma etch process is utilized to etch the etch stop layer 406 selectively to the conductive interconnects 402A and 402B and the first dielectric layer 401. The second etch process exposes the conductive interconnects 402 A and 402B and the first dielectric layer 401.

Figure 4C illustrates the structure of Figure 4B following the formation of a memory material layer stack 410 in the memory region 400 and in the logic region 450 of the substrate to form memory devices in the memory region 400 of the substrate 404. In an embodiment, the memory material layer stack 410 is blanket deposited on the exposed conductive interconnects 402 A and 402B, on the first dielectric layer 401, on an exposed sidewall of the etch stop layer 406, on an exposed sidewall and on the uppermost surface of the second dielectric layer 408. In an embodiment, the memory material layer stack 410 includes at least 3 or more layers to fabricate magnetic tunnel junction (MTJ) memory devices. In an embodiment, the memory material layer stack 410 includes at least 3 or more layers to fabricate resistive random access memory (RRAM) devices.

Figure 4D illustrates the structure of Figure 4C following the formation of memory devices 412A and 412B in the memory region 400. In an embodiment, a photoresist mask is formed on an uppermost surface of the memory material layer stack 410. In an embodiment, the memory material layer stack 410 is plasma etched. In an embodiment, the plasma etch forms a memory device 412A on the conductive interconnect 402 A and a memory device 412B on the conductive interconnect 402B.

In an embodiment, the process of plasma etch leaves a memory spacer 412C on the dielectric layer 401, adjacent to the sidewall of the etch stop layer 406 and adjacent to the sidewall of the second dielectric layer 408.

Figure 4E illustrates the structure of Figure 4D following a blanket deposition of a dielectric spacer layer 414 in the memory region 400 and in the logic region 450 of the substrate 404. In an embodiment, the dielectric spacer layer 414 is blanket deposited using a physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment, the dielectric spacer layer 414 is blanket deposited and covers the memory device 412A and the memory device 412B, conductive interconnects 402 A and 402B and the first dielectric layer 401. The dielectric spacer layer 414 is also deposited on the memory spacer 412C and on the second dielectric layer 408.

In an embodiment, the dielectric spacer layer 414 may be any suitable dielectric material such as but not limited to carbon doped silicon nitride or silicon nitride. A dielectric spacer layer 414 including a silicon nitride acts as a polish stop while planarizing a dielectric layer that will deposited and planarized in a subsequent process operation. In an embodiment, the dielectric spacer layer 414 has a thickness that ranges from 10nm-30nm.

In an embodiment, the dielectric spacer layer 414 can be etched (not shown) before a subsequent operation to deposit a third dielectric layer. If the dielectric spacer layer 414 is etched, then dielectric spacers are formed adjacent to sidewalls of the memory devices 412A and 412B. In an embodiment, an isolated dielectric spacer will also be formed adjacent to the memory spacer 412C.

Figure 4F illustrates the structure of Figure 4E following the deposition of a third dielectric layer 416 over the memory region 400 and the logic region 450 and a planarization process to expose uppermost portions of the memory devices 412A and 412B. In an

embodiment, the third dielectric layer 416 is blanket deposited using a physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment, the third dielectric layer 416 is deposited to a total thickness between 120nm - 150nm. In an embodiment, the third dielectric layer 416 is planarized. In an embodiment, the planarization process includes a polish process and leaves the third dielectric layer 416 in the memory region 400 and removes the third dielectric layer 416 completely from the logic region 450. The planarization process in continued until the dielectric spacer layer 414 is removed from the uppermost surface of the memory devices 412A and 412B. The polish process also removes the dielectric spacer layer 414 from above the second dielectric layer 408 in the logic region 450. In an embodiment, a vertical portion 414B of the dielectric spacer layer 414 adjacent to the memory spacer 412C of the memory material layer stack 410 remains after the planarization process. The planarization process leaves the third dielectric layer 416, the memory devices 412A and 412B, portions of the dielectric spacer layer 414, the memory spacer 412C and the second dielectric layer 408 having uppermost surfaces that are coplanar or substantially coplanar.

Figure 4G illustrates the structure of Figure 4F following the deposition of a top hat electrode layer 418. In an embodiment, the top hat electrode layer 418 is blanket deposited using a physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. The top hat electrode layer 418 includes a conductive metal selected from the group consisting of tantalum, titanium, tungsten or a metal alloy selected from the group consisting of, tantalum nitride, titanium nitride and tungsten nitride. In an embodiment, the top hat electrode layer 418 has a thickness between 40nm-70nm. In an embodiment, the top hat electrode layer 418 has a thickness chosen to accommodate a subsequent formation of a second set of conductive interconnects in the logic region 450. An uppermost portion of the top hat electrode layer 418 will also be sacrificed during a subsequent planarization process.

Figure 4H illustrates the structure of Figure 4G following the formation of top hat electrodes 420A and 420B above memory device 412A and memory device 412B, respectively. In an embodiment, a photoresist mask is formed above the top hat electrode layer 418. In an embodiment, the top hat electrode layer 418 is plasma etched to form the top hat electrodes 420A and 420B. The plasma etching process removes the top hat electrode layer 418 from the logic region 450. In an embodiment, the top hat electrodes 420A and 420B include a material such as TiN, TaN, Ta, W or WN. In an embodiment, the top hat electrode 420A has a width that is greater than a width of the memory device 412A and the top hat electrode 420B has a width that is greater than a width of the memory device 412B as illustrated in Figure 4H. In an

embodiment, the width of the top hat electrode 420A is substantially the same as the width of the top hat electrode 420B. In an embodiment, the width of the top hat electrode 420A is larger than the width of the top hat electrode 420B. In an embodiment, the sidewall of the top hat electrode 420A or 420B may be slightly tapered as a result of the plasma etch process.

In an embodiment, the top hat electrode 420A can be mis-aligned from the memory device 412A. In an embodiment, when the top hat electrode 420A is mis-aligned from the memory device 412A, the top hat electrode 420B is also mis-aligned from the memory device 412B. In an embodiment, the mis-alignment between top hat electrode 420A and memory device 412A is between 3nm-10nm. In an embodiment, the mis-alignment between top hat electrode 420B and memory device 412B is between 3nm-10nm.

Figure 41 illustrates the structure of Figure 4H following the deposition of a fourth dielectric layer 422 over the top hat electrodes 420 A and 420B, on the third dielectric layer 416, on the portion of the dielectric spacer 414B, on the memory spacer 412C and on the second dielectric layer 408, followed by a planarization process to expose uppermost surfaces of the top hat electrodes 420 A and 420B.

In an embodiment, the fourth dielectric layer 422 is substantially similar to the material of the second dielectric layer 408. Forming a fourth dielectric layer 422 that is substantially similar to the material of the second dielectric layer 408 facilitates the formation of a second set of conductive interconnects in the logic region 450. In an embodiment, the planarization process utilized to remove portions of the fourth dielectric layer 422 is similar to the planarization process utilized to remove portions of the third dielectric layer 416. In an embodiment, uppermost surfaces of the top hat electrode 420A and 420B and uppermost surface of the fourth dielectric layer 422 are coplanar or substantial coplanar after the planarization process.

Figure 4 J illustrates the structure of Figure 41 following the formation of pairs of vias 456A and 456B and a second set of conductive interconnects 454A and 454B in the logic region 450. In an embodiment, the process of forming the pairs of vias 456A and 456B and the conductive interconnects 454A and 454B in the logic region 450 involves a conventional dual damascene processes. In an embodiment, the process involves forming openings in the fourth dielectric layer 422 and in the second dielectric layer 408. In an embodiment, a pair of vias 456A are formed under the conductive interconnect 454A and a pair of vias 456B are formed under the conductive interconnect 454B. In an embodiment, the conductive interconnects 454 A and 454B have uppermost surfaces that are coplanar or substantially coplanar to uppermost surfaces of the top hat electrodes 420 A and 420B.

In an embodiment, the memory device 412A and the top hat electrode 402 A have a combined height, HMT, that is approximately equal to a combined height, Hcv, of the conductive interconnect 454A and pair of vias 456A. In an embodiment, the height of the memory devices 412A and 412B and the top hat electrodes 420A and 420B can be adjusted depending on the height of the second set of conductive interconnects 454A and 454B and on the height of the pairs of vias 456A and 456B.

Figure 4K illustrates the structure of Figure 4 J following the formation of memory vias 43 OA and 430B and a memory conductive interconnect 428 connecting the memory vias 43 OA and 430B, in the memory region 400 and the formation of a third set of conductive interconnects 458A and 458B and pairs of vias 460A and 460B in the logic region 450.

In an embodiment, prior to forming conductive interconnects and vias, a second etch stop layer 424 is deposited in the memory region 400 and in the logic region 450. In an embodiment, the second etch stop layer 424 is blanket deposited on the fourth dielectric layer 422, on the top hat electrode 420A, top hat electrode 420B, and on the second set of conductive interconnects 454A and 454B. The deposition process and materials utilized to form the second etch stop layer 424 is similar or substantially similar to the deposition process and materials utilized to form the etch stop layer 406. A fifth dielectric layer 426 is disposed on the second etch stop layer 424. The deposition process and materials utilized to form the fifth dielectric layer 426 is similar or substantially similar to the deposition process and materials utilized to form the fourth dielectric layer 422.

In an embodiment, the process of forming the third set of conductive interconnects 458 A and 458B in the logic region 450 includes materials and a conventional dual damascene processes similar to the materials and processes utilized to form the second set of conductive interconnects 454 A and 454B. In an embodiment, the process of forming the third pair of vias 460A and 460B in the logic region 450 includes materials and a conventional dual damascene processes similar to the materials and processes utilized to form the second pair of vias 456A and 456B. In an embodiment, the dual damascene process involves forming openings in the dielectric layer 426 in the logic region 450.

In an embodiment, the memory via 430A is formed on the top hat electrode 420A and the memory via 430B is formed on the top hat electrode 420B. In an embodiment, the memory via 43 OA and the memory via 430B are formed by a conventional dual damascene process. In an embodiment, the memory via 430A can be mis-aligned from the top hat electrode 420A. In an embodiment, the memory via 430B can be mis-aligned from the top hat electrode 420B. In an embodiment, the mis-alignment between memory via 430A and top hat electrode 420A and the mis-alignment between memory via 430B and top hat electrode 420B are each between 3nm- lOnm. In an embodiment, the memory via 430A and the memory via 430B are physically connected together by a conductive interconnect 428.

Figure 5 illustrates a cross-sectional view of a memory device such as a memory device 300 including a top hat electrode, such as a top hat electrode 308. In an embodiment, the memory device 300 is formed on a conductive interconnect, such as a conductive interconnect 502 that is coupled to an access transistor 508, in accordance with embodiments of the present disclosure. In an embodiment, the top hat electrode 308 is disposed on a memory device such as a memory device 300. The top hat electrode 308 is also disposed above a dielectric spacer such as the dielectric spacer 302. The dielectric spacer 302 is surrounded by a second dielectric layer 524 that is substantially the same as the dielectric layer 503. The top hat electrode 308 is surrounded by a third dielectric layer 526. In an embodiment, the third dielectric layer 526 is substantially the same as the second dielectric layer 524. A via 542 is disposed in a fourth dielectric layer 528 on the top hat electrode 308. Via 542 is substantially the same as the via 43 OA described in association with Figure 4K.

In an embodiment, a memory device 300, is disposed on a conductive interconnect 302. In an embodiment, the memory device 300 has a width that is less than a width of the conductive interconnect 302. In one such embodiment, the memory device 300 is confined to the conductive interconnect 302. The conductive interconnect 502 is similar or substantially similar to conductive interconnect 102 described in association with Figure 3 A.

In an embodiment, the conductive interconnect 502 is disposed on a contact structure

504 above a drain region 506 of an access transistor 508 disposed above a substrate 510. In an embodiment, a gate contact 520 and a source contact 522 are formed in the dielectric layer 503 above a gate electrode layer 512 and source region 518, respectively.

In an embodiment, a gate conductive interconnect 532 is disposed on and electrically coupled with the gate contact 520 and a source conductive interconnect 534 is disposed on and electrically coupled with the source contact 522. The gate conductive interconnect 532 and the source conductive interconnect 534 are disposed in the dielectric layer 503. The gate conductive interconnect 532, the source conductive interconnect 534 and the conductive interconnect 502 have uppermost surfaces that are coplanar or substantially co-planar. In an embodiment, via 544 is disposed in the second dielectric layer 524, the third dielectric layer 526 and in the fourth dielectric layer 528 on the gate conductive interconnect 532. In an embodiment, via 546 is disposed in the second dielectric layer 524, the third dielectric layer 526 and in the fourth dielectric layer 528 on the source conductive interconnect 534. Via 542, 544 and 546 have uppermost surfaces that are planar or substantially co-planar with each other and with the fourth dielectric layer 528.

In an embodiment, the underlying substrate 510 represents a surface used to manufacture integrated circuits. In an embodiment, suitable substrate 510 includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, the substrate 510 includes other semiconductor materials such as germanium, silicon germanium, or a suitable group III-V or group III-N compound. In an embodiment, the substrate 510 may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, the access transistor 508 associated with substrate 510 are metal- oxide- semi conductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 510. In various implementations of the invention, the access transistor 508 may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

In an embodiment, the access transistor 508 of substrate 510 includes a gate stack formed of at least two layers, a gate dielectric layer 514 and a gate electrode layer 512. The gate dielectric layer 514 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 514 to improve its quality when a high-k material is used.

The gate electrode layer 512 of the access transistor 508 of substrate 510 is formed on the gate dielectric layer 514 and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an MOS transistor. In some implementations, the gate electrode layer 512 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode layer 512 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode layer 512 with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode layer 512 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode layer 512 with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode layer 512 may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode layer 512 may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode layer 512 may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode layer 512 may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the invention, a pair of sidewall spacers 516 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers 516 may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source region 518 and drain region 506 are formed within the substrate adjacent to the gate stack of each MOS transistor. The source region 518 and drain region 506 are generally formed using either an implantation/diffusion process or an

etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 518 and drain region 506. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 518 and drain region 506. In some implementations, the source region 518 and drain region 506 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further

embodiments, the source region 518 and drain region 506 may be formed using one or more alternate semiconductor materials such as germanium or a suitable group III-V compound. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 518 and drain region 506.

Figure 6 illustrates a computing device 600 in accordance with one embodiment of the disclosure. The computing device 600 houses a board 602. The board 602 may include a number of components, including but not limited to a processor 604 and at least one

communication chip 606. The processor 604 is physically and electrically coupled to the board 602. In some implementations the at least one communication chip 606 is also physically and electrically coupled to the board 602. In further implementations, the communication chip 606 is part of the processor 604.

Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to the board 602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 606 enables wireless communications for the transfer of data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 606 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.11 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 600 may include a plurality of communication chips 606. For instance, a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more memory elements such as a resistive random access memory (RRAM) device 200 having a top hat electrode 110. In another embodiment, the integrated circuit die of the processor includes one or more memory elements, such as a magnetic tunnel junction (MTJ) memory device 250 with a top hat electrode 110. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 606 also includes an integrated circuit die packaged within the communication chip 606. In accordance with another implementation of an embodiment of the disclosure, the integrated circuit die of the communication chip includes at least one memory device 300 with top hat electrode 308 integrated with an access transistor such as access transistor 508 described in association with Figure 5, built in accordance with embodiments of the present disclosure. In further implementations, another component housed within the computing device 600 may contain a stand-alone integrated circuit memory die that includes one or more memory elements, built in accordance with embodiments of the present disclosure.

In various implementations, the computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other electronic device that processes data.

Figure 7 illustrates an integrated circuit (IC) structure that includes one or more embodiments of the present disclosure. The integrated circuit (IC) structure 700 is an

intervening substrate used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 may be, for instance, an integrated circuit die. The second substrate 704 may be, for instance, a memory module, a computer mother, or another integrated circuit die. In an embodiment, the memory module includes at least one memory device such as a memory device 300 with a top hat electrode 308 described above. Generally, the purpose of an integrated circuit (IC) structure 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure 700 may couple an integrated circuit die to a ball grid array (BGA) 706 that can subsequently be coupled to the second substrate 704. In some embodiments, the first and second substrates 702/704 are attached to opposing sides of the integrated circuit (IC) structure 700. In other embodiments, the first and second substrates 702/704 are attached to the same side of the integrated circuit (IC) structure 700. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 700.

The integrated circuit (IC) structure 700 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The integrated circuit (IC) structure may include metal interconnects 708 and vias 710, including but not limited to through-silicon vias (TSVs) 710. The integrated circuit (IC) structure 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, memory devices including at least one memory device 300 with top hat electrode 308, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 700. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 700.

Accordingly, one or more embodiments of the present disclosure relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present disclosure relate to the fabrication of a memory device with a top hat electrode such as a memory device 300 with a top hat electrode 308. Such a memory device 300 with a top hat electrode 308 may be used in an embedded non-volatile memory application.

Thus, embodiments of the present disclosure include a top hat electrode for memory applications and methods of fabrication.

Example 1 : An apparatus includes a conductive interconnect disposed above a substrate. A memory device is disposed above the conductive interconnect and coupled with the conductive interconnect. The memory device has sidewalls and an uppermost surface. A conductive electrode is disposed on the memory device, where the conductive electrode has sidewalls, a lowermost surface and an uppermost surface, and where the sidewalls of the conductive electrode extend beyond the sidewalls of the memory device. A via is disposed on the conductive electrode. The via has sidewalls and a lowermost surface in contact with the uppermost surface of the conductive electrode.

Example 2: The apparatus of example 1, wherein the conductive electrode includes a conductive metal selected from the group consisting of tantalum, titanium, tungsten or a metal alloy selected from the group consisting of, tantalum nitride, titanium nitride and tungsten nitride.

Example 3 : The apparatus of example 1 or 2, wherein the conductive electrode has a center along a horizontal direction that is aligned with a center along a horizontal direction of the memory device.

Example 4: The apparatus of example 1 or 2, wherein the conductive electrode has a center along a horizontal direction that is mis-aligned with a center along a horizontal direction of the memory device by an amount between 3nm-10nm.

Example 5: The apparatus of example 1 or 2, wherein the sidewalls of the conductive electrode extend beyond the sidewalls of the memory device by an amount between 10nm-60nm.

Example 6: The apparatus of example 1, wherein the uppermost surface of the memory device has a planar cross-sectional area that is between 2% and 35% of a planar cross-sectional area of the lowermost surface of the conductive electrode.

Example 7: The apparatus of example 1, wherein the lowermost surface of the via has a planar cross-sectional area that is between 5% and 35% of a planar cross-sectional area of the uppermost surface of the conductive electrode.

Example 8: The apparatus of example 1, wherein a portion of the via is adjacent to one or more sidewalls of the conductive electrode.

Example 9: The apparatus of example 1, wherein the via has a center along a horizontal direction that is aligned from a center along a horizontal direction of the conductive electrode.

Example 10: The apparatus of example 1 or 9, wherein the via has a center along a horizontal direction that is mis-aligned from a center along a horizontal direction of the conductive electrode by an amount between 3nm-10nm.

Example 11 : An apparatus includes a conductive interconnect disposed above a substrate. A first dielectric layer laterally surrounds the conductive interconnect and a memory device is disposed on the conductive interconnect and coupled with the conductive interconnect. The memory device has sidewalls and an uppermost surface. A dielectric spacer is disposed on the conductive interconnect, laterally adjacent to the memory device, the dielectric spacer has sidewalls and an uppermost surface. The apparatus further includes a second dielectric layer laterally adjacent to the sidewalls of the dielectric spacer. The second dielectric layer has an uppermost surface coplanar with the uppermost surface of the dielectric spacer and coplanar with the uppermost surface of the memory device. A conductive electrode is disposed on the memory device, on the uppermost surface of the dielectric spacer and on a portion of the second dielectric layer. The conductive electrode has sidewalls, a lowermost surface and an uppermost surface, wherein the sidewalls of the conductive electrode extend beyond sidewalls of the dielectric spacer adjacent to the second dielectric layer. A third dielectric layer laterally surrounds the sidewalls of the conductive electrode. A via is disposed on the conductive electrode, the via has sidewalls and a lowermost surface that is in contact with the uppermost surface of the conductive electrode.

Example 12: The apparatus of example 11, wherein the conductive electrode includes a conductive metal selected from the group consisting of tantalum, titanium, tungsten or a metal alloy selected from the group consisting of, tantalum nitride, titanium nitride and tungsten nitride.

Example 13 : The apparatus of example 11, wherein the conductive electrode has a center along a horizontal direction that is aligned with a center along a horizontal direction of the memory device.

Example 14: The apparatus of example 13, wherein the center along a horizontal direction of the conductive electrode is mis-aligned from the center along a horizontal direction of the memory device by an amount between 3nm-10nm.

Example 15: The apparatus of example 11, wherein the uppermost surface of the memory device has a planar cross-sectional area that is between 2% and 35% of a planar cross- sectional area of the lowermost surface of the conductive electrode.

Example 16: The apparatus of example 11, wherein the lowermost surface of the via has a planar cross-sectional area that is between 5% and 35% of a planar cross-sectional area of the uppermost surface of the conductive electrode.

Example 17: The apparatus of example 11, wherein a portion of the via is adjacent to the sidewalls of the conductive electrode.

Example 18: The apparatus of example 11, wherein conductive electrode has a center along a horizontal direction that is mis-aligned from a center along a horizontal direction of the conductive electrode by an amount between 3nm-10nm.

Example 19: The apparatus of example 11, wherein the dielectric spacer is a continuous layer over the conductive interconnect and over the first dielectric layer.

Example 20: The apparatus of example 11, wherein the dielectric spacer extends over the dielectric layer onto an uppermost surface of a conductive interconnect of an adjacent second memory device.

Example 21 : A method of fabricating an apparatus includes forming a conductive interconnect in a first dielectric layer above a substrate. The method further includes forming a memory device on the conductive interconnect, forming a dielectric spacer on the sidewalls of the memory device and on the conductive interconnect. The method further forming a second dielectric layer on the memory device and on the dielectric spacer, planarizing the second dielectric layer, an uppermost portion of the memory device and portions of the dielectric spacer. The method further forming a conductive electrode layer on the memory device, on an uppermost surface of the dielectric spacer and on the second dielectric layer. The method further includes patterning the conductive electrode layer to form a conductive electrode, depositing a third dielectric layer on the conductive electrode and on the second dielectric layer. The method further includes planarizing the third dielectric layer and an uppermost portion of the conductive electrode and depositing a fourth dielectric layer on the conductive electrode and on the third dielectric layer. The method further includes forming a via on the conductive electrode layer in the fourth dielectric layer.

Example 22: The method of example 21, wherein forming the dielectric spacer includes depositing the dielectric spacer layer on the first dielectric layer separating a first conductive interconnect and a conductive interconnect of an adjacent memory device. Example 23 : The method of example 22, wherein forming the dielectric spacer further includes etching the dielectric spacer layer before depositing the second dielectric layer.

Example 24: The method of example 21, wherein planarizing the second dielectric layer includes planarizing an uppermost portion of the dielectric spacer formed on an uppermost surface of the memory device.

Claims

What is claimed is: 1. An apparatus, comprising:

a conductive interconnect above a substrate;

a memory device above the conductive interconnect and coupled with the conductive interconnect, the memory device having sidewalls and an uppermost surface;

a conductive electrode on the memory device, the conductive electrode having sidewalls, a lowermost surface and an uppermost surface, wherein the sidewalls of the conductive electrode extend beyond the sidewalls of the memory device; and

a via on the conductive electrode, the via having sidewalls and a lowermost surface in contact with the uppermost surface of the conductive electrode.

2. The apparatus of claim 1, wherein the conductive electrode includes a conductive metal selected from the group consisting of tantalum, titanium, tungsten or a metal alloy selected from the group consisting of, tantalum nitride, titanium nitride and tungsten nitride.

3. The apparatus of claim 1, wherein the conductive electrode has a center along a horizontal direction that is aligned with a center along a horizontal direction of the memory device.

4. The apparatus of claim 1, wherein the conductive electrode has a center along a horizontal direction that is mis-aligned from a center along a horizontal direction of the memory device by an amount between 3nm-10nm.

5. The apparatus of claim 1, wherein the sidewalls of the conductive electrode extend beyond the sidewalls of the memory device by an amount between 10nm-60nm.

6. The apparatus of claim 1, wherein the uppermost surface of the memory device has a planar cross-sectional area that is between 2% and 35% of a planar cross-sectional area of the lowermost surface of the conductive electrode.

7. The apparatus of claim 1, wherein the lowermost surface of the via has a planar cross- sectional area that is between 5% and 35% of a planar cross-sectional area of the uppermost surface of the conductive electrode.

8. The apparatus of claim 1, wherein a portion of the via is adjacent to one or more sidewalls of the conductive electrode.

9. The apparatus of claim 1, wherein the via has a center along a horizontal direction that is aligned from a center along a horizontal direction of the conductive electrode.

10. The apparatus of claim 9, wherein the via has a center along a horizontal direction that is mis-aligned from a center along a horizontal direction of the conductive electrode by an amount between 3nm-10nm.

11. An apparatus, comprising:

a conductive interconnect above a substrate;

a first dielectric layer laterally surrounding the conductive interconnect;

a dielectric spacer on the conductive interconnect, laterally adjacent to the memory device, the dielectric spacer having sidewalls and an uppermost surface;

a second dielectric layer laterally adjacent to the sidewalls of the dielectric spacer, the second dielectric layer having an uppermost surface coplanar with the uppermost surface of the dielectric spacer and coplanar with the uppermost surface of the memory device;

a conductive electrode on the memory device, on the uppermost surface of the dielectric spacer and on a portion of the second dielectric layer, the conductive electrode having sidewalls, a lowermost surface and an uppermost surface, wherein the sidewalls of the conductive electrode extend beyond sidewalls of the dielectric spacer adjacent to the second dielectric layer;

a third dielectric layer laterally surrounding the sidewalls of the conductive electrode; and a via on the conductive electrode, the via having sidewalls and a lowermost surface in contact with the uppermost surface of the conductive electrode.

12. The apparatus of claim 11, wherein the conductive electrode includes a conductive metal selected from the group consisting of tantalum, titanium, tungsten or a metal alloy selected from the group consisting of, tantalum nitride, titanium nitride and tungsten nitride.

13. The apparatus of claim 11, wherein the conductive electrode has a center along a horizontal direction that is aligned with a center along a horizontal direction of the memory device.

14. The apparatus of claim 13, wherein the center along a horizontal direction of the conductive electrode is mis-aligned from the center along a horizontal direction of the memory device by an amount between 3nm-10nm.

15. The apparatus of claim 11, wherein the uppermost surface of the memory device has a planar cross-sectional area that is between 2% and 35% of a planar cross-sectional area of the lowermost surface of the conductive electrode.

16. The apparatus of claim 11, wherein the lowermost surface of the via has a planar cross- sectional area that is between 5% and 35% of a planar cross-sectional area of the uppermost surface of the conductive electrode.

17. The apparatus of claim 11, wherein a portion of the via is adjacent to the sidewalls of the conductive electrode.

18. The apparatus of claim 11, wherein conductive electrode has a center along a horizontal direction that is mis-aligned from a center along a horizontal direction of the conductive el ectrode by an amount b etween 3 nm- 1 Onm .

19. The apparatus of claim 11, wherein the dielectric spacer is a continuous layer over the conductive interconnect and over the first dielectric layer.

20. The apparatus of claim 11, wherein the dielectric spacer extends over the dielectric layer onto an uppermost surface of a conductive interconnect of an adjacent second memory device.

21. A method of fabricating an apparatus:

forming a conductive interconnect in a first dielectric layer above a substrate;

forming a memory device on the conductive interconnect;

forming a dielectric spacer on the sidewalls of the memory device and on the conductive interconnect;

forming a second dielectric layer on the memory device and on the dielectric spacer; planarizing the second dielectric layer, an uppermost portion of the memory device and portions of the dielectric spacer; forming a conductive electrode layer on the memory device, on an uppermost surface of the dielectric spacer and on the second dielectric layer;

patterning the conductive electrode layer to form a conductive electrode;

depositing a third dielectric layer on the conductive electrode and on the second dielectric layer;

planarizing the third dielectric layer and an uppermost portion of the conductive electrode;

depositing a fourth dielectric layer on the conductive electrode and on the third dielectric layer; and

forming a via on the conductive electrode layer in the fourth dielectric layer.

22. The method of claim 21, wherein forming the dielectric spacer includes depositing the dielectric spacer layer on the first dielectric layer separating a first conductive interconnect and a conductive interconnect of an adjacent memory device.

23. The method of claim 22, wherein forming the dielectric spacer further includes etching the dielectric spacer layer before depositing the second dielectric layer.

24. The method of claim 21, wherein planarizing the second dielectric layer includes planarizing an uppermost portion of the dielectric spacer formed on an uppermost surface of the memory device.