WO2018236331A1

WO2018236331A1 - Metal structures for integrated circuit components

Info

Publication number: WO2018236331A1
Application number: PCT/US2017/038055
Authority: WO
Inventors: Yang Cao; Akm Shaestagir CHOWDHURY; Christopher D. Thomas; Jeffrey GRUNES; Chi-Hwa Tsang
Original assignee: Intel Corporation
Priority date: 2017-06-18
Filing date: 2017-06-18
Publication date: 2018-12-27

Abstract

Disclosed herein are metal structures for integrated circuit (IC) components, as well as related methods and devices. In some embodiments, an IC component may include a metal interconnect and an electrolessly-deposited metal capping layer on the metal interconnect. In some embodiments, an IC component may include a dielectric material and a via extending through the dielectric material. The via may include a metal fill, and the metal fill may include electrolessly-deposited cobalt.

Description

METAL STRUCTURES FOR INTEGRATED CIRCUIT COMPONENTS

Background

[0001] In conventional integrated circuit (IC) components (e.g., dies, package substrates, interposers, etc.), copper is frequently deposited using conventional techniques to form conductive interconnects within the component.

Brief Description of the Drawings

[0002] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0003] FIGS. 1-9 illustrate stages in an example process of manufacturing metal structures in an integrated circuit (IC) component, in accordance with various embodiments.

[0004] FIGS. 10-13 illustrate stages in another example process of manufacturing metal structures in an IC component, in accordance with various embodiments.

[0005] FIG. 14 is a flow diagram of a method of depositing a metal on a surface, in accordance with various embodiments.

[0006] FIG. 15 is a top view of a wafer and dies that may include a metal structure, in accordance with any of the embodiments disclosed herein.

[0007] FIG. 16 is a cross-sectional side view of an IC device that may include a metal structure, in accordance with any of the embodiments disclosed herein.

[0008] FIG. 17 is a cross-sectional side view of an IC package that may include a metal structure, in accordance with various embodiments.

[0009] FIG. 18 is a cross-sectional side view of an IC device assembly that may include a metal structure, in accordance with any of the embodiments disclosed herein.

[0010] FIG. 19 is a block diagram of an example electrical device that may include a metal structure, in accordance with any of the embodiments disclosed herein.

Detailed Description

[0011] Disclosed herein are metal structures for integrated circuit (IC) components, as well as related methods and devices. In some embodiments, for example, an IC component may include a metal interconnect and an electrolessly-deposited metal capping layer on the metal interconnect. In some embodiments, an IC component may include a dielectric material and a via extending through the dielectric material. The via may include a metal fill, and the metal fill may include an electrolessly-deposited cobalt. [0012] Some conventional IC components have used conventionally deposited copper interconnects, relying on copper's high bulk conductivity. However, as electrical features (e.g., lines and vias) become smaller, the advantages of conventional copper's high bulk conductivity may be offset by its tendency to diffuse into surrounding materials after deposition. To mitigate this diffusion, conventional copper interconnects may include a diffusion barrier, but the barriers themselves take up space in the device, shrinking the amount of copper that can be included (and consequently increasing the resistance of the interconnect). New techniques for depositing copper, and other metals, may provide performance and/or manufacturing advantages. For example, cobalt has a lower bulk conductivity than copper, but may be less likely to electromigrate into neighboring materials, and thus may not require a thick diffusion barrier. For small interconnects, therefore, cobalt may be a promising material. Further, other metal structures using different materials, such as capping layers, may be advantageously included in an IC component (e.g., along with

conventional copper interconnects).

[0013] Conventional metal deposition techniques, however, have been limited in their ability to deposit cobalt and other metals with a sufficiently high purity to achieve an acceptably low resistance. For example, some conventional chemical vapor deposition (CVD) techniques for cobalt deposition may include carbon in an amount of 3% or more. The resistivity of such CVD cobalt may be too high for use in an interconnect other conductive structure. Electroplated cobalt may be purer than CVD cobalt, but conventional electroplating techniques for cobalt deposition may require a thick seed layer (deposited, e.g., by CVD) in order to achieve sufficient conductivity of the deposition surface. When the features to be filled with the electroplated cobalt are small or thin, the thick (and less pure) seed layer may fill or substantially fill the available volume, leaving little to no room for the purer electroplated film. Some conventional physical vapor deposition (PVD) techniques for cobalt deposition may result in "pinch off" of the cobalt at the top of a high aspect ratio feature, leaving an unacceptable void.

[0014] Disclosed herein are electroless metal deposition techniques that may be used to create highly pure metal structures. For example, various ones of the techniques disclosed herein may be used to deposit highly pure metals in small cavities (and thereby create small metal features). In another example, the metal deposition techniques disclosed herein may be used to form

interconnects and/or capping layers in an IC component (e.g., a die, a package substrate, an interposer, etc.) to route electrical signals. In particular, metal structures, and techniques for forming such structures, are disclosed herein. The metal structures disclosed herein may be significantly more pure than would be achievable using conventional deposition techniques, meeting and exceeding the threshold for use in modern IC components. Some interconnects formed using the techniques disclosed herein may be in contact with a device layer of the IC component (e.g., as discussed below with reference to FIG. 16) and/or in contact with other interconnects (e.g., in interconnect layers that are higher up in a metallization stack, as discussed below with reference to FIG. 16).

[0015] The "metal structures" disclosed herein may include structures (e.g., vias, lines, and/or capping layers) formed of any suitable metal, such as cobalt, copper, nickel, platinum, gold, ruthenium, or palladium, or binary or ternary alloys of these metals. Additionally, although particular metal structures are illustrated in the accompanying drawings, the techniques disclosed herein may be used to form any suitable metal structures, such as contact pads or other conductive structures.

[0016] In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0017] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0018] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.

[0019] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a "package" and an "IC package" are synonymous. When used to describe a range of dimensions, the phrase "between X and Y" represents a range that includes X and Y.

[0020] FIGS. 1-9 illustrate stages in an example process of manufacturing metal structures 100 in an IC component, in accordance with various embodiments. In particular, FIGS. 1-9 illustrate a dual Damascene process that may be used to form metal vias 100b and metal lines 100a. The use of a dual Damascene process setting is simply illustrative, and the electroless metal deposition techniques (and the resulting metal fills) disclosed herein may be used in any desired process (e.g., subtractive, additive, single Damascene, etc.). Although FIGS. 1-9 show the formation of metal structures 100 in contact with lines 107 in a lower interconnect layer, this is simply for ease of illustration, and the metal structures 100 disclosed herein may contact any suitable structures, such as the gates or source/drain regions of transistors, or other devices, in a device layer (e.g., as discussed below with reference to FIG. 16).

[0021] FIG. 1 is a side cross-sectional view of an assembly 500 including a first interconnect layer 140-1, an etch stop material 191 on the first interconnect layer 140-1, and an insulating material 190 on the etch stop material 191. The use of the term "first" to refer to the interconnect layer 140-1 does not imply that the interconnect layer 140-1 is the Ml (or "bottommost") layer in a metallization stack; the term "first" is simply used to identify the interconnect layer 140-1. Generally speaking, the first interconnect layer 140-1 may be any layer in a metallization stack. Metallization stacks are discussed in further detail below with reference to FIG. 16. Further, as noted above, the techniques disclosed herein may be used to form metal structures 100 in contact with the device layer of a die; in such embodiments, the first interconnect layer 140-1 may be replaced with the device layer (e.g., as discussed below with reference to FIG. 16).

[0022] The first interconnect layer 140-1 may include one or more lines 107. The lines 107 may include a conductive material, such as a metal. In some embodiments, the lines 107 may include cobalt, copper, ruthenium, silicon (e.g., as cobalt silicide), nickel (e.g., as nickel silicide), tungsten, aluminum, tin, titanium nitride, niobium titanium nitride, tantalum, niobium, and other niobium compounds (e.g., niobium tin and niobium germanium). Although a particular number of lines 107 are illustrated in FIG. 1, any suitable number of lines 107 may be included in the first interconnect layer 140-1. When the assembly 500 is a stage in the manufacture of a die (e.g., as discussed below with reference to FIG. 16), the lines 107 may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of a substrate of the die. In some embodiments, the first interconnect layer 140-1 may include one or more vias (not shown) to route electrical signals in a direction that is substantially perpendicular to the plane of the lines 107. An insulating material 105 may be disposed around the lines 107 (and vias, not shown) in the first interconnect layer 140-1. The insulating material 105 may include any suitable insulating material, such as one or more of silicon, oxygen (e.g., in the form of silicon oxide), carbon (e.g., in the form of carbon-doped oxide), nitrogen (e.g., in the form of silicon nitride), an organic polymer, and/or an organosilicate. In some embodiments, the insulating material 105 may be an ILD. In some embodiments, the lines 107 (and/or vias, not shown) in the first interconnect layer 140-1 may be metal structures 100 in accordance with any of the embodiments disclosed herein; in other embodiments, the lines 107 (and/or vias, not shown) in the first interconnect layer 140-1 may not be metal structures 100 (and may, e.g., have different material composition than the metal structures 100 disclosed herein).

[0023] In the assembly 500, the etch stop material 191 may include any suitable material, such as a nitride, silicon carbide, silicon nitride, carbon-doped silicon nitride, or silicon oxycarbide. In some embodiments, the etch stop material 191 may be deposited using CVD. The etch stop material 191 may have any suitable thickness. In some embodiments, the etch stop material 191 may have a thickness that is less than 20 nanometers (e.g., between 8 nanometers and 12 nanometers). The insulating material 190 may be a dielectric material, such as any suitable interlayer dielectric (ILD). In some embodiments, the insulating material 190 may be an oxide material, silicon oxide, carbon- doped oxide, silicon oxynitride, and/or a polymer material. In some embodiments, the insulating material 190 may be deposited using CVD. The insulating material 190 may have any suitable thickness. In some embodiments, the insulating material 190 may have a thickness between 10 nanometers and 30 nanometers (e.g., between 10 nanometers and 20 nanometers).

[0024] FIG. 2 is a side cross-sectional view of an assembly 502 subsequent to providing a resist material 177 on the assembly 500 (FIG. 1) and patterning the resist material 177. The resist material 177 may be any suitable resist for patterning the insulating material 190, as discussed below with reference to FIG. 3 (e.g., a photoresist). The patterned resist material 177 may include cavities 179 that extend down to and expose portions of the insulating material 190. The patterning of the resist material 177 may be performed in accordance with any suitable technique (e.g., a photolithography technique).

[0025] FIG. 3 is a side cross-sectional view of an assembly 504 subsequent to etching the insulating material 190 in accordance with the pattern provided by the patterned resist material 177 of the assembly 502 (FIG. 2), and removing the remaining resist material 177. In particular, cavities 187 may be formed in the insulating material 190 at locations corresponding to the locations of the cavities 179 in the patterned resist material 177. The cavities 187 may extend down to the etch stop material 191 (which may serve as an etch stop for the formation of the cavities 187), exposing portions of the top surface of the etch stop material 191. In some embodiments, the cavities 187 may have a taper, and may be narrower closer to the first interconnect layer 140-1, as illustrated. [0026] FIG. 4 is a side cross-sectional view of an assembly 506 subsequent to providing a resist material 175 on the assembly 504 (FIG. 3) and patterning the resist material 175. The provision and patterning of the resist material 175 may take any suitable form (e.g., as discussed above with reference to FIG. 2). In some embodiments, the resist material 175 may have the same material composition as the resist material 177; in other embodiments, the resist material 175 and the resist material 177 may have different material compositions. The patterned resist material 175 may include cavities 181 that extend down to and expose portions of the insulating material 190, and also expose the cavities 187 in the insulating material 190.

[0027] FIG. 5 is a side cross-sectional view of an assembly 508 subsequent to etching the insulating material 190 and the etch stop material 191 in accordance with the pattern provided by the patterned resist material 175 of the assembly 506 (FIG. 4), and removing the remaining resist material 175. In particular, a timed etch may be used to remove some of the insulating material 190 that was not protected by the resist material 175, leaving cavities 195 (which may also be referred to as "trenches"). After the timed etch, the etch stop material 191 at the bottom of the cavities 187 may be removed to form cavities 194. In some embodiments, the cavities 194 may be tapered (e.g., as illustrated). The cavities 195 may extend over the cavities 194, as shown. In some embodiments, the cavities 194 may have a width (at their widest point) that is between 15 nanometers and 25 nanometers (e.g., between 15 nanometers and 20 nanometers). In some embodiments, adjacent cavities 194 may be spaced apart by a distance as small as 15 nanometers (e.g., between 15 nanometers and 25 nanometers).

[0028] FIG. 6 is a cross-sectional view of an assembly 510 subsequent to providing a conformal liner material 117 on the assembly 508 (FIG. 5). In particular, the liner material 117 may be provided on the exposed insulating material 190 and etch stop material 191, as well as at the bottom of the cavities 194 (in FIG. 6, on the exposed lines 107). In some embodiments, the liner material 117 may be removed from the bottom of the cavities 194 before further processing (not shown), remaining on the exposed insulating material 190 an etch stop material 191. In some embodiments, the liner material 117 may be an adhesion liner, facilitating mechanical adhesion between the assembly 510 and the conductive material that will be subsequently provided (e.g., the seed layer 119 and the metal fill 189 discussed below). In some such embodiments, the liner material 117 may include a refractory metal or a refractory metal nitride, such as titanium, tantalum, titanium nitride, titanium zirconium nitride, ruthenium, doped ruthenium (e.g., ruthenium doped with phosphorous), or tantalum nitride. In some embodiments, the liner material 117 may include tantalum

nitride/tantalum (TNT). In some embodiments, the liner material 117 may include titanium nitride. In some embodiments, the liner material 117 may provide a barrier against metal diffusion (e.g., between lines/vias and proximate insulating material), and/or may reduce electromigration between lines and vias. In some such embodiments, the liner material 117 may include copper doped with aluminum, or copper doped with manganese (e.g., to reduce electromigration). Having the liner material 117 provide an adhesion liner may be particularly advantageous for metal structures 100; a diffusion barrier may not be necessary. The liner material 117 may be provided using any suitable technique, such as atomic layer deposition (ALD), CVD, or sputtering, for example. The liner material 117 may have any suitable thickness (e.g., between 2 and 70 Angstroms, or between 10 angstroms and 70 angstroms, in some embodiments). In some embodiments, no liner material 117 may be present.

[0029] FIG. 7 is a cross-sectional view of an assembly 512 subsequent to providing a conformal seed layer 119 of conductive material on the assembly 510 (FIG. 6) such that the seed layer 119 extends over the walls and bottoms of the cavities 194 and 195 (as well as over the exposed top surfaces of the insulating material 190). In particular, the seed layer 119 may be in conductive contact with the lines 107 in the first interconnect layer 140-1. The seed layer 119 may provide a catalytic surface for the electroless deposition of a metal fill 189, as discussed below with reference to FIG. 8. In some embodiments, the seed layer 119 may include cobalt (e.g., when the metal fill 189 includes cobalt). The seed layer 119 may be formed using any suitable technique, such as CVD, to any suitable thickness. For example, the seed layer 119 may have a thickness between 20 angstroms and 50 angstroms (e.g., when the seed layer 119 and the metal fill 189 include cobalt). The seed layer 119 may have a sheet resistance that is greater than 100-200 ohms/sq. For example, the seed layer 119 may have a sheet resistance that is greater than 2000 ohms/sq (e.g., greater than 2500 ohms/sq). More generally, the sheet resistance of the seed layer 119 may be too high (e.g., as a consequence of the low thickness of the seed layer 119) for electroplating to be successfully performed.

[0030] FIG. 8 is a cross-sectional view of an assembly 514 subsequent to electrolessly depositing a metal fill 189 on the seed layer 119 of the assembly 512 (FIG. 7). In particular, the metal fill 189 may fill the cavities 194 and 195, and in some embodiments, may extend beyond the cavities 194 and 195 over the adjacent insulating material 190 (as shown). The electroless deposition of the metal fill 189 may include providing a plating bath solution of a metal source, a reducing agent, and other agents to the seed layer 119, and uniformly heating the environment to allow the metal to crystallize and grow on the seed layer 119 (without having to provide an electrical potential, as in an electroplating process). In some embodiments, the other agents in the plating bath solution may include a nonvolatile chelator; the use of a non-volatile chelator may represent an improvement over some conventional electroless deposition processes, which may use ammonia or other volatile chelators that may be less suitable for high volume manufacturing settings due to their rapid outgassing changing the concentration and pH of the solution. Achieving pure electroless deposition of cobalt without using volatile complexing agents allows cobalt to be practically used in interconnects.

[0031] In some embodiments, the plating bath solution may include a metal source, a reducing agent, and a bath makeup solution. For example, when the metal fill 189 is to include cobalt, the metal source may include cobalt in the form of cobalt sulfate petahydrate, cobalt chloride, or cobalt hydroxide. In some examples, the metal source may include copper, nickel, platinum, gold, ruthenium, or palladium (e.g., when the metal fill 189 is to include these respective materials). The reducing agent may include hydrazine (e.g., hydrazine sulfate, hydrazine chloride, other hydrazine derivatives) or glyoxylic acid, for example. The bath makeup solution may include a chelator, such as citric acid, acetic acid, glycine, ethanolamine, ethylenediamine, thylenediaminetetraacetic acid (EDTA), nitrilotriacetic acid (NTA), or iminodiacetic acid (IDA). In some embodiments, the chelator may include ammonia. The bath makeup solution may include a surfactant, such as polyethylene glycol (PEG), polyoxyalkylene alkyl ether, a grain refiner, a brightener, superfill additives, polypropylene glycol, poly acrylic acid, bis(3-sulfopropyl)disulfide, 3-mercapto-l-propanesulfonate, thiourea, and/or thioglycolic acid. When the surfactant is PEG, the molecular weight of the PEG may be between 1000 and 10000. The bath makeup solution may include a pH base adjustor, such as tetramethylammonium hydroxide.

[0032] During fabrication, the bath makeup solution (which may be pre-mixed), the metal source, and the reducing agent may be combined in the fabrication tool to form the plating bath, along with sufficient deionized water to achieve a desired concentration of the components of the plating bath. The concentration of the chelator in the plating bath solution may be between 0.05 M and 0.5 M, in some embodiments. The concentration of the surfactant in the plating bath solution may be less than 200 milligrams/liter, in some embodiments. In some embodiments, the concentration of the pH base adjustor in the plating bath solution may be less than 300 grams/liter. The aqueous environment of the electroless reaction may be controlled as suitable to achieve desired metal growth. In some embodiments, the temperature of the aqueous environment may be maintained between 70 degrees Celsius and 95 degrees Celsius. In some embodiments, the pH of the plating bath may be maintained between 11 and 13 at room temperature. In some embodiments, the assembly 514 may be immersed in the plating bath, while in other embodiments, the plating bath may be sprayed onto the seed layer 119. Various ones of the electroless deposition techniques disclosed herein may enable selective deposition on metals (e.g., on copper) without deposition on insulating materials (e.g., without depositing on ILD or other dielectric materials).

[0033] In some embodiments, the metal fill 189 may be predominantly cobalt. In some such embodiments, the metal fill 189 may have a cobalt content greater than 99% (e.g., greater than 99.3%, greater than 99.5% or greater than 99.8%). Other materials that may be present in a cobalt metal fill 189 may include hydrogen (e.g., less than 0.2%), boron (e.g., less than 0.2 ppm), carbon (e.g., less than 0.01%), nitrogen (e.g., less than 32 ppm), oxygen (e.g., less than 22 ppm), sodium (e.g., less than 0.3 ppm), sulfur (e.g., less than 6 ppm), phosphorous (e.g., less than 3 ppm), chlorine (e.g., less than 0.9 ppm), and potassium (e.g., less than 0.03 ppm). In some embodiments, the resistivity of the cobalt metal fill 189 may be less than 8 microohms/cm. For example, the resistivity of the cobalt metal fill 189 may be between 6.6 microohms/cm and 7 microohms/cm (at 200 nanometers thickness) (e.g., 6.8 microohms/cm). In other embodiments, the metal fill 189 may be predominantly copper, nickel, platinum, gold, ruthenium, or palladium. In some embodiments, the metal fill 189 may be a binary or ternary alloy of cobalt, copper, nickel, platinum, gold, ruthenium, or palladium.

[0034] In some embodiments, the metal fill 189 may exhibit none or very low intrinsic film stress. This may reduce the likelihood that the metal fill 189 may crack or delaminate under thermal cycling, thus improving device reliability relative to deposition techniques that result in more significant intrinsic film stress (e.g., CVD and electroplating).

[0035] FIG. 9 is a cross-sectional view of an assembly 516 subsequent to planarizing the assembly 514 (FIG. 8) to remove the metal fill 189 that extended beyond the cavities 194 and 195 of the assembly 514. A chemical mechanical polishing (CMP) technique may be used to planarize the assembly 514. In some embodiments, the planarization of the assembly 514 may also remove some of the insulating material 190. The resulting metal fill 189 that fills the cavities 195 may provide metal vias 100b in conductive contact with the lines 107 (or other interconnects in the first interconnect layer 140-1), and the metal fill 189 that fills the cavities 194 may provide metal lines 100a in conductive contact with the metal vias 100b. The metal lines 100a may be part of a second interconnect layer 140-2. The use of the term "second" to refer to the interconnect layer 140-2 does not imply that the interconnect layer 140-2 is the M2 (or "second") layer in a metallization stack; the term "second" is simply used to identify the interconnect layer 140-2.

[0036] Additional vias and lines (e.g., metal vias 100b and metal lines 100a, or vias and lines with other material compositions) may be formed on the assembly 516 by repeating the operations discussed above with reference to FIGS. 1-9 to form any desired interconnects.

[0037] FIGS. 10-13 illustrate stages in another example process of manufacturing metal structures 100 in an IC component, in accordance with various embodiments. In particular, FIGS. 10-13 illustrate a process that may be used to form metal capping layers 100c (including, e.g., cobalt, copper, nickel, platinum, gold, ruthenium, or palladium). FIGS. 10-13 illustrate the formation of metal capping layers 100c in a dual Damascene process setting, but the use of a dual Damascene process setting is simply illustrative, and the metal capping layers 100c disclosed herein may be used in any desired process (e.g., subtractive, additive, single Damascene, etc.). Although FIGS. 10-13 show the formation of metal capping layers 100c in contact with metal interconnects 103 in a lower interconnect layer, this is simply for ease of illustration, and the metal capping layers 100c disclosed herein may contact any suitable structures, such as any suitable metal or other material for which capping may be useful (e.g., for passivation, to mitigate electromigration, etc.). Some of the elements of FIGS. 10-13 may have the same reference numeral as elements in FIGS. 1-9;

embodiments of these elements are not repeated with reference to FIGS. 10-13, and these elements may take any suitable form (e.g., the form of any suitable ones of the embodiments discussed above with reference to FIGS. 1-9).

[0038] FIG. 10 is a side cross-sectional view of an assembly 550 including a first interconnect layer 140-1 (including one or more lines 107 and an insulating material 105 around the lines 107), an etch stop material 191 on the first interconnect layer 140-1, an insulating material 190 on the etch stop material 191. Further, as noted above, the techniques disclosed herein may be used to form metal structures 100 in contact with the device layer of a die; in such embodiments, the first interconnect layer 140-1 may be replaced with the device layer (e.g., as discussed below with reference to FIG. 16). In some embodiments, the lines 107 (and/or vias, not shown) in the first interconnect layer 140-1 may include metal lines 100a and/or metal vias 100b, in accordance with any of the embodiments disclosed herein; in other embodiments, the lines 107 (and/or vias, not shown) in the first interconnect layer 140-1 may not be metal structures 100 (and may, e.g., have different material composition than the metal structures 100 disclosed herein).

[0039] In FIG. 10, one or more metal interconnects 103 may extend through the insulating material 190 and the etch stop material 191. The metal interconnects 103 may have a metal fill 125 including predominantly cobalt, copper, tungsten, aluminum, titanium, ruthenium, nickel, platinum, palladium, rhodium, rhenium, iridium, or any other suitable conductive material or combination of materials. In some embodiments, the metal interconnects 103 may include a liner material 121 between the metal fill 125 and the adjacent insulating material 190, etch stop material 191, and lines 107. In some embodiments, the liner material 121 may be an adhesion liner, facilitating mechanical adhesion between the metal fill 125 and the surrounding materials. In some such embodiments, the liner material 121 may include a refractory metal or a refractory metal nitride, such as titanium, tantalum, titanium nitride, titanium zirconium nitride, ruthenium, doped ruthenium (e.g., ruthenium doped with phosphorous), or tantalum nitride. In some embodiments, the liner material 121 may include TNT. In some embodiments, the liner material 121 may include titanium nitride. In some embodiments, the liner material 121 may provide a barrier against metal diffusion (e.g., between the metal fill 125 and adjacent materials), and/or may reduce electromigration. In some such embodiments, the liner material 121 may include copper doped with aluminum, or copper doped with manganese (e.g., to reduce electromigration).

[0040] FIG. 10 depicts a metal oxide 123 formed on the exposed surface of the metal fill 125. The metal oxide 123 may form after the metal fill 125 is initially deposited and polished (e.g., by CMP), then exposed to oxygen (e.g., in the air while the assembly 550 is being transferred between tools in a fabrication facility). The metal oxide 123 may be an oxide of a metal in the metal fill 125; for example, when the metal fill 125 is copper, the metal oxide 123 may be a copper oxide.

[0041] FIG. 11 is a side cross-sectional view of an assembly 552 subsequent to removing the metal oxide 123, and a portion of the metal fill 125, from the assembly 550 (FIG. 10) by etching, and then providing a seed layer 119 on the exposed metal fill 125. The seed layer 119 may take any of the forms discussed above (e.g., with reference to FIG. 7). For example, the seed layer 119 may be a layer of CVD cobalt with a thickness between 20 angstroms and 50 angstroms. The etch may be a wet etch, such as a hydrofluoric acid or sulfuric acid etch.

[0042] FIG. 12 is a side cross-sectional view of an assembly 554 subsequent to electrolessly depositing a metal capping layer 100c on the seed layer 119 of the assembly 552 (FIG. 11). The electroless deposition of the metal capping layer 100c may be performed in accordance with any of the embodiments of electroless metal deposition discussed above with reference to FIG. 8.

[0043] FIG. 13 is a side cross-sectional view of an assembly 556 subsequent to providing an additional layer of etch stop material 191 and insulating material 190 on the assembly 554 (FIG. 12). Additional metal interconnects 103 may be formed through this additional material to form another interconnect layer 140 (not shown). In some embodiments, one or more interconnects in another interconnect layer 140 may include metal lines 100a, metal vias 100b, and/or metal capping layers 100c. More generally, any desired interconnect structures may be formed.

[0044] FIG. 14 is a flow diagram of a method 1000 of depositing a metal on a surface, in accordance with various embodiments. Although the operations of the method 1000 may be illustrated with reference to particular embodiments of the metals disclosed herein (e.g., cobalt, copper, nickel, platinum, gold, ruthenium, or palladium), the method 1000 may be used to deposit any suitable metal on any suitable surface. Operations are illustrated once each and in a particular order in FIG. 14, but the operations may be reordered and/or repeated as desired (e.g., with different operations performed in parallel when manufacturing multiple electronic components simultaneously).

[0045] At 1002, a heated solution may be provided on the surface. The heated solution may include the metal and hydrazine, and may have a pH greater than 10 (e.g., between 11 and 13). For example, a heated solution as discussed above with reference to FIG. 8 may be provided on a seed layer 119.

[0046] At 1004, the metal from the heated solution may be allowed to crystallize on the surface. For example, metal from the heated solution may crystallize on the seed layer 119 to form a metal fill 189, as discussed above with reference to FIG. 8.

[0047] The metal structures 100 disclosed herein may be included in any suitable electronic component. FIGS. 5-19 illustrate various examples of apparatuses that may include any of the metal structures 100 disclosed herein.

[0048] FIG. 15 is a top view of a wafer 1500 and dies 1502 that may include one or more metal structures 100, or may be included in an IC package whose substrate includes one or more metal structures 100 (e.g., as discussed below with reference to FIG. 17) in accordance with any of the embodiments disclosed herein. The wafer 1500 may be composed of semiconductor material and may include one or more dies 1502 having IC structures formed on a surface of the wafer 1500. Each of the dies 1502 may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer 1500 may undergo a singulation process in which each of the dies 1502 is separated from one another to provide discrete "chips" of the semiconductor product. The die 1502 may include one or more metal structures 100 (e.g., as discussed below with reference to FIG. 16), one or more transistors (e.g., some of the transistors 1640 of FIG. 16, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer 1500 or the die 1502 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive- bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on a same die 1502 as a processing device (e.g., the processing device 1802 of FIG. 19) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0049] FIG. 16 is a cross-sectional side view of an IC device 1600 that may include one or more metal structures 100, or may be included in an IC package whose substrate includes one or more metal structures 100 (e.g., as discussed below with reference to FIG. 17), in accordance with any of the embodiments disclosed herein. One or more of the IC devices 1600 may be included in one or more dies 1502 (FIG. 15). The IC device 1600 may be formed on a substrate 1602 (e.g., the wafer 1500 of FIG. 15) and may be included in a die (e.g., the die 1502 of FIG. 15). The substrate 1602 may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems (or a combination of both). The substrate 1602 may include, for example, a crystalline substrate formed using a bulk silicon or an SOI substructure. In some embodiments, the substrate 1602 may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group ll-VI, lll-V, or IV may also be used to form the substrate 1602. Although a few examples of materials from which the substrate 1602 may be formed are described here, any material that may serve as a foundation for an IC device 1600 may be used. The substrate 1602 may be part of a singulated die (e.g., the dies 1502 of FIG. 15) or a wafer (e.g., the wafer 1500 of FIG. 15).

[0050] The IC device 1600 may include one or more device layers 1604 disposed on the substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in FIG. 16 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all- around gate transistors, such as nanoribbon and nanowire transistors.

[0051] Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some

embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used. [0052] The gate electrode layer may be formed on the gate dielectric layer and may include at least one P-type work function metal or N-type work function metal, depending on whether the transistor 1640 is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

[0053] In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is

substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0054] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0055] The S/D regions 1620 may be formed within the substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S/D regions 1620 may be formed using either an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 1602 to form the S/D regions 1620. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 1602 may follow the ion-implantation process. In the latter process, the substrate 1602 may first be etched to form recesses at the locations of the S/D regions 1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1620. In some implementations, the S/D regions 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1620 may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1620.

[0056] Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1640) of the device layer 1604 through one or more interconnect layers disposed on the device layer 1604 (illustrated in FIG. 16 as interconnect layers 1606-1610). For example, electrically conductive features of the device layer 1604 (e.g., the gate 1622 and the S/D contacts 1624) may be electrically coupled with the interconnects 1628 of the interconnect layers 1606-1610. The one or more interconnect layers 1606-1610 may form a metallization stack (also referred to as an "ILD stack") 1619 of the IC device 1600. Any of the interconnect layer 1606- 1610 may include metal structures 100 (e.g., as discussed above with reference to the interconnect layers 140).

[0057] The interconnects 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnects 1628 depicted in FIG. 16). Although a particular number of interconnect layers 1606-1610 is depicted in FIG. 16, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0058] In some embodiments, the interconnects 1628 may include lines 1628a and/or vias 1628b filled with an electrically conductive material such as a metal. The lines 1628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 1602 upon which the device layer 1604 is formed. For example, the lines 1628a may route electrical signals in a direction in and out of the page from the perspective of FIG. 16. The vias 1628b may be arranged to route electrical signals in a direction of a plane that is substantially

perpendicular to the surface of the substrate 1602 upon which the device layer 1604 is formed. In some embodiments, the vias 1628b may electrically couple lines 1628a of different interconnect layers 1606-1610 together. In some embodiments, one or more of the lines 1628a in one or more of the interconnect layers 1606-1610 may be metal lines 100a, and one or more of the vias 1628b in one or more of the interconnect layers 1606-1610 may be metal vias 100b. In some embodiments, interconnect layers "lower" in the metallization stack (i.e., closer to the device layer 1604) may include metal structures 100, while interconnect layers "higher" in the metallization stack may include interconnects 1628 that are not metal structures 100; for example, the "higher"

interconnects 1628 may be copper interconnects 1628.

[0059] The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between the interconnects 1628, as shown in FIG. 16. In some embodiments, the dielectric material 1626 disposed between the interconnects 1628 in different ones of the interconnect layers 1606-1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606-1610 may be the same.

[0060] A first interconnect layer 1606 (referred to as Metal 1 or "Ml") may be formed directly on the device layer 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628a and/or vias 1628b, as shown. The lines 1628a of the first interconnect layer 1606 may be coupled with contacts (e.g., the S/D contacts 1624) of the device layer 1604.

[0061] A second interconnect layer 1608 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 with the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the lines 1628a and the vias 1628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual Damascene process) in some embodiments.

[0062] A third interconnect layer 1610 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are "higher up" in the metallization stack 1619 in the IC device 1600 (i.e., further away from the device layer 1604) may be thicker.

[0063] The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606-1610. In FIG. 16, the conductive contacts 1636 are illustrated as taking the form of bond pads. The conductive contacts 1636 may be electrically coupled with the interconnects 1628 and configured to route the electrical signals of the transistor(s) 1640 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 1636 to mechanically and/or electrically couple a chip including the IC device 1600 with another component (e.g., a circuit board). The IC device 1600 may include additional or alternate structures to route the electrical signals from the interconnect layers 1606-1610; for example, the conductive contacts 1636 may include other analogous features (e.g., posts) that route the electrical signals to external components.

[0064] FIG. 17 is a cross-sectional view of an example IC package 1650 that may include one or more metal structures 100. The package substrate 1652 may be formed of a dielectric material, and may have conductive pathways extending through the dielectric material between the face 1672 and the face 1674, or between different locations on the 1672, and/or between different locations on the face 1674. These conductive pathways may take the form of any of the interconnects 1628 discussed above with reference to FIG. 16. Any number of metal structures 100 (with any suitable structure) may be included in a package substrate 1652. In some embodiments, no metal structures 100 may be included in the package substrate 1652.

[0065] The IC package 1650 may include a die 1656 coupled to the package substrate 1652 via conductive contacts 1654 of the die 1656, first-level interconnects 1658, and conductive contacts 1660 of the package substrate 1652. The conductive contacts 1660 may be coupled to conductive pathways 1662 through the package substrate 1652, allowing circuitry within the die 1656 to electrically couple to various ones of the conductive contacts 1664 (or to other devices included in the package substrate 1652, not shown). The first-level interconnects 1658 illustrated in FIG. 17 are solder bumps, but any suitable first-level interconnects 1658 may be used. As used herein, a "conductive contact" may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

[0066] In some embodiments, an underfill material 1666 may be disposed between the die 1656 and the package substrate 1652 around the first-level interconnects 1658, and a mold compound 1668 may be disposed around the die 1656 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the mold compound 1668. Example materials that may be used for the underfill material 1666 and the mold compound 1668 are epoxy mold materials, as suitable. Second-level interconnects 1670 may be coupled to the conductive contacts 1664. The second-level interconnects 1670 illustrated in FIG. 17 are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects 16770 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects 1670 may be used to couple the IC package 1650 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to FIG. 18.

[0067] In FIG. 17, the IC package 1650 is a flip chip package, and may include one or more metal structures 100 in the package substrate 1652. In some embodiments, no metal structures 100 may be included in the package substrate 1652. The die 1656 may take the form of any of the embodiments of the die 1502 discussed herein (e.g., may include any of the embodiments of the IC device 1600). In some embodiments, the die 1656 may include one or more metal structures 100 (e.g., as discussed above with reference to FIG. 15 and FIG. 16); in other embodiments, the die 1656 may not include any metal structures 100.

[0068] Although the IC package 1650 illustrated in FIG. 17 is a flip chip package, other package architectures may be used. For example, the IC package 1650 may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 1650 may be a wafer-level chip scale package (WLCSP) or a panel fanout (FO) package. Although a single die 1656 is illustrated in the IC package 1650 of FIG. 17, an IC package 1650 may include multiple dies 1656 (e.g., with one or more of the multiple dies 1656 coupled to metal structures 100 included in the package substrate 1652). An IC package 1650 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face 1672 or the second face 1674 of the package substrate 1652. More generally, an IC package 1650 may include any other active or passive components known in the art.

[0069] FIG. 18 is a cross-sectional side view of an IC device assembly 1700 that may include one or more IC packages or other electronic components (e.g., a die) including one or more metal structures 100, in accordance with any of the embodiments disclosed herein. The IC device assembly 1700 includes a number of components disposed on a circuit board 1702 (which may be, e.g., a motherboard). The IC device assembly 1700 includes components disposed on a first face 1740 of the circuit board 1702 and an opposing second face 1742 of the circuit board 1702;

generally, components may be disposed on one or both faces 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 may take the form of any of the embodiments of the IC package 1650 discussed above with reference to FIG. 17 (e.g., may include one or more metal structures 100 in a package substrate 1652 or in a die).

[0070] In some embodiments, the circuit board 1702 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate.

[0071] The IC device assembly 1700 illustrated in FIG. 18 includes a package-on-interposer structure 1736 coupled to the first face 1740 of the circuit board 1702 by coupling components 1716. The coupling components 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702, and may include solder balls (as shown in FIG. 18), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0072] The package-on-interposer structure 1736 may include an IC package 1720 coupled to an interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in FIG. 18, multiple IC packages may be coupled to the interposer 1704; indeed, additional interposers may be coupled to the interposer 1704. The interposer 1704 may provide an intervening substrate used to bridge the circuit board 1702 and the IC package 1720. The IC package 1720 may be or include, for example, a die (the die 1502 of FIG. 15), an IC device (e.g., the IC device 1600 of FIG. 16), or any other suitable component. Generally, the interposer 1704 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 1704 may couple the IC package 1720 (e.g., a die) to a set of BGA conductive contacts of the coupling components 1716 for coupling to the circuit board 1702. In the embodiment illustrated in FIG. 18, the IC package 1720 and the circuit board 1702 are attached to opposing sides of the interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be attached to the same side of the interposer 1704. In some embodiments, three or more components may be interconnected by way of the interposer 1704.

[0073] The interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to through-silicon vias (TSVs) 1706. The interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art. In some embodiments, the interposer 1704 may include one or more metal structures 100.

[0074] The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.

[0075] The IC device assembly 1700 illustrated in FIG. 18 includes a package-on-package structure 1734 coupled to the second face 1742 of the circuit board 1702 by coupling components 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by coupling components 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling components 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. The package-on-package structure 1734 may be configured in accordance with any of the package-on-package structures known in the art.

[0076] FIG. 19 is a block diagram of an example electrical device 1800 that may include one or more metal structures 100, in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the electrical device 1800 may include one or more of the IC packages 1650, IC devices 1600, or dies 1502 disclosed herein. A number of components are illustrated in FIG. 19 as included in the electrical device 1800, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

[0077] Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components illustrated in FIG. 19, but the electrical device 1800 may include interface circuitry for coupling to the one or more components. For example, the electrical device 1800 may not include a display device 1806, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1806 may be coupled. In another set of examples, the electrical device 1800 may not include an audio input device 1824 or an audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1824 or audio output device 1808 may be coupled.

[0078] The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0079] In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0080] The communication chip 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0081] In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1812 may include multiple communication chips. For instance, a first communication chip 1812 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communications, and a second communication chip 1812 may be dedicated to wired communications.

[0082] The electrical device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).

[0083] The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display

(LCD), a light-emitting diode display, or a flat panel display, for example.

[0084] The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0085] The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

[0086] The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the electrical device 1800, as known in the art.

[0087] The electrical device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0088] The electrical device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0089] The electrical device 1800 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.

[0090] The electroless cobalt deposition techniques disclosed herein may not only be used to provide high purity cobalt for interconnects, but may be used to deposit cobalt in any suitable setting. For example, microelectromechanical systems (MEMS) systems (e.g., three-dimensional MEMS) may include metal structures formed using the electroless cobalt deposition techniques disclosed herein.

[0091] The following paragraphs provide various examples of the embodiments disclosed herein.

[0092] Example 1 is an integrated circuit (IC) component, including: a dielectric material; and a via extending through the dielectric material, wherein the via includes a metal fill, and the metal fill includes at least 99% cobalt.

[0093] Example 2 may include the subject matter of Example 1, and may further specify that the metal fill includes at least 99.3% cobalt. [0094] Example 3 may include the subject matter of any of Examples 1-2, and may further specify that the metal fill includes at least 99.5% cobalt.

[0095] Example 4 may include the subject matter of any of Examples 1-3, and may further specify that the metal fill includes at least 99.8% cobalt.

[0096] Example 5 may include the subject matter of any of Examples 1-4, and may further specify that the via includes a layer of liner material at least partially between the dielectric material and the metal fill.

[0097] Example 6 may include the subject matter of Example 5, and may further specify that the liner material includes titanium.

[0098] Example 7 may include the subject matter of Example 6, and may further specify that the liner material includes nitrogen.

[0099] Example 8 may include the subject matter of any of Examples 5-6, and may further specify that the via further includes a layer of seed material, and the layer of liner material is at least partially between the dielectric material and the layer of seed material.

[0100] Example 9 may include the subject matter of Example 8, and may further specify that the seed material includes cobalt.

[0101] Example 10 may include the subject matter of Example 9, and may further specify that the seed material includes less than 97% cobalt.

[0102] Example 11 may include the subject matter of any of Examples 9-10, and may further specify that the seed material includes at least 3% carbon.

[0103] Example 12 may include the subject matter of any of Examples 8-11, and may further specify that the layer of seed material has a thickness between 20 angstroms and 50 angstroms.

[0104] Example 13 may include the subject matter of any of Examples 1-12, and may further specify that the via further includes a layer of seed material at least partially between the dielectric material and the metal fill.

[0105] Example 14 may include the subject matter of Example 13, and may further specify that the seed material includes cobalt.

[0106] Example 15 may include the subject matter of Example 14, and may further specify that the seed material includes less than 97% cobalt.

[0107] Example 16 may include the subject matter of any of Examples 14-15, and may further specify that the seed material includes at least 3% carbon.

[0108] Example 17 may include the subject matter of any of Examples 13-16, and may further specify that the layer of seed material has a thickness between 20 angstroms and 50 angstroms. [0109] Example 18 may include the subject matter of any of Examples 1-17, and may further specify that the IC component is a die.

[0110] Example 19 may include the subject matter of any of Examples 1-18, and may further include a line in contact with the via, wherein the line includes cobalt.

[0111] Example 20 may include the subject matter of Example 19, and may further specify that the line includes at least 99% cobalt.

[0112] Example 21 may include the subject matter of any of Examples 1-17, and may further specify that the IC component is a package substrate.

[0113] Example 22 may include the subject matter of any of Examples 1-20, and may further specify that the via is in contact with a device in a device layer of the IC component.

[0114] Example 23 is a method of depositing a metal on a surface, including: providing a heated solution on the surface, wherein the heated solution includes the metal and hydrazine, and has a pH greater than 10; and allowing the metal from the heated solution to crystallize on the surface.

[0115] Example 24 may include the subject matter of Example 23, and may further specify that the heated solution includes citrate, acetic acid, ethylenediaminetetraacetic acid, tartaric acid, or boric acid.

[0116] Example 25 may include the subject matter of any of Examples 23-24, and may further specify that the heated solution has a temperature between 75 and 95 degrees Celsius.

[0117] Example 26 may include the subject matter of any of Examples 23-25, and may further specify that the surface has a sheet resistance greater than or equal to 2500 ohms/sq.

[0118] Example 27 may include the subject matter of any of Examples 23-26, and may further specify that providing the heated solution on the surface includes spraying the heated solution on the surface.

[0119] Example 28 may include the subject matter of any of Examples 23-27, and may further specify that the surface includes the metal.

[0120] Example 29 may include the subject matter of any of Examples 23-28, and may further specify that the surface includes a recess for a via.

[0121] Example 30 may include the subject matter of any of Examples 23-29, and may further specify that the metal includes cobalt.

[0122] Example 31 may include the subject matter of any of Examples 23-30, and may further specify that the metal includes copper, nickel, platinum, gold, ruthenium, or palladium.

[0123] Example 32 is a computing device, including: a circuit board; and a die coupled to the circuit board, wherein the die includes an interconnect in a metallization stack, the interconnect includes a metal fill, and the metal fill includes at least 99% cobalt. [0124] Example 33 may include the subject matter of Example 32, and may further specify that the interconnect includes a via.

[0125] Example 34 may include the subject matter of any of Examples 32-33, and may further include:

[0126] an antenna coupled to the circuit board.

[0127] Example 35 may include the subject matter of any of Examples 32-34, and may further specify that the computing device is a tablet or smartphone.

[0128] Example 36 is an integrated circuit (IC) component, including: a metal interconnect; and a metal capping layer on the metal interconnect, wherein the metal capping layer includes at least 99% cobalt.

[0129] Example 37 may include the subject matter of Example 36, and may further specify that the metal capping layer includes at least 99.3% cobalt.

[0130] Example 38 may include the subject matter of Example 36-37, and may further specify that the metal capping layer includes at least 99.5% cobalt.

[0131] Example 39 may include the subject matter of Example 36-38, and may further specify that the metal capping layer includes at least 99.8% cobalt.

[0132] Example 40 may include the subject matter of any of Examples 36-39, and may further specify that the metal capping layer extends over a liner material, and the liner material is between the metal interconnect and a dielectric material.

[0133] Example 41 may include the subject matter of Example 40, and may further specify that the metal interconnect includes copper.

[0134] Example 42 may include the subject matter of Example 40, and may further specify that the liner material includes nitrogen.

[0135] Example 43 may include the subject matter of any of Examples 36-42, and may further specify that the metal capping layer is on a layer of seed material between the metal capping layer and the metal interconnect.

[0136] Example 44 may include the subject matter of Example 43, and may further specify that the seed material includes cobalt.

[0137] Example 45 may include the subject matter of Example 44, and may further specify that the seed material includes less than 97% cobalt.

[0138] Example 46 may include the subject matter of any of Examples 44-45, and may further specify that the seed material includes at least 3% carbon.

[0139] Example 47 may include the subject matter of any of Examples 43-46, and may further specify that the layer of seed material has a thickness between 20 angstroms and 50 angstroms. [0140] Example 48 may include the subject matter of any of Examples 36-47, and may further specify that the IC component is a die.

[0141] Example 49 may include the subject matter of any of Examples 36-48, and may further include:

[0142] a cobalt interconnect in contact with the metal interconnect.

[0143] Example 50 may include the subject matter of Example 49, and may further specify that the cobalt interconnect includes at least 99% cobalt.

[0144] Example 51 may include the subject matter of any of Examples 36-47, and may further specify that the IC component is a package substrate.

[0145] Example 52 may include the subject matter of any of Examples 36-51, and may further specify that the metal interconnect is in contact with a device in a device layer of the IC component.

[0146] Example 53 is a bath makeup solution for electroless metal deposition, including: a chelator, wherein the chelator does not include ammonia; a surfactant; and a pH base adjustor.

[0147] Example 54 may include the subject matter of Example 53, and may further specify that the chelator includes citric acid, acetic acid, glycine, ethanolamine, ethylenediamine,

thylenediaminetetraacetic acid (EDTA), nitrilotriacetic acid (NTA), or iminodiacetic acid (IDA).

[0148] Example 55 may include the subject matter of Example 53, and may further specify that the surfactant includes polyethylene glycol, polyoxyalkylene alkyl ether, polypropylene glycol, poly acrylic acid, bis(3-sulfopropyl)disulfide, 3-mercapto-l-propanesulfonate, thiourea, or thioglycolic acid.

[0149] Example 56 may include the subject matter of any of Examples 53-55, and may further specify that the pH base adjustor includes tetramethylammonium hydroxide.

Claims

Claims:

1. An integrated circuit (IC) component, comprising:

a metal interconnect; and

a metal capping layer on the metal interconnect, wherein the metal capping layer includes at least 99% cobalt.

2. The IC component of claim 1, wherein the metal capping layer includes at least 99.3% cobalt.

3. The IC component of any of claims 1-2, wherein the metal capping layer extends over a liner material, and the liner material is between the metal interconnect and a dielectric material.

4. The IC component of claim 3, wherein the metal interconnect includes copper.

5. The IC component of any of claims 1-2, wherein the metal capping layer is on a layer of seed material between the metal capping layer and the metal interconnect.

6. The IC component of claim 5, wherein the seed material includes cobalt.

7. The IC component of claim 6, wherein the seed material includes less than 97% cobalt.

8. The IC component of claim 6, wherein the seed material includes at least 3% carbon.

9. The IC component of claim 5, wherein the layer of seed material has a thickness between 20 angstroms and 50 angstroms.

10. A bath makeup solution for electroless metal deposition, comprising:

a chelator, wherein the chelator does not include ammonia;

a surfactant; and

a pH base adjustor.

11. The bath makeup solution of claim 10, wherein the chelator includes citric acid, acetic acid, glycine, ethanolamine, ethylenediamine, thylenediaminetetraacetic acid (EDTA), nitrilotriacetic acid (NTA), or iminodiacetic acid (IDA).

12. The bath makeup solution of claim 10, wherein the surfactant includes polyethylene glycol, polyoxyalkylene alkyl ether, polypropylene glycol, poly acrylic acid, bis(3-sulfopropyl)disulfide, 3- mercapto-l-propanesulfonate, thiourea, or thioglycolic acid.

13. The bath makeup solution of any of claims 10-12, wherein the pH base adjustor includes tetramethylammonium hydroxide.

14. A method of depositing a metal on a surface, comprising:

providing a heated solution on the surface, wherein the heated solution includes the metal and hydrazine, and has a pH greater than 10; and

allowing the metal from the heated solution to crystallize on the surface.

15. The method of claim 14, wherein the heated solution includes citrate, acetic acid,

ethylenediaminetetraacetic acid, tartaric acid, or boric acid.

16. The method of claim 14, wherein the heated solution has a temperature between 75 and 95 degrees Celsius.

17. The method of any of claims 14-16, wherein the surface has a sheet resistance greater than or equal to 2500 ohms/sq.

18. The method of any of claims 14-16, wherein providing the heated solution on the surface includes spraying the heated solution on the surface.

19. The method of any of claims 14-16, wherein the surface includes the metal.

20. The method of any of claims 14-16, wherein the surface includes a recess for a via.

21. The method of any of claims 14-16, wherein the metal includes cobalt.

22. The method of any of claims 14-16, wherein the metal includes copper, nickel, platinum, gold, ruthenium, or palladium.

23. A computing device, comprising:

a circuit board; and

a die coupled to the circuit board, wherein the die includes an interconnect in a metallization stack, the interconnect includes a metal fill, and the metal fill includes at least 99% cobalt.

24. The computing device of claim 23, wherein the interconnect includes a via.

25. The computing device of any of claims 23-24, further comprising:

an antenna coupled to the circuit board.