WO2018227830A1 - 主从机tdma时隙同步校准方法及装置 - Google Patents
主从机tdma时隙同步校准方法及装置 Download PDFInfo
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- WO2018227830A1 WO2018227830A1 PCT/CN2017/105618 CN2017105618W WO2018227830A1 WO 2018227830 A1 WO2018227830 A1 WO 2018227830A1 CN 2017105618 W CN2017105618 W CN 2017105618W WO 2018227830 A1 WO2018227830 A1 WO 2018227830A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0644—External master-clock
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0652—Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0647—Synchronisation among TDM nodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0652—Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP]
- H04J3/0655—Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP] using timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/14—Monitoring arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/0005—Synchronisation arrangements synchronizing of arrival of multiple uplinks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/004—Synchronisation arrangements compensating for timing error of reception due to propagation delay
Definitions
- the present application relates to the field of data transmission technologies, and in particular, to a master-slave TDMA slot synchronization calibration method and apparatus.
- time division multiple access (TDMA) time slot synchronization most of them rely on the RTC clock or the GPS module to provide accurate clock source for time slot synchronization, that is, an RTC needs to be set (Real- Time Clock)
- the clock source or the Global Positioning System (GPS) module provides accurate clock information. Thereafter, the clock information is used for slot synchronization.
- GPS Global Positioning System
- an RTC clock source or a GPS module not only increases cost, but also has limitations when used. For example, when the GPS module is used, in the indoor environment, the GPS signal is weak or disappears, and the solution cannot be implemented. When the RTC clock source is used, the RTC clock needs to be calibrated to ensure the accuracy of the clock information.
- the embodiment of the present application provides a master-slave TDMA time slot synchronization calibration method and device, which are used to solve the technical problems in the related art.
- a master-slave TDMA slot synchronization calibration method comprising:
- the synchronization frame includes a first count value of the timing counter in the host
- At least one of the slaves parses the synchronization frame to obtain the first count value
- adjusting the TDMA slot of the slave according to the first count value and the second count value of the timer counter in the slave to enable the TDMA of the slave The slot is synchronized with the TDMA time slot of the host.
- the method before the step of the at least one slave receiving the synchronization frame from the host, the method includes:
- a frequency division operation is performed on the clock source in the slave to determine a time granularity of the timer counter in the slave;
- the step of adjusting the TDMA time slot of the slave according to the first count value and the second count value of the timer counter in the slave comprises:
- the first count value is smaller than the second count value, and the difference between the two is the second value B, subtracting the second value B from the third count value in the comparison register of the slave to obtain the fourth value And counting the value, and controlling the timing counter to recount when the second count value reaches the fourth count value.
- a master-slave TDMA slot synchronization calibration method comprising:
- the host acquires a first count value of the timer counter
- the host reads the third count value in the compare register
- the method before the step of the host acquiring the first count value of the timing counter, the method includes:
- a master-slave TDMA slot synchronization calibration apparatus which is configured in each slave, and the apparatus includes:
- a receiving module configured to receive a synchronization frame from the host;
- the synchronization frame includes a first count value of the timing counter in the host;
- a parsing module configured to parse the synchronization frame by the slave to obtain the first count value
- An adjustment module configured to adjust a TDMA time slot of the slave according to the first count value and a second count value of the timer counter in the slave, so that the TDMA time slot of the slave and the TDMA time of the host The gap remains synchronized.
- the device further includes:
- a first determining module configured to perform a frequency dividing operation on the clock source in the slave to determine a time granularity of the timing counter in the slave;
- the first setting module is configured to set a third count value of the comparison register in the slave.
- the adjusting module includes:
- a first comparing unit configured to keep the second count value of the timer counter in the slave unchanged when the difference between the first count value and the second count value is zero;
- a second comparing unit configured to delay the second count value of the timer counter in the slave when the first count value is greater than the second count value, and the difference between the two is the first value A After the first value A time granularity, the timer counter is controlled to be re-counted;
- a third comparing unit configured to: when the first count value is smaller than the second count value, and the difference between the two is the second value B, subtract the third count value from the comparison register of the slave The second value B obtains a fourth count value, and the timer counter is controlled to recount when the second count value reaches the fourth count value.
- a master-slave TDMA slot synchronization calibration apparatus characterized in that, in each slave, the apparatus comprises:
- An obtaining module configured to acquire a first count value of a timing counter in the host
- a reading module configured to read a third count value in the comparison register in the host
- a generating module configured to: when the first count value is equal to the third count value, execute a preset interrupt program generation synchronization frame to send to at least one slave device, and control the timer counter to recount.
- the device further includes:
- a second determining module configured to perform a frequency dividing operation on the clock source in the host to determine a time granularity of the timing counter in the host;
- a second setting module configured to set a third count value of the comparison register in the host.
- the foregoing method provided by the embodiment of the present application receives the synchronization frame generated by the host, and then parses out the first count value included in the synchronization frame, and finally adjusts the slave according to the first count value and the second count value in the local timer count.
- TDMA time slot of the machine It can be seen that the present application directly utilizes the respective clock sources of the master and the slave to synchronize, without increasing the RTC clock source and the GPS module, thereby reducing the cost and improving the accuracy.
- FIG. 1 is a schematic flow chart of a master-slave TDMA time slot synchronization calibration method according to an embodiment of the present application
- FIG. 2 is a schematic flow chart of a master-slave TDMA slot synchronization calibration method according to another embodiment of the present application
- FIG. 3 is a block diagram of a master-slave TDMA slot synchronization calibration apparatus according to an embodiment of the present application
- FIG. 4 is a block diagram of a master-slave TDMA slot synchronization calibration apparatus according to another embodiment of the present application.
- FIG. 5 is a block diagram of a master-slave TDMA slot synchronization calibration apparatus according to still another embodiment of the present application.
- FIG. 6 is a block diagram of a master-slave TDMA slot synchronization calibration apparatus according to still another embodiment of the present application.
- FIG. 7 is a block diagram of a master-slave TDMA slot synchronization calibration apparatus according to still another embodiment of the present application.
- FIG. 8 is a block diagram of a master-slave TDMA slot synchronization calibration apparatus according to still another embodiment of the present application.
- FIG. 9 is a block diagram of a master-slave TDMA slot synchronization calibration apparatus according to still another embodiment of the present application.
- FIG. 1 is a schematic flow chart of a master-slave TDMA slot synchronization calibration method according to an exemplary embodiment. As shown in FIG. 1, the master-slave TDMA slot synchronization calibration method includes:
- Step 101 At least one slave receives a synchronization frame from the host; the synchronization frame includes a first count value of the timer counter in the host;
- Step 102 At least one of the slaves parses the synchronization frame to obtain the first count value.
- Step 103 For each of the slaves, adjust a TDMA slot of the slave according to the first count value and a second count value of the timer counter in the slave, so that the slave TDMA slot and The TDMA time slots of the host remain synchronized.
- the clock source that is included in the MCU of the microcontroller in the master and the slave is the clock source of the TDMA time slot synchronization.
- a frequency division operation is performed on a clock source of a microcontroller MCU in a host to determine a time granularity of a timing counter in the host.
- the granularity of each time is usually in the millisecond level.
- the operating mode of the compare register in the host is set, for example, the auto-reload function of the enable timer counter is re-counted, and the third count value of the compare register in the host is set.
- the controller in the host When the first count value of the timer counter is equal to the third count value of the comparison register, the controller in the host generates an interrupt signal to execute the preset interrupt routine, and the first count value of the timer counter is automatically cleared and recounted.
- the first count value of the timer counter can be set to reach a count value of 20 ms each time, and an interrupt signal is generated to reach a preset interrupt program when the 20 ms is reached, and the counting is restarted. .
- the slave needs to perform the TDMA time slot calibration to match the host time.
- the gap is synchronized.
- a synchronization frame is constructed and the first count value of the timer counter of the host is sent to at least one slave for reference. Then, each slave obtains the first count value carried in the synchronization frame by parsing the synchronization frame, and then compares with the local second count value, and finally adjusts the difference between the first count value and the second count value to adjust the local The second count value of the timer counter, thereby achieving the purpose of calibrating the time slot.
- the host periodically sends a synchronization frame to each slave device, so that each slave device performs TDMA time slot synchronization with the host, as shown in FIG. 2, including:
- Step 201 When the first count value and the second count value are the same, that is, the difference between the two is zero, the local timer counter of the slave does not need to perform a calibration operation.
- Step 202 The first count value carried by the synchronization frame is greater than the second count value in the slave, and the difference between the first count value and the second count value is the first value A, and the slave adjusts according to the first value A.
- the second count value of the local timer counter In this case, the first value A needs to be added on the basis of the second count value of the timer counter, so that the slave timer counter delays the A time granularity before triggering the interrupt and reloading the count value, thereby ensuring that the slave is restarting.
- the second count value of the slave is synchronized with the first count value in the host.
- Step 203 The first count value carried by the synchronization frame is smaller than the second count value, and the difference between the first count value and the second count value is the second value B, and the slave adjusts the local timing according to the second value B.
- the second count value of the counter At this time, it is necessary to subtract the second count value B on the basis of the second count value, so that the slave timer counter triggers the interrupt after the B time granularity and reloads the count value, thereby ensuring that the slave reloads the count value.
- the second count value of the local timer counter is synchronized with the first count value of the host.
- the host and the slave microcontroller MCU have their own clock source, and as the clock source of the TDMA time slot synchronization, the master and the slave can be synchronized. It can be seen that the solution of the present application is simple to implement, has strong applicability, and does not need to add additional device cost.
- a master-slave TDMA slot synchronization calibration device is provided. And arranged in each slave, as shown in FIG. 3, the device includes:
- the receiving module 301 is configured to receive a synchronization frame from the host, where the synchronization frame includes a first count value of the timer counter in the host;
- the parsing module 302 is configured to parse the synchronization frame by the slave to obtain the first count value
- the adjusting module 303 is configured to adjust a TDMA slot of the slave according to the first count value and a second count value of the timer counter in the slave, so that the TDMA slot of the slave and the TDMA of the host The time slots are kept in sync.
- the apparatus further includes:
- a first determining module 401 configured to perform a frequency dividing operation on the clock source in the slave to determine a time granularity of the timing counter in the slave;
- the first setting module 402 is configured to set a third count value of the comparison register in the slave.
- the adjustment module includes:
- the first comparing unit 501 is configured to keep the second count value of the timer counter in the slave unchanged when the difference between the first count value and the second count value is zero;
- the second comparison unit 502 is configured to delay the second count value of the timer counter in the slave when the first count value is greater than the second count value, and the difference between the two is the first value A After the first value is A time granularity, the timer counter is controlled to recount;
- the third comparison unit 503 is configured to: when the first count value is smaller than the second count value, and the difference between the two is the second value B, subtract the third count value from the comparison register of the slave The second value B obtains a fourth count value, and the timer counter is controlled to recount when the second count value reaches the fourth count value.
- a master-slave TDMA slot synchronization calibration apparatus which is configured in each slave, as shown in FIG. 6, the apparatus includes:
- the obtaining module 601 is configured to acquire a first count value of the timer counter in the host;
- the reading module 602 is configured to read a third count value in the comparison register in the host;
- the generating module 603 is configured to: when the first count value is equal to the third count value, execute a preset interrupt program generation synchronization frame to send to at least one slave device, and control the timer counter to recount.
- the apparatus further includes:
- a second determining module 701 configured to perform a frequency dividing operation on a clock source in the host to determine a time granularity of the timing counter in the host;
- the second setting module 702 is configured to set a third count value of the comparison register in the host.
- a master-slave TDMA slot synchronization calibration apparatus configured in each slave, as shown in FIG. 8, the apparatus includes: at least one processor 801; The processor 801 is communicatively coupled to at least one memory 802, wherein:
- the memory 802 stores program instructions executable by the processor 801, and the processor 801 calls the program instructions to perform the methods provided in the embodiment shown in FIG. 1 and related embodiments, including, for example:
- the synchronization frame includes a first count value of the timer counter in the host
- the slave parses the synchronization frame to obtain the first count value
- the processor 801 and the memory 802 complete communication with each other through the bus 803.
- a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions, when the program When the instructions are executed by the computer, the computer is caused to perform the method as provided in the embodiment shown in FIG. 1 and related embodiments, including, for example:
- the synchronization frame includes a first count value of the timer counter in the host
- the slave parses the synchronization frame to obtain the first count value
- a non-transitory computer readable storage medium storing computer instructions that cause a computer to perform the implementation as shown in FIG. Examples and methods provided by related embodiments include, for example:
- the synchronization frame includes a first count value of the timer counter in the host
- the slave parses the synchronization frame to obtain the first count value
- a master-slave TDMA time slot synchronization calibration apparatus configured in each of the slaves, as shown in FIG. 9, the apparatus, comprising: at least one processor 901; At least one memory 902 communicatively coupled to processor 901, wherein:
- the memory 902 stores program instructions that can be executed by the processor 901, and the processor 901 calls the program instructions to perform the processes involved in the fourth aspect of the embodiments of the present application and related embodiments, including, for example:
- the host acquires a first count value of the timer counter
- the host reads the third count value in the compare register
- the processor 901 and the memory 902 complete communication with each other through the bus 903.
- a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions, when the program When the instructions are executed by a computer, causing the computer to perform the fourth aspect of the embodiments of the present application and related embodiments
- the process for example, includes:
- the host acquires a first count value of the timer counter
- the host reads the third count value in the compare register
- a non-transitory computer readable storage medium storing computer instructions for causing a computer to execute the fourth embodiment of the present application.
- the host acquires a first count value of the timer counter
- the host reads the third count value in the compare register
- the foregoing method provided by the embodiment of the present application receives the synchronization frame generated by the host, and then parses out the first count value included in the synchronization frame, and finally adjusts the slave according to the first count value and the second count value in the local timer count.
- TDMA time slot of the machine It can be seen that the present application directly utilizes the clock source of the master and the slave to synchronize, without increasing the RTC clock source and the GPS module, reducing the cost and improving the accuracy, and has strong industrial applicability.
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Abstract
本申请是关于一种主从机TDMA时隙同步校准方法及装置。所述方法包括:至少一个从机接收来自主机的同步帧;所述同步帧中包括所述主机中定时计数器的第一计数值;至少一个所述从机解析所述同步帧得到所述第一计数值;针对每个所述从机,根据所述第一计数值和该从机中定时计数器的第二计数值调整该从机的TDMA时隙,以使所述从机的TDMA时隙与所述主机的TDMA时隙保持同步。可见,本申请直接利用主机和从机各自时钟源进行同步,无需增加RTC时钟源和GPS模块,降低成本的同时提高准确性。
Description
本申请要求于2017年06月14日提交中国专利局、申请号为201710446549.7、发明名称为“主从机TDMA时隙同步校准方法及装置”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本申请涉及数据传输技术领域,尤其涉及一种主从机TDMA时隙同步校准方法及装置。
目前时分多址(Time Division Multiple Access,TDMA)时隙同步的实现方法中,大部分都要依靠RTC时钟或者是GPS模块来提供精准的时钟源进行时隙同步,即需要设置一个RTC(Real-time Clock)时钟源或者全球卫星定位***(Globle Positioning System,GPS)模块提供精准的时钟信息。之后,利用该时钟信息进行时隙同步。
然而,采用RTC时钟源或者GPS模块不仅会增加成本,而且使用时具有局限性。例如,采用GPS模块时,在室内环境下,由于GPS信号较弱或者消失,导致方案无法实现,采用RTC时钟源时,需要对RTC时钟进行校准才能确保时钟信息的准确性。
发明内容
为克服相关技术中存在的问题,本申请实施例提供一种主从机TDMA时隙同步校准方法及装置,用以解决相关技术中的技术问题。
根据本申请实施例的第一方面,提供一种主从机TDMA时隙同步校准方法,所述方法包括:
至少一个从机接收来自主机的同步帧;所述同步帧中包括所述主机中定时计数器的第一计数值;
至少一个所述从机解析所述同步帧得到所述第一计数值;
针对每个所述从机,根据所述第一计数值和该从机中定时计数器的第二计数值调整该从机的TDMA时隙,以使所述从机的TDMA时
隙与所述主机的TDMA时隙保持同步。
可选地,至少一个从机接收来自主机的同步帧的步骤之前,所述方法包括:
针对每个从机,对该从机中时钟源进行分频操作以确定所述从机中定时计数器的时间粒度;
设置所述从机中比较寄存器的第三计数值。
可选地,根据所述第一计数值和该从机中定时计数器的第二计数值调整该从机的TDMA时隙的步骤,包括:
若所述第一计数值与所述第二计数值之差为零,则保持该从机中定时计数器的第二计数值不变;
若所述第一计数值大于所述第二计数值,且两者之差为第一数值A,则使该从机中定时计数器的第二计数值延时所述第一数值A个时间粒度之后再控制所述定时计数器重新计数;
若所述第一计数值小于所述第二计数值,且两者之差为第二数值B,则将该从机的比较寄存器中第三计数值减去所述第二数值B得到第四计数值,在所述第二计数值到达所述第四计数值时控制所述定时计数器重新计数。
根据本申请实施例的第二方面,提供一种主从机TDMA时隙同步校准方法,所述方法包括:
主机获取定时计数器的第一计数值;
主机读取比较寄存器中的第三计数值;
在所述第一计数值与所述第三计数值相等时,执行预设中断程序生成同步帧发送给至少一个从机,并控制所述定时计数器重新计数。
可选地,主机获取定时计数器的第一计数值的步骤之前,所述方法包括:
对所述主机中时钟源进行分频操作以确定所述主机中定时计数器的时间粒度;
设置所述主机中比较寄存器的第三计数值。
根据本申请实施例的第三方面,提供一种主从机TDMA时隙同步校准装置,配置在每个从机中,所述装置包括:
接收模块,用于接收来自主机的同步帧;所述同步帧中包括所述主机中定时计数器的第一计数值;
解析模块,用于从机解析所述同步帧得到所述第一计数值;
调整模块,用于根据所述第一计数值和该从机中定时计数器的第二计数值调整该从机的TDMA时隙,以使所述从机的TDMA时隙与所述主机的TDMA时隙保持同步。
可选地,所述装置还包括:
第一确定模块,用于对该从机中时钟源进行分频操作以确定所述从机中定时计数器的时间粒度;
第一设置模块,用于设置所述从机中比较寄存器的第三计数值。
可选地,所述调整模块包括:
第一比较单元,用于在所述第一计数值与所述第二计数值之差为零时,保持该从机中定时计数器的第二计数值不变;
第二比较单元,用于在所述第一计数值大于所述第二计数值,且两者之差为第一数值A时,使该从机中定时计数器的第二计数值延时所述第一数值A个时间粒度之后再控制所述定时计数器重新计数;
第三比较单元,用于在所述第一计数值小于所述第二计数值,且两者之差为第二数值B时,将该从机的比较寄存器中第三计数值减去所述第二数值B得到第四计数值,在所述第二计数值到达所述第四计数值时控制所述定时计数器重新计数。
根据本申请实施例的第四方面,提供一种主从机TDMA时隙同步校准装置,其特征在于,配置在每个从机中,所述装置包括:
获取模块,用于获取主机中定时计数器的第一计数值;
读取模块,用于读取所述主机中比较寄存器中的第三计数值;
生成模块,用于在所述第一计数值与所述第三计数值相等时,执行预设中断程序生成同步帧发送给至少一个从机,并控制所述定时计数器重新计数。
可选地,所述装置还包括:
第二确定模块,用于对所述主机中时钟源进行分频操作以确定所述主机中定时计数器的时间粒度;
第二设置模块,用于设置所述主机中比较寄存器的第三计数值。
本申请的实施例提供的技术方案可以包括以下有益效果:
本申请实施例提供的上述方法,通过接收主机生成的同步帧,然后解析出同步帧中包括的第一计数值,最后根据该第一计数值与本地定时计数中的第二计数值调整该从机的TDMA时隙。可见,本申请直接利用主机和从机各自时钟源进行同步,无需增加RTC时钟源和GPS模块,降低成本的同时提高准确性。
应当理解的是,以上的一般描述和后文的细节描述仅是示例性和解释性的,并不能限制本申请。
此处的附图被并入说明书中并构成本说明书的一部分,示出了符合本发明的实施例,并与说明书一起用于解释本发明的原理。
图1是本申请一实施例提供的主从机TDMA时隙同步校准方法的流程示意图;
图2是本申请另一实施例提供的主从机TDMA时隙同步校准方法的流程示意图;
图3是本申请一实施例提供的主从机TDMA时隙同步校准装置的框图;
图4是本申请另一实施例提供的主从机TDMA时隙同步校准装置的框图;
图5是本申请又一实施例提供的主从机TDMA时隙同步校准装置的框图;
图6是本申请再一实施例提供的主从机TDMA时隙同步校准装置的框图;
图7是本申请又一实施例提供的主从机TDMA时隙同步校准装置的框图;
图8是本申请又一实施例提供的主从机TDMA时隙同步校准装置的框图;
图9是本申请又一实施例提供的主从机TDMA时隙同步校准装置的框图。
这里将详细地对示例性实施例进行说明,其示例表示在附图中。下面的描述涉及附图时,除非另有表示,不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本发明相一致的所有实施方式。相反,它们仅是与如所附权利要求书中所详述的、本发明的一些方面相一致的装置和方法的例子。
图1是根据一示例性实施例示出的主从机TDMA时隙同步校准方法的流程示意图。如图1所示,该主从机TDMA时隙同步校准方法,包括:
步骤101,至少一个从机接收来自主机的同步帧;所述同步帧中包括所述主机中定时计数器的第一计数值;
步骤102,至少一个所述从机解析所述同步帧得到所述第一计数值;
步骤103,针对每个所述从机,根据所述第一计数值和该从机中定时计数器的第二计数值调整该从机的TDMA时隙,以使所述从机的TDMA时隙与所述主机的TDMA时隙保持同步。
下面针对主机与至少一个从机交互过程,详细说明上述主从机TDMA时隙同步校准方法。
本申请实施例中,利用主机和从机中微控制器MCU里面自带的时钟源为TDMA时隙同步的时钟源。
首先,本申请一实施例中,对主机中微控制器MCU的时钟源进行分频操作,以确定主机中定时计数器的时间粒度。每个时间粒度通常为毫秒级别。然后,设置主机中比较寄存器的工作模式,例如,使能定时计数器的自动重加载功能即重新计数,并且设置主机中比较寄存器的第三计数值。当定时计数器的第一计数值与比较寄存器的第三计数值相等时,主机中控制器便会产生中断信号来执行预设中断程序,同时定时计数器的第一计数值自动清零并重新计数。
例如,定义一个TDMA的时隙为20ms,则可以通过设置定时计数器的第一计数值来达到每次计数值为20ms,在到达20ms时产生一个中断信号来执行预设中断程序,并重新开始计数。
通常情况下,一个TDMA***中会存在一个主机和至少一个从机的情况,因此,由于主机和从机启动定时计数器的时刻不一样,所以从机需要进行TDMA时隙的校准才能跟主机的时隙进行同步。
为使从机的时隙跟主机的时隙保持一致,本申请一实施例中构造一个同步帧并将主机的定时计数器的第一计数值发送给至少一个从机进行参考。然后,每个从机通过解析同步帧得到该同步帧中携带的第一计数值,然后跟本地的第二计数值进行比较,最后第一计数值和第二计数值两者之差来调整本地定时计数器的第二计数值,从而达到校准时隙的目的。
本申请一实施例中,主机定时向每个从机发送同步帧,以使每个从机与主机进行TDMA时隙同步,如图2所示,包括:
步骤201:在第一计数值和第二计数值相同,即两者之差为零,则该从机的本地定时计数器不需要进行校准操作。
步骤202:同步帧携带的第一计数值大于从机中第二计数值,且第一计数值与第二计数值两者之差为第一数值A,该从机根据第一数值A来调整本地定时计数器的第二计数值。这种情况需要在定时计数器的第二计数值的基础上增加上述第一数值A,使得从机的定时计数器延后A个时间粒度后才触发中断并重新加载计数值,从而确保从机在重新加载计数值后,该从机的第二计数值与主机中第一计数值保持同步。
步骤203:同步帧携带的第一计数值小于从而中第二计数值,且第一计数值和第二计数值两者之差为第二数值B,从机根据第二数值B来调整本地定时计数器的第二计数值。此时,需要在第二计数值的基础上减法第二计数值B,使得从机的定时计数器提前B个时间粒度后触发中断并重新加载计数值,从而确保从机在重新加载计数值后,本地定时计数器的第二计数值与主机的第一计数值保持同步。
至此,本申请实施例中,利用主机和从机中微控制器MCU里面都自带有时钟源,作为TDMA时隙同步的时钟源,可以实现主机和从机同步。可见,本申请的方案实现简单,适用性较强,不需要增加额外的器件成本。
根据本申请另一实施例提供一种主从机TDMA时隙同步校准装
置,配置在每个从机中,如图3所示,所述装置包括:
接收模块301,用于接收来自主机的同步帧;所述同步帧中包括所述主机中定时计数器的第一计数值;
解析模块302,用于从机解析所述同步帧得到所述第一计数值;
调整模块303,用于根据所述第一计数值和该从机中定时计数器的第二计数值调整该从机的TDMA时隙,以使所述从机的TDMA时隙与所述主机的TDMA时隙保持同步。
可选地,如图4所示,所述装置还包括:
第一确定模块401,用于对该从机中时钟源进行分频操作以确定所述从机中定时计数器的时间粒度;
第一设置模块402,用于设置所述从机中比较寄存器的第三计数值。
可选地,如图5所示,所述调整模块包括:
第一比较单元501,用于在所述第一计数值与所述第二计数值之差为零时,保持该从机中定时计数器的第二计数值不变;
第二比较单元502,用于在所述第一计数值大于所述第二计数值,且两者之差为第一数值A时,使该从机中定时计数器的第二计数值延时所述第一数值A个时间粒度之后再控制所述定时计数器重新计数;
第三比较单元503,用于在所述第一计数值小于所述第二计数值,且两者之差为第二数值B时,将该从机的比较寄存器中第三计数值减去所述第二数值B得到第四计数值,在所述第二计数值到达所述第四计数值时控制所述定时计数器重新计数。
根据本申请实施例的第四方面,提供一种主从机TDMA时隙同步校准装置,配置在每个从机中,如图6所示,所述装置包括:
获取模块601,用于获取所述主机中定时计数器的第一计数值;
读取模块602,用于读取所述主机中比较寄存器中的第三计数值;
生成模块603,用于在所述第一计数值与所述第三计数值相等时,执行预设中断程序生成同步帧发送给至少一个从机,并控制所述定时计数器重新计数。
可选地,如图7所示,所述装置还包括:
第二确定模块701,用于对所述主机中时钟源进行分频操作以确定所述主机中定时计数器的时间粒度;
第二设置模块702,用于设置所述主机中比较寄存器的第三计数值。
关于上述实施例中的装置,其中各个单元或者模块执行操作的具体方式已经在有关该方法的实施例中进行了详细描述,此处将不做详细阐述说明。
根据本申请实施例的第五方面,提供一种主从机TDMA时隙同步校准装置,配置在每个从机中,如图8所示,所述装置包括:至少一个处理器801;以及与处理器801通信连接的至少一个存储器802,其中:
存储器802存储有可被处理器801执行的程序指令,处理器801调用程序指令能够执行如图1所示的实施例及其相关实施例所提供的方法,例如包括:
接收来自主机的同步帧;所述同步帧中包括所述主机中定时计数器的第一计数值;
从机解析所述同步帧得到所述第一计数值;
根据所述第一计数值和该从机中定时计数器的第二计数值调整该从机的TDMA时隙,以使所述从机的TDMA时隙与所述主机的TDMA时隙保持同步。
参照图8,本实施例中,所述处理器801、存储器802通过总线803完成相互间的通信。
根据本申请实施例的第六方面,提供一种计算机程序产品,所述计算机程序产品包括存储在非暂态计算机可读存储介质上的计算机程序,所述计算机程序包括程序指令,当所述程序指令被计算机执行时,使所述计算机执行如图1所示的实施例及其相关实施例所提供的方法,例如包括:
接收来自主机的同步帧;所述同步帧中包括所述主机中定时计数器的第一计数值;
从机解析所述同步帧得到所述第一计数值;
根据所述第一计数值和该从机中定时计数器的第二计数值调整该从机的TDMA时隙,以使所述从机的TDMA时隙与所述主机的TDMA时隙保持同步。
根据本申请实施例的第七方面,提供一种非暂态计算机可读存储介质,所述非暂态计算机可读存储介质存储计算机指令,所述计算机指令使计算机执行如图1所示的实施例及其相关实施例所提供的方法,例如包括:
接收来自主机的同步帧;所述同步帧中包括所述主机中定时计数器的第一计数值;
从机解析所述同步帧得到所述第一计数值;
根据所述第一计数值和该从机中定时计数器的第二计数值调整该从机的TDMA时隙,以使所述从机的TDMA时隙与所述主机的TDMA时隙保持同步。
根据本申请实施例的第八方面,提供一种主从机TDMA时隙同步校准装置,配置在每个从机中,如图9所示,所述装置,包括:至少一个处理器901;以及与处理器901通信连接的至少一个存储器902,其中:
存储器902存储有可被处理器901执行的程序指令,处理器901调用程序指令能够执行本申请实施例的第四方面及其相关实施例所涉及的流程,例如包括:
主机获取定时计数器的第一计数值;
主机读取比较寄存器中的第三计数值;
在所述第一计数值与所述第三计数值相等时,执行预设中断程序生成同步帧发送给至少一个从机,并控制所述定时计数器重新计数。
参照图9,本实施例中,所述处理器901、存储器902通过总线903完成相互间的通信。
根据本申请实施例的第九方面,提供一种计算机程序产品,所述计算机程序产品包括存储在非暂态计算机可读存储介质上的计算机程序,所述计算机程序包括程序指令,当所述程序指令被计算机执行时,使所述计算机执行本申请实施例的第四方面及其相关实施例所涉及的
流程,例如包括:
主机获取定时计数器的第一计数值;
主机读取比较寄存器中的第三计数值;
在所述第一计数值与所述第三计数值相等时,执行预设中断程序生成同步帧发送给至少一个从机,并控制所述定时计数器重新计数。
根据本申请实施例的第十方面,提供一种非暂态计算机可读存储介质,所述非暂态计算机可读存储介质存储计算机指令,所述计算机指令使计算机执行本申请实施例的第四方面及其相关实施例所涉及的流程,例如包括:
主机获取定时计数器的第一计数值;
主机读取比较寄存器中的第三计数值;
在所述第一计数值与所述第三计数值相等时,执行预设中断程序生成同步帧发送给至少一个从机,并控制所述定时计数器重新计数。
本领域技术人员在考虑说明书及实践这里公开的公开后,将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化,这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的,本申请的真正范围和精神由下面的权利要求指出。
应当理解的是,本申请并不局限于上面已经描述并在附图中示出的精确结构,并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求来限制。
本申请实施例提供的上述方法,通过接收主机生成的同步帧,然后解析出同步帧中包括的第一计数值,最后根据该第一计数值与本地定时计数中的第二计数值调整该从机的TDMA时隙。可见,本申请直接利用主机和从机各自时钟源进行同步,无需增加RTC时钟源和GPS模块,降低成本的同时提高准确性,具有很强的工业实用性。
Claims (16)
- 一种主从机TDMA时隙同步校准方法,其特征在于,所述方法包括:至少一个从机接收来自主机的同步帧;所述同步帧中包括所述主机中定时计数器的第一计数值;至少一个所述从机解析所述同步帧得到所述第一计数值;针对每个所述从机,根据所述第一计数值和该从机中定时计数器的第二计数值调整该从机的TDMA时隙,以使所述从机的TDMA时隙与所述主机的TDMA时隙保持同步。
- 根据权利要求1所述的主从机TDMA时隙同步校准方法,其特征在于,至少一个从机接收来自主机的同步帧的步骤之前,所述方法包括:针对每个从机,对该从机中时钟源进行分频操作以确定所述从机中定时计数器的时间粒度;设置所述从机中比较寄存器的第三计数值。
- 根据权利要求1所述的主从机TDMA时隙同步校准方法,其特征在于,根据所述第一计数值和该从机中定时计数器的第二计数值调整该从机的TDMA时隙的步骤,包括:若所述第一计数值与所述第二计数值之差为零,则保持该从机中定时计数器的第二计数值不变;若所述第一计数值大于所述第二计数值,且两者之差为第一数值A,则使该从机中定时计数器的第二计数值延时所述第一数值A个时间粒度之后再控制所述定时计数器重新计数;若所述第一计数值小于所述第二计数值,且两者之差为第二数值B,则将该从机的比较寄存器中第三计数值减去所述第二数值B得到第四计数值,在所述第二计数值到达所述第四计数值时控制所述定时计数器重新计数。
- 一种主从机TDMA时隙同步校准方法,其特征在于,所述方法包括:主机获取定时计数器的第一计数值;主机读取比较寄存器中的第三计数值;在所述第一计数值与所述第三计数值相等时,执行预设中断程序生成同步帧发送给至少一个从机,并控制所述定时计数器重新计数。
- 根据权利要求4所述的主从机TDMA时隙同步校准方法,其特征在于,主机获取定时计数器的第一计数值的步骤之前,所述方法包括:对所述主机中时钟源进行分频操作以确定所述主机中定时计数器的时间粒度;设置所述主机中比较寄存器的第三计数值。
- 一种主从机TDMA时隙同步校准装置,其特征在于,配置在每个从机中,所述装置包括:接收模块,用于接收来自主机的同步帧;所述同步帧中包括所述主机中定时计数器的第一计数值;解析模块,用于从机解析所述同步帧得到所述第一计数值;调整模块,用于根据所述第一计数值和该从机中定时计数器的第二计数值调整该从机的TDMA时隙,以使所述从机的TDMA时隙与所述主机的TDMA时隙保持同步。
- 根据权利要求6所述的主从机TDMA时隙同步校准装置,其特征在于,所述装置还包括:第一确定模块,用于对该从机中时钟源进行分频操作以确定所述从机中定时计数器的时间粒度;第一设置模块,用于设置所述从机中比较寄存器的第三计数值。
- 根据权利要求6所述的主从机TDMA时隙同步校准装置,其特征在于,所述调整模块包括:第一比较单元,用于在所述第一计数值与所述第二计数值之差为零时,保持该从机中定时计数器的第二计数值不变;第二比较单元,用于在所述第一计数值大于所述第二计数值,且两者之差为第一数值A时,使该从机中定时计数器的第二计数值延时所述第一数值A个时间粒度之后再控制所述定时计数器重新计数;第三比较单元,用于在所述第一计数值小于所述第二计数值,且两者之差为第二数值B时,将该从机的比较寄存器中第三计数值减去所述第二数值B得到第四计数值,在所述第二计数值到达所述第四计数值时控制所述定时计数器重新计数。
- 一种主从机TDMA时隙同步校准装置,其特征在于,配置在每个从机中,所述装置包括:获取模块,用于获取主机中定时计数器的第一计数值;读取模块,用于读取所述主机中比较寄存器中的第三计数值;生成模块,用于在所述第一计数值与所述第三计数值相等时,执行预设中断程序生成同步帧发送给至少一个从机,并控制所述定时计数器重新计数。
- 根据权利要求9所述的主从机TDMA时隙同步校准装置,其特征在于,所述装置还包括:第二确定模块,用于对所述主机中时钟源进行分频操作以确定所述主机中定时计数器的时间粒度;第二设置模块,用于设置所述主机中比较寄存器的第三计数值。
- 一种主从机TDMA时隙同步校准装置,其特征在于,包括:至少一个处理器;以及与所述处理器通信连接的至少一个存储器,其中:所述存储器存储有可被所述处理器执行的程序指令,所述处理器调用所述程序指令能够执行如权利要求1至3任一所述的方法。
- 一种计算机程序产品,其特征在于,所述计算机程序产品包括存储在非暂态计算机可读存储介质上的计算机程序,所述计算机程序包括程序指令,当所述程序指令被计算机执行时,使所述计算机执行如权利要求1至3任一所述的方法。
- 一种非暂态计算机可读存储介质,其特征在于,所述非暂态计算机可读存储介质存储计算机指令,所述计算机指令使计算机执行如权利要求1至3任一所述的方法。
- 一种主从机TDMA时隙同步校准装置,其特征在于,包括:至少一个处理器;以及与所述处理器通信连接的至少一个存储器,其中:所述存储器存储有可被所述处理器执行的程序指令,所述处理器调用所述程序指令能够执行如权利要求4或5所述的方法。
- 一种计算机程序产品,其特征在于,所述计算机程序产品包括存储在非暂态计算机可读存储介质上的计算机程序,所述计算机程序包括程序指令,当所述程序指令被计算机执行时,使所述计算机执行如权利要求4或5所述的方法。
- 一种非暂态计算机可读存储介质,其特征在于,所述非暂态计算机可读存储介质存储计算机指令,所述计算机指令使计算机执行如权利要求4或5所述的方法。
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Publication number | Priority date | Publication date | Assignee | Title |
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US11075670B2 (en) * | 2017-08-22 | 2021-07-27 | Harxon Corporation | Method and device for frequency hopping synchronization, receiver and transmitter |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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CN107040327B (zh) * | 2017-06-14 | 2019-04-02 | 深圳市华信天线技术有限公司 | 主从机tdma时隙同步校准方法及装置 |
CN107659368B (zh) * | 2017-09-30 | 2019-03-15 | 北京天狼讯业信息技术有限公司 | 一种手持通信设备的同步设备和同步方法 |
CN108134626A (zh) * | 2018-01-16 | 2018-06-08 | 四川安迪科技实业有限公司 | 一种vsat网时间同步方法 |
US10698857B2 (en) | 2018-09-28 | 2020-06-30 | Bristol, Inc | Systems, methods, and apparatus to synchronize data bus access |
FR3108817B1 (fr) | 2020-03-26 | 2022-03-04 | Safran | Procédé de communication selon un protocole TDMA entre un dispositif maître et au moins un dispositif esclave |
CN112311521B (zh) * | 2020-10-30 | 2023-11-17 | 昆腾微电子股份有限公司 | 一种设备组音频同步方法、装置、电子设备和存储介质 |
CN115834282A (zh) * | 2022-11-07 | 2023-03-21 | 交控科技股份有限公司 | 一种can总线通信方法、装置、设备及可读存储介质 |
CN118057261A (zh) * | 2022-11-18 | 2024-05-21 | 北京有竹居网络技术有限公司 | 时钟同步方法及装置、电子设备和存储介质 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0918941A (ja) * | 1995-07-04 | 1997-01-17 | Matsushita Electric Ind Co Ltd | 無線通信システム |
CN1905424A (zh) * | 2005-04-15 | 2007-01-31 | 卓联半导体股份有限公司 | 在粒状分组网络上恢复定时的方法 |
CN106413075A (zh) * | 2015-08-03 | 2017-02-15 | 中兴通讯股份有限公司 | 一种时钟同步的方法和***、端站 |
CN107040327A (zh) * | 2017-06-14 | 2017-08-11 | 深圳市华信天线技术有限公司 | 主从机tdma时隙同步校准方法及装置 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5694392A (en) * | 1995-10-30 | 1997-12-02 | Vlsi Technology, Inc. | Timing system for mobile cellular radio receivers |
US20040028071A1 (en) | 1999-09-10 | 2004-02-12 | Interval Research Corporation, A Washington Corporation | Apparatus and method for managing variable-sized data slots with timestamp counters within a TDMA frame |
US6698022B1 (en) * | 1999-12-15 | 2004-02-24 | Fujitsu Limited | Timestamp-based timing recovery for cable modem media access controller |
US6975610B1 (en) * | 2000-06-19 | 2005-12-13 | Koninklijke Philips Electronics N.V. | System and method for communicating between a plurality of asynchronous systems |
DE10144070A1 (de) * | 2001-09-07 | 2003-03-27 | Philips Corp Intellectual Pty | Kommunikationsnetzwerk und Verfahren zur Steuerung des Kommunikationsnetzwerks |
NO20016328D0 (no) * | 2001-12-21 | 2001-12-21 | Ericsson Telefon Ab L M | Fremgangsmåte og arrangement for transmisjon av bitströmmer gjennom en datanode |
JP3993508B2 (ja) * | 2002-12-02 | 2007-10-17 | 株式会社エヌ・ティ・ティ・ドコモ | 無線アクセスネットワークシステム、無線通信方法、同期サーバ及びノード装置 |
JP4080366B2 (ja) * | 2003-04-01 | 2008-04-23 | シャープ株式会社 | ネットワーク端末、ネットワークシステム、ネットワーク端末の制御方法 |
US7296124B1 (en) * | 2004-06-29 | 2007-11-13 | National Semiconductor Corporation | Memory interface supporting multi-stream operation |
CN1960242B (zh) * | 2006-10-17 | 2011-09-07 | 中控科技集团有限公司 | 实现时钟同步的方法、装置、***及分布式*** |
CN101729420B (zh) * | 2009-12-15 | 2012-11-14 | 杭州迪普科技有限公司 | 一种数据处理方法及装置 |
CN105706016B (zh) * | 2013-09-11 | 2019-07-19 | 欧力天工美国公司 | 用于时钟同步的***、方法和移动设备 |
JP2016100705A (ja) * | 2014-11-20 | 2016-05-30 | セイコーエプソン株式会社 | 時刻同期システム |
CN106559157A (zh) * | 2015-09-29 | 2017-04-05 | 中兴通讯股份有限公司 | 一种时钟同步方法、装置及通信设备 |
EP3156904A1 (en) | 2015-10-13 | 2017-04-19 | Autoliv Development AB | A vehicle safety electronic control system |
-
2017
- 2017-06-14 CN CN201710446549.7A patent/CN107040327B/zh active Active
- 2017-10-11 EP EP17895503.5A patent/EP3444975A4/en not_active Withdrawn
- 2017-10-11 WO PCT/CN2017/105618 patent/WO2018227830A1/zh unknown
- 2017-10-11 US US16/080,568 patent/US10892840B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0918941A (ja) * | 1995-07-04 | 1997-01-17 | Matsushita Electric Ind Co Ltd | 無線通信システム |
CN1905424A (zh) * | 2005-04-15 | 2007-01-31 | 卓联半导体股份有限公司 | 在粒状分组网络上恢复定时的方法 |
CN106413075A (zh) * | 2015-08-03 | 2017-02-15 | 中兴通讯股份有限公司 | 一种时钟同步的方法和***、端站 |
CN107040327A (zh) * | 2017-06-14 | 2017-08-11 | 深圳市华信天线技术有限公司 | 主从机tdma时隙同步校准方法及装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP3444975A4 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11075670B2 (en) * | 2017-08-22 | 2021-07-27 | Harxon Corporation | Method and device for frequency hopping synchronization, receiver and transmitter |
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