WO2018222915A1 - Two-dimensional patterning of integrated circuit layer by tilted ion implantation - Google Patents

Two-dimensional patterning of integrated circuit layer by tilted ion implantation Download PDF

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Publication number
WO2018222915A1
WO2018222915A1 PCT/US2018/035461 US2018035461W WO2018222915A1 WO 2018222915 A1 WO2018222915 A1 WO 2018222915A1 US 2018035461 W US2018035461 W US 2018035461W WO 2018222915 A1 WO2018222915 A1 WO 2018222915A1
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Prior art keywords
hard mask
mask layer
pattern
substrate
substructure
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PCT/US2018/035461
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French (fr)
Inventor
Tsu-Jae King Liu
Fei Ding
Yi-Ting Wu
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The Regents Of The University Of California
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Publication of WO2018222915A1 publication Critical patent/WO2018222915A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00031—Regular or irregular arrays of nanoscale structures, e.g. etch mask layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/05—Arrays
    • B81B2207/056—Arrays of static structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation

Definitions

  • the field of currently claimed embodiments of this invention relates to integrated circuits and methods of producing integrated circuits, and more particularly to integrated circuits produced and methods of production using tilted ion implantation techniques.
  • Photolithography uses light to transfer a geometric pattern from a photomask to the surface of a silicon (Si) wafer substrate comprising multiple chips.
  • the size of the features on the mask is larger than that of the features on the wafer, by the demagnification factor (typically 4-5) of the optical projection system, which provides for lower mask cost.) "Blurring" of the pattern on the wafer produced by the
  • a hard (inorganic) mask material is used rather than photoresist to pattern the IC layer with better etch selectivity; in this case, extra processes are required to deposit the hard mask layer prior to photoresist coating, to etch the hard mask layer, and to remove the hard mask layer after it is used to pattern the IC layer, i.e., 7 processes are needed.
  • the minimum pitch (J ) of features defined by photolithography is limited by diffraction and is proportional to the wavelength of light, ⁇ :
  • P mitl 2 /n. s ii, ⁇
  • ⁇ is the propagation angle of the projection lens system (typically -70°)
  • m is the lowest index of refraction of the propagation medium.
  • J n is twice the lithographic resolution limit.
  • the second technique is referred to as “spacer lithography” or “self-aligned double patterning (SADP)” and is illustrated in FIGS. 2A-2J. It involves even more processes than the litho-etch-litho-etch technique and also requires extra lithography and etch processes to eliminate the portions of the spacers located at the ends of the sacrificial linear features (called “mandrels”); otherwise, the spacers formed along the sidewalls of the same mandrel feature may be interconnected.
  • spacer lithography or “self-aligned double patterning
  • DSA directed self-assembly of a diblock copolymer film: the film is coated onto a wafer with lithographically defined features on its surface, which serve as a guide for the formation of the sub- lithographic features; self-assembly (phase separation) occurs upon heating to form features as small as a few nanometers, depending on the degree of polymerization (number of monomer repeats in the chain) and the block-block interaction parameter.
  • Drawbacks of this technique include a limited range of feature sizes and pitches for a given diblock copolymer material formulation, and feature-edge roughness which does not scale well with the feature size. Therefore, a need remains for improved methods of producing integrated circuits and the improved integrated circuits.
  • An aspect of the present disclosure is to provide a method of producing a micro-device or a nano-device having at least one layer with a sub-lithographic two- dimensional pattern.
  • the method includes providing a substrate comprising a
  • substructure and a hard mask layer formed on the substructure performing a plurality of sequential photolithographic and tilted ion implantation processes to produce a pattern of ion implanted regions in the hard mask layer; selectively etching at least one of the ion implanted regions in the hard mask layer to expose the substructure to produce a two- dimensional pattern in the hard mask layer; and selectively etching the substructure of the substrate in exposed regions to transfer the two-dimensional pattern in the hard mask layer to the substructure of the substrate so as to produce a sub-lithographic two- dimensional structure therein.
  • a further aspect of the present disclosure is to produce a device according to the above method.
  • the device produced according to the above method may include a two-dimensional (2D) pattern, the two-dimensional pattern having a minimum feature pitch smaller than a minimum pitch of a photolithographic process and having a minimum feature size smaller than a photolithographic resolution limit that is achieved solely by using a photolithographic process without using ion implantation.
  • Another aspect of the present disclosure is to provide a structure for producing a device having sub-lithographic two-dimensional structures comprising a substrate comprising a substructure and a hard mask layer formed on the substructure.
  • the hard mask layer defines a two-dimensional pattern therein that exposes the substructure of the substrate according to the two-dimensional pattern.
  • FIG. 1 A is a schematic illustration of a cross-section illustrating the
  • double exposure double etch technique, where the IC layer to be patterned is coated with a hard mask layer
  • FIG. IB is a schematic illustration of the cross-section, where a first layer of light-sensitive "photoresist" is coated onto the hard mask layer;
  • FIG. 1C is a schematic illustration of the cross-section, where
  • photolithography light exposure through a mask, followed by immersion in a chemical developer solution to remove photoresist in regions exposed to light
  • photoresist layer is used to print features in the photoresist layer (note that these features usually are "trimmed" to become narrower than the lithographic resolution limit);
  • FIG. ID is a schematic illustration of the cross-section, where an etch process is used to remove regions of the hard mask layer in regions not protected by the etch-resistant photoresist;
  • FIG. IE is a schematic illustration of the cross-section, where photoresist is selectively removed
  • FIG. IF is a schematic illustration of the cross-section, a second layer of photoresist is coated thereon;
  • FIG. 1G is a schematic illustration of the cross-section, where
  • FIG. 1H is a schematic illustration of the cross-section, where an etch process is used to remove regions of the IC layer not protected by either the hard mask or photoresist;
  • FIG. II is a schematic illustration of the cross-section, where hard mask and photoresist layers are selectively removed.
  • FIG. 2A is a schematic illustration of a cross-section illustrating the self- aligned double patterning technique, where the IC layer to be patterned is coated with a sacrificial layer;
  • FIG. 2B is a schematic illustration of the cross-section, where photoresist is coated onto the sacrificial layer
  • FIG. 2C is a schematic illustration of the cross-section, where
  • photolithography is used to print features in the photoresist layer
  • FIG. 2D is a schematic illustration of the cross-section, where an etch process is used to remove regions of the sacrificial layer in regions not protected by the photoresist;
  • FIG. 2E is a schematic illustration of the cross-section, where photoresist is selectively removed
  • FIG. 2F is a schematic illustration of the cross-section, where a relatively thin hard mask layer is conformally deposited
  • FIG. 2G is a schematic illustration of the cross-section, where an anisotropic etch process is used to form hard-mask "spacers" along the sidewalls of the "mandrel” sacrificial layer features (note that the width of these spacers is correlated with the thickness of the deposited hard mask layer, and can be much smaller than the lithographic resolution limit);
  • FIG. 2H is a schematic illustration of the cross-section, where the sacrificial layer is selectively removed
  • FIG. 21 is a schematic illustration of the cross-section, where an etch process is used to remove regions of the IC layer not protected by the spacers;
  • FIG. 2J is a schematic illustration of the cross-section, where the spacers are selectively removed.
  • FIG. 3 A is a schematic illustration of a cross-section illustrating how a sub-lithographic feature is created in a hard mask layer using a sequence of
  • photolithography and tilted ion implantation processes where photoresist features (formed using a photolithography process) serve to block incoming ions (whose trajectories are indicated by the arrows) from reaching a thin hard mask layer on the surface of the IC substrate, according to an embodiment of the present disclosure
  • FIG. 4A is a schematic plan view showing a first exemplary 2D IC -layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present disclosure
  • FIG. 4B is a schematic plan view showing ID patterns (labeled A, B, C,
  • FIG. 4C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion implantation to generate the four ID patterns A, B, C, D, according to an embodiment of the present disclosure
  • FIG. 5A is a schematic plan view showing a second example of a 2D IC- layer pattern with sub-lithographic features and feature pitch, according to an
  • FIG. 5B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form the 2D pattern, according to an embodiment of the present disclosure
  • FIG. 5C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion
  • FIG. 6A is a schematic plan view showing a third example of a 2D IC- layer pattern according to another embodiment of the current invention with sub- lithographic features and feature pitch, according to an embodiment of the present disclosure
  • FIG. 6B is a schematic plan view showing ID patterns labeled A, B, C, D which when overlaid form the 2D pattern, according to an embodiment of the present disclosure
  • FIG. 6C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion
  • FIG.7A is a schematic plan view showing a fourth example of a 2D IC- layer pattern according to another embodiment of the current invention with sub- lithographic features and feature pitch, according to an embodiment of the present disclosure
  • FIG.7B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present disclosure
  • FIG.7C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the three ID patterns, according to an embodiment of the present disclosure
  • FIG. 8A is a schematic plan view showing a fifth example of a 2D IC- layer pattern with sub-lithographic features and feature pitch, according to an
  • FIG. 8B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present disclosure
  • FIG. 8C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion
  • FIG. 9A is a schematic plan view showing a sixth example of a 2D IC- layer pattern with sub-lithographic features and feature pitch, according to an
  • FIG. 9B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present disclosure.
  • FIG. 9C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion
  • An IC manufacturing method for achieving a two-dimensional (2D) pattern with minimum feature pitch smaller than the minimum pitch of the photolithographic process (J n) and with minimum feature size smaller than the lithographic resolution limit (.Pmin/2) is disclosed.
  • This new method uses multiple lithography processes, each followed by a tilted ion implantation (TII) process, to create a latent 2D pattern in a hard mask layer.
  • TII tilted ion implantation
  • the 2D pattern in the hard mask is "developed” by etching the hard mask material either selectively in the implanted regions or selectively in the non-implanted regions.
  • the 2D pattern is transferred to an underlying IC layer by an etch process.
  • FIGS. 3A-3B illustrate how a latent sub-lithographic pattern is created in a hard mask layer on the surface of an IC substrate, using a sequence of photolithography and TII processes ("litho-TII" for short), according to an embodiment of the present disclosure.
  • FIG. 3A is a schematic illustration of a cross-section illustrating how a sub- lithographic feature is created in a hard mask layer using a sequence of photolithography and tilted ion implantation processes (litho-TII) [S.W. Kim et al., Journal of Vacuum Science and Technology B, vol.
  • photoresist features formed using a photolithography process serve to block incoming ions (whose trajectories are indicated by the arrows) from reaching a thin hard mask layer on the surface of the IC substrate.
  • Ion implantation is a relatively simple process as compared to lithography, deposition and etch processes, as it does not require steps to pre-coat, pre-clean, or pre- bake the wafer. It is used in IC manufacturing to introduce impurity atoms in precise amounts (dose in the range from I0 n /cm 2 to 10 16 /cni 2 ) into the surface region of the wafer, over a range of depths ("projected range" determined by the implant energy, which can range from ⁇ 1 keV to 60 keV in common ini planters). The implantation tilt angle can be readily adjusted in the range from -60° to +60°.
  • the implanted species can be inert species such as argon (Ar) or xenon (Xe), or other inert species.
  • the implanted species can also be oxygen (O), nitrogen (N), or silicon (Si) depending on the hard mask material (silicon oxide, silicon nitride, SiOxNy, SiOxCy, etc.).
  • the atoms e.g., Ar, Xe, O, N, Si, etc.
  • the ions are then neutralized with an electron gun once the ions hit the target.
  • the implant dose can be in the range from 1E14 to 1E15 per square centimeter, with less than +/- 5% variation across the wafer.
  • FIGS. 4A-4C show plan-view schematics of a first exemplary 2D pattern, how it can be formed as a composite of overlaid ID patterns, and a corresponding set of dark-field lithographic mask features ⁇ i.e., corresponding to the rectangular regions from which photoresist is to be removed in developer solution) that can be used to define the ID patterns via multiple litho-TII sequences.
  • FIG. 4A is a schematic plan view showing a 2D IC -layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present disclosure.
  • FIG. 4B is a schematic plan view showing ID patterns (labeled A, B, C, D) which when overlaid form the 2D pattern shown in FIG.
  • FIG. 4C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to generate the four ID patterns A, B, C, D, according to an embodiment of the present disclosure.
  • t e lithographic resolution limit is indicated as Pm 2.
  • the ion trajectory direction is indicated by the dashed arrows (shown in
  • FIG. 4C according to the line type for each dark-field mask feature.
  • a hard mask layer is deposited onto the IC layer; then litho-TII is performed using each of the four masks in sequence; afterwards the hard mask is selectively etched to form the composite 2D pattern, after which the 2D pattern is transferred to the IC layer by a selective etch process.
  • the constituent orthogonal ID pattern features overlap.
  • the degree of overlap in each direction can be adjusted in practice to minimize unwanted blurring or bloating while ensuring a continuous bend.
  • the resultant 2D pattern is "dark-field.”
  • the unimplanted regions of the hard mask layer are subsequently selectively etched away (i.e., implantation serves to retard the etch rate of the hard mask material), then the resultant 2D pattern is "bright-field.”
  • litho-TII lithographic tilted ion implantation
  • the features of the lithographic masks can be automatically generated by first decomposing each 2D feature into a minimum number of horizontal and vertical overlapping ID features (see, FIG. 4B), then apportioning all of the ID features of the decomposed pattern across multiple masks as needed to comply with lithographic design rules (similarly as is done today for the conventional LELE method), and finally generating for each I D feature a rectangular mask feature that circumscribes three sides of the ID feature - corresponding to the region to be implanted - and that complies with the resolution limit (Pmm/2), as illustrated in FIG. 4C.
  • FIG. 9A-9C show various rectangular mask features and configurations that could be used to form other 213 patterns using this method according to some embodiments of the current invention.
  • FIG. 5A is a schematic plan view showing a second example of a 2D IC-layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG. 5B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form the 2D pattern, according to an embodiment of the present invention.
  • FIG. 5C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to generate the three ID patterns A, B and C, according to an embodiment of the present invention.
  • FIG. 5A is a schematic plan view showing a second example of a 2D IC-layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG. 5B is a schematic plan view showing ID patterns labeled A
  • FIG. 6A is a schematic plan view showing a third example of a 2D IC-layer pattern according to another embodiment of the current invention with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG. 6B is a schematic plan view showing ID patterns labeled A, B, C, D which when overlaid form the 2D pattern, according to an embodiment of the present invention.
  • FIG. 6C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the four ID patterns A, B, C and D, according to an embodiment of the present invention.
  • FIG.7A is a schematic plan view showing a fourth example of a 2D IC-layer pattern according to another embodiment of the current invention with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG.7B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present invention.
  • FIG.7C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the three ID patterns A, B and C, according to an embodiment of the present invention.
  • FIG.7A is a schematic plan view showing a fourth example of a 2D IC-layer pattern according to another embodiment of the current invention with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG.7B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the
  • FIG. 8A is a schematic plan view showing a fifth example of a 2D IC-layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG. 8B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present invention.
  • FIG. 8C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the three ID patterns A, B and C, according to an embodiment of the present invention.
  • FIG. 9A is a schematic plan view showing a sixth example of a 2D IC-layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG. 9A is a schematic plan view showing a sixth example of a 2D IC-layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG. 9B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present invention.
  • FIG. 9A is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the three ID patterns A, B and C, according to an embodiment of the present invention.
  • a minimum feature size of each of the mask patterns can be less than or equal to the lithographic resolution limit .Pmin/2, for example.
  • an embodiment of the present invention provides a method of producing a micro-device or a nano-device having at least one layer with a sub-lithographic two-dimensional pattern.
  • the method includes providing a substrate comprising a substructure and a hard mask layer formed on the substructure.
  • the method further includes performing a plurality of sequential photolithographic and tilted ion implantation processes to produce a pattern of ion implanted regions in the hard mask layer.
  • the method also includes selectively etching at least one of the ion implanted regions in the hard mask layer to expose the substructure to produce a two-dimensional pattern in the hard mask layer.
  • the method further includes etching the substructure of the substrate in exposed regions to transfer the two- dimensional pattern in the hard mask layer to the substructure of the substrate so as to produce a sub-lithographic two-dimensional structure therein.
  • the angle a may be equal to substantially 90 degrees.
  • the method further includes removing remaining portions of the hard mask from the substructure of the substrate.
  • the performing the plurality of sequential photolithographic and tilted ion implantation processes includes resolving the sub- lithographic two-dimensional pattern as a plurality of linear patterns for performing a plurality of sequential photolithographic and tilted ion implantation processes.
  • the method may further includes performing additional processing steps such that the method is a method of producing an integrated microsystem.
  • the method may also include performing additional processing steps such that the method is a method of producing a micro-electro-mechanical (MEM) or nano- electro-mechanical (NEM) device.
  • providing the substrate may include forming the hard mask layer on the substructure of the substrate.
  • providing the substrate comprises forming the hard mask layer on the substructure of the substrate. In an embodiment, providing the substrate comprises providing a substrate having a semiconductor layer. In an embodiment, the method may further include forming the hard mask layer on the substructure, the hard mask layer comprising an oxide layer.
  • the oxide layer may include silicon oxide (Si0 2 ).
  • performing the tilted ion implantation processes includes introducing impurity atoms in precise amounts into a selected surface region of the hard mask layer.
  • the impurity atoms may be introduced over a range of depths depending upon an energy of incident ions on the surface, for example.
  • the implantation tilt angle can also be adjusted in a range from -60° to +60° depending on desired implantation configuration, for example.
  • Another embodiment of the present invention is to produce a device according to the above described method.
  • the device includes a two-dimensional pattern having a minimum feature pitch smaller than a minimum pitch of a photolithographic process and having a minimum feature size smaller than a photolithographic resolution limit that is achieved solely by using a photolithographic process without using ion implantation.
  • Another embodiment of the present invention is to provide a structure for producing a device having sub-lithographic two-dimensional structures.
  • the device includes a substrate having a substructure and a hard mask layer formed on the substructure.
  • the hard mask layer defines a two-dimensional pattern therein that exposes the substructure of the substrate according to the two-dimensional pattern.
  • sub-lithographic is intended to refer to feature sizes and/or spacing between features that are smaller than that which can be achieved with a corresponding photolithographic process itself.
  • the "pitch" of linear features is defined as the distance between their centerlines. For the case in which a patterning process produces the smallest feature size and/or pitch that is possible with a single photolithographic exposure step at the time (i.e., at the resolution limit of photolithography), a sub-lithographic process produces feature sizes and/or achieves feature pitches that are even smaller.
  • the broad concepts of methods according to some embodiments of the current invention are not limited to only this example. In some cases, it may be desirable to use methods in accordance with some embodiments of the current invention in combination with feature and/or pitch sizes that are larger than the resolution limit of the photolithographic process.
  • photolithography is intended to refer to any lithographic processes that use "light” (i.e., electromagnetic radiation) of any wavelength including, but not limited to, visible light, ultraviolet light, deep ultraviolet light, and extreme ultraviolet light, for example.
  • photolithographic process is intended to have a broad definition that can include multiple steps such as, but not limited to, forming a layer of photoresist, exposing the photoresist layer to a pattern of light, and developing the photoresist layer to remove one of regions exposed to the light or regions unexposed to the light. It can also include additional deposition and processing steps, including, but not limited to multiple photolithographic processes.
  • ion implantation process is intended to refer to any process by which ions are impacted into a solid to change the physical, chemical, or electrical properties of the solid.
  • tiltted ion implantation is intended to refer to an ion implantation process in which the trajectory of the ions is not substantially orthogonal to the surface of the solid.
  • linear pattern or "one-dimensional pattern” is intended to mean a pattern with one or more features that each extends in only one direction, with a substantially uniform width along its length, as is understood within the art.
  • two-dimensional pattern is intended to mean a pattern having features that extend in two orthogonal directions.
  • two-dimensional structure is intended to mean a structure having features that extend in two orthogonal directions within the same layer.
  • a two-dimensional pattern can be resolved as a combination of a plurality of linear patterns that can be defined sequentially.
  • the broad concepts of the current invention are not limited to only two- dimensional patterns that can be resolved as a combination of linear features.
  • ion implant defined pattern is intended to refer to a pattern that is defined by one or more ion implantation processes. Regions outside of the ion implant defined pattern may or may not have been subjected to an ion implantation process.
  • the term "hard mask layer” is intended to refer to a material layer that is patterned according to one or more processes and that is subsequently used as a mask to transfer its pattern to an underlying material layer.
  • the processes can include ion implantation processes using embodiments of the current invention either with or without other conventional processes in the same layer in some embodiments.
  • substrate' is intended to have a broad definition which can include a simple structure such as, but not limited to, a semiconductor wafer with a hard mask layer, but can in other embodiments be a more complex structure in itself having one or more additional layers of materials and/or other previously produced substructures.
  • the semiconductor wafer can be, but is not limited to, a silicon wafer, for example.

Abstract

A method of producing a micro-device or a nano-device having at least one layer with a sub-lithographic two-dimensional pattern is described herein. The method includes providing a substrate comprising a substructure and a hard mask layer formed on the substructure; performing a plurality of sequential photolithographic and tilted ion implantation processes to produce a pattern of ion implanted regions in the hard mask layer; selectively etching at least one of the ion implanted regions in the hard mask layer to expose the substructure to produce a two-dimensional pattern in the hard mask layer; and selectively etching the substructure of the substrate in exposed regions to transfer the two-dimensional pattern in the hard mask layer to the substructure of the substrate so as to produce a sub-lithographic two-dimensional structure therein.

Description

TWO-DIMENSIONAL PATTERNING OF INTEGRATED CIRCUIT LAYER BY TILTED ION IMPLANTATION
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority benefit to U.S. Provisional Patent
Application No. 62/513,104 filed on May 31, 2017, the entire content of which is incorporated herein by reference. All references cited anywhere in this specification, including the Background and Detailed Description sections, are incorporated by reference as if each had been individually incorporated.
BACKGROUND
1. Technical Field
[0002] The field of currently claimed embodiments of this invention relates to integrated circuits and methods of producing integrated circuits, and more particularly to integrated circuits produced and methods of production using tilted ion implantation techniques.
2. Discussion of Related Art
[0003] The proliferation of information technology (IT), which has had dramatic economic and social impact, has been enabled by the steady advancement of integrated circuit (IC) technology following Moore's Law, which states that the number of transistors on an IC "chip" doubles every two years. Gordon Moore observed in 1965 that "The complexity for minimum component costs has increased at a rate of roughly a factor of twoper year..." (He revised this rate in 1975, to be 2 times every 2 years.) In other words, theprimary reason for increasing the number of components (transistors) on a chip is to lower the manufacturing cost per component. Increased integration also has the benefits of providing for improved system performance and energy efficiency. Therefore, the semiconductor industry has steadily scaled linear transistor dimensions, by
approximately 0.7 times with every new generation of manufacturing technology, over the past 50 years. The most advanced chips today comprise over 10 billion transistors within an area of a few cm2. The pace of IC technology advancement has slowed down for the most recent generations, however, due to fundamental limits of the conventional photolithographic patterning process.
[0004] Photolithography uses light to transfer a geometric pattern from a photomask to the surface of a silicon (Si) wafer substrate comprising multiple chips. (The size of the features on the mask is larger than that of the features on the wafer, by the demagnification factor (typically 4-5) of the optical projection system, which provides for lower mask cost.) "Blurring" of the pattern on the wafer produced by the
photolithographic process worsens as the size of the features shrinks further below the wavelength of the light, which is 193 nm for the most advanced exposure tools used in high-volume IC manufacturing today. The more complex the shape of a sub -wavelength feature, the more difficult it is to print with good fidelity. For example, "two- dimensional" features that have serifs such as brackets ( [ ) or bends such as in the letter "L" or zig-zags ( |— ' ) are much more difficult to print than "one-dimensional" features, i.e., straight lines, due to more complex diffraction effects. Therefore, for the most advanced chips produced today, the densest IC layer patterns are restricted to comprise only linear ("one-dimensional") features, often with uniform pitch (i.e., uniform line- width and spacing).
[0005] Conventional patterning of an IC layer involves 4 processes: (1) coating of a light-sensitive organic material called photoresist, (2) photolithography, i.e., light exposure through a mask followed by immersion in a chemical developer solution to reproduce the mask pattern in the photoresist layer, (3) selective etch to transfer the pattern from the photoresist layer into the IC layer, and (4) selective removal of the photoresist layer. For layers with critical dimensions, a hard (inorganic) mask material is used rather than photoresist to pattern the IC layer with better etch selectivity; in this case, extra processes are required to deposit the hard mask layer prior to photoresist coating, to etch the hard mask layer, and to remove the hard mask layer after it is used to pattern the IC layer, i.e., 7 processes are needed. The minimum pitch (J ) of features defined by photolithography is limited by diffraction and is proportional to the wavelength of light, λ:
Pmitl = 2 /n.sii, θ where is a process factor with a physical lower limit of 0.25, Θ is the propagation angle of the projection lens system (typically -70°), and m is the lowest index of refraction of the propagation medium. (J n is twice the lithographic resolution limit.) For a state-of- the-art 193 nm water-immersion ( = 1.44) exposure tool, Pm ~ 90 nm.
[0006] Due to the low transmittance of blank mask materials and/or the limited availability of high-intensity light sources for wavelengths shorter than 193 nm, the semiconductor industry has resorted to "multiple-patterning" techniques to increase the density of linear features patterned in an IC layer on a chip. Only the two most commonly used of these will be reviewed here, for brevity. The first technique is referred to as "double exposure, double etch" or "litho-etch-litho-etch (LELE)" and is illustrated in FIGS. 1 A- II. As implied by its name, it involves roughly twice the number of processes as the conventional process to pattern a single IC layer. The second technique is referred to as "spacer lithography" or "self-aligned double patterning (SADP)" and is illustrated in FIGS. 2A-2J. It involves even more processes than the litho-etch-litho-etch technique and also requires extra lithography and etch processes to eliminate the portions of the spacers located at the ends of the sacrificial linear features (called "mandrels"); otherwise, the spacers formed along the sidewalls of the same mandrel feature may be interconnected.
[0007] The additional cost due to extra lithography or deposition and etch processes (each of which involve multiple steps, e.g., anti-reflection coating, bake, pre- clean, etc.) associated with multiple-patterning techniques, as well as the need for multiple one-dimensionally patterned wiring layers (each comprising parallel linear features running in a direction orthogonal to that of features in adjacent layers) to interconnect transistors on a chip, threaten to bring Moore's Law to an end. This in turn would stunt not only the growth of the semiconductor industry but also the growth of the world-wide economy. (IT-using and IT -producing industries are estimated to generate nearly all economic productivity growth in the U.S. economy from 2010-2020 [D.W. Jorgensen et al., Journal of Productivity Analysis, vol. 36, no. 2, pp. 159-175, 2011].)
[0008] To address the issue of increasing patterning cost, alternative methods for defining sub-lithographic features {i.e. with minimum feature size smaller than the resolution limit of photolithography) are needed. One example is directed self-assembly (DSA) of a diblock copolymer film: the film is coated onto a wafer with lithographically defined features on its surface, which serve as a guide for the formation of the sub- lithographic features; self-assembly (phase separation) occurs upon heating to form features as small as a few nanometers, depending on the degree of polymerization (number of monomer repeats in the chain) and the block-block interaction parameter. Drawbacks of this technique include a limited range of feature sizes and pitches for a given diblock copolymer material formulation, and feature-edge roughness which does not scale well with the feature size. Therefore, a need remains for improved methods of producing integrated circuits and the improved integrated circuits.
SUMMARY OF THE DISCLOSURE
[0009] An aspect of the present disclosure is to provide a method of producing a micro-device or a nano-device having at least one layer with a sub-lithographic two- dimensional pattern. The method includes providing a substrate comprising a
substructure and a hard mask layer formed on the substructure; performing a plurality of sequential photolithographic and tilted ion implantation processes to produce a pattern of ion implanted regions in the hard mask layer; selectively etching at least one of the ion implanted regions in the hard mask layer to expose the substructure to produce a two- dimensional pattern in the hard mask layer; and selectively etching the substructure of the substrate in exposed regions to transfer the two-dimensional pattern in the hard mask layer to the substructure of the substrate so as to produce a sub-lithographic two- dimensional structure therein.
[0010] A further aspect of the present disclosure is to produce a device according to the above method. The device produced according to the above method may include a two-dimensional (2D) pattern, the two-dimensional pattern having a minimum feature pitch smaller than a minimum pitch of a photolithographic process and having a minimum feature size smaller than a photolithographic resolution limit that is achieved solely by using a photolithographic process without using ion implantation.
[0011] Another aspect of the present disclosure is to provide a structure for producing a device having sub-lithographic two-dimensional structures comprising a substrate comprising a substructure and a hard mask layer formed on the substructure. The hard mask layer defines a two-dimensional pattern therein that exposes the substructure of the substrate according to the two-dimensional pattern.
BRIEF DESCRIPTION OF THE DRAWINGS [0012] The present disclosure, as well as the methods of operation and functions of the related elements of structure and the combination of parts and economies of manufacture, will become more apparent upon consideration of the following description and the appended claims with reference to the accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate corresponding parts in the various figures. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the invention.
[0013] FIG. 1 A is a schematic illustration of a cross-section illustrating the
"double exposure double etch" technique, where the IC layer to be patterned is coated with a hard mask layer;
[0014] FIG. IB is a schematic illustration of the cross-section, where a first layer of light-sensitive "photoresist" is coated onto the hard mask layer;
[0015] FIG. 1C is a schematic illustration of the cross-section, where
photolithography (light exposure through a mask, followed by immersion in a chemical developer solution to remove photoresist in regions exposed to light) is used to print features in the photoresist layer (note that these features usually are "trimmed" to become narrower than the lithographic resolution limit);
[0016] FIG. ID is a schematic illustration of the cross-section, where an etch process is used to remove regions of the hard mask layer in regions not protected by the etch-resistant photoresist;
[0017] FIG. IE is a schematic illustration of the cross-section, where photoresist is selectively removed;
[0018] FIG. IF is a schematic illustration of the cross-section, a second layer of photoresist is coated thereon;
[0019] FIG. 1G is a schematic illustration of the cross-section, where
photolithography is used to print features in the photoresist layer, inevitably misaligned with the features defined by the 1st photoresist layer; [0020] FIG. 1H is a schematic illustration of the cross-section, where an etch process is used to remove regions of the IC layer not protected by either the hard mask or photoresist;
[0021] FIG. II is a schematic illustration of the cross-section, where hard mask and photoresist layers are selectively removed.
[0022] FIG. 2A is a schematic illustration of a cross-section illustrating the self- aligned double patterning technique, where the IC layer to be patterned is coated with a sacrificial layer;
[0023] FIG. 2B is a schematic illustration of the cross-section, where photoresist is coated onto the sacrificial layer;
[0024] FIG. 2C is a schematic illustration of the cross-section, where
photolithography is used to print features in the photoresist layer;
[0025] FIG. 2D is a schematic illustration of the cross-section, where an etch process is used to remove regions of the sacrificial layer in regions not protected by the photoresist;
[0026] FIG. 2E is a schematic illustration of the cross-section, where photoresist is selectively removed;
[0027] FIG. 2F is a schematic illustration of the cross-section, where a relatively thin hard mask layer is conformally deposited;
[0028] FIG. 2G is a schematic illustration of the cross-section, where an anisotropic etch process is used to form hard-mask "spacers" along the sidewalls of the "mandrel" sacrificial layer features (note that the width of these spacers is correlated with the thickness of the deposited hard mask layer, and can be much smaller than the lithographic resolution limit);
[0029] FIG. 2H is a schematic illustration of the cross-section, where the sacrificial layer is selectively removed;
[0030] FIG. 21 is a schematic illustration of the cross-section, where an etch process is used to remove regions of the IC layer not protected by the spacers; [0031] FIG. 2J is a schematic illustration of the cross-section, where the spacers are selectively removed.
[0032] FIG. 3 A is a schematic illustration of a cross-section illustrating how a sub-lithographic feature is created in a hard mask layer using a sequence of
photolithography and tilted ion implantation processes (litho-TII), where photoresist features (formed using a photolithography process) serve to block incoming ions (whose trajectories are indicated by the arrows) from reaching a thin hard mask layer on the surface of the IC substrate, according to an embodiment of the present disclosure;
[0033] FIG. 3B is a schematic illustration of the cross-section, where the implanted region of the hard mask layer has a dimension x = I - /z(tan Θ - cot a) that is smaller than the mask-defined feature of size /, according to an embodiment of the present disclosure;
[0034] FIG. 4A is a schematic plan view showing a first exemplary 2D IC -layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present disclosure;
[0035] FIG. 4B is a schematic plan view showing ID patterns (labeled A, B, C,
D) which when overlaid form the 2D pattern shown in FIG. 4A, according to an embodiment of the present disclosure;
[0036] FIG. 4C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion implantation to generate the four ID patterns A, B, C, D, according to an embodiment of the present disclosure;
[0037] FIG. 5A is a schematic plan view showing a second example of a 2D IC- layer pattern with sub-lithographic features and feature pitch, according to an
embodiment of the present disclosure;
[0038] FIG. 5B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form the 2D pattern, according to an embodiment of the present disclosure; [0039] FIG. 5C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion
implantation to generate the three ID patterns, according to an embodiment of the present disclosure;
[0040] FIG. 6A is a schematic plan view showing a third example of a 2D IC- layer pattern according to another embodiment of the current invention with sub- lithographic features and feature pitch, according to an embodiment of the present disclosure;
[0041] FIG. 6B is a schematic plan view showing ID patterns labeled A, B, C, D which when overlaid form the 2D pattern, according to an embodiment of the present disclosure;
[0042] FIG. 6C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion
implantation to define the four ID patterns, according to an embodiment of the present disclosure;
[0043] FIG.7A is a schematic plan view showing a fourth example of a 2D IC- layer pattern according to another embodiment of the current invention with sub- lithographic features and feature pitch, according to an embodiment of the present disclosure;
[0044] FIG.7B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present disclosure;
[0045] FIG.7C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the three ID patterns, according to an embodiment of the present disclosure;
[0046] FIG. 8A is a schematic plan view showing a fifth example of a 2D IC- layer pattern with sub-lithographic features and feature pitch, according to an
embodiment of the present disclosure; [0047] FIG. 8B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present disclosure;
[0048] FIG. 8C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion
implantation to define the three ID patterns, according to an embodiment of the present disclosure;
[0049] FIG. 9A is a schematic plan view showing a sixth example of a 2D IC- layer pattern with sub-lithographic features and feature pitch, according to an
embodiment of the present disclosure;
[0050] FIG. 9B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present disclosure; and
[0051] FIG. 9C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion
implantation to define the three ID patterns, according to an embodiment of the present disclosure.
DETAILED DESCRIPTION
[0052] Some embodiments of the current invention are discussed in detail below.
In describing embodiments, specific terminology is employed for the sake of clarity. However, the invention is not intended to be limited to the specific terminology so selected. A person skilled in the relevant art will recognize that other equivalent components can be employed and other methods developed without departing from the broad concepts of the current invention. All references cited anywhere in this specification, including the Background and Detailed Description sections, are incorporated by reference as if each had been individually incorporated.
[0053] An IC manufacturing method for achieving a two-dimensional (2D) pattern with minimum feature pitch smaller than the minimum pitch of the photolithographic process (J n) and with minimum feature size smaller than the lithographic resolution limit (.Pmin/2) is disclosed. This new method uses multiple lithography processes, each followed by a tilted ion implantation (TII) process, to create a latent 2D pattern in a hard mask layer. Subsequently, the 2D pattern in the hard mask is "developed" by etching the hard mask material either selectively in the implanted regions or selectively in the non-implanted regions. Afterwards the 2D pattern is transferred to an underlying IC layer by an etch process. Although the methods are described herein being used for manufacturing an Integrated Circuit (IC) device, in general, the present methods can be used to produce any micro-device or a nano-device having at least one layer with a sub-lithographic two-dimensional pattern.
[0054] FIGS. 3A-3B illustrate how a latent sub-lithographic pattern is created in a hard mask layer on the surface of an IC substrate, using a sequence of photolithography and TII processes ("litho-TII" for short), according to an embodiment of the present disclosure. FIG. 3A is a schematic illustration of a cross-section illustrating how a sub- lithographic feature is created in a hard mask layer using a sequence of photolithography and tilted ion implantation processes (litho-TII) [S.W. Kim et al., Journal of Vacuum Science and Technology B, vol. 34, 040608, 2016], where photoresist features (formed using a photolithography process) serve to block incoming ions (whose trajectories are indicated by the arrows) from reaching a thin hard mask layer on the surface of the IC substrate. FIG. 3B is a schematic illustration of the cross-section, where the implanted region of the hard mask layer has a dimension x = I - /z(tan Θ - cot a) that is smaller than the mask-defined feature of size /, wherein h corresponds to a height of the mask-defined feature, angle Θ corresponds to an angle of a trajectory of incident ions relative to a normal to the surface of the substrate, and angle a corresponds to an angle of a wall of the mask-defined feature relative to the surface of the substrate.
[0055] Ion implantation is a relatively simple process as compared to lithography, deposition and etch processes, as it does not require steps to pre-coat, pre-clean, or pre- bake the wafer. It is used in IC manufacturing to introduce impurity atoms in precise amounts (dose in the range from I0n/cm2 to 1016/cni2) into the surface region of the wafer, over a range of depths ("projected range" determined by the implant energy, which can range from <1 keV to 60 keV in common ini planters). The implantation tilt angle can be readily adjusted in the range from -60° to +60°. It has been experimentally found that the rate at which silicon-dioxide (Si02) is etched in dilute hydrofluoric (HF) acid solution can be enhanced (by up to 9x) by implantation-induced damage [S.W. Kim el a!., Journal of Vacuum Science and Technology B. vol. 34, 040608, 2016]. By leveraging this effect together with the shadowing effect of mask features (defined by conventional lithography or by multiple-patterning techniques) overlying the hard mask layer surface, features smaller than the lithographic resolution limit - down to below 10 nm - can be achieved, and the density of features can be doubled [P. Zheng el αί,, IEEE Tramaciions on Electron Devices, vol. 64, no. 1, pp. 231-236, 2017], Note that an implant-defined feature size can be easily fine-tuned by adjusting the ion implant tilt angle Θ. (See also PCT/US2016/030218 filed April 29, 2016 assigned to the same assignee as the current- application, the entire content of which is hereby incorporated by reference.)
[0056] In some embodiments, the implanted species can be inert species such as argon (Ar) or xenon (Xe), or other inert species. The implanted species can also be oxygen (O), nitrogen (N), or silicon (Si) depending on the hard mask material (silicon oxide, silicon nitride, SiOxNy, SiOxCy, etc.). Inside the ion implanter, the atoms (e.g., Ar, Xe, O, N, Si, etc.) are ionized so as to be accelerated and guided toward the substrate material (wafer target). The ions are then neutralized with an electron gun once the ions hit the target. In an embodiment, the implant dose can be in the range from 1E14 to 1E15 per square centimeter, with less than +/- 5% variation across the wafer.
[0057] FIGS. 4A-4C show plan-view schematics of a first exemplary 2D pattern, how it can be formed as a composite of overlaid ID patterns, and a corresponding set of dark-field lithographic mask features {i.e., corresponding to the rectangular regions from which photoresist is to be removed in developer solution) that can be used to define the ID patterns via multiple litho-TII sequences. FIG. 4A is a schematic plan view showing a 2D IC -layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present disclosure. FIG. 4B is a schematic plan view showing ID patterns (labeled A, B, C, D) which when overlaid form the 2D pattern shown in FIG. 4A, according to an embodiment of the present disclosure. FIG. 4C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to generate the four ID patterns A, B, C, D, according to an embodiment of the present disclosure. In FIGS. 4A-4C, t e lithographic resolution limit is indicated as Pm 2. [0058] The ion trajectory direction is indicated by the dashed arrows (shown in
FIG. 4C), according to the line type for each dark-field mask feature. According to an embodiment of the current invention, firstly a hard mask layer is deposited onto the IC layer; then litho-TII is performed using each of the four masks in sequence; afterwards the hard mask is selectively etched to form the composite 2D pattern, after which the 2D pattern is transferred to the IC layer by a selective etch process.
[0059] Note that at each right-angle bend in the 2D pattern, the constituent orthogonal ID pattern features overlap. The degree of overlap in each direction can be adjusted in practice to minimize unwanted blurring or bloating while ensuring a continuous bend. Note also that if the implanted regions of the hard mask layer are subsequently selectively etched away, then the resultant 2D pattern is "dark-field." On the other hand, if the unimplanted regions of the hard mask layer are subsequently selectively etched away (i.e., implantation serves to retard the etch rate of the hard mask material), then the resultant 2D pattern is "bright-field."
[0060] It should be understood that there are many additional variations of 2D patterns which can be formed in an IC layer using this ne patterning method as follows:
1) Coat the IC layer with a hard mask layer;
2) Perform multiple lithographic tilted ion implantation (litho-TII) processes in sequence such that each litho-TII process sequence forms a latent ID pattern in the hard mask layer;
3) Selectively etch the hard mask layer to form a composite 2D pattern; and
4) Transfer the 2D pattern to the IC layer by a selective etch process.
[0061] In an embodiment, the features of the lithographic masks can be automatically generated by first decomposing each 2D feature into a minimum number of horizontal and vertical overlapping ID features (see, FIG. 4B), then apportioning all of the ID features of the decomposed pattern across multiple masks as needed to comply with lithographic design rules (similarly as is done today for the conventional LELE method), and finally generating for each I D feature a rectangular mask feature that circumscribes three sides of the ID feature - corresponding to the region to be implanted - and that complies with the resolution limit (Pmm/2), as illustrated in FIG. 4C. [0062] FIGS. 5A-5C through FIGS. 9A-9C show various rectangular mask features and configurations that could be used to form other 213 patterns using this method according to some embodiments of the current invention. FIG. 5A is a schematic plan view showing a second example of a 2D IC-layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present invention. FIG. 5B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form the 2D pattern, according to an embodiment of the present invention. FIG. 5C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to generate the three ID patterns A, B and C, according to an embodiment of the present invention. FIG. 6A is a schematic plan view showing a third example of a 2D IC-layer pattern according to another embodiment of the current invention with sub-lithographic features and feature pitch, according to an embodiment of the present invention. FIG. 6B is a schematic plan view showing ID patterns labeled A, B, C, D which when overlaid form the 2D pattern, according to an embodiment of the present invention. FIG. 6C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the four ID patterns A, B, C and D, according to an embodiment of the present invention. FIG.7A is a schematic plan view showing a fourth example of a 2D IC-layer pattern according to another embodiment of the current invention with sub-lithographic features and feature pitch, according to an embodiment of the present invention. FIG.7B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present invention. FIG.7C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the three ID patterns A, B and C, according to an embodiment of the present invention. FIG. 8A is a schematic plan view showing a fifth example of a 2D IC-layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present invention. FIG. 8B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present invention. FIG. 8C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the three ID patterns A, B and C, according to an embodiment of the present invention. FIG. 9A is a schematic plan view showing a sixth example of a 2D IC-layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present invention. FIG. 9B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present invention. FIG. 9A is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the three ID patterns A, B and C, according to an embodiment of the present invention. In the embodiments shown in FIGS. 4A-4C through FIGS. 9A-9C, a minimum feature size of each of the mask patterns can be less than or equal to the lithographic resolution limit .Pmin/2, for example.
[0063] Various benefits are provided by this new patterning method over the conventional LELE method. These benefits can include smaller minimum feature size (better critical dimension control) and hence smaller possible minimum pitch. Benefits of using this new patterning method over the conventional SADP method can also include the ability to form more complex 2D patterns. Although the most complex and dense 2D patterns would require a larger number of lithography processes to realize, it should be understood by a person of ordinary skill in the art that 2D patterning can not only significantly reduce the number of IC wiring ("interconnect") layers required, but also provide for more compact (smaller area) IC blocks, resulting in significant reductions in IC manufacturing cost to enable the semiconductor industry to extend the era of Moore's Law.
[0064] As it can be appreciated from the above paragraphs, an embodiment of the present invention provides a method of producing a micro-device or a nano-device having at least one layer with a sub-lithographic two-dimensional pattern. The method includes providing a substrate comprising a substructure and a hard mask layer formed on the substructure. The method further includes performing a plurality of sequential photolithographic and tilted ion implantation processes to produce a pattern of ion implanted regions in the hard mask layer. The method also includes selectively etching at least one of the ion implanted regions in the hard mask layer to expose the substructure to produce a two-dimensional pattern in the hard mask layer. The method further includes etching the substructure of the substrate in exposed regions to transfer the two- dimensional pattern in the hard mask layer to the substructure of the substrate so as to produce a sub-lithographic two-dimensional structure therein. [0065] In an embodiment, the performing the plurality of sequential photolithographic and tilted ion implantation processes to produce the pattern of ion implanted regions in the hard mask layer may include performing the plurality of sequential photolithographic and tilted ion implantation processes to produce an implanted region of the hard mask layer having a dimension x = I - /z(tan Θ - cot a) that is smaller than a mask-defined feature of size /, wherein h corresponds to a height of the mask-defined feature, angle Θ corresponds to an angle of a trajectory of incident ions relative to a wall of the mask-defined feature, and angle a corresponds to an angle of the wall of the mask-defined feature relative to the substrate. For example, the angle a may be equal to substantially 90 degrees.
[0066] In an embodiment, the method further includes removing remaining portions of the hard mask from the substructure of the substrate.
[0067] In an embodiment, the performing the plurality of sequential photolithographic and tilted ion implantation processes includes resolving the sub- lithographic two-dimensional pattern as a plurality of linear patterns for performing a plurality of sequential photolithographic and tilted ion implantation processes. In an embodiment, the method may further includes performing additional processing steps such that the method is a method of producing an integrated microsystem. In an embodiment, the method may also include performing additional processing steps such that the method is a method of producing a micro-electro-mechanical (MEM) or nano- electro-mechanical (NEM) device. In an embodiment, providing the substrate may include forming the hard mask layer on the substructure of the substrate. In an embodiment, providing the substrate comprises forming the hard mask layer on the substructure of the substrate. In an embodiment, providing the substrate comprises providing a substrate having a semiconductor layer. In an embodiment, the method may further include forming the hard mask layer on the substructure, the hard mask layer comprising an oxide layer. For example, the oxide layer may include silicon oxide (Si02).
[0068] In an embodiment, performing the tilted ion implantation processes includes introducing impurity atoms in precise amounts into a selected surface region of the hard mask layer. The impurity atoms may be introduced over a range of depths depending upon an energy of incident ions on the surface, for example. The implantation tilt angle can also be adjusted in a range from -60° to +60° depending on desired implantation configuration, for example.
[0069] Another embodiment of the present invention is to produce a device according to the above described method. The device includes a two-dimensional pattern having a minimum feature pitch smaller than a minimum pitch of a photolithographic process and having a minimum feature size smaller than a photolithographic resolution limit that is achieved solely by using a photolithographic process without using ion implantation.
[0070] Another embodiment of the present invention is to provide a structure for producing a device having sub-lithographic two-dimensional structures. The device includes a substrate having a substructure and a hard mask layer formed on the substructure. The hard mask layer defines a two-dimensional pattern therein that exposes the substructure of the substrate according to the two-dimensional pattern.
[0071] The following defines some terms used in the claims and the specification:
[0072] The term "sub-lithographic" is intended to refer to feature sizes and/or spacing between features that are smaller than that which can be achieved with a corresponding photolithographic process itself. The "pitch" of linear features is defined as the distance between their centerlines. For the case in which a patterning process produces the smallest feature size and/or pitch that is possible with a single photolithographic exposure step at the time (i.e., at the resolution limit of photolithography), a sub-lithographic process produces feature sizes and/or achieves feature pitches that are even smaller. However, the broad concepts of methods according to some embodiments of the current invention are not limited to only this example. In some cases, it may be desirable to use methods in accordance with some embodiments of the current invention in combination with feature and/or pitch sizes that are larger than the resolution limit of the photolithographic process.
[0073] The term "photolithography" is intended to refer to any lithographic processes that use "light" (i.e., electromagnetic radiation) of any wavelength including, but not limited to, visible light, ultraviolet light, deep ultraviolet light, and extreme ultraviolet light, for example. [0074] The term "photolithographic process" is intended to have a broad definition that can include multiple steps such as, but not limited to, forming a layer of photoresist, exposing the photoresist layer to a pattern of light, and developing the photoresist layer to remove one of regions exposed to the light or regions unexposed to the light. It can also include additional deposition and processing steps, including, but not limited to multiple photolithographic processes.
[0075] The term "ion implantation process" is intended to refer to any process by which ions are impacted into a solid to change the physical, chemical, or electrical properties of the solid. The term "tilted ion implantation" (Til) is intended to refer to an ion implantation process in which the trajectory of the ions is not substantially orthogonal to the surface of the solid.
[0076] The term "linear pattern" or "one-dimensional pattern" is intended to mean a pattern with one or more features that each extends in only one direction, with a substantially uniform width along its length, as is understood within the art.
[0077] The term "two-dimensional pattern" is intended to mean a pattern having features that extend in two orthogonal directions. The term "two-dimensional structure" is intended to mean a structure having features that extend in two orthogonal directions within the same layer. In some embodiments, a two-dimensional pattern can be resolved as a combination of a plurality of linear patterns that can be defined sequentially. However, the broad concepts of the current invention are not limited to only two- dimensional patterns that can be resolved as a combination of linear features.
[0078] The term "ion implant defined pattern" is intended to refer to a pattern that is defined by one or more ion implantation processes. Regions outside of the ion implant defined pattern may or may not have been subjected to an ion implantation process.
[0079] The term "hard mask layer" is intended to refer to a material layer that is patterned according to one or more processes and that is subsequently used as a mask to transfer its pattern to an underlying material layer. The processes can include ion implantation processes using embodiments of the current invention either with or without other conventional processes in the same layer in some embodiments. [0080] The term "substrate' is intended to have a broad definition which can include a simple structure such as, but not limited to, a semiconductor wafer with a hard mask layer, but can in other embodiments be a more complex structure in itself having one or more additional layers of materials and/or other previously produced substructures. The semiconductor wafer can be, but is not limited to, a silicon wafer, for example.
[0081] The above examples describe etching of ion implanted regions preferentially over non-implanted, or less implanted, regions. However, a negative etching method could be used according to other embodiments of the current invention using materials that etch less preferentially when implanted with ions.
[0082] The embodiments illustrated and discussed in this specification are intended only to teach those skilled in the art how to make and use the invention. In describing embodiments of the disclosure, specific terminology is employed for the sake of clarity. However, the disclosure is not intended to be limited to the specific terminology so selected. The above-described embodiments of the disclosure may be modified or varied, without departing from the invention, as appreciated by those skilled in the art in light of the above teachings. It is therefore to be understood that, within the scope of the claims and their equivalents, the invention may be practiced otherwise than as specifically described. For example, it is to be understood that the present disclosure contemplates that, to the extent possible, one or more features of any embodiment can be combined with one or more features of any other embodiment.

Claims

WE CLAIM:
1. A method of producing a micro-device or a nano-device having at least one layer with a sub-lithographic two-dimensional pattern, comprising:
providing a substrate comprising a substructure and a hard mask layer formed on said substructure;
performing a plurality of sequential photolithographic and tilted ion implantation processes to produce a pattern of ion implanted regions in said hard mask layer;
selectively etching at least a portion of said pattern of ion implanted regions in said hard mask layer to expose said substructure to produce a two-dimensional pattern in said hard mask layer; and
selectively etching said substructure of said substrate in exposed regions to transfer said two-dimensional pattern in said hard mask layer to said substructure of said substrate so as to produce a sub-lithographic two-dimensional structure therein.
2. The method according to claim 1, wherein the performing the plurality of sequential photolithographic and tilted ion implantation processes to produce said pattern of ion implanted regions in said hard mask layer comprises performing the plurality of sequential photolithographic and tilted ion implantation processes to produce an implanted region of the hard mask layer having a dimension x = I - /z(tan Θ - cot a) that is smaller than a mask-defined feature of size /, wherein h corresponds to a height of said mask-defined feature, angle Θ corresponds to an angle of a trajectory of incident ions relative to a normal to a surface of the substrate, and angle a corresponds to an angle of a wall of the mask-defined feature relative to the surface of the substrate.
3. The method of claim 1, further comprising removing remaining portions of said hard mask from said substructure of said substrate.
4. The method of claim 1, wherein said performing said plurality of sequential photolithographic and tilted ion implantation processes comprises resolving said sub- lithographic two-dimensional pattern as a plurality of linear patterns for performing a plurality of sequential photolithographic and tilted ion implantation processes.
5. The method according to claim 4, wherein said plurality of linear patterns comprises a first linear pattern that overlaps with a second linear pattern at an angle.
6. The method according to claim 5, wherein said angle is substantially 90 degrees.
7. The method of any one of claims 1-6, further comprising performing additional processing steps such that said method is a method of producing an electronic integrated circuit.
8. The method of any one of claims 1-6, further comprising performing additional processing steps such that said method is a method of producing a micro-electromechanical (MEM) or nano-electro-mechanical (NEM) device.
9. The method according to any one of claims 1-6, wherein said providing said substrate comprises forming said hard mask layer on said substructure of said substrate.
10. The method according to any one of claims 1-6, wherein providing said substrate comprises providing a substrate having a semiconductor layer.
11. The method according to any one of claims 1-6, further comprising forming the hard mask layer on said substructure, the hard mask layer comprising an oxide layer.
12. The method according to claim 11, wherein the oxide layer comprises silicon dioxide (S1O2).
13. The method according to any one of claims 1-6, wherein performing the tilted ion implantation processes comprises introducing impurity atoms in selected amounts into selected regions of said hard mask layer.
14. The method according to claim 13, wherein said introducing impurity atoms into said hard mask layer comprises introducing the impurity atoms over a selected range of depths based on a selected energy of incident ions impinging on the surface of the substrate.
15. The method according to claim 14, wherein said introducing impurity atoms comprises adjusting an implantation tilt angle in a range from -60° to +60° depending on a selected implantation configuration.
16. A device produced according to the method of any one of claims 1-15.
17. The device produced according to claim 16, comprising a layer with a two- dimensional (2D) pattern, the two-dimensional pattern having a minimum feature pitch smaller than a minimum pitch of a photolithographic process and having a minimum feature size smaller than a photolithographic resolution limit that is achieved solely by using a photolithographic process without using ion implantation.
18. A structure for producing a device having sub-lithographic two-dimensional structures, said structure comprising a substrate,
wherein said substrate comprises a substructure and a hard mask layer formed on said substructure, and
wherein said hard mask layer defines a two-dimensional pattern therein that exposes said substructure of said substrate according to said two-dimensional pattern.
PCT/US2018/035461 2017-05-31 2018-05-31 Two-dimensional patterning of integrated circuit layer by tilted ion implantation WO2018222915A1 (en)

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