WO2018214225A1 - 显示像素结构、阵列基板及显示装置 - Google Patents

显示像素结构、阵列基板及显示装置 Download PDF

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Publication number
WO2018214225A1
WO2018214225A1 PCT/CN2017/090418 CN2017090418W WO2018214225A1 WO 2018214225 A1 WO2018214225 A1 WO 2018214225A1 CN 2017090418 W CN2017090418 W CN 2017090418W WO 2018214225 A1 WO2018214225 A1 WO 2018214225A1
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Prior art keywords
pixel
sub
ratio
tft switch
width
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PCT/CN2017/090418
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English (en)
French (fr)
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马亮
叶为平
王聪
廖作敏
夏军
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武汉华星光电技术有限公司
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Priority to US15/737,211 priority Critical patent/US10290273B2/en
Publication of WO2018214225A1 publication Critical patent/WO2018214225A1/zh

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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display pixel structure, an array substrate, and a display device.
  • the RGBW pixel design can reduce the power consumption of the panel, when displaying a solid color or a color picture, compared with the RGB display panel, under the same background display, the solid color brightness displayed by the panel using the RGBW pixel design is It will be low, the screen display may be distorted, and even affect the clarity and display of the picture to a certain extent.
  • the RGBW pixel panel in order to reduce the power consumption of the panel and at the same time improve the display effect of the panel, most of the solutions are asymmetric RGBW pixel design and shaped RGBW pixel design.
  • the ratio of the RGB pixels can be increased, and the ratio of the W pixels can be reduced, thereby reducing the distortion of the RGBW panel color image caused by the W pixels, thereby improving the optical display effect of the color image.
  • the storage capacitance is also different, and the parasitic capacitance of the R, G, B, and W four-color sub-pixels is the same as that of the TFT, which will result in W pixels and R, G, B pixel feedthrough voltage, charging and leakage, which will cause crosstalk in the panel (Crosstalk), flicker (Flicker) and other issues.
  • the embodiment of the invention provides a display pixel structure, an array substrate and a display device, which can eliminate the difference of the Feedthrough voltage, the charging and the leakage caused by the difference in the storage capacitance and the TFT and the parasitic capacitance in each pixel, and finally cause crosstalk ( Crosstalk), flicker phenomenon.
  • an embodiment of the present invention provides a display pixel structure including a plurality of pixel units arranged in a matrix, each pixel unit including a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel.
  • Each sub-pixel includes a TFT switch; a width/length ratio of the TFT switch of the first sub-pixel, the second sub-pixel and the third sub-pixel, and a TFT switch of the fourth sub-pixel Ratio between the width/length ratio, and the ratio between the storage capacitance of one of the first sub-pixel, the second sub-pixel, and the third sub-pixel and the storage capacitance of the fourth sub-pixel Equivalent; or an average value of a width/length ratio of a TFT switch of at least two of the first sub-pixel, the second sub-pixel, and the third sub-pixel and a TFT switch of the fourth sub-pixel a ratio between the width/length ratio is equal to an average value of the storage capacitances of at least two of the first sub-pixel, the second sub-pixel, and the third sub-pixel and a storage capacitance of the fourth sub-pixel The ratio between the two.
  • the storage capacitances of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all equal, and the width of the TFT switch of the first sub-pixel, the second sub-pixel, and the third sub-pixel is
  • the length ratios are the same, and the width/length ratio of the TFT switches of any one of the first sub-pixel, the second sub-pixel, and the third sub-pixel is wider than the TFT switch of the fourth sub-pixel/
  • the ratio between the length ratios is equal to the ratio between the storage capacitance of any one of the first sub-pixel, the second sub-pixel, and the third sub-pixel and the storage capacitance of the fourth sub-pixel.
  • the length of the TFT switch of any one of the first sub-pixel, the second sub-pixel, and the third sub-pixel is The length of the TFT switch of the fourth sub-pixel is the same, the width of the TFT switch of any one of the first sub-pixel, the second sub-pixel, and the third sub-pixel and the width of the TFT switch of the fourth sub-pixel.
  • the ratio between the ratio is equal to the ratio between the storage capacitance of any one of the first sub-pixel, the second sub-pixel, and the third sub-pixel and the storage capacitance of the fourth sub-pixel.
  • the width of the TFT switch of any one of the first sub-pixel, the second sub-pixel, and the third sub-pixel is the same as the width of the TFT switch of the fourth sub-pixel, the first sub-pixel, the second sub-pixel, a ratio between a length of a TFT switch of any one of the third sub-pixels and a length of the TFT switch of the fourth sub-pixel and storage of any one of the first sub-pixel, the second sub-pixel, and the third sub-pixel.
  • the ratio between the capacitance and the storage capacitance of the fourth sub-pixel is equal.
  • the TFT switch of any one of the first sub-pixel, the second sub-pixel, and the third sub-pixel is The length and width of the TFT switch of the fourth sub-pixel are different, and the width/length ratio of the TFT switch corresponding to any one of the first sub-pixel, the second sub-pixel, and the third sub-pixel respectively a ratio between a width/length ratio of the TFT switches of the four sub-pixels and a storage capacitance of any one of the first sub-pixel, the second sub-pixel, and the third sub-pixel and a storage capacitance of the fourth sub-pixel The ratio is equal.
  • the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel have the same area, and the first sub-pixel, the second sub-pixel, and the The third sub-pixel is disposed in the fourth sub-pixel together with the TFT switch of the fourth sub-pixel.
  • the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel in each of the pixel units are arranged in a matrix of two rows and two columns; the first sub-child The pixel, the second sub-pixel, and the third sub-pixel are respectively one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and the fourth sub-pixel is a white sub-pixel or a yellow sub-pixel.
  • the display pixel structure further includes a plurality of gate lines disposed in parallel and a plurality of data lines disposed perpendicular to the gate lines, wherein the gate lines and the data lines enclose the first sub-pixel The second sub-pixel, the third sub-pixel, and the fourth sub-pixel.
  • an embodiment of the present invention further provides an array substrate, wherein the array substrate comprises the above display pixel structure.
  • an embodiment of the present invention further provides a display device, where the display device includes the above array substrate.
  • the display pixel structure, the array substrate, and the display device provided in the embodiments of the present invention can eliminate the asymmetric RGBW pixel design or the alien RGBW pixel design, because the storage capacitance is different in each pixel, and the TFT and the parasitic capacitance are the same. The resulting difference in feedback voltage, charging, and leakage, and the resulting crosstalk and flicker.
  • FIG. 1 is a schematic diagram of a pixel arrangement of a display pixel structure according to the present invention.
  • FIG. 2 is a schematic view showing the structure inside the display pixel structure of the present invention.
  • FIG. 3 is a cross-sectional structural view of an array substrate of the present invention.
  • connection In the description of the present invention, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined.
  • the ground connection, or the integral connection may be a mechanical connection; it may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two elements.
  • the specific meaning of the above terms in the present invention can be understood in a specific case by those skilled in the art.
  • Embodiments of the present invention provide a display pixel structure, which can eliminate crosstalk and flicker caused by different feedback voltages, charging, and leakage of pixels in a profiled or asymmetric pixel design. The details are described below separately.
  • FIG. 1 is a schematic diagram of a pixel arrangement of a display pixel structure according to the present invention
  • FIG. 2 is a schematic structural view of the interior of the display pixel structure according to the present invention.
  • a display pixel structure includes a plurality of pixel units 10 arranged in a matrix, each of the pixel units 10 including first sub-pixels, second sub-pixels, and third sub-pixels having different colors and a fourth sub-pixel, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively one of a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, the fourth The sub-pixel is a white sub-pixel W or a yellow sub-pixel Y.
  • the white sub-pixel W is taken as an example of the fourth sub-pixel.
  • Storage capacitors of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B in each of the pixel units 10 (hereinafter collectively referred to as R, G, and B three-color sub-pixels together with the three color sub-pixels)
  • the storage capacitance of the white sub-pixel W may be smaller than the storage capacitance of any one of the R, G, and B three-color sub-pixels.
  • Each of the sub-pixels includes a Thin Film Transistor (TFT) switch 11 and a pixel electrode 13, and the width/length ratio of the TFT switch 11 of one of the R, G, and B tris sub-pixels is The ratio between the width/length ratio of the TFT switch 11 of the white sub-pixel W is equal to the ratio between the storage capacitance of one of the R, G, and B tris sub-pixels and the storage capacitance of the white sub-pixel W; or a ratio between an average value of the width/length ratio of the TFT switches 11 of at least two of the R, G, and B tris sub-pixels and a width/length ratio of the TFT switch 11 of the white sub-pixel W, The ratio between the average value of the storage capacitors of at least two of the R, G, and B tris sub-pixels and the storage capacitance of the white sub-pixel W is equal.
  • the width/length ratio of the TFT switch 11 refers to the ratio of the width to the length of the channel portion of the
  • the parasitic capacitance of the sub-pixel is proportional to the width/length ratio, after setting the width/length ratio of each sub-pixel in the above manner, the parasitic capacitance of each sub-pixel is also adjusted accordingly, so that it is effectively prevented
  • the storage capacitance between the sub-pixels is different and the parasitic capacitance is the same, causing display defects due to the difference in the Feedthrough voltage.
  • the display pixel structure of the present embodiment corresponds to a ratio between a width/length ratio of the TFT switch 11 of the white sub-pixel W and a width/length ratio of the TFT switch 11 of at least one of the R, G, and B tris sub-pixels.
  • the ratio between the storage capacitance of the white sub-pixel W and the storage capacitance of at least one of the R, G, and B three-color sub-pixels is set to eliminate the three colors of the white sub-pixel W and the R, G, and B colors in the prior art. Crosstalk and flicker caused by any one of the sub-pixels with different storage capacitors and the same TFT switch and parasitic capacitance.
  • the storage capacitances of the R, G, and B three-color sub-pixels are the same, and the width/length ratio of the TFT switches 11 of the R, G, and B three-color sub-pixels are also the same.
  • the ratio of the width/length ratio of the TFT switch 11 of any one of the R, G, and B tris sub-pixels to the width/length ratio of the TFT switch 11 of the white sub-pixel W, and the R, G The ratio between the storage capacitance of any of the B tris sub-pixels and the storage capacitance of the white sub-pixel W is equal.
  • the TFT switch 11 of the TFT switch and the white sub-pixel W of any one of the R, G, and B tris sub-pixels If the lengths are set to be the same, the ratio of the width of the TFT switch 11 of any one of the R, G, and B tris sub-pixels to the white sub-pixel W and any one of the R, G, and B tri-color sub-pixels is The ratio of the storage capacitances of both white sub-pixels W is equal.
  • any one of the R, G, and B tris sub-pixels has the same length as the TFT switch 11 of the white sub-pixel W, that is, L, and R
  • the width of the TFT switch 11 of the G, B three-color sub-pixel is W1
  • the width of the TFT switch 11 of the white sub-pixel W is W2
  • the W1 is greater than W2
  • the width-to-length ratio W1/L of one TFT switch 11 and the width-to-length ratio W2/L of the TFT switch 11 of the white sub-pixel W are W1/W2, and any one of the R, G, and B three-color sub-pixels
  • the storage capacitor has the same ratio of the storage capacitance of the white sub-pixel W.
  • the TFT switch of any one of the R, G, and B three-color sub-pixels and the white sub-pixel W may be used.
  • the width of the TFT switch 11 is set to be the same, and the ratio of the length of the TFT switch 11 of any one of the R, G, and B tris sub-pixels to the white sub-pixel W and the R, G, and B tritrons. The ratio of the storage capacitance of either one of the pixels to the white sub-pixel W is equal.
  • the TFT switch 11 of any one of the R, G, and B tris sub-pixels and the white sub-pixel W may be disposed.
  • the width and the length are different, but the ratio of the width/length ratio of the TFT switch 11 of any one of the R, G, and B tris sub-pixels to the width/length ratio of the TFT switch 11 of the white sub-pixel W is the same as the R
  • the ratio between the storage capacitor of any one of the G and B tris sub-pixels and the storage capacitance of the white sub-pixel W is equal.
  • the width/length ratio of any one of the R, G, and B tris sub-pixels and the width/length ratio of the TFT switch 11 of the white sub-pixel W is equal to a ratio between a storage capacitor of any one of the R, G, and B tris sub-pixels and a storage capacitor of the white sub-pixel W.
  • the width and length of the TFT switch 11 of any one of the R, G, and B tris sub-pixels and the white sub-pixel W are integrated, and the aperture ratio of the sub-pixel is integrated to maximize all
  • the aperture ratio of the sub-pixel is a setting standard. Therefore, in the present embodiment, in order to maximize the aperture ratio of all the sub-pixels, the lengths of the TFT switches 11 of the respective sub-pixels are set to be the same, and any one of the R, G, and B three-color sub-pixels and the TFT of the white sub-pixel W are set.
  • the ratio between the widths of the switches 11 can be set corresponding to the ratio between the one of the R, G, and B tris sub-pixels and the storage capacitance of the white sub-pixel W.
  • the R, G, and B tris sub-pixels have the same area as the white sub-pixel W, and both of them can adopt a 2*2 (ie, two rows and two columns) matrix.
  • the TFT switches 11 of the R, G, and B tris sub-pixels and the TFT switches 11 of the white sub-pixel W in each pixel unit are disposed together in the white sub-pixel W of the pixel unit. Therefore, the area occupied by the pixel electrode 13 of the white sub-pixel W is smaller than the area occupied by the pixel electrode 13 of any one of the R, G, and B three-color sub-pixels to provide sufficient space for the R, G. , B tri-color sub-pixel and white sub-pixel W TFT switch.
  • the TFT switches 11 of the four sub-pixels in each of the pixel units 10 are disposed in the white sub-pixel W in such a manner as to surround the pixel electrodes 13 of the white sub-pixels W in the pixel unit 10.
  • the red sub-pixel R and the green sub-pixel G in the pixel unit The sub-pixels are arranged in the first row, and the blue sub-pixels B and the white sub-pixels W are arranged in the next row of the red sub-pixel R and the green sub-pixel G.
  • the red sub-pixel R and the green sub-pixel G are TFTs.
  • the switch 11 is provided at one end of the pixel electrode 13 of the white sub-pixel W, and the TFT switch 11 of the blue sub-pixel B and the white sub-pixel W is provided at the other end of the pixel electrode 13 of the white sub-pixel W.
  • the pixel electrodes 13 of the four sub-pixels of the R, G, and B trichromatic sub-pixels and the white sub-pixel W have the same shape, and the pixel electrode 13 of the white sub-pixel W is small in size (ie, the pixel of the white sub-pixel W).
  • the electrode 13 is smaller than the pixel electrode of the red sub-pixel R, the green sub-pixel G, or the blue sub-pixel B, and thus can provide a sufficient space to accommodate the four TFT switches 11 in the pixel unit 10, and also makes the white sub-pixel
  • the storage capacitance of W is smaller than the storage capacitance of any one of the R, G, and B three-color sub-pixels.
  • the pixel electrode 13 of each sub-pixel includes a stripe strip electrode body (not labeled) and a connecting portion (not labeled) extending from the end of the electrode body.
  • the connecting portion It may be in the form of a block, such as a circular or square block, to facilitate connection to the TFT switch 11 through a via.
  • the display pixel structure further includes a plurality of gate lines 20 arranged in parallel and a plurality of data lines 30 disposed perpendicular to the gate lines 20, the gate lines 20 and the data lines 30 enclosing a pixel unit
  • Each of the sub-pixels of 10, the TFT switch 11 of each of the sub-pixels is connected to the gate line 20 and the data line 30.
  • the TFT switch 11 further includes an active layer 111, a gate 112, a source 113, and a drain 115.
  • the gate 112 is disposed in the channel region of the active layer 111.
  • the source 113 and the drain 115 are connected to contact regions at both ends of the active layer 111.
  • the active layer 111 is connected to the data line 30 through the first via 50, and the source 113 and the drain 115 are formed in the first via 50; the pixel electrode 13 passes through Two vias 60 and the first vias 50 are connected to the active layer 111.
  • the structure of the TFT switch 11 is the same as that of the TFT switch in the conventional pixel circuit, and the description will not be repeated here in detail.
  • the materials of the gate line 20, the data line 30, the gate 112, the source 113, the drain 115, the pixel electrode 13, and the like may be one of molybdenum, titanium, aluminum, and copper. Or a variety of stack combinations.
  • first via hole 50 and the second via hole 60 are both rectangular.
  • red sub-pixel R Formed by red sub-pixel R, green sub-pixel G, blue sub-pixel B, and yellow sub-pixel Y
  • the pixel unit is identical in structure and design principle to the pixel unit formed by the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the white sub-pixel W, that is, the display pixel structure based on the RGBY pixel design and The design principles of the above display pixel structure based on the RGBW pixel design are the same, and the description will not be repeated here.
  • the invention provides a novel pixel design suitable for RGBW or RGBY display panels, which can be applied to various asymmetric pixel designs and shaped pixel designs, such as RGBW panel pixel design, by selecting corresponding width/length ratios for abnormal pixels.
  • the TFT compensates for display defects caused by different pixel structures, thereby improving the stability of the panel of the alien RGBW or RGBY pixel design, and achieving a balance between product energy consumption and display effect.
  • Embodiments of the present invention also provide an array substrate including the above display pixel structure.
  • the embodiment of the invention further provides a liquid crystal display device comprising the above array substrate.
  • the liquid crystal display device may specifically be: a liquid crystal panel, a liquid crystal television, a liquid crystal display, an electronic paper, a digital photo frame, a mobile phone, or the like.
  • the TFT with the corresponding width/length ratio is selected for the abnormal pixel design or the asymmetric pixel design to compensate for the display failure caused by the difference in pixel structure. Therefore, the stability of the panel of the shaped RGBW or RGBY pixel design can be improved, and the balance between the product energy consumption and the display effect can be achieved.

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Abstract

一种显示像素结构，包括呈矩阵排列的多个像素单元（10），每个像素单元（10）包括第一子像素、第二子像素、第三子像素以及第四子像素。每一子像素均包括一TFT开关（11）。其中，第一子像素、第二子像素及第三子像素中任一个的TFT开关（11）的宽/长比或者多个的TFT开关（11）的宽/长比平均值与第四子像素的TFT开关（11）的宽/长比之间的比值，均等于第一子像素、第二子像素及第三子像素中任一个的存储电容或者多个的存储电容的平均值与第四子像素的存储电容之间的比值。还提供了一种阵列基板以及液晶显示装置。

Description

显示像素结构、阵列基板及显示装置
本申请要求2017年05月20日递交的发明名称为“显示像素结构、阵列基板及显示装置”的申请号为201710359945.6的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示技术领域，尤其涉及一种显示像素结构、阵列基板及显示装置。
背景技术
随着显示面板的多元化发展，人们对手机、电脑等显示装置的需求也越来越严格。为了能满足大众的需求，面板厂商也对显示面板的设计做出相应调整，例如，改变设计以降低面板的功耗，改用其他色阻材料以提高面板的显示效果等等。在降低面板功耗的设计上，可以通过减小阵列基板行驱动技术(Gate Driver on Array，GOA)的驱动薄膜晶体管(Thin Film Transisor，TFT)及改变像素的设计来实现，随之而产生的改变像素设计的方案就有例如RGBW面板设计。虽然选用RGBW像素设计能降低面板的功耗，然而，在显示纯色或者是彩色画面时，与RGB显示面板相比，在同样的背景显示画面下，采用RGBW像素设计的面板所显示的纯色亮度就会偏低，画面显示可能会失真，甚至会在一定程度上影响画面的清晰度及显示效果。
针对上述问题，在设计RGBW像素的面板时，为了能够降低面板的功耗，同时又能提升面板的显示效果，大多采用了非对称RGBW像素设计及异形RGBW像素设计等解决方案。在具体设计过程中，可以通过增加RGB像素的所占比，对应降低W像素的所占比来实现，从而降低W像素引起的RGBW面板彩色画面的失真度，进而提升彩色画面的光学显示效果。由于RGB像素与W像素的设计不同即非对称像素设计，其存储电容也有差异，而R、G、B、W四色子像素的寄生电容与TFT却相同，如此将会导致W像素与R、G、B像素的Feedthrough电压、充电和漏电的不同，从而会导致面板出现串扰 (Crosstalk)、闪烁(Flicker)等问题。
发明内容
本发明实施例提供一种显示像素结构、阵列基板及显示装置，可以消除由于各像素中存储电容不同、TFT与寄生电容却相同而引起的Feedthrough电压、充电、漏电的不同，最终引起的串扰(Crosstalk)、闪烁(Flicker)现象。
一方面，本发明实施例提供了一种显示像素结构，包括呈矩阵排列的多个像素单元，每个像素单元包括第一子像素、第二子像素、第三子像素以及第四子像素，每一子像素均包括一TFT开关；所述第一子像素、所述第二子像素与所述第三子像素之一的TFT开关的宽/长比与所述第四子像素的TFT开关的宽/长比之间的比值，与所述第一子像素、所述第二子像素及所述第三子像素之一的存储电容与所述第四子像素的存储电容之间的比值相等；或者，所述第一子像素、所述第二子像素及所述第三子像素中至少两个的TFT开关的宽/长比的平均值与所述第四子像素的TFT开关的宽/长比之间的比值等于所述第一子像素、所述第二子像素及所述第三子像素中至少两个的存储电容的平均值与所述第四子像素的存储电容之间的比值。
其中，所述第一子像素、第二子像素与第三子像素的存储电容均相等，所述第一子像素、所述第二子像素及所述第三子像素的TFT开关的宽/长比均相同，且所述第一子像素、所述第二子像素及所述第三子像素中任意一个的TFT开关的宽/长比与所述第四子像素的TFT开关的宽/长比之间的比值，与所述第一子像素、所述第二子像素及所述第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
其中，当所述第一子像素、第二子像素、第三子像素的存储电容相同时，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的长度与所述第四子像素的TFT开关的长度相同，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的宽度与所述第四子像素的TFT开关的宽度之间的比值与所述第一子像素、第二子像素、第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
其中，当所述第一子像素、第二子像素、第三子像素的存储电容相同时， 所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的宽度与所述第四子像素的TFT开关的宽度相同，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的长度与所述第四子像素的TFT开关的长度之间的比值与所述第一子像素、第二子像素、第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
其中，当所述第一子像素、第二子像素、第三子像素的存储电容相同时，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关与所述第四子像素的TFT开关的长度与宽度均不相同，而分别对应于所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的宽/长比与所述第四子像素的TFT开关的宽/长比之间的比值与所述第一子像素、第二子像素、第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
其中，所述第一子像素、所述第二子像素、所述第三子像素与所述第四子像素的面积相同，并且所述第一子像素、所述第二子像素、所述第三子像素与所述第四子像素的TFT开关一并设置于所述第四子像素中。
其中，每一所述像素单元中的第一子像素、所述第二子像素、所述第三子像素和所述第四子像素采用两行两列的矩阵方式排列；所述第一子像素、第二子像素、第三子像素分别为红色子像素、绿色子像素与蓝色子像素中的一种，所述第四子像素为白色子像素或者黄色子像素。
其中，所述显示像素结构还包括多条平行设置的栅极线以及多条垂直于所述栅极线设置的数据线，所述栅极线与所述数据线围成所述第一子像素、所述第二子像素、所述第三子像素以及所述第四子像素。
另一方面，本发明实施例还提供了一种阵列基板，所述阵列基板包括上述显示像素结构。
另一方面，本发明实施例还提供了一种显示装置，所述显示装置包括上述阵列基板。
综上所述，本发明实施例中提供的显示像素结构、阵列基板及显示装置，可以消除非对称RGBW像素设计或异形RGBW像素设计中由于各像素中存储电容不同、TFT与寄生电容却相同而引起的反馈电压、充电、漏电的不同，最终引起的串扰与闪烁现象。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明显示像素结构的像素排列示意图。
图2为本发明显示像素结构内部的结构示意图。
图3为本发明阵列基板的剖视结构示意图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。显然，所描述的实施方式是本发明的一部分实施方式，而不是全部实施方式。基于本发明中的实施方式，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施方式，都应属于本发明保护的范围。
此外，以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本发明，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸地连接，或者一体地连接；可以是机械连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
此外，在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。若本说明书中出现“工序”的用语，其不仅是指独立的工序，在与其它 工序无法明确区别时，只要能实现所述工序所预期的作用则也包括在本用语中。另外，本说明书中用“～”表示的数值范围是指将“～”前后记载的数值分别作为最小值及最大值包括在内的范围。在附图中，结构相似或相同的单元用相同的标号表示。
本发明实施例提供了一种显示像素结构，可以消除异形或者非对称像素设计中由于各像素的反馈电压、充电、漏电的不同而引起的串扰与闪烁现象。以下分别进行详细说明。
请同时参阅图1及图2，图1为本发明显示像素结构的像素排列示意图，图2为本发明显示像素结构内部的结构示意图。本发明实施例中提供一种显示像素结构，其包括呈矩阵排列的多个像素单元10，每个像素单元10包括颜色各不相同的第一子像素、第二子像素、第三子像素与第四子像素，其中，所述第一子像素、第二子像素、第三子像素可分别为红色子像素R、绿色子像素G与蓝色子像素B中的一种，所述第四子像素为白色子像素W或者黄色子像素Y。在本发明的实施例中，以白色子像素W作为第四子像素为例进行说明。
每个所述像素单元10中的红色子像素R、绿色子像素G与蓝色子像素B(以下将上述三个颜色的子像素一起统称为R、G、B三色子像素)的存储电容可以相同，也可以不同，所述白色子像素W的存储电容通常小于R、G、B三色子像素中的任意一个子像素的存储电容。其中，每一所述子像素均包括一薄膜晶体管(Thin Film Transistor，TFT)开关11以及像素电极13，并且该R、G、B三色子像素其中一个的TFT开关11的宽/长比与白色子像素W的TFT开关11的宽/长比之间的比值，与所述R、G、B三色子像素其中一个的存储电容与白色子像素W的存储电容之间的比值相等；或者所述R、G、B三色子像素中至少两个的TFT开关11的宽/长比的平均值与所述白色子像素W的TFT开关11的宽/长比之间的比值，与所述R、G、B三色子像素中至少两个的存储电容的平均值与所述白色子像素W的存储电容之间的比值相等。其中，所述TFT开关11的宽/长比指的是该TFT开关11的沟道部分的宽度与长度的比值。
由于子像素的寄生电容与宽/长比成正比，通过上述方式设置了各子像素的宽/长比后，则各子像素的寄生电容也要相应调整，如此可有效防止由于各 子像素之间的存储电容不同而寄生电容却相同进而引起由于Feedthrough电压差异而导致的显示不良。
本实施例的显示像素结构，将白色子像素W的TFT开关11的宽/长比与R、G、B三色子像素中至少一个的TFT开关11的宽/长比之间的比值对应所述白色子像素W的存储电容与R、G、B三色子像素中至少一个的存储电容之间的比值进行设置，可消除现有技术中由于白色子像素W与R、G、B三色子像素中任意一个存储电容不同、而TFT开关以及寄生电容却相同而引起的串扰(Crosstalk)和闪烁(Flicker)等现象。
在本发明的一个实施方式中，所述R、G、B三色子像素的存储电容相同，所述R、G、B三色子像素的TFT开关11的宽/长比也都相同，对应的，所述R、G、B三色子像素中任意一个的TFT开关11的宽/长比与所述白色子像素W的TFT开关11的宽/长比的比值，与所述R、G、B三色子像素中任意一个的存储电容与白色子像素W的存储电容之间的比值相等。
进一步的，当所述R、G、B三色子像素的存储电容相同时，将所述R、G、B三色子像素中任意一个的TFT开关与白色子像素W二者的TFT开关11的长度设置为相同，则R、G、B三色子像素中任意一个与白色子像素W二者的TFT开关11的宽度的比值与所述R、G、B三色子像素中任意一个与白色子像素W二者的存储电容的比值相等。请一并结合图2，在本实施例中，所述R、G、B三色子像素中任一个与所述白色子像素W的TFT开关11的长度相同，即均为L，而R、G、B三色子像素的TFT开关11的宽度都为W1，白色子像素W的TFT开关11的宽度为W2，并且所述W1大于W2，所述R、G、B三色子像素中任一个的TFT开关11的宽长比W1/L与白色子像素W的TFT开关11的宽长比W2/L的比值为W1/W2，与所述R、G、B三色子像素中任意一个的存储电容与白色子像素W的存储电容的比值相等。
可以理解，相应地，当所述R、G、B三色子像素的存储电容相同时，也可以将所述R、G、B三色子像素中任意一个的TFT开关与白色子像素W二者的TFT开关11的宽度设置为相同，则R、G、B三色子像素中任意一个与白色子像素W二者的TFT开关11的长度的比值与所述R、G、B三色子像素中任意一个与白色子像素W二者的存储电容的比值相等。
可以理解，当所述R、G、B三色子像素的存储电容相同时，也可以设置所述R、G、B三色子像素中任意一个与白色子像素W二者的TFT开关11的宽度与长度均不同，但所述R、G、B三色子像素中任意一个的TFT开关11的宽/长比与白色子像素W的TFT开关11的宽/长比的比值与所述R、G、B三色子像素中任意一个的存储电容与白色子像素W的存储电容之间的比值相等。
在本发明的一个实施方式中，所述R、G、B三色子像素中任意一个TFT开关11的宽/长比与所述白色子像素W的TFT开关11的宽/长比之间的比值，与所述R、G、B三色子像素中任意一个的存储电容与所述白色子像素W的存储电容之间的比值相等。
具体的，上述R、G、B三色子像素中任意一个与白色子像素W的TFT开关11的宽度与长度的设置，综合了子像素的开口率(Aperture ratio)进行考量，以最大化所有子像素的开口率为设置标准。因此，本实施例中，为了最大化所有子像素的开口率，将各子像素的TFT开关11的长度设置为相同，R、G、B三色子像素中任意一个与白色子像素W的TFT开关11的宽度之间的比值可对应所述R、G、B三色子像素中任意一个与白色子像素W的存储电容之间的比值进行设定。通过上述设计，不仅可以尽可能地增大各子像素的开口率，还可以简化所述TFT开关11的加工制程。
在本发明的一个本实施例中，所述R、G、B三色子像素与所述白色子像素W的面积相同，且二者均可采用2*2(即两行两列)矩阵的方式排列，并且每一像素单元中的R、G、B三色子像素的TFT开关11以及白色子像素W的TFT开关11一起设置于该像素单元的白色子像素W中。因此，所述白色子像素W的像素电极13所占的面积小于所述R、G、B三色子像素中任意一个的像素电极13所占的面积，以提供足够的空间容纳该R、G、B三色子像素以及白色子像素W的TFT开关。
可以理解的是，每一所述像素单元10中的四个子像素的TFT开关11以环绕该像素单元10中的白色子像素W的像素电极13的方式设置于该白色子像素W中。
在本发明的一个实施方式中，像素单元中的红色子像素R、绿色子像素G 子像素排列设置于第一行，蓝色子像素B、白色子像素W像素排列设置于红色子像素R、绿色子像素G的下一行，对应的，红色子像素R、绿色子像素G的TFT开关11设置于白色子像素W的像素电极13的一端，蓝色子像素B、白色子像素W的TFT开关11设置于白色子像素W的像素电极13的另一端。
进一步的，所述R、G、B三色子像素以及白色子像素W这四个子像素的像素电极13形状相同，并且白色子像素W的像素电极13尺寸偏小(即白色子像素W的像素电极13小于上述红色子像素R、绿色子像素G或蓝色子像素B的像素电极)，因此能够提供足够的空间容纳该像素单元10中的四个TFT开关11的同时，也使得白色子像素W的存储电容小于R、G、B三色子像素中任意一个的存储电容。其中，每一子像素的像素电极13均包括镂空的条状电极主体(图未标)以及由所述电极主体末端延伸形成连接部(图未标)，在本发明实施例中，该连接部可为块状，如圆形或方形块状，以便于通过一过孔连接至所述TFT开关11。
进一步的，所述显示像素结构还包括多条平行设置的栅极线20以及多条垂直于所述栅极线20设置的数据线30，所述栅极线20与数据线30围成像素单元10的各个子像素，每一所述子像素的TFT开关11连接至所述栅极线20与所述数据线30。
请一并结合图3，进一步的，所述TFT开关11包括有源层111、栅极112、源极113以及漏极115，其中，所述栅极112设于有源层111沟道区域的正上方，所述源极113与漏极115连接至所述有源层111两端的接触区。具体的，所述有源层111通过第一过孔50连接至数据线30，所述源极113与所述漏极115形成于所述第一过孔50中；所述像素电极13通过第二过孔60和所述第一过孔50连接至所述有源层111。该TFT开关11的结构与现有的像素电路中的TFT开关的结构相同，在此就不再详细扩展描述。
可以理解的是，所述栅极线20、数据线30、栅极112、源极113、漏极115以及所述像素电极13等的材料均可为钼、钛、铝、铜中的一种或多种的堆栈组合。
可以理解的是，所述第一过孔50与所述第二过孔60的形状均为矩形。
由红色子像素R、绿色子像素G、蓝色子像素B和黄色子像素Y形成的 像素单元与由所述红色子像素R、绿色子像素G、蓝色子像素B和所述白色子像素W形成的像素单元的结构和设计原理相同，即，基于RGBY像素设计的显示像素结构与上述基于RGBW像素设计的显示像素结构的设计原理相同，在此不再重复描述。
本发明提出一种适用于RGBW或者RGBY显示面板的新型像素设计，可以适用于各种非对称像素设计、异形像素设计，如RGBW面板像素设计，通过对异常像素选用相对应的宽/长比的TFT来补偿因像素结构不同而造成的显示不良，从而能提升异形RGBW或者RGBY像素设计的面板的稳定性，达到产品能耗与显示效果的均衡。
本发明实施例还提供一种阵列基板，其包括上述的显示像素结构。
本发明实施例还提供一种液晶显示装置，起包括上述的阵列基板。
该阵列基板的具体结构与上述实施例相同，在此不再赘述。
该液晶显示装置具体可以为：液晶面板、液晶电视、液晶显示器、电子纸、数码相框、手机等等。
本实施例中液晶显示装置，在采用RGBW或者RGBY像素设计的面板中，通过对异常像素设计或者非对称像素设计选用相对应的宽/长比的TFT来补偿因像素结构不同而造成的显示不良，从而能提升异形RGBW或者RGBY像素设计的面板的稳定性，达到产品能耗与显示效果的均衡。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上对本发明实施例所提供的阵列基板及其制作方法和液晶显示装置进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种显示像素结构，包括呈矩阵排列的多个像素单元，每个像素单元包括第一子像素、第二子像素、第三子像素以及第四子像素，每一子像素均包括一TFT开关，其中，所述第一子像素、所述第二子像素与所述第三子像素中任一个的TFT开关的宽/长比与所述第四子像素的TFT开关的宽/长比之间的比值，与所述第一子像素、所述第二子像素及所述第三子像素中任一个的存储电容与所述第四子像素的存储电容之间的比值相等；或者，所述第一子像素、所述第二子像素及所述第三子像素中至少两个的TFT开关的宽/长比的平均值与所述第四子像素的TFT开关的宽/长比之间的比值等于所述第一子像素、所述第二子像素及所述第三子像素中至少两个的存储电容的平均值与所述第四子像素的存储电容之间的比值。
  2. 如权利要求1所述的显示像素结构，其中，所述第一子像素、第二子像素与第三子像素的存储电容均相等，所述第一子像素、所述第二子像素及所述第三子像素的TFT开关的宽/长比均相同，且所述第一子像素、所述第二子像素及所述第三子像素中任意一个的TFT开关的宽/长比与所述第四子像素的TFT开关的宽/长比之间的比值，与所述第一子像素、所述第二子像素及所述第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
  3. 如权利要求2所述的显示像素结构，其中，当所述第一子像素、第二子像素、第三子像素的存储电容相同时，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的长度与所述第四子像素的TFT开关的长度相同，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的宽度与所述第四子像素的TFT开关的宽度之间的比值与所述第一子像素、第二子像素、第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
  4. 如权利要求2所述的显示像素结构，其中，当所述第一子像素、第二子 像素、第三子像素的存储电容相同时，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的宽度与所述第四子像素的TFT开关的宽度相同，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的长度与所述第四子像素的TFT开关的长度之间的比值与所述第一子像素、第二子像素、第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
  5. 如权利要求2所述的显示像素结构，其中，当所述第一子像素、第二子像素、第三子像素的存储电容相同时，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关与所述第四子像素的TFT开关的长度与宽度均不相同，而分别对应于所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的宽/长比与所述第四子像素的TFT开关的宽/长比之间的比值与所述第一子像素、第二子像素、第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
  6. 如权利要求1所述的显示像素结构，其中，所述第一子像素、所述第二子像素、所述第三子像素与所述第四子像素的面积相同，并且所述第一子像素、所述第二子像素、所述第三子像素与所述第四子像素的TFT开关一并设置于所述第四子像素中。
  7. 如权利要求1所述的显示像素结构，其中，每一所述像素单元中的第一子像素、所述第二子像素、所述第三子像素和所述第四子像素采用两行两列的矩阵方式排列；所述第一子像素、第二子像素、第三子像素分别为红色子像素、绿色子像素与蓝色子像素中的一种，所述第四子像素为白色子像素或者黄色子像素。
  8. 如权利要求1所述的显示像素结构，其中，所述显示像素结构还包括多条平行设置的栅极线以及多条垂直于所述栅极线设置的数据线，所述栅极线与所述数据线围成所述第一子像素、所述第二子像素、所述第三子像素以及所述 第四子像素。
  9. 一种阵列基板，包括显示像素结构，所述显示像素结构包括呈矩阵排列的多个像素单元，每个像素单元包括第一子像素、第二子像素、第三子像素以及第四子像素，每一子像素均包括一TFT开关，其中，所述第一子像素、所述第二子像素与所述第三子像素中任一个的TFT开关的宽/长比与所述第四子像素的TFT开关的宽/长比之间的比值，与所述第一子像素、所述第二子像素及所述第三子像素中任一个的存储电容与所述第四子像素的存储电容之间的比值相等；或者，所述第一子像素、所述第二子像素及所述第三子像素中至少两个的TFT开关的宽/长比的平均值与所述第四子像素的TFT开关的宽/长比之间的比值等于所述第一子像素、所述第二子像素及所述第三子像素中至少两个的存储电容的平均值与所述第四子像素的存储电容之间的比值。
  10. 如权利要求9所述的阵列基板，其中，所述第一子像素、第二子像素与第三子像素的存储电容均相等，所述第一子像素、所述第二子像素及所述第三子像素的TFT开关的宽/长比均相同，且所述第一子像素、所述第二子像素及所述第三子像素中任意一个的TFT开关的宽/长比与所述第四子像素的TFT开关的宽/长比之间的比值，与所述第一子像素、所述第二子像素及所述第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
  11. 如权利要求10所述的阵列基板，其中，当所述第一子像素、第二子像素、第三子像素的存储电容相同时，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的长度与所述第四子像素的TFT开关的长度相同，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的宽度与所述第四子像素的TFT开关的宽度之间的比值与所述第一子像素、第二子像素、第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
  12. 如权利要求10所述的阵列基板，其中，当所述第一子像素、第二子像 素、第三子像素的存储电容相同时，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的宽度与所述第四子像素的TFT开关的宽度相同，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的长度与所述第四子像素的TFT开关的长度之间的比值与所述第一子像素、第二子像素、第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
  13. 如权利要求10所述的阵列基板，其中，当所述第一子像素、第二子像素、第三子像素的存储电容相同时，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关与所述第四子像素的TFT开关的长度与宽度均不相同，而分别对应于所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的宽/长比与所述第四子像素的TFT开关的宽/长比之间的比值与所述第一子像素、第二子像素、第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
  14. 如权利要求9所述的阵列基板，其中，所述第一子像素、所述第二子像素、所述第三子像素与所述第四子像素的面积相同，并且所述第一子像素、所述第二子像素、所述第三子像素与所述第四子像素的TFT开关一并设置于所述第四子像素中。
  15. 如权利要求9所述的阵列基板，其中，每一所述像素单元中的第一子像素、所述第二子像素、所述第三子像素和所述第四子像素采用两行两列的矩阵方式排列；所述第一子像素、第二子像素、第三子像素分别为红色子像素、绿色子像素与蓝色子像素中的一种，所述第四子像素为白色子像素或者黄色子像素。
  16. 一种显示装置，包括阵列基板，所述阵列基板包括显示像素结构，所述显示像素结构包括呈矩阵排列的多个像素单元，每个像素单元包括第一子像素、第二子像素、第三子像素以及第四子像素，每一子像素均包括一TFT开关， 其中，所述第一子像素、所述第二子像素与所述第三子像素中任一个的TFT开关的宽/长比与所述第四子像素的TFT开关的宽/长比之间的比值，与所述第一子像素、所述第二子像素及所述第三子像素中任一个的存储电容与所述第四子像素的存储电容之间的比值相等；或者，所述第一子像素、所述第二子像素及所述第三子像素中至少两个的TFT开关的宽/长比的平均值与所述第四子像素的TFT开关的宽/长比之间的比值等于所述第一子像素、所述第二子像素及所述第三子像素中至少两个的存储电容的平均值与所述第四子像素的存储电容之间的比值。
  17. 如权利要求16所述的显示装置，其中，所述第一子像素、第二子像素与第三子像素的存储电容均相等，所述第一子像素、所述第二子像素及所述第三子像素的TFT开关的宽/长比均相同，且所述第一子像素、所述第二子像素及所述第三子像素中任意一个的TFT开关的宽/长比与所述第四子像素的TFT开关的宽/长比之间的比值，与所述第一子像素、所述第二子像素及所述第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
  18. 如权利要求17所述的显示装置，其中，当所述第一子像素、第二子像素、第三子像素的存储电容相同时，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的长度与所述第四子像素的TFT开关的长度相同，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的宽度与所述第四子像素的TFT开关的宽度之间的比值与所述第一子像素、第二子像素、第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
  19. 如权利要求17所述的显示装置，其中，当所述第一子像素、第二子像素、第三子像素的存储电容相同时，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的宽度与所述第四子像素的TFT开关的宽度相同，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的长度与所述第四子像素的TFT开关的长度之间的比值与所述第一子像素、第二子像素、第 三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
  20. 如权利要求17所述的显示装置，其中，当所述第一子像素、第二子像素、第三子像素的存储电容相同时，所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关与所述第四子像素的TFT开关的长度与宽度均不相同，而分别对应于所述第一子像素、第二子像素、第三子像素中任意一个的TFT开关的宽/长比与所述第四子像素的TFT开关的宽/长比之间的比值与所述第一子像素、第二子像素、第三子像素中任意一个的存储电容与所述第四子像素的存储电容之间的比值相等。
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