WO2018201377A1

WO2018201377A1 - A unified error correction and error detection code generator

Info

Publication number: WO2018201377A1
Application number: PCT/CN2017/083003
Authority: WO
Inventors: Keeth Saliya JAYASINGHE; Yu Chen; Dongyang DU; Jie Chen
Original assignee: Nokia Technologies Oy; Alcatel-Lucent Shanghai Bell Co., Ltd.
Priority date: 2017-05-04
Filing date: 2017-05-04
Publication date: 2018-11-08
Also published as: CN110603759A; CN110603759B

Abstract

It is provided a method, comprising generating J addon bits if K information bits are sequentially inputted into a generating means comprising J registers; retrieving J*addon bits from the J registers after at least one of the K information bits had been inputted into the generating means and before the K information bits are inputted into the generating means; constructing a codeblock comprising each of the K information bits, the J addon bits, and the J*addon bits, wherein each of the K information bits, the J addon bits, and the J*addon bits is at a respective predetermined position of the codeblock; polar encoding the codeblock.

Description

A UNIFIED ERROR CORRECTION AND ERROR DETECTION CODE GENERATOR

Field of the invention

The present invention relates to an apparatus， a method， and a computer program product related to error detection.

Abbreviations

3GPP 3^rd Generation Partnership Project

5G 5^th Generation

BLER Block Error Ratio

CRC Cyclic Redundancy Check

DCI Downlink Control Information

DL Downlink

eMBB Enhanced Mobile Broadband

FAR False Alarm Rate

mMTC Massive MTC

MTC Machine-type Communication

PC Polar Coding

RAN Radio Access Network

RRC Radio Resource Control

TX Transmit/Transmission

UCI Uplink Control Information

UL Uplink

XOR Exclusive OR

Background of the invention

Polar code， proposed in [1] ， is decided to be used for 5G eMBB control channel and maybe also for mMTC， because it has a few advantages compared to the other candidate coding schemes， e.g. low complexity， capacity achieving.

According to [2] ， polar codes are constructed based on channel polarization principle. It refers to the fact that a set of identical channels (i.e.， many uses of the same channel over time) can be converted into a set of channels that consists only of almost perfect channels or almost useless channels. This conversion can be done in a simple recursive manner. E.g.， two identical copies of a binary-input channel P： X₁ → Y₁ are converted to two new channels

and

Since

is a 1--1 transform， it follows that

Some thought also shows that I (P₁) ≤ I (P) ≤ I (P₂) ， i.e. P₁ is a worse channel than P， and P₂ is better. In that sense， the channel is polarized. The idea is then to enhance polarization by applying the same 2-by-2 transform to P₁ and P₂ and so. Even further channel polarization can be attained by applying this procedure recursively， to get N ＝ 8， N ＝ 16， N ＝ 32， ...distinct channels. When N is large， the bit-channels

become either almost perfect， i.e.

or almost useless， i.e.

Moreover， the fraction of almost perfect bit-channels approaches the channel capacity I (P) .

From an encoding perspective， polar coding consists of placing data bits U_i in the good bit-channel positions i， and fixed pre-known bits (similar to zero-padding， say U_i ＝ 0) in the bad bit-channel positions i， the latter are also known as frozen bits. Thus， in polar code design， a key aspect is to identify the locations of the data bits and frozen bits.

The inventors proposed a CRC distribution scheme for Polar code where the CRC bits are distributed inside the information bits to assist the Polar decoding. The scheme was well received and it is considered to be a promising solution for Polar code for eMBB control channel. And it was listed as one of the alternatives in the meeting agreements.

It was agreed in 3GPP RAN1 88bis meeting that the inventors are going to evaluate the following variants：

Agreement：

· J CRC bits are provided (which may be used for error detection and may also be used to assist decoding and potentially for early termination)

- J may be different in DL and UL

- J may depend on the payload size in the UL (0 not precluded)

· In addition， J’assistance bits are provided in reliable locations (which may be used to assist decoding and potentially for early termination)

· J + J’＜＝ the number of bits required to satisfy the FAR target (nFAR) + 6- Working assumption：

· For DL， n_FAR ＝ 16 (at least for eMBB-related DCI)

· For UL， n_FAR ＝ 8 or 16 (at least for eMBB-related UCI； note that this applies for UL cases with CRC)

· J’＞0

· Working assumption： J”＜＝2 additional assistance bits are provided in unreliable locations (which may be used to assist decoding and potentially for early termination)

- Can be revisited in RAN1#89 if significant benefit is shown from a larger value of J”without undue complexity-companies are encouraged to additionally evaluate J”＝8

· The J’ (and J”if any) bits may be CRC and/or PC and/or hash bits (downscope if possible)

· Placement of the J， J’ (and J”if any) assistance bits is for further study after the study of early termination techniques

- Appended？

- Distributed？

· evenly？

· unevenly？

And also：

Conclusion：

- Study until RAN1#89 polar code construction techniques to facilitate early termination (i.e. before decoding all the information bits) without degrading BLER performance or latency (especially considering the time for deinterleaving the information and assistance bits) compared to purely implementation based methods such as path-metric based pruning

○ e.g. assistance bits distributed in the codeword in such a way that error detection can be performed after partial decoding

○ Investigate performance， complexity and FAR impacts

○ Study of use of data-independent scrambling to facilitate early termination is also not precluded

So in general， a total of J + J’+ J”bits may be supported for error detection and error correction. The J’+J”＝J^＊bits may also be named assistance bits， which describes that the bits may be used to improve the decoding performance， including decoding paths pruning， early termination. As for the implementation perspective， the encoding and decoding become quite complex.

One straightforward implementation example is shown in Fig. 1. The information bits are processed by a first module to generate the J’assistance bits， and then by a second module to generate the J”assistance bits， and then by the CRC module to generate the J CRC bits. After those modules follows a permutation module， so that the J’assistance bits are transmitted， by the polar encoding module， on the reliable subchannels and the J”bits are transmitted on the unreliable subchannels. The permutation module may also be used to distribute the J CRC bits inside the information bits to support early termination. If J”＝0， the second module may be omitted.

The scheme of Fig. 1 needs three (for J”＝0) or four different modules to generate the J+J”assistance bits and the J CRC bits. Hence， it is quite complex and lacks flexibility because the J’and J”assistance bits may be used by the receiver depending on the decoding algorithm.

Though the CRC generator module is quite mature， it needs two additional modules to generate J’and J”assistance bits. Because these assistance bits needs to be placed on reliable and unreliable subchannels， respectively， they are generated by different modules as a straightforward scheme.

At the decoder side， the same process may be followed to do tree pruning and error detection with these assistance bits. So this makes the encoding and decoding complex and may take a longer processing time.

One may also generate the assistance bits as normal parity check bits for the information bits in the normal order. It was considered that this method may achieve the same effect in a simpler manner.

Parity check bits do not follow any specific order. Hence， in the view of the inventors， they are useless when protecting a block of information bits. CRC is more suited for correcting/detecting an information block. Still， when comparing single CRC bit versus a first parity bit， it could appear the same. But， if one considers more than one parity bit， the other parity bits do not have any relation to the previous parity bit or information bits. In contrast， CRC bits may cover overlapping sets of information bits.

References

[1] E. Arikan， “Channel polarization： a method for constructing capacity achieving codes for symmetric binary-input memoryless channels， ” submitted for publication， Oct. 2007.

[2] 3GPP Tdoc R1-164184， “Polar code design for NR” ， Intel Corporation

Summary of the invention

It is an object of the present invention to improve the prior art.

According to a first aspect of the invention， there is provided an apparatus， comprising generating means comprising J registers and configured to generate J addon bits if K information bits are sequentially inputted into the generating means； retrieving means configured to retrieve J^＊addon bits from the J registers after at least one of the K information bits had been inputted into the generating means and before the K information bits are inputted into the generating means； constructing means configured to construct a codeblock comprising each of the K information bits， the J addon bits， and the J^＊addon bits， wherein each of the K information bits， the J addon bits， and the J^＊addon bits is at a respective predetermined position of the codeblock； encoding means configured to polar encode the codeblock.

The retrieving means may be configured to retrieve each of the J^＊addon bits from a respective predetermined register after a respective predetermined input number of the K information bits is inputted into the generating means， wherein each of the predetermined input numbers is smaller than K.

The respective predetermined registers may be the same for all of the J^＊addon bits.

The respective predetermined input numbers may be the same for all the J^＊addon bits.

Each of the J addon bits and the J^＊addon bits may be based on a different subset of the K information bits.

The retrieving means may be configured to retrieve each of the J addon bits and J^＊addon bits such that it is generated based on at least a predetermined number of information bits， wherein the predetermined number is equal to or larger than 2.

One of the J^＊addon bits may be based on m information bits； m＜K； and the constructing means may be configured to arrange the one of the J^＊addon bits in the codeblock immediately before the first one of the m information bits， between the m information bits， or immediately after the m information bits.

The constructing means may comprise a permutating means configured to permutate at least two of the the J addon bits and the J^＊addon bits.

The J addon bits may be an error detection code， and the J^＊addon bits may be assistance bits.

The generating means may be a cyclic redundancy check generator and the J addon bits may be a cyclic redundancy check code.

According to a second aspect of the invention， there is provided a method， comprising generating J addon bits if K information bits are sequentially inputted into a generating means comprising J registers； retrieving J^＊addon bits from the J registers after at least one of the K information bits had been inputted into the generating means and before the K information bits are inputted into the generating means； constructing a codeblock comprising each of the K information bits， the J addon bits， and the J^＊addon bits， wherein each of the K information bits， the J addon bits， and the J^＊addon bits is at a respective predetermined position of the codeblock； polar encoding the codeblock.

The retrieving may comprise retrieving each of the J^＊addon bits from a respective predetermined register after a respective predetermined input number of the K information bits is inputted into the generating means， wherein each of the predetermined input numbers is smaller than K.

The retrieving may comprise retrieving each of the J addon bits and J^＊addon bits such that it is generated based on at least a predetermined number of information bits， wherein the predetermined number is equal to or larger than 2.

One of the J^＊addon bits may be based on m information bits； m＜K； and the constructing may comprise arranging the one of the J^＊addon bits in the codeblock immediately before the first one of the m information bits， between the m information bits， or immediately after the m information bits.

The constructing may comprise permutating at least two of the the J addon bits and the J^＊addon bits.

The method may be a method of coding.

According to a third aspect of the invention， there is provided a computer program product comprising a set of instructions which， when executed on an apparatus， is configured to cause the apparatus to carry out the method according to the second aspect. The computer program product may be embodied as a computer-readable medium or directly Ioadable into a computer.

According to some embodiments of the invention， at least one of the following advantages may be achieved：

● Only one error detection code generator is needed；

● No modification of the error detection code generator is needed；

● Calculation of the error detection code and the assistance bits may need a minimum amount of iterations；

● Flexibility in the design of the error detection code generator to fulfill further requirements (e.g. no restriction on the selection of the polynomial of the CRC generator caused by the generation of the assistance bits) .

It is to be understood that any of the above modifications can be applied singly or in combination to the respective aspects to which they refer， unless they are explicitly stated as excluding alternatives.

Brief description of the drawings

Further details， features， objects， and advantages are apparent from the following detailed description of the preferred embodiments of the present invention which is to be taken in conjunction with the appended drawings， wherein：

Fig. 1 shows an encoding unit；

Fig. 2 shows a CRC generator included in some embodiments of the invention；

Fig. 3 shows an addon bit generator used in variant 1 according to some embodiments of the invention；

Fig. 4 shows a principle of addon bit generation and placing of variant 2 according to some embodiments of the invention；

Fig. 5 shows an addon bit generator used in variant 3 according to some embodiments of the invention；

Fig. 6 shows a principle of addon bit generation and placing of variant 3 according to some embodiments of the invention；

Fig. 7 shows a CRC generator corresponding to x³+x²+1 included in some embodiments of the invention；

Fig. 8 shows a CCITT CRC-16 generator included in some embodiments of the invention；

Fig. 9 shows an apparatus according to an embodiment of the invention；

Fig. 10 shows a method according to an embodiment of the invention； and

Fig. 11 shows an apparatus according to an embodiment of the invention.

Detailed description of certain embodiments

Herein below， certain embodiments of the present invention are described in detail with reference to the accompanying drawings， wherein the features of the embodiments can be freely combined with each other unless otherwise described. However， it is to be expressly understood that the description of certain embodiments is given by way of example only， and that it is by no way intended to be understood as limiting the invention to the disclosed details.

Moreover， it is to be understood that the apparatus is configured to perform the corresponding method， although in some cases only the apparatus or only the method are described.

According to some embodiments of the invention， one CRC generator is used to generate both the J CRC bits and the J’+J”＝J^＊bits for the purpose of assisting the polar decoding. In the following， these J+J’+J”bits may be also named “addon bits” . J’or J”may be 0. The addon bits may be used for error detection and error correction in the decoding of the information bits after polar encoding.

According to some embodiments of the invention， a CRC generator is used to generate not only the J CRC bits， but also the J’and J”assistance bits. More precisely， a J bit CRC generator is used to generate all the error detection bits and error correction bits (addon bits) . Part of these addon bits (including J CRC bits， J’+J”assistance bits) are obtained from the shift registers when all the information bits are input into it， similarly to the conventional CRC generation， and part of these addon bits are generated from a respective intermediate value of the shift registers， i.e. when only part of the information bits are inputted into the CRC generator. Here， “intermediate output” or “intermediate value” means a value of the respective register when at least one of the information bits is inputted into the CRC generator and before all the information bits of the information block are input into the CRC generator.

The concept of a CRC generator used in some embodiments of the invention is shown in Fig. 2. The information bits are inputted sequentially into the shift registers. Between some of the shift registers， there is a respective XOR operator where the value of the preceding register is added to the value of the last register (feedback) . At any time of the shifting operation the values in the registers may be generated by a different number of information bits， and these values depend on the number of XOR operators and the consecutive registers between two XOR operators. “Adding bits” means applying an XOR operation on the bits (i.e.， disregarding overflow) .

In the following， three variants of this concept are described.

Variant 1： All the addon bits are generated on the fly and no permutation is used

Suppose the subchannel indices of the polar encoder are sorted by their reliability {q0， q1， q2， ...， qk} . The index indicates the reliability from high to Iow. Usually the subchanels with high reliability are those at the end of the polar code input and the unreliable subchannels are generally at the beginning， though some reliable subchannels and unreliable subchannels could be interlaced. The number of J’and J”assistance bits to be generated and the subchannels for their transmission may be obtained by some algorithm or based on a specification. Some examples are given later. So， the subchannel indices for the J’assistance bits may be： {IR₀， IR₁， ...IR_J’-1} ， and the indices for the J”assistance bits are {IU₀， IU₁， ...IU_J”-1} ， wherein IR_i denotes a reliable subchannel， and IU_i denotes an unreliable subchannel. The J CRC bits may follow the information bits and the (potentially interlaced) assistance bits.

Generating and placing the addon bits into the “correct” subchannels may be done as follows： The subchannels are filled one after the other， substantially in parallel with inputting the information bits into the CRC generator. This is called “on the fly” . If the subchannel index of the subchannel to be filled indicates that the subchannel carries an information bit， fill the information bit in it. If the subchannel index of the subchannel to be filled indicates that the subchannel carries a J’type of assistance bit， take the value of one of the shift registers and fill it in the respective subchannel. If the subchannel index of the subchannel to be filled indicates that the subchannel carries a J”type of assistance bit， take the value of one of the shift registers and fill it in the respective subchannel.

Since the number of subchannels is larger than the number of information bits by the number of addon bits， in some embodiments， more than one subchannel are filled without inputting a further information bit into the CRC generator. For example， every time a subchannel is filled with an addon bit， the filling may proceed to the next subchannel without inputting a further information bit. As another example， after every q^th information bit， 2 subchannels may be filled without inputting a further information bit into the CRC generator. q may depend on the number of assistance bits (J’+J”＝J^＊) and the number of information bits in the codeblock.

The shift registers to generate J’+J”＝J^＊assistance bits may be different for different assistance bits. One example of such a register is the one just after an XOR operator. Another example is using different registers for subsequent assistance bits. For example， wherein the register for a subsequent assistance bit is the next register just after the previous register. If needed， this may be done in a cyclic manner. Another example is that a fixed shift register， e.g. the first one， is used to generate all the assistance bits. Duplication of information should be avoided when selecting the registers for generating the assistance bits， i.e.， each of the assistance bits should be based on a different combination of the information bits. Hence， in the last example (fixed shift register) ， at least one information bit should be inputted into the CRC register between two assistance bits.

When all the information bits are passed into the CRC generator， the value of the shift registers may be taken as the J CRC bits.

In some embodiments， part or all of the J CRC bits may be generated similarly on the fly if the CRC bits are interlaced with the information bits. That is， part or all of the J CRC may not be obtained as the final values of the shift registers when all information bits are inputted. This may be very useful to satisfy the early termination requirement. In this case， part or all of the J’+J”-J^＊assistance bits may be obtained when all the information bits are inputted into the CRC register.

Fig. 3 shows how the CRC generator of variant 1 generates the J CRC bits， the J’assistance bits， and the J”assistance bits.

Variant 2： All the addon bits are generated on the fly with simple permutation

Variant 2 is based on variant 1. As shown in Fig. 4， the assistance bits are generated only after B information bits (B＞0) were inputted into the CRC generator. The assistance bits are generated in the same manner as in variant 1 by looking up the subchannel index. And then the first B information bits are transmitted after the K-B information bits where there are totally K information bits to be transmitted. The CRC bits or part of the CRC bits are transmitted after the first B information bits.

The benefit of this variant is that the assistance bits are generated when the shift registers have enough feedbacks. Namely， each XOR operation results in a feedback， and hence the value of some of the shift registers are the binary sum of multiple information bits. When there are enough feedbacks， one assistance bit may link to multiple information bits， providing better error correction and error detection capability.

Variant 3： All the addon bits are generated on the fly with real permutation

In variant 3， the J’and J”assistance bits and the CRC bits are all generated by the CRC generator， similar to variants 1 and 2. Then， a permutation is performed to achieve better flexibility (see Fig. 5) . As shown in Fig. 6， first and second line， based on the K information bits， J’+J”＝J^＊assistance bits and J CRC bits are generated on the fly， wherein the J^＊assistance bits may be interlaced between the information bits， and the J CRC bits are appended. Then， this bit sequence is permutated. E.g.， as shown in the third line of Fig. 6， some of the J CRC bits are interlaced in the information bits， too. Thus， only Jx (Jx＜J) CRC bits are appended.

By the permutation， additional operations and feature may be supported：

● Some/all the CRC bits may be transmitted forward to better support early termination.

● The information bits related to a specific CRC bit may be transmitted forward so that the checking can be performed for that CRC bit early.

● The related information bits for the J’assistance bits which are transmitted on the reliable subchannels may be placed on the reliable or unreliable subchannels to achieve better performance in terms of error detection and error correction. If used for error detection， it is found placing these assistance bits on the reliable subchannels may achieve better performance.

● The related information bits for the J”assistance bits which are transmitted on the unreliable subchannels may be placed on the reliable or unreliable subchannels to achieve better performance in terms of error detection and error correction. If used for error correction， it is found placing these assistance bits on the unreliable subchannel may achieve better performance.

● It is also possible to just place the related information bits ahead of the assistance bits.

The better flexibility of this variant also includes that a ratio of the number of related information bits to the number of assistance bits is controllable. The maximum number of information bits related to an assistance bit is determined by the number of feedbacks performed. The reason is that when the number of inputted information bits exceeds the number of shift registers， the mentioned feedback happens. So with this scheme， arbitrary number of summed information bits based on the assistance bit to be generated can be obtained as long as there are information bits yet to be processed. An example of a shift register based CRC generator can be found in Fig. 2.

It is also possible that the assistance bits are obtained by multiple shift registers at the same time. When there are K₁， K₂， ...K_J’information bits inputted into the CRC generator， where K₁， K₂， ...K_J’are integers ＞＝0， or values that are proportional to the information block size. One example of the specific register is the register just after an XOR operator. The registers and K₁， K₂， .. K_j’values are selected to avoid duplication in the assistance bits. l.e.， two assistance bits should not be based on the same combination of information bits.

As an example， the assistance bits may be selected such that the number of information bits involved in the XOR operation exceeds a specific threshold. As another example， the assistance bits may be taken from the first J’or J”shift registers， or from the registers starting from that register which has the maximum number information bits involved in the XOR operation.

The receiver may use a CRC detector corresponding to the CRC generator. The same assistance bit will be generated when the decoded information bits are inputted it. In the Polar decoding， the receiver can compare the received assistance bit (s) and the locally generated bit (s) to check if the path is correct. The paths that do not pass the CRC bit check will be given a penalty of any real number. For example， the penalty value may be {1 3 5 15， ∞} . Penalty is a value used to alter the path metric. A path is considered to be more unreliable the higher the penalty is. In a specific decoding step. A penalty may be given this corresponding value to reduce its path metric. Paths with lower path metric are easier to be dropped during decoding.

The above-mentioned operations and parameters may be known by both the transmitter and the receiver (e.g. defined in the 3GPP specifications) ， or they could also be configured by signaling， e.g. RRC signaling， so that they are known by the transmitter and the receiver.

An example of J is 16 (16 bit CRC) for downlink and 8 (8 bit CRC) for uplink. J’may be 3 (3 assistance bits on reliable channels) ， and J”may be 2 (2 bits on unreliable channels) .

Hereinafter， two embodiments of the invention are explained at greater detail.

Embodiment 1：

As shown in Figure 2， in this embodiment， a CRC generator corresponding to x³+x²+1 is used. There are three registers denoted by R1， R2 and R3. There are two XOR operators denoted by X1 and X2.

Suppose information bits [b_n-1， b_n-2， ...， b₂， b₁， b₀] are to be processed. And the information bits are sent into the CRC generator one by one based on the ascending order of its index.

In this embodiment， 3 assistance bits are to be generated. For other number of assistance bits， a similar method may be used.

One scheme to generate the 3 assistance bits is based on the number of inputted information bits. The assistance bits are obtained as the value of the first register R1 when 4， 6， and 8 information bits are inputted， respectively.

When 4 information bits b₀ to b₃ are inputted， the first register has the value c₀ ＝ b₀+b₃， which is the first assistance bit.

When 6 information bits b₀ to b₅ are inputted， the first register has the value c₁ ＝ b₀+b₁+b₂+b₅， which is the second assistance bit.

When 8 information bits b₀ to b₇ are inputted， the first register has the value c₂ ＝ b₀+b₂+b₃+b₄+b₇， which is the third assistance bit.

As an alternative， the 3 assistance bits may be obtained from the three registers when K information bits are inputted， e.g. K＝8. Then the three assistance bits are：

c₀ ＝ b₀+b₂+b₃+b₄+b₇ (value of the first register R1 when 8 information bits b₀ to b₇ are inputted)

c₁ ＝ b₁+b₂+b₃+b₆ (value of the second register R2 when 8 information bits b₀ to b₇ are inputted)

c₂ ＝ b₁+b₃+b₄+b₅ (value of the third register R3 when 8 information bits b₀ to b7 are inputted)

Embodiment 2：

In this embodiment， CCITT CRC-16 generator shown in Fig. 3 is used. It comprises 16 registers denoted by R0 ～ R15， and three XOR operators.

Information bits [b_n-1， b_n-2， ...， b₂， b₁， b₀] are to be processed. The information bits are sent into the CRC generator one by one based on the ascending order or its index.

The 16 CRC bits are obtained when all the n information bits are input into the generator， by taking out of the register values. In this embodiment， the number of assistance bits J’＝ 4. The assistance bits are obtained by taking the value of the register R5 when 18， 19， 20， 21 information bits are inputted into the CRC generator， respectively. Then the four assistance bits are：

c₀ ＝ b₁+b₁₇+b₁₂

c₁ ＝ b₂+b₁₈+b₁₃

c₂ ＝ b₃+b₁₉+b₁₄

c₃ ＝ b₄+b₂₀+b₁₅

In the embodiment， the assistance bits are transmitted after a permutation so that they follow their corresponding information bits. Hence， the transmission sequence may be：

[b₁ b₁₇ b₁₂ c₀ b₂ b₁₈ b₁₃ c₁ b₃ b₁₉ b₁₄ c₂ b₄ b₂₀ b₁₅ c₃] ， where the bits are transmitted from left to right.

Fig. 4 shows an apparatus according to an embodiment of the invention. The apparatus may be an encoding unit of an eNodeB or a UE or an element thereof. Fig. 5 shows a method according to an embodiment of the invention. The apparatus according to Fig. 4 may perform the method of Fig. 5 but is not limited to this method. The method of Fig. 5 may be performed by the apparatus of Fig. 4 but is not limited to being performed by this apparatus.

The apparatus comprises generating means 10， retrieving means 20， constructing means 30， and encoding means 40. Each of the generating means 10， retrieving means 20， constructing means 30， and encoding means 40 may be a generating processor， retrieving processor， constructing processor， and encoding processor， respectively. Each of the generating means 10， retrieving means 20， constructing means 30， and encoding means 40 may be a generator， retriever， constructor， and encoder， respectively.

The generating means 10 comprises J registers. It may consist of J registers. The generating means 10 generates J addon bits (e.g. an error detection code such as a CRC code) of J bits if K information bits are sequentially inputted into the generating means 10 (S10) . The K information bits may be denoted as an information block. J is a natural number (J＝1 or 2 or 3...) .

The retrieving means 20 retrieves J^＊addon bits from the J registers after at least one of the K information bits had been inputted into the generating means 10 and before the K information bits are inputted into the generating means 10 (S20) . That is， the retrieving means 20 retrieves the J^＊addon bits as intermediate values of the registers. J^＊is a natural number (J’＝1 or 2 or 3...) . J^＊may be predetermined. For example， the J^＊addon bits may be assistance bits， with J’bits for reliable subchannels and J”bits for unreliable subchannels， wherein J^＊＝J’+J”.

The constructing means 30 constructs a codeblock comprising each of the K information bits， the J addon bits generated by the generating means 10 if the K information bits are inputted into the generating means 10， and the J^＊addon bits retrieved by the retrieving means 20 (S30) . The constructing means 30 constructs the codeblock such that each of the K information bits， the J addon bits， and the J^＊addon bits is at a respective predetermined position of the codeblock. The codeblock may consist of the K information bits， the J addon bits， and the J^＊addon bits.

Fig. 6 shows an apparatus according to an embodiment of the invention. The apparatus comprises at least one processor 410， at least one memory 420 including computer program code， and the at least one processor 410， with the at least one memory 420 and the computer program code， being arranged to cause the apparatus to at least perform at least the method according to Fig. 5.

Some embodiments of the invention may be employed in 3GPP devices， e.g. in the encoding unit thereof. However， embodiments of the invention are not limited to 3GPP devices. They may be employed in any kind of devices where polar coding is employed.

Some embodiments of the invention may use another error detection code than CRC if this error detection code can generate intermediate values. For example， any block code with Hamming distance t can detect t-1 errors. An example are Hamming codes.

One piece of information may be transmitted in one or plural messages from one entity to another entity. Each of these messages may comprise further (different) pieces of information.

Names of network elements， protocols， and methods are based on current standards. In other versions or other technologies， the names of these network elements and/or protocols and/or methods may be different， as long as they provide a corresponding functionality.

The format of the messages and information elements is not limited those shown in some of the figures. These formats are to be seen as examples only.

If not otherwise stated or otherwise made clear from the context， the statement that two entities are different means that they perform different functions. It does not necessarily mean that they are based on different hardware. That is， each of the entities described in the present description may be based on a different hardware， or some or all of the entities may be based on the same hardware. It does not necessarily mean that they are based on different software. That is， each of the entities described in the present description may be based on different software， or some or all of the entities may be based on the same software. Each of the entities described in the present description may be embodied in the cloud.

According to the above description， it should thus be apparent that example embodiments of the present invention provide， for example， a base station such as a eNodeB， or a component such as a TX path or an encoding unit thereof， or a terminal such as a User Equipment or a MTC device， or a component such as a TX path or an encoding unit thereof， an apparatus embodying the same， a method for controlling and/or operating the same， and computer program (s) controlling and/or operating the same as well as mediums carrying such computer program (s) and forming computer program product (s) .

Implementations of any of the above described blocks， apparatuses， systems， techniques or methods include， as non-limiting examples， implementations as hardware， software， firmware， special purpose circuits or logic， general purpose hardware or controller or other computing devices， or some combination thereof.

It is to be understood that what is described above is what is presently considered the preferred embodiments of the present invention. However， it should be noted that the description of the preferred embodiments is given by way of example only and that various modifications may be made without departing from the scope of the invention as defined by the appended claims.

Claims

Apparatus， comprising

generating means comprising J registers and configured to generate J addon bits if K information bits are sequentially inputted into the generating means；

retrieving means configured to retrieve J^＊ addon bits from the J registers after at least one of the K information bits had been inputted into the generating means and before the K information bits are inputted into the generating means；

constructing means configured to construct a codeblock comprising each of the K information bits， the J addon bits， and the J^＊ addon bits， wherein each of the K information bits， the J addon bits， and the J^＊ addon bits is at a respective predetermined position of the codeblock；

encoding means configured to polar encode the codeblock.
The apparatus according to claim 1， wherein the retrieving means is configured to retrieve each of the J^＊ addon bits from a respective predetermined register after a respective predetermined input number of the K information bits is inputted into the generating means， wherein each of the predetermined input numbers is smaller than K.
The apparatus according to claim 2， wherein the respective predetermined registers are the same for all of the J^＊ addon bits.
The apparatus according to claim 2， wherein the respective predetermined input numbers are the same for all the J^＊ addon bits.
The apparatus according to any of claims 1 to 4， wherein each of the J addon bits and the J^＊ addon bits is based on a different subset of the K information bits.
The apparatus according to any of claims 1 to 5， wherein the retrieving means is configured to retrieve each of the J addon bits and J^＊ addon bits such that it is generated based on at least a predetermined number of information bits， wherein the predetermined number is equal to or larger than 2.
The apparatus according to any of claims 1 to 6， wherein

one of the J^＊ addon bits is based on m information bits；

m＜K； and

the constructing means is configured to arrange the one of the J^＊ addon bits in the codeblock immediately before the first one of the m information bits， between the m information bits， or immediately after the m information bits.
The apparatus according to any of claims 1 to 7， wherein the constructing means comprises

a permutating means configured to permutate at least two of the the J addon bits and the J^＊ addon bits.
The apparatus according to any of claims 1 to 8， wherein the J addon bits are an error detection code， and the J^＊ addon bits are assistance bits.
The apparatus according to any of claims 1 to 9， wherein the generating means is a cyclic redundancy check generator and the J addon bits are a cyclic redundancy check code.
Method， comprising

generating J addon bits if K information bits are sequentially inputted into a generating means comprising J registers；

retrieving J^＊ addon bits from the J registers after at least one of the K information bits had been inputted into the generating means and before the K information bits are inputted into the generating means；

constructing a codeblock comprising each of the K information bits， the J addon bits， and the J^＊ addon bits， wherein each of the K information bits， the J addon bits， and the J^＊ addon bits is at a respective predetermined position of the codeblock；

polar encoding the codeblock.
The method according to claim 11， wherein the retrieving comprises retrieving each of the J^＊ addon bits from a respective predetermined register after a respective predetermined input number of the K information bits is inputted into the generating means， wherein each of the predetermined input numbers is smaller than K.
The method according to claim 12， wherein the respective predetermined registers are the same for all of the J^＊ addon bits.
The method according to claim 12， wherein the respective predetermined input numbers are the same for all the J^＊ addon bits.
The method according to any of claims 11 to 14， wherein each of the J addon bits and the J^＊ addon bits is based on a different subset of the K information bits.
The method according to any of claims 11 to 15， wherein the retrieving comprises retrieving each of the J addon bits and J^＊ addon bits such that it is generated based on at least a predetermined number of information bits， wherein the predetermined number is equal to or larger than 2.
The method according to any of claims 11 to 16， wherein

one of the J^＊ addon bits is based on m information bits；

m＜K； and

the constructing comprises arranging the one of the J^＊ addon bits in the codeblock immediately before the first one of the m information bits， between the m information bits， or immediately after the m information bits.
The method according to any of claims 11 to 17， wherein the constructing comprises permutating at least two of the the J addon bits and the J^＊ addon bits.
The method according to any of claims 11 to 18， wherein the J addon bits are an error detection code， and the J^＊ addon bits are assistance bits.
The method according to any of claims 11 to 19， wherein the generating means is a cyclic redundancy check generator and the J addon bits are a cyclic redundancy check code.
A computer program product comprising a set of instructions which， when executed on an apparatus， is configured to cause the apparatus to carry out the method according to any of claims 11 to 20.
The computer program product according to claim 21， embodied as a computer-readable medium or directly loadable into a computer.