WO2018182731A1

WO2018182731A1 - Steep subthreshold slope vertical fet using threshold switching material

Info

Publication number: WO2018182731A1
Application number: PCT/US2017/025552
Authority: WO
Inventors: Abhishek A. Sharma; Ravi Pillarisetty; Van H. Le; Gilbert Dewey
Original assignee: Intel Corporation
Priority date: 2017-03-31
Filing date: 2017-03-31
Publication date: 2018-10-04

Abstract

A transistor apparatus including a transistor body disposed on a substrate, the body including a first diffusion region and a second diffusion region on the first diffusion region, wherein the first diffusion region and the second diffusion region are separated by a channel; a threshold switching material (TSM) coupled to one of the first diffusion region and the second diffusion region; and a gate stack including a gate electrode and a gate dielectric material. A method of forming an integrated circuit including forming a plurality of bodies in a row on a substrate, each of the plurality of bodies including a transistor including a first diffusion region, a second diffusion region and a channel, wherein the second diffusion region is on the first diffusion region and separated by the channel; and forming a threshold switching material (TSM) in contact with the second diffusion region.

Description

STEEP SUBTHRESHOLD SLOPE VERTICAL FET

USING THRESHOLD SWITCHING MATERIAL

BACKGROUND

Field

Integrated circuit devices.

Description of Related Art

In a subthreshold region, the drain current of a metal oxide semiconductor field effect transistor (MOSFET) tends to increase exponentially with increasing gate voltage. A change in gate voltage for decade change in drain current in a subthreshold mode is referred to as a subthreshold slope. The subthreshold slope determines how far below a threshold voltage the gate voltage must be dropped to obtain any specific level of channel leakage for an "off device. A MOSFET generally has a 59 millivolt/decade (mV/dec) subthreshold slope due to thermal injection of carriers at the p-n junction. The 59 mV/dec limit tends to limit a power budget and evidences leakage. The 59 mV/dec cannot be under driven negative due to gate- induced drain leakage.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a top perspective view of an embodiment of an array of vertical FET wherein each transistor in the array including a threshold switching material in contact with each transistors and wherein each transistor is connected to a bottom address line (e.g., a bottom bit line) and a top address line (e.g., a top bit line).

Figure 2 shows the structure of Figure 1 through line 2-2'.

Figure 3 shows a substrate having a device layer, a passivation layer and first diffusion region material film on a surface and a channel material film on the first diffusion region material film.

Figure 4 shows the structure of Figure 3 following the definition of the fin structures in the first diffusion region material film and the channel material film and a deposition of dielectric material between the fin structures.

Figure 5 shows the structure of Figure 4 following a recessing of the dielectric material to a height of a film to expose an entire length dimension of the channel material film.

Figure 6 shows the structure of Figure 5 following the introduction of a gate dielectric and gate electrode material in trenches formed by recessing the dielectric material. Figure 7 shows the structure of Figure 6 following a recessing of the gate stack material in each trench to expose a portion of the channel material film.

Figure 8 shows the structure of Figure 7 following a removal of the mask on each fin and the conversion of the exposed portion of the channel material film into second diffusion region material.

Figure 9 shows a top view of the structure of Figure 8 following the patterning of a masking material generally perpendicular to a direction of the gate stacks.

Figure 10 shows the structure of Figure 9 through line 10-10' to show a yz- dimension following the formation of trenches through the fins in areas of the fins that were not protected by a mask.

Figure 11 shows the structure of Figure 10 following the deposition of a dielectric material in the trenches.

Figure 12 shows a top view of the structure of Figure 11.

Figure 13 shows the structure of Figure 12 through line 13-13' after the deposition of threshold switching material and electrically conductive material on the second diffusion region material.

Figure 14 is a flow chart of the methods illustrated in Figures 1-13.

Figure 15 shows a top perspective view of another embodiment of an array of vertical transistors including a threshold switching material in direct contact with each transistor and wherein each transistor in the array is connected to a bottom address line (e.g., a bottom bit line) and a top address line (e.g., a top bit line).

Figure 16 shows the structure of Figure 22 through line 16-16'.

Figure 17 shows a substrate having a device layer, a passivation layer, a threshold switching material layer and first diffusion region material film on a surface and a channel material film on the first diffusion region material film.

Figure 18 shows the structure of Figure 17 following the definition of the fin structures in the first diffusion region material film and the channel material film and a deposition of dielectric material between the fin structures.

Figure 19 shows the structure of Figure 18 following a recessing of the dielectric material to a height of a film to expose an entire length dimension of the channel material film.

Figure 20 shows the structure of Figure 19 following the introduction of a gate dielectric and gate electrode material in trenches formed by recessing the dielectric material. Figure 21 shows the structure of Figure 20 following a recessing of the gate stack material in each trench to expose a portion of the channel material film.

Figure 22 shows the structure of Figure 21 following a removal of the mask on each fin and the conversion of the exposed portion of the channel material film into second diffusion region material.

Figure 23 shows a top view of the structure of Figure 22 following the patterning of a masking material generally perpendicular to a direction of the gate stacks.

Figure 24 shows the structure of Figure 23 through line 24-24' to show a yz- dimension following the formation of trenches through the fins in areas of the fins that were not protected by a mask.

Figure 25 shows the structure of Figure 24 following the deposition of a dielectric material in the trenches.

Figure 26 shows a top view of the structure of Figure 25.

Figure 27 shows the structure of Figure 26 through line 27-27' after the replacement of the mask with electrically conductive material.

Figure 28 is a flow chart of the methods illustrated in Figures 17-27.

Figure 29 is an interposer implementing one or more embodiments.

Figure 30 illustrates an embodiment of a computing device. DETAILED DESCRIPTION

A transistor apparatus is described. In one embodiment, the transistor apparatus includes a transistor body disposed on a substrate, the body including a first diffusion region and a second diffusion region on the first diffusion region, wherein the first diffusion region and the second diffusion region are separated by a channel. Disposed on one of the first diffusion region and the second diffusion region is a threshold switching material (TSM). A gate stack including a gate electrode and a dielectric material is disposed on the channel. In one embodiment, the transistor apparatus that includes the threshold switching material on a source of the transistor device, the transistor device shows a sub-60 mV subthreshold slope and ultra-low leakage in the "off state (e.g., less than le - 10Α/μπι) and high current in the "on" state. A method of forming a transistor is also described.

Figure 1 shows a top perspective view of an embodiment of an array of field effect transistor (FET) devices such as metal oxide semiconductor field effect transistor (MOSFET) devices, tunneling field effect transistor (TFET) device, or other FET devices. Each transistor in the array is connected to a bottom address line (e.g., a bottom bit line) and a top address line (a top bit line). Dielectric material that otherwise would surround each transistor device and the bit lines is not illustrated so that the array is visible. Figure 2 shows the structure of Figure 1 through line 2-2'. In this embodiment, non-planar vertical transistors (as viewed) are described that include diffusion regions (source/drain) and a conducting channel in a stacked arrangement (one on the other) above a base surface of a substrate as transistor bodies or fins. In the views shown, the transistor bodies or fins are projected vertically from a base surface of the substrate. A gate electrode is disposed on the channel on less than an entire perimeter area portion of the channel of the transistor body or fin (e.g., on one side of a multi-sided body or fin).

Referring to Figure 1 and Figure 2, in one embodiment, substrate 110 is a single crystal semiconductor substrate such as a bulk semiconductor (e.g., bulk silicon) or an SOI structure. Substrate 110 may be less than an entire portion of a chip. Disposed on substrate 110, in this example, is device layer 112 that may include a large number of devices (e.g., transistors, capacitors, resistors, etc.). Overlying device layer 112 is dielectric layer 115 (e.g., Si0₂ or a low-k dielectric material) and, representatively, one or more metallization layers. Disposed on dielectric layer 115 is first address lines 117. Figure 2 shows four first address lines 117 each having a z-dimension width, a y-dimension thickness and an x-dimension length. Disposed on each of first address lines 117 are vertical FETs. Figure 1 shows five vertical FETs disposed in an exemplary row in an x-dimension (M=5) on respective first address lines and four transistors in an exemplary column in a z-dimension (N=4). Transistor 120 is a representative of each of the transistors. Transistor 120 includes a vertically projecting body or fin including first diffusion region 125 (e.g., a drain), channel 130 and second diffusion region 135 (e.g., a source) with channel 130 on first diffusion region 125 and second diffusion region 135 on channel 130. Where substrate 110 is a silicon substrate, in one embodiment, first diffusion region 125 is a doped silicon material (e.g., n-doped or p- doped) representatively different than the substrate. Alternative materials for first diffusion region 125 include, but are not limited to, germanium or a group III-V compound

semiconductor material. Specific examples include germanium (Ge), silicon germanium (SiGe), gallium arsenide (G7s), indium antimony (InSb), indium gallium arsenide (InG7s), gallium antimony (GaSb), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO) and tin oxide (SnO). The material of first diffusion region 125 may be crystalline (e.g., polycrystalline) or amorphous. In one example, first diffusion region 125 has a height, hi, on the order of 10 nanometers (nm) to 50 nm (e.g., 25-30 nm). Channel 130 is disposed on first diffusion region 125. Where a material for first diffusion region 125 is a doped silicon material, a material of channel 130 is, for example, a silicon material that may or may not be lightly doped (e.g., an intrinsic material). Disposed on channel 130 is second diffusion region 135 that is, for example, a material similar to a material of first diffusion region 125 and doped similar to first diffusion region 125.

In the example shown in Figure 1 and Figure 2, the transistor bodies or fins have a generally rectangular cross-section with two pairs of opposing sidewalls. It is appreciated that a cross-sectional shape of a transistor body or fin will depend on how the body or fin is formed and therefore may adopt other shapes such as circular or other quadrilateral shape (e.g., trapezoidal). Also, in the illustration, first diffusion region 125 and second diffusion region 135 appear to have similar dimensions. As will be explained later, the regions are formed separately and therefore may have dissimilar shapes (e.g., different cross-sections).

Disposed on channel 130 and offset from the body or fin is a gate stack including gate dielectric 140 and gate electrode 150. In this embodiment, the gate stack is disposed on one sidewall of the channel. In one embodiment, gate dielectric 140 is a silicon dioxide (Si0₂) or a dielectric material having a dielectric constant greater than silicon dioxide (a high-k material) or a combination of silicon dioxide and a high-k material(s) or a combination of high-k materials. Representatively, gate dielectric 140 has a thickness on the order of a few nanometers. As illustrated in Figure 2, gate dielectric 140 is disposed on less than an entire perimeter area portion of channel 130 (e.g., gate dielectric 140 is disposed on one side of a multi-sided channel). Disposed on gate dielectric 140 is gate electrode 150 of, for example, an electrically conductive material such as a metal material (e.g., tantalum), a metal nitride or a silicide. As shown more clearly in Figure 1, in one embodiment, gate electrode 150 extends as an indivisible body through the array in a z-dimension and, in such manner, is connected to multiple channels of transistor bodies or fins in the column of the array. In this embodiment, gate electrode 150 may serve as an address line for each of the transistors aligned in a z-dimension column. In such an embodiment including multiple columns, each gate electrode may be connected to address line driver 196.

Disposed on and directly and electrically connected to each of the second diffusion regions (second diffusion region 135) is a layer of threshold switching material (TSM). In one embodiment, TSM 185 is a material that when disposed on a source of an FET will reduce a subthreshold slope of the device beyond 59 mV/dec. In one embodiment, TSM 185 also referred to as an ovonic threshold switch (OTS) is selected from a semiconductor material or an oxide. Representative semiconductor material includes silicon, germanium or a compound semiconductor material selected from elements from group 13 to group 16 of the Periodic Table of the Elements (formerly groups III- VI). Specific examples of semiconductor materials for TSM 185 include, but are not limited to, amorphous or crystalline (e.g., poly crystalline) silicon, germanium, germanium -tellurium (GeTe_x), aluminum-silicon (AISi), aluminum-antimony -tellurium (AlSbTe) and silicon -tellurium - arsenic-germanium (SiTeAsGe). In one embodiment, TSM 185 has a thickness on the order of 5 nm to 20 nm. TSM 185 may be formed as a blanket film across the array or patterned into distinct lines have a width dimension similar to a width dimension, WTSM, of the second diffusion region to which it is physically connected (second diffusion region 135) as illustrated.

Overlying TSM 185 in the structure of Figure 1 and Figure 2 are second address lines. In one embodiment, in the illustration shown in Figure 1, each second address line 190 is connected to five transistors in a row and is disposed in a parallel alignment with first address line 117. Second address line 190 may be a metal material such as copper that may be part of a back end of line (BEOL) metallization layer. Figure 1 shows each of first address lines 117 are electrically connected to first bit line driver 193 and each of second address lines 190 are electrically connected to second bit line driver 195. Each gate electrode 150 defining a word line, in this embodiment, is connected to word line driver 196.

Figures 3-13 describe a method for forming the transistor array as shown in Figure 1 and Figure 2. Figure 14 is a flow chart of the method. A formation process for an array of n-type FETs is described. Again, it should be appreciated that the techniques for forming a transistor presented here are not limited to any particular device conductivity or transistor type. Referring to Figure 3 and with reference to Figure 14, the process begins following, in this example, any FEOL fabrication such as the forming of transistor or other devices on a substrate, the passivating of such devices and the formation of contacts to such devices. Figure 3 shows substrate 210 that may be any material that may serve as a foundation on which an array of vertical FETs may be constructed. Representatively, substrate 210 is a portion of a larger substrate that is a wafer. In one embodiment, substrate 210 is a bulk semiconductor material such as a single crystal silicon or an SOI structure.

Disposed on a surface of substrate 210 (a top surface as viewed) is device layer 212 of, for example, a number of transistor, capacitor, and/or resistor devices. Overlying device layer 212 is passivation layer 215. In one embodiment, passivation layer 215 is a Si0₂ layer or a low-k dielectric material. Passivation layer 215, in one embodiment, may be a base dielectric layer passivating the front end of line (FEOL) fabrication and, in another embodiment, may be insulating material passivating the FEOL fabrication and also insulating material between metallization layers formed as part of BEOL fabrication. Overlying or disposed on passivation layer 215 is conductive layer 217. Conductive layer 217 is an electrically conductive material that would be suitable, in one embodiment, to serve as an address line for an array of transistors connected thereto. In one embodiment, conductive layer 217 is a copper material that may be deposited by an electroplating process over an array area on a surface of an area including passivation layer 215 (block 305, Figure 14). In another embodiment, conductive layer 217 is titanium nitride or tungsten deposited by, for example, a CVD or PVD process. In one embodiment, conductive layer 217 may be part of a metallization layer (e.g., M1-M6) in a BEOL fabrication.

Figure 3 shows film 225 deposited on conductive layer 217. Film 225 is, for example, an amorphous or crystalline (e.g., poly crystalline) semiconductor material such as silicon, germanium (Ge), silicon germanium (SiGe), gallium arsenide (G7s), indium antimony (InSb), indium gallium arsenide (InG7s), gallium antimony (GaSb), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO) or tin oxide (SnO). For n-type transistors, film 225 is n-doped (n+) and is epitaxially grown or deposited to a representative thickness on the order of 25 nanometers (nm) as a first diffusion region film (block 310, Figure 14). Formed on film 225 is a film for a channel of a transistor (block 315, Figure 14). In one embodiment, film 230 is undoped (intrinsic) or lightly doped semiconductor material that has a representative thickness on the order of 75 nm. Where film 225 is silicon, film 230 may also be silicon that is formed by an epitaxial growth or deposition process.

Figure 4 shows the structure of Figure 3 following the definition of fin structures in film 225 and film 230 (block 320, Figure 14) and a deposition of dielectric material between the fins (block 325, Figure 14). Figure 4 representatively shows five fins. The fins may be formed by a mask and etch process wherein mask 233 (e.g., hard mask of, for example, silicon nitride) is introduced on a surface (superior surface) of film 230 to protect areas of film 230 and underlying film 225 where the fins would be defined and provide openings in non-fin areas. Once mask 233 is patterned, the structure may be anisotropically etched to remove the material in unprotected areas. As shown in Figure 4, in one embodiment, the etch is selective for a material of film 225 and film 230 but does not etch conductive layer 217. In this manner, trench or trenches 247 formed adjacent to the five fins have a depth to a surface of conductive layer 217. In one embodiment, each of the five fins, as shown in

Figure 4, has a thickness dimension, t, on the order of 10 nm. Representatively, a suitable etch for etching silicon films is a HF -based chemistry. Between adjacent fins is trench 247 having a representative width in an x-direction, w_t, on the order of 40 nm. Following the definition of the fins, trenches 247 are filled with dielectric material 245 such as silicon dioxide or a low-k dielectric material.

Figure 5 shows the structure of Figure 4 following a recessing of dielectric layer 245 to a height of film 225 to expose an entire length dimension of film 230 (block 330, Figure 14). In one embodiment, such recessing may be done by retaining mask 233 and etching the dielectric material using a timed etch. As illustrated in Figure 5, the depth of the etch forms trenches 247 having a depth of the length of film 230 (e.g., 75 nm).

Figure 6 shows the structure of Figure 5 following the introduction of a gate dielectric and gate electrode material in the trenches of the structure. Initially, a gate dielectric material is introduced (block 335, Figure 14). Gate dielectric 240 is, for example, silicon dioxide or a high-k dielectric material or a mixture of silicon dioxide and a high-k material or materials. As shown in Figure 6, gate dielectric material 240 is introduced by, for example, CVD deposition to a thickness on the order of few nanometers in a manner that it conforms to the sidewalls of each trench 247 and a superior surface of dielectric layer 245. After forming gate dielectric 240, gate electrode 250 is formed in the trenches (block 340, Figure 14). Representative materials for gate electrode 250 include, but are not limited to, tungsten, tantalum, titanium or a nitride, a metal alloy, silicide or another material. In one embodiment, gate electrode 250 may be introduced by a CVD or other deposition process. In one embodiment, a material for gate electrode 250 is introduced in an amount to fill each trench 247. In this embodiment, the gate stack is offset from its corresponding transistor body or fin. By offset from a transistor body is meant that a gate stack does not share x- dimension coordinates with the transistor body or fin to which it is connected. The formation of a gate stack including gate dielectric 240 and gate electrode 250 in trenches 247 adjacent or offset from a fin allows the gate stack to be self-aligned to the fins. The fins define the dimensions of trenches 247 and the gate stacks are formed to fill the trenches. Following the introduction of gate electrode 250 in each trench, a surface of the structure (a top or superior surface as viewed) may be polished by, for example, a chemical-mechanical polish to planarize the structure.

Figure 7 shows the structure of Figure 6 following a recessing of the gate stack material (gate dielectric 240 and gate electrode 250) in each trench 247 (block 345, Figure 14). In one embodiment, a combination of dry or wet etches may be used to recess a metal gate electrode material and a high-k gate dielectric material. A recess is performed to expose a portion of film 230 such that the exposed portion can be modified or converted to form a second diffusion region in each fin. In one embodiment, the recess of gate dielectric 240 and gate electrode 250 exposes approximately 20 nm of film 230.

Figure 8 shows the structure of Figure 7 following a removal of the mask on each fin and the conversion of a portion of film 230 into second diffusion region material. The removal of mask 233 exposes a top portion of film 230. Following the removal, the exposed portion of film 230 may be converted to a second diffusion region material (block 350,

Figure 14). In one embodiment, second diffusion region 235 is formed by implanting an n- type implant such as arsenic or phosphorous into the exposed portion of film 230 to form an n⁺ second diffusion region. In another embodiment, a portion of film 230 can be removed and replaced with another material to form second diffusion region 235. Figure 8 shows second diffusion region 235 having an x-dimension (thickness dimension) similar to that of film 230. In another embodiment, the x-dimension may be greater than an x-dimension of film 230 to form, for example, a raised diffusion region. In still another embodiment, an optional dielectric layer of silicon dioxide or a low-k dielectric material or a combination of materials may be formed on an exposed portion of the gate stack prior to the formation of second diffusion region 235 as a sidewall spacer on the gate electrode.

Figure 8 shows the structure of Figure 7 following the introduction of a dielectric material in trenches 247. In one embodiment, dielectric material 255 is silicon dioxide or a low-k dielectric material or a combination of materials that may be introduced by a deposition process. Following the deposition, a top surface of the structure (as viewed) may be planarized.

Figure 9 shows a top view of the structure of Figure 8 following patterning of a masking material generally perpendicular to a direction of the gate stacks. A width, w_m, of mask 266 is selected to define a z-dimension thickness or width of individual transistor bodies or fins in a column. A representative width is on the order of 20 nm to 500 nm (e.g., 50 nm to 100 nm). One suitable material for mask 266 is a silicon nitride material.

Figure 10 shows the structure of Figure 9 through line 10-10' to show a yz- dimension following the formation of trenches through the fins in areas of the fins that were not protected by mask 266 (block 355, Figure 14). In one embodiment, the trenches are formed by anisotropically etching a portion of second diffusion region 235, film 230, film 225 and conductive layer 217. Such etch is selective to the noted materials and stops on passivation layer 215. Such etch also does not etch dielectric material 255 above each gate stack. Figure 11 shows the structure of Figure 10 following the deposition of dielectric material 270 in trenches 267 (block 360, Figure 14). In this embodiment, dielectric material 270 is deposited to at least a height of mask 266. Figure 12 shows a top view of the structure of Figure 11. Once dielectric material 270 is deposited, the structure may be planarized by, for example, a polish. Following the deposition and optional planarization, mask 266 is removed by, for example, an etch.

Figure 13 shows the structure of Figure 12 through line 13-13' following the deposition of threshold switching material (TSM) (block, 365, Figure 14) and electrically conductive material (block 370, Figure 14). Figure 13 shows TSM 285 such as a

semiconductor material or an oxide directly connected to (in physical contact with) second diffusion region 235 of each of five transistors in a row. In one embodiment, TSM 285 may be introduced by a CVD process to a thickness on the order of 5 nm to 20 nm.

Following the deposition of TSM 285, electrically conductive material is introduced on TSM to form a signal line for each row of the array. Figure 13 shows electrically conductive material 290 such as a metal (e.g., copper) disposed on and physically connected to TSM 285 on each of five transistors in a row. Conductive material 290 may serve as a second address line (e.g., a second bit line) as described above with respect to Figures 1-2. The structure shown in Figure 13 is similar to that described above with respect to Figures 1-2

In the above description of forming TSM 285, the TSM was formed in the trenches in dielectric material 270 left by the removal of mask 266. In another embodiment, mask 266 may be removed prior to or after the deposition of dielectric material 270. After dielectric material 270 is deposited (and the mask removed), the structure may be planarized. TSM 285 may then be deposited as a blanket across the surface of structure (a surface including dielectric material 270). This may be followed by a Damascene process to form lines of conductive material 290 of, for example, copper. Such Damascene process may include, for example, a seeding of the surface of the structure with a copper seed material, masking of the structure to define openings for bit lines, depositing conductive material 290 by an electroplating process and the removal of the masking and excess seed material. TSM 285 that is not covered by conductive material 290 may be retained or removed by an etch.

Figure 15 shows a top perspective view of another embodiment of an array of vertical transistors including a TSM layer directly connected to a diffusion region of each transistor and wherein each transistor in the array is connected to a bottom address line (e.g., a bottom bit line) and a top address line (e.g., a top bit line). Dielectric material surrounding the transistors is not shown in Figure 15 so that the array may be visible. Figure 16 shows the structure of Figure 15 through line 16-16'. In this embodiment, non-planar, vertical (as viewed) BEOL transistors are described that include diffusion regions and a conducting channel in a stacked arrangement (one on the other) on a substrate. Transistor 420 is representative of the transistors in the array.

Referring to Figure 15 and Figure 16, in one embodiment, substrate 410 is a semiconductor substrate such as a bulk semiconductor (e.g., bulk silicon) or an SOI structure. Substrate 410 may be less than an entire portion of a chip. Disposed on substrate 410, in this example, is device layer 412 that may include a large number of devices (e.g., transistors, capacitors, resistors, etc.). Overlying device layer 412 is dielectric layer 415 (e.g., Si0₂ or a low-k dielectric material) and, representatively, one or more metallization layers. Disposed on dielectric layer 415 is first address lines 417. Figure 15 shows four first address lines 417 defining, representatively, four rows. Disposed on a surface of each address line is TSM layer 485. Also disposed on each of first address lines 417 are vertical FETs. The vertical FETs are directly in conect with TSM layer 485. Figure 15 shows five vertical FETs disposed on respective first address lines. Transistor 420 is a representative of each of the transistors. Transister 420 includes first diffusion region 425 such as a source in physical and electrical contact with TSM layer 485. Disposed on first diffusion region 425 is channel 430. Disposed on channel 430 is second diffusion region 435. First diffusion region 425, channel 430 and second diffusion region 435 are illustrated as a quadrilateral (e.g., rectangular) body or fin projecting generally vertically from a surface of TSM layer 485. Offset in an x- direction from the transistor body or fin and connected to only one side of the quadrilateral structure of the channel of the transistor body or fin is a gate stack including gate dielectric 440 of, for example, silicon dioxide or a high-k material or a combination of materials and gate electrode 450 of, for example, a metal material (e.g., tantalum), a metal nitride or a silicide. As shown in Figure 15, the gate stack extends through the array in a z-dimension and, in such manner, is connected to multiple channels of transistor bodies or fins in the array. Figure 15 shows a gate stack connected to four transistor bodies or fins to

representatively define a column where gate electrode 450 may serve as an address line for each of the transistors aligned in a z-dimension column.

Disposed on and electrically connected to each of the second diffusion regions (second diffusion region 435) are respective second address lines 490. In one embodiment, in the illustration shown in Figure 15, each second address line 490 is connected to five transistors in a row and is disposed in a parallel alignment with first address line 417. Second address line 490 may be a metal material such as copper that may be part of a BEOL metallization layer. Figure 15 shows each of first address lines 417 are electrically connected to first bit line driver 493 and each of second address lines 490 are electrically connected to second bit line driver 495. Each gate electrode 450 defining a word line, in this embodiment, is connected to word line driver 496.

Figures 17-27 describe a method for forming the transistor array as shown in Figure 15 and Figure 16. Figure 28 is a flow chart of the method. A formation process for an array of n-type FETs is described. Again, it should be appreciated that the techniques for forming a transistor presented here are not limited to any particular device conductivity or transistor type. Referring to Figure 17 and with reference to Figure 28, the process begins following, in this example, any FEOL fabrication such as the forming of transistor or other devices on a substrate, the passivating of such devices and the formation of contacts to such devices. Figure 17 shows substrate 510 that may be any material that may serve as a foundation on which an array of vertical FETs may be constructed. Representatively, substrate 510 is a portion of a larger substrate that is a wafer. In one embodiment, substrate 510 is a bulk semiconductor material such as a single crystal silicon or an SOI structure.

Disposed on a surface of substrate 510 (a top surface as viewed) is device layer 512 of, for example, a number of transistor, capacitor, and/or resistor devices. Overlying device layer 512 is passivation layer 515. In one embodiment, passivation layer 515 is a Si0₂ layer or a low-k dielectric material. Passivation layer 515, in one embodiment, may be a base dielectric layer passivating the FEOL fabrication and, in another embodiment, may be insulating material passivating the FEOL fabrication and also insulating material between metallization layers formed as part of BEOL fabrication. Overlying or disposed on passivation layer 515 is conductive layer 517. Conductive layer 517 is an electrically conductive material that would be suitable, in one embodiment, to serve as an address line for an array of transistors connected thereto. In one embodiment, conductive layer 517 is a copper material that may be deposited by an electroplating process over an array area on a surface of an area including passivation layer 515 (block 605, Figure 28). In another embodiment, conductive layer 517 is titanium nitride or tungsten deposited by, for example, a CVD or PVD process. In one embodiment, conductive layer 517 may be part of a metallization layer (e.g., M1-M6) in a BEOL fabrication.

Disposed on conductiver layer 517 is TSM layer 585. In one embodiment, TSM layer 585 is a semiconductor material or an oxide such as described above deposited, for example, by CVD to a thickness of 5 nm to 20 nm (block 610, Figure 28). Figure 17 shows film 525 deposited on conductive layer 517. Film 525 is, for example, an amorphous or crystalline (e.g., polycrystalline) semiconductor material such as silicon, germanium (Ge), silicon germanium (SiGe), gallium arsenide (G7s), indium antimony (InSb), indium gallium arsenide (InG7s), gallium antimony (GaSb), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO) or tin oxide (SnO). For n-type transistors, film 525 is n-doped (n+) and is epitaxially grown or deposited to a representative thickness on the order of 25 nm as a first diffusion region film (block 610, Figure 28). Formed on film 525 is a film for a channel of a transistor (block 615, Figure 28). In one embodiment, film 530 is undoped (intrinsic) or lightly doped semiconductor material that has a representative thickness on the order of 75 nm. Where film 525 is silicon, film 530 may also be silicon that is formed by an epitaxial growth or deposition process.

Figure 18 shows the structure of Figure 17 following the definition of fin structures in film 525 and film 530 (block 620, Figure 28) and a deposition of dielectric material between the fins (block 625, Figure 28). Figure 18 representatively shows five fins. The fins may be formed by a mask and etch process wherein mask 533 (e.g., hard mask of, for example, silicon nitride) is introduced on a surface (superior surface) of film 530 to protect areas of film 530 and underlying film 525 where the fins would be defined and provide openings in non-fin areas. Once mask 533 is patterned, the structure may be anisotropically etched to remove the material in unprotected areas. As shown in Figure 25, in one embodiment, the etch is selective for a material of film 525 and film 530 but does not etch TSM layer 585. In this manner, trench or trenches 547 formed adjacent to the five fins have a depth to a surface of TSM layer 585. In another embodiment, TSM layer 585 is also etched by the anisotropic etch so that the bodies or fins include TSM layer 585 at a base. In such an embodiment, the etch (e.g., one or more etchants) does not etch conductive layer 517. In one embodiment, each of the five fins, as shown in Figure 18, has a thickness dimension, t, on the order of 10 nm. Between adjacent fins is trench 547 having a representative width in an x-direction, w_t, on the order of 40 nm. Following the definition of the fins, trenches 547 are filled with dielectric material 545 such as silicon dioxide or a low-k dielectric material.

Figure 19 shows the structure of Figure 18 following a recessing of dielectric layer 545 to a height of film 525 to expose an entire length dimension of film 530 (block 630, Figure 28). In one embodiment, such recessing may be done by retaining mask 533 and etching the dielectric material using a timed etch. As illustrated in Figure 19, the depth of the etch forms trenches 547 having a depth of the length of film 530 (e.g., 75 nm). Figure 20 shows the structure of Figure 19 following the introduction of a gate dielectric and gate electrode material in the trenches of the structure. Initially, a gate dielectric material is introduced (block 635, Figure 28). Gate dielectric 540 is, for example, silicon dioxide or a high-k dielectric material or a mixture of silicon dioxide and a high-k material or materials. As shown in Figure 20, gate dielectric material 540 is introduced by, for example, CVD deposition to a thickness on the order of few nanometers in a manner that it conforms to the sidewalls of each trench 547 and a superior surface of dielectric layer 545. After forming gate dielectric 540, gate electrode 550 is formed in the trenches (block 640, Figure 28). Representative materials for gate electrode 550 include, but are not limited to, tungsten, tantalum, titanium or a nitride, a metal alloy, silicide or another material. In one embodiment, gate electrode 550 may be introduced by a CVD or other deposition process. In one embodiment, a material for gate electrode 550 is introduced in an amount to fill each trench 547. Following the introduction of gate electrode 550 in each trench, a surface of the structure (a top or superior surface as viewed) may be polished by, for example, a chemical- mechanical polish to planarize the structure.

Figure 21 shows the structure of Figure 20 following a recessing of the gate stack material (gate dielectric 540 and gate electrode 550) in each trench 547 (block 645, Figure 28). In one embodiment, a combination of dry or wet etches may be used to recess a metal gate electrode material and a high-k gate dielectric material. A recess is performed to expose a portion of film 530 such that the exposed portion can be modified or converted to form a second diffusion region in each fin. In one embodiment, the recess of gate dielectric 540 and gate electrode 550 exposes approximately 20 nm of film 530.

Figure 22 shows the structure of Figure 21 following a removal of the mask on each fin and the conversion of a portion of film 530 into second diffusion region material. The removal of mask 533 exposes a top portion of film 530. Following the removal, the exposed portion of film 530 may be converted to a second diffusion region material (block 650,

Figure 28). In one embodiment, second diffusion region 535 is formed by implanting an n- type implant such as arsenic or phosphorous into the exposed portion of film 530 to form an n⁺ second diffusion region. In another embodiment, a portion of film 530 can be removed and replaced with another material to form second diffusion region 535. Figure 22 shows second diffusion region 535 having an x-dimension (thickness dimension) similar to that of film 530. In another embodiment, the x-dimension may be greater than an x-dimension of film 530 to form, for example, a raised diffusion region. In still another embodiment, an optional dielectric layer of silicon dioxide or a low-k dielectric material or a combination of materials may be formed on an exposed portion of the gate stack prior to the formation of second diffusion region 535 as a sidewall spacer on the gate electrode.

Figure 22 also shows the structure following the introduction of a dielectric material in trenches 547. In one embodiment, dielectric material 555 is silicon dioxide or a low-k dielectric material or a combination of materials that may be introduced by a deposition process. Following the deposition, a top surface of the structure (as viewed) may be planarized.

Figure 23 shows a top view of the structure of Figure 22 following patterning of a masking material generally perpendicular to a direction of the gate stacks. A width, w_m, of mask 566 is selected to define a z-dimension thickness or width of individual transistor bodies or fins in a column. A representative width is on the order of 20 nm to 500 nm (e.g., 50 nm to 100 nm). One suitable material for mask 566 is a silicon nitride material.

Figure 24 shows the structure of Figure 23 through line 24-24' to show a yz- dimension following the formation of trenches through the fins in areas of the fins that were not protected by mask 566 (block 655, Figure 28). In one embodiment, the trenches are formed by anisotropically etching a portion of second diffusion region 535, film 530, film 525, TSM layer 585 and conductive layer 517 by an etch or series of etches. Such etching is selective to the noted materials and stops on passivation layer 515. Such etching also does not etch dielectric material 555 above each gate stack.

Figure 25 shows the structure of Figure 24 following the deposition of dielectric material 570 in trenches 667 (block 660, Figure 28). In this embodiment, dielectric material 570 is deposited to at least a height of mask 566. Figure 26 shows a top view of the structure of Figure 25. Once dielectric material 570 is deposited, the structure may be planarized by, for example, a polish. Following the deposition and optional planarization, mask 566 is removed by, for example, an etch and replaced with electrically conductive material such as a metallization metal (e.g., copper).

Figure 27 shows the structure of Figure 26 through line 27-27' after the replacement of mask 566 with electrically conductive material (block 665, Figure 28). Figure 27 shows electrically conductive material 590 such as a metal (e.g., copper) physically connected to second diffusion region 525 of each of five transistors in a row. Conductive material 590 may serve as a second address line (e.g., a second bit line) as described above with respect to Figures 15-16. The structure shown in Figure 27 is similar to that described above with respect to Figures 15-16. In one embodiment, the transistor arrays described above with respect to Figures 1 and 2 or Figures 15 and 16 can be used to store information that could be used in a programmable array.

Figure 29 illustrates interposer 700 that includes one or more embodiments.

Interposer 700 is an intervening substrate used to bridge a first substrate 702 to second substrate 704. First substrate 702 may be, for instance, an integrated circuit die. Second substrate 704 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, interposer 700 may connect an integrated circuit die to ball grid array (BGA) 706 that can subsequently be connected to second substrate 704. In some embodiments, first and second substrates 702/704 are attached to opposing sides of interposer 700. In other embodiments, first and second substrates 702/704 are attached to the same side of interposer 700. In further embodiments, three or more substrates are interconnected by way of interposer 700.

Interposer 700 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 708 and vias 710, including but not limited to through-silicon vias (TSVs) 712. Interposer 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on interposer 700.

In accordance with embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 700.

Figure 30 illustrates computing device 800 in accordance with one embodiment. Computing device 800 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a

motherboard. The components in computing device 800 include, but are not limited to, integrated circuit die 802 and at least one communication chip 808. In some implementations communication chip 808 is fabricated as part of integrated circuit die 802. Integrated circuit die 802 may include CPU 804 as well as on-die memory 806, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM).

Computing device 800 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die.

These other components include, but are not limited to, volatile memory 810 (e.g., DRAM), non-volatile memory 812 (e.g., ROM or flash memory), graphics processing unit 814 (GPU), digital signal processor 816, crypto processor 842 (a specialized processor that executes cryptographic algorithms within hardware), chipset 820, antenna 822, display or a touchscreen display 824, touchscreen controller 826, battery 828 or other power source, a power amplifier (not shown), global positioning system (GPS) device 844, compass 830, motion coprocessor or sensors 832 (that may include an accelerometer, a gyroscope, and a compass), speaker 834, camera 836, user input devices 838 (such as a keyboard, mouse, stylus, and touchpad), and mass storage device 840 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

Communications chip 808 enables wireless communications for the transfer of data to and from computing device 800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chip 808 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA,

TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device 800 may include a plurality of communication chips 808. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second

communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Processor 804 of computing device 800 includes one or more devices, such as vertical transistors and a threshold switching material in direct contact with such transistors, that are formed in accordance with embodiments presented above. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communication chip 808 may also include one or more devices, such as vertical transistors and a threshold switching material in direct contact with such transistors, that are formed in accordance with embodiments presented above.

In further embodiments, another component housed within computing device 800 may contain one or more devices, such as vertical transistors and a threshold switching material in direct contact with such transistors, that are formed in accordance with implementations presented above.

In various embodiments, computing device 800 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 800 may be any other electronic device that processes data.

EXAMPLES

Example 1 is a transistor apparatus including a transistor body disposed on a substrate, the body including a first diffusion region and a second diffusion region on the first diffusion region, wherein the first diffusion region and the second diffusion region are separated by a channel; a threshold switching material (TSM) coupled to one of the first diffusion region and the second diffusion region; and a gate stack including a gate electrode and a gate dielectric material.

In Example 2, the TSM of the apparatus of Example 1 is on the second diffusion region between the second diffusion region and an electrically conductive material.

In Example 3, the TSM of the apparatus of Example 2 includes a width dimension equivalent to a width dimension of the body of the transistor.

In Example 4, the electrically conductive material of the apparatus of Example 3 includes a width dimension equivalent to the width dimension of the TSM.

In Example 5, the electrically conductive material of the apparatus of any of

Examples 2-4 is an address line.

In Example 6, the second diffusion region of the apparatus of any of Examples 2-5 is a source.

In Example 7, the TSM of the apparatus of any of Examples 1-6 is selected from a semiconductor material and an oxide.

In Example 8, the TSM of the apparatus of Example 7 is a semiconductor selected from silicon, germanium or a compound semiconductor selected from elements from one of group 14 to group 16 of the Periodic Table of the Elements.

Example 9 is an integrated circuit array including a plurality of transistors aligned in a row on a substrate, wherein each of the plurality of transistors includes a body, the body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel; a threshold switching material (TSM) coupled to one of the first diffusion region and the second diffusion region of each of the plurality of transistors; and an address line coupled to one of the first diffusion region and the second diffusion region of each of the plurality of transistors, wherein the TSM is disposed between the address line and the one of the first diffusion region and the second diffusion region.

In Example 10, the TSM and the address line each of the array of Example 9 have a width dimension equivalent to a width dimension of the body of each of plurality of transistors.

In Example 11, each of the transistors of the array of Example 9 further includes a gate electrode coupled to the channel and offset from the body.

In Example 12, the plurality of transistors of the array of Example 9 includes a first plurality of transistors and the address line includes a first address line, the array further including a second plurality of transistors aligned in a column on the substrate with a projection of the column intersecting a projection of the row and each of the second plurality of transistors includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel, a TSM coupled to one of the first diffusion region and the second diffusion region and a gate electrode offset from the body and coupled as an indivisible body to the channel of each body of the second plurality of transistors as a second address line.

In Example 13, the gate electrode coupled to the channel of each body of the plurality of second transistors of the array of Example 12 is coupled to a channel of one of the bodies of the first plurality of transistors.

In Example 14, the second address line of the array of Example 13 is perpendicular to the first address line.

In Example 15, the substrate of the array of Example 9 includes a device layer on the substrate and a plurality of metallization layers on the device layer, wherein the plurality of transistors are disposed between ones of the plurality of metallization layers. In Example 16, the TSM of the array of Example 9 is selected from a semiconductor material and an oxide.

In Example 17, the TSM of the array of Example 16 is a semiconductor selected from silicon, germanium or a compound semiconductor selected from elements from one of group 14 to group 16 of the Periodic Table of the Elements.

Example 18 is a method of forming an integrated circuit including forming a plurality of bodies in a row on a substrate, each of the plurality of bodies including a transistor including a first diffusion region, a second diffusion region and a channel, wherein the second diffusion region is on the first diffusion region and separated by the channel; and forming a threshold switching material (TSM) in contact with the second diffusion region.

In Example 19, prior to forming a TSM, the method of Example 18 includes patterning a masking material on each of the plurality of bodies; and etching each of the plurality of bodies through the masking material to define a width dimension, wherein the width dimension is defined by a width dimension of the masking material.

In Example 20, patterning the masking material in the method of Example 19 includes patterning the masking material perpendicular to the row.

In Example 21, forming a TSM in the method of Example 19 includes replacing the masking material with a threshold switching material (TSM) and an address line material, wherein the TSM is disposed between each of the plurality of bodies and the address line material.

In Example 22, the substrate in the method of Example 19 includes a device layer on the substrate and a plurality of metallization layers on the device layer, wherein forming the bodies in a plurality of rows on a substrate includes forming the transistor bodies between ones of the plurality of metallization layers.

The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope, as those skilled in the relevant art will recognize.

These modifications may be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

1. A transistor apparatus comprising:

a transistor body disposed on a substrate, the body comprising a first diffusion region and a second diffusion region on the first diffusion region, wherein the first diffusion region and the second diffusion region are separated by a channel;

a threshold switching material (TSM) coupled to one of the first diffusion region and the second diffusion region; and

a gate stack comprising a gate electrode and a gate dielectric material.

2. The apparatus of claim 1, wherein the TSM is on the second diffusion region between the second diffusion region and an electrically conductive material.

3. The apparatus of claim 2, wherein the TSM comprises a width dimension equivalent to a width dimension of the body of the transistor.

4. The apparatus of claim 3, wherein the electrically conductive material comprises a width dimension equivalent to the width dimension of the TSM.

5. The apparatus of claim 2, wherein the electrically conductive material is an address line.

6. The apparatus of claim 2, wherein the second diffusion region is a source.

7. The apparatus of claim 1, wherein the TSM is selected from a semiconductor material and an oxide.

8. The apparatus of claim 7, wherein the TSM is a semiconductor selected from silicon, germanium or a compound semiconductor selected from elements from one of group 14 to group 16 of the Periodic Table of the Elements.

9. An integrated circuit array comprising:

a plurality of transistors aligned in a row on a substrate, wherein each of the plurality of transistors comprises a body, the body comprising a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel;

a threshold switching material (TSM) coupled to one of the first diffusion region and the second diffusion region of each of the plurality of transistors; and

an address line coupled to one of the first diffusion region and the second diffusion region of each of the plurality of transistors, wherein the TSM is disposed between the address line and the one of the first diffusion region and the second diffusion region.

10. The array of claim 9, wherein the TSM and the address line each have a width dimension equivalent to a width dimension of the body of each of plurality of transistors.

11. The array of claim 9, wherein each of the transistors further comprises a gate electrode coupled to the channel and offset from the body.

12. The array of claim 9, wherein the plurality of transistors comprises a first plurality of transistors and the address line comprises a first address line, the array further comprising a second plurality of transistors aligned in a column on the substrate with a projection of the column intersecting a projection of the row and each of the second plurality of transistors comprises a body comprising a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel, a TSM coupled to one of the first diffusion region and the second diffusion region and a gate electrode offset from the body and coupled as an indivisible body to the channel of each body of the second plurality of transistors as a second address line.

13. The array of claim 12, wherein the gate electrode coupled to the channel of each body of the plurality of second transistors is coupled to a channel of one of the bodies of the first plurality of transistors.

14. The array of claim 13, wherein the second address line is perpendicular to the first address line.

15. The array of claim 9, wherein the substrate comprises a device layer on the substrate and a plurality of metallization layers on the device layer, wherein the plurality of transistors are disposed between ones of the plurality of metallization layers.

16. The array of claim 9, wherein the TSM is selected from a semiconductor material and an oxide.

17. The array of claim 16, wherein the TSM is a semiconductor selected from silicon, germanium or a compound semiconductor selected from elements from one of group 14 to group 16 of the Periodic Table of the Elements.

18. A method of forming an integrated circuit comprising:

forming a plurality of bodies in a row on a substrate, each of the plurality of bodies comprising a transistor comprising a first diffusion region, a second diffusion region and a channel, wherein the second diffusion region is on the first diffusion region and separated by the channel; and

forming a threshold switching material (TSM) in contact with the second diffusion region.

19. The method of claim 18, wherein prior to forming a TSM, the method comprises: patterning a masking material on each of the plurality of bodies; and

etching each of the plurality of bodies through the masking material to define a width dimension, wherein the width dimension is defined by a width dimension of the masking material.

20. The method of claim 19, wherein patterning the masking material comprises patterning the masking material perpendicular to the row.

21. The method of claim 19, wherein forming a TSM comprises replacing the masking material with a threshold switching material (TSM) and an address line material, wherein the TSM is disposed between each of the plurality of bodies and the address line material.

22. The method of claim 19, wherein the substrate comprises a device layer on the substrate and a plurality of metallization layers on the device layer, wherein forming the bodies in a plurality of rows on a substrate comprises forming the transistor bodies between ones of the plurality of metallization layers.